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Searched refs:CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h11198 #define CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK (0x80U) macro
11204 …int32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SYSCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK)
DMIMXRT735S_cm33_core1.h11234 #define CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK (0x80U) macro
11240 …int32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SYSCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK)
DMIMXRT735S_ezhv.h20768 #define CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK (0x80U) macro
20774 …int32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SYSCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h11234 #define CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK (0x80U) macro
11240 …int32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SYSCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK)
DMIMXRT758S_hifi1.h11198 #define CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK (0x80U) macro
11204 …int32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SYSCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK)
DMIMXRT758S_ezhv.h20768 #define CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK (0x80U) macro
20774 …int32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SYSCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h11198 #define CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK (0x80U) macro
11204 …int32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SYSCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK)
DMIMXRT798S_cm33_core1.h11234 #define CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK (0x80U) macro
11240 …int32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SYSCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK)
DMIMXRT798S_ezhv.h20768 #define CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK (0x80U) macro
20774 …int32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SYSCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SYSCON1_MASK)