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Searched refs:CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h11190 #define CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK (0x40U) macro
11196 …2_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SLEEPCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK)
DMIMXRT735S_cm33_core1.h11226 #define CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK (0x40U) macro
11232 …2_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SLEEPCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK)
DMIMXRT735S_ezhv.h20760 #define CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK (0x40U) macro
20766 …2_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SLEEPCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h11226 #define CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK (0x40U) macro
11232 …2_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SLEEPCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK)
DMIMXRT758S_hifi1.h11190 #define CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK (0x40U) macro
11196 …2_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SLEEPCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK)
DMIMXRT758S_ezhv.h20760 #define CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK (0x40U) macro
20766 …2_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SLEEPCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h11190 #define CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK (0x40U) macro
11196 …2_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SLEEPCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK)
DMIMXRT798S_cm33_core1.h11226 #define CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK (0x40U) macro
11232 …2_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SLEEPCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK)
DMIMXRT798S_ezhv.h20760 #define CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK (0x40U) macro
20766 …2_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_CLR_SLEEPCON1_SHIFT)) & CLKCTL1_PSCCTL0_CLR_SLEEPCON1_MASK)