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Searched refs:CLKCTL0_PSCCTL2_SET_I3C1_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h18619 #define CLKCTL0_PSCCTL2_SET_I3C1_MASK (0x20000U) macro
18625 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_I3C1_SHIFT)) & CLKCTL0_PSCCTL2_SET_I3C1_MASK)
DMIMXRT798S_cm33_core0.h18680 #define CLKCTL0_PSCCTL2_SET_I3C1_MASK (0x20000U) macro
18686 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_I3C1_SHIFT)) & CLKCTL0_PSCCTL2_SET_I3C1_MASK)
DMIMXRT798S_ezhv.h18125 #define CLKCTL0_PSCCTL2_SET_I3C1_MASK (0x20000U) macro
18131 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_I3C1_SHIFT)) & CLKCTL0_PSCCTL2_SET_I3C1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h18125 #define CLKCTL0_PSCCTL2_SET_I3C1_MASK (0x20000U) macro
18131 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_I3C1_SHIFT)) & CLKCTL0_PSCCTL2_SET_I3C1_MASK)
DMIMXRT735S_cm33_core0.h18680 #define CLKCTL0_PSCCTL2_SET_I3C1_MASK (0x20000U) macro
18686 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_I3C1_SHIFT)) & CLKCTL0_PSCCTL2_SET_I3C1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h18680 #define CLKCTL0_PSCCTL2_SET_I3C1_MASK (0x20000U) macro
18686 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_I3C1_SHIFT)) & CLKCTL0_PSCCTL2_SET_I3C1_MASK)
DMIMXRT758S_ezhv.h18125 #define CLKCTL0_PSCCTL2_SET_I3C1_MASK (0x20000U) macro
18131 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_SET_I3C1_SHIFT)) & CLKCTL0_PSCCTL2_SET_I3C1_MASK)