Home
last modified time | relevance | path

Searched refs:CLKCTL0_PSCCTL2_CLR_SAI2_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h19275 #define CLKCTL0_PSCCTL2_CLR_SAI2_MASK (0x8000U) macro
19281 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SAI2_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SAI2_MASK)
DMIMXRT798S_cm33_core0.h19336 #define CLKCTL0_PSCCTL2_CLR_SAI2_MASK (0x8000U) macro
19342 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SAI2_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SAI2_MASK)
DMIMXRT798S_ezhv.h18781 #define CLKCTL0_PSCCTL2_CLR_SAI2_MASK (0x8000U) macro
18787 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SAI2_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SAI2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h18781 #define CLKCTL0_PSCCTL2_CLR_SAI2_MASK (0x8000U) macro
18787 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SAI2_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SAI2_MASK)
DMIMXRT735S_cm33_core0.h19336 #define CLKCTL0_PSCCTL2_CLR_SAI2_MASK (0x8000U) macro
19342 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SAI2_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SAI2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h19336 #define CLKCTL0_PSCCTL2_CLR_SAI2_MASK (0x8000U) macro
19342 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SAI2_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SAI2_MASK)
DMIMXRT758S_ezhv.h18781 #define CLKCTL0_PSCCTL2_CLR_SAI2_MASK (0x8000U) macro
18787 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL2_CLR_SAI2_SHIFT)) & CLKCTL0_PSCCTL2_CLR_SAI2_MASK)