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Searched refs:CLKCTL0_PSCCTL1_SET_XSPI1_MASK (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_power.c839 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; in AT_QUICKACCESS_SECTION_CODE()
842 CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; in AT_QUICKACCESS_SECTION_CODE()
862 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_power.c839 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; in AT_QUICKACCESS_SECTION_CODE()
842 CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; in AT_QUICKACCESS_SECTION_CODE()
862 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_power.c839 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; in AT_QUICKACCESS_SECTION_CODE()
842 CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; in AT_QUICKACCESS_SECTION_CODE()
862 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt700evk/project_template/
Dboard.c296 CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; in BOARD_SetXspiClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h18327 #define CLKCTL0_PSCCTL1_SET_XSPI1_MASK (0x800U) macro
18333 …(((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_XSPI1_SHIFT)) & CLKCTL0_PSCCTL1_SET_XSPI1_MASK)
DMIMXRT798S_cm33_core0.h18388 #define CLKCTL0_PSCCTL1_SET_XSPI1_MASK (0x800U) macro
18394 …(((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_XSPI1_SHIFT)) & CLKCTL0_PSCCTL1_SET_XSPI1_MASK)
DMIMXRT798S_ezhv.h17833 #define CLKCTL0_PSCCTL1_SET_XSPI1_MASK (0x800U) macro
17839 …(((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_XSPI1_SHIFT)) & CLKCTL0_PSCCTL1_SET_XSPI1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h17833 #define CLKCTL0_PSCCTL1_SET_XSPI1_MASK (0x800U) macro
17839 …(((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_XSPI1_SHIFT)) & CLKCTL0_PSCCTL1_SET_XSPI1_MASK)
DMIMXRT735S_cm33_core0.h18388 #define CLKCTL0_PSCCTL1_SET_XSPI1_MASK (0x800U) macro
18394 …(((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_XSPI1_SHIFT)) & CLKCTL0_PSCCTL1_SET_XSPI1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h18388 #define CLKCTL0_PSCCTL1_SET_XSPI1_MASK (0x800U) macro
18394 …(((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_XSPI1_SHIFT)) & CLKCTL0_PSCCTL1_SET_XSPI1_MASK)
DMIMXRT758S_ezhv.h17833 #define CLKCTL0_PSCCTL1_SET_XSPI1_MASK (0x800U) macro
17839 …(((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_SET_XSPI1_SHIFT)) & CLKCTL0_PSCCTL1_SET_XSPI1_MASK)