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Searched refs:CLKCTL0_PSCCTL1_CDOG2_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h17791 #define CLKCTL0_PSCCTL1_CDOG2_MASK (0x20000000U) macro
17797 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CDOG2_SHIFT)) & CLKCTL0_PSCCTL1_CDOG2_MASK)
DMIMXRT798S_cm33_core0.h17852 #define CLKCTL0_PSCCTL1_CDOG2_MASK (0x20000000U) macro
17858 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CDOG2_SHIFT)) & CLKCTL0_PSCCTL1_CDOG2_MASK)
DMIMXRT798S_ezhv.h17297 #define CLKCTL0_PSCCTL1_CDOG2_MASK (0x20000000U) macro
17303 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CDOG2_SHIFT)) & CLKCTL0_PSCCTL1_CDOG2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h17297 #define CLKCTL0_PSCCTL1_CDOG2_MASK (0x20000000U) macro
17303 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CDOG2_SHIFT)) & CLKCTL0_PSCCTL1_CDOG2_MASK)
DMIMXRT735S_cm33_core0.h17852 #define CLKCTL0_PSCCTL1_CDOG2_MASK (0x20000000U) macro
17858 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CDOG2_SHIFT)) & CLKCTL0_PSCCTL1_CDOG2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h17852 #define CLKCTL0_PSCCTL1_CDOG2_MASK (0x20000000U) macro
17858 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CDOG2_SHIFT)) & CLKCTL0_PSCCTL1_CDOG2_MASK)
DMIMXRT758S_ezhv.h17297 #define CLKCTL0_PSCCTL1_CDOG2_MASK (0x20000000U) macro
17303 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_PSCCTL1_CDOG2_SHIFT)) & CLKCTL0_PSCCTL1_CDOG2_MASK)