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Searched refs:CLKCTL0_ADC0FCLKDIV_DIV_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.c465 return freq / ((CLKCTL0->ADC0FCLKDIV & CLKCTL0_ADC0FCLKDIV_DIV_MASK) + 1U); in CLOCK_GetAdcClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.c465 return freq / ((CLKCTL0->ADC0FCLKDIV & CLKCTL0_ADC0FCLKDIV_DIV_MASK) + 1U); in CLOCK_GetAdcClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.c466 return freq / ((CLKCTL0->ADC0FCLKDIV & CLKCTL0_ADC0FCLKDIV_DIV_MASK) + 1U); in CLOCK_GetAdcClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.c466 return freq / ((CLKCTL0->ADC0FCLKDIV & CLKCTL0_ADC0FCLKDIV_DIV_MASK) + 1U); in CLOCK_GetAdcClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.c466 return freq / ((CLKCTL0->ADC0FCLKDIV & CLKCTL0_ADC0FCLKDIV_DIV_MASK) + 1U); in CLOCK_GetAdcClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h2545 #define CLKCTL0_ADC0FCLKDIV_DIV_MASK (0xFFU) macro
2548 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_DIV_SHIFT)) & CLKCTL0_ADC0FCLKDIV_DIV_MASK)
DMIMXRT685S_cm33.h8256 #define CLKCTL0_ADC0FCLKDIV_DIV_MASK (0xFFU) macro
8259 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_DIV_SHIFT)) & CLKCTL0_ADC0FCLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h8256 #define CLKCTL0_ADC0FCLKDIV_DIV_MASK (0xFFU) macro
8259 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_DIV_SHIFT)) & CLKCTL0_ADC0FCLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h3666 #define CLKCTL0_ADC0FCLKDIV_DIV_MASK (0xFFU) macro
3669 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_DIV_SHIFT)) & CLKCTL0_ADC0FCLKDIV_DIV_MASK)
DMIMXRT595S_cm33.h9904 #define CLKCTL0_ADC0FCLKDIV_DIV_MASK (0xFFU) macro
9907 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_DIV_SHIFT)) & CLKCTL0_ADC0FCLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h9900 #define CLKCTL0_ADC0FCLKDIV_DIV_MASK (0xFFU) macro
9903 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_DIV_SHIFT)) & CLKCTL0_ADC0FCLKDIV_DIV_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h9903 #define CLKCTL0_ADC0FCLKDIV_DIV_MASK (0xFFU) macro
9906 … (((uint32_t)(((uint32_t)(x)) << CLKCTL0_ADC0FCLKDIV_DIV_SHIFT)) & CLKCTL0_ADC0FCLKDIV_DIV_MASK)