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Searched refs:CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h3940 …__IO uint32_t CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL; /**< CPU1 to CPU2 message FIFO control, offset: 0… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h6109 …__IO uint32_t CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL; /**< CPU1 to CPU2 message FIFO control, offset: 0… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h6371 …__IO uint32_t CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL; /**< CPU1 to CPU2 message FIFO control, offset: 0… member
DMCXW727C_cm33_core1.h14871 …__IO uint32_t CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL; /**< CPU1 to CPU2 message FIFO control, offset: 0… member