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Searched refs:CIU2_BCA1_CPU2_INT_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h3948 …__IO uint32_t CIU2_BCA1_CPU2_INT_MASK; /**< BCA1 to CPU2 Interrupt Mask, offset: 0x200 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h6117 …__IO uint32_t CIU2_BCA1_CPU2_INT_MASK; /**< BCA1 to CPU2 Interrupt Mask, offset: 0x200 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h6379 …__IO uint32_t CIU2_BCA1_CPU2_INT_MASK; /**< BCA1 to CPU2 Interrupt Mask, offset: 0x200 */ member
DMCXW727C_cm33_core1.h14879 …__IO uint32_t CIU2_BCA1_CPU2_INT_MASK; /**< BCA1 to CPU2 Interrupt Mask, offset: 0x200 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h17567 …__IO uint32_t CIU2_BCA1_CPU2_INT_MASK; /**< BCA1 to CPU2 Interrupt Mask, offset: 0x200 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h17567 …__IO uint32_t CIU2_BCA1_CPU2_INT_MASK; /**< BCA1 to CPU2 Interrupt Mask, offset: 0x200 */ member