1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_DMA_TCD.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_DMA_TCD 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_DMA_TCD_H_) /* Check if memory map has not been already included */ 58 #define S32K344_DMA_TCD_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DMA_TCD Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DMA_TCD_Peripheral_Access_Layer DMA_TCD Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DMA_TCD - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CH0_CSR; /**< Channel Control and Status, offset: 0x0 */ 74 __IO uint32_t CH0_ES; /**< Channel Error Status, offset: 0x4 */ 75 __IO uint32_t CH0_INT; /**< Channel Interrupt Status, offset: 0x8 */ 76 __IO uint32_t CH0_SBR; /**< Channel System Bus, offset: 0xC */ 77 __IO uint32_t CH0_PRI; /**< Channel Priority, offset: 0x10 */ 78 uint8_t RESERVED_0[12]; 79 __IO uint32_t TCD0_SADDR; /**< TCD Source Address, offset: 0x20 */ 80 __IO uint16_t TCD0_SOFF; /**< TCD Signed Source Address Offset, offset: 0x24 */ 81 __IO uint16_t TCD0_ATTR; /**< TCD Transfer Attributes, offset: 0x26 */ 82 union { /* offset: 0x28 */ 83 __IO uint32_t TCD0_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x28 */ 84 __IO uint32_t TCD0_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x28 */ 85 } NBYTES0; 86 __IO uint32_t TCD0_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x2C */ 87 __IO uint32_t TCD0_DADDR; /**< TCD Destination Address, offset: 0x30 */ 88 __IO uint16_t TCD0_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x34 */ 89 union { /* offset: 0x36 */ 90 __IO uint16_t TCD0_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x36 */ 91 __IO uint16_t TCD0_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x36 */ 92 } CITER0; 93 __IO uint32_t TCD0_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x38 */ 94 __IO uint16_t TCD0_CSR; /**< TCD Control and Status, offset: 0x3C */ 95 union { /* offset: 0x3E */ 96 __IO uint16_t TCD0_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x3E */ 97 __IO uint16_t TCD0_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x3E */ 98 } BITER0; 99 uint8_t RESERVED_1[16320]; 100 __IO uint32_t CH1_CSR; /**< Channel Control and Status, offset: 0x4000 */ 101 __IO uint32_t CH1_ES; /**< Channel Error Status, offset: 0x4004 */ 102 __IO uint32_t CH1_INT; /**< Channel Interrupt Status, offset: 0x4008 */ 103 __IO uint32_t CH1_SBR; /**< Channel System Bus, offset: 0x400C */ 104 __IO uint32_t CH1_PRI; /**< Channel Priority, offset: 0x4010 */ 105 uint8_t RESERVED_2[12]; 106 __IO uint32_t TCD1_SADDR; /**< TCD Source Address, offset: 0x4020 */ 107 __IO uint16_t TCD1_SOFF; /**< TCD Signed Source Address Offset, offset: 0x4024 */ 108 __IO uint16_t TCD1_ATTR; /**< TCD Transfer Attributes, offset: 0x4026 */ 109 union { /* offset: 0x4028 */ 110 __IO uint32_t TCD1_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x4028 */ 111 __IO uint32_t TCD1_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x4028 */ 112 } NBYTES1; 113 __IO uint32_t TCD1_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x402C */ 114 __IO uint32_t TCD1_DADDR; /**< TCD Destination Address, offset: 0x4030 */ 115 __IO uint16_t TCD1_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x4034 */ 116 union { /* offset: 0x4036 */ 117 __IO uint16_t TCD1_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x4036 */ 118 __IO uint16_t TCD1_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x4036 */ 119 } CITER1; 120 __IO uint32_t TCD1_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x4038 */ 121 __IO uint16_t TCD1_CSR; /**< TCD Control and Status, offset: 0x403C */ 122 union { /* offset: 0x403E */ 123 __IO uint16_t TCD1_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x403E */ 124 __IO uint16_t TCD1_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x403E */ 125 } BITER1; 126 uint8_t RESERVED_3[16320]; 127 __IO uint32_t CH2_CSR; /**< Channel Control and Status, offset: 0x8000 */ 128 __IO uint32_t CH2_ES; /**< Channel Error Status, offset: 0x8004 */ 129 __IO uint32_t CH2_INT; /**< Channel Interrupt Status, offset: 0x8008 */ 130 __IO uint32_t CH2_SBR; /**< Channel System Bus, offset: 0x800C */ 131 __IO uint32_t CH2_PRI; /**< Channel Priority, offset: 0x8010 */ 132 uint8_t RESERVED_4[12]; 133 __IO uint32_t TCD2_SADDR; /**< TCD Source Address, offset: 0x8020 */ 134 __IO uint16_t TCD2_SOFF; /**< TCD Signed Source Address Offset, offset: 0x8024 */ 135 __IO uint16_t TCD2_ATTR; /**< TCD Transfer Attributes, offset: 0x8026 */ 136 union { /* offset: 0x8028 */ 137 __IO uint32_t TCD2_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x8028 */ 138 __IO uint32_t TCD2_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x8028 */ 139 } NBYTES2; 140 __IO uint32_t TCD2_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x802C */ 141 __IO uint32_t TCD2_DADDR; /**< TCD Destination Address, offset: 0x8030 */ 142 __IO uint16_t TCD2_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x8034 */ 143 union { /* offset: 0x8036 */ 144 __IO uint16_t TCD2_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x8036 */ 145 __IO uint16_t TCD2_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x8036 */ 146 } CITER2; 147 __IO uint32_t TCD2_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x8038 */ 148 __IO uint16_t TCD2_CSR; /**< TCD Control and Status, offset: 0x803C */ 149 union { /* offset: 0x803E */ 150 __IO uint16_t TCD2_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x803E */ 151 __IO uint16_t TCD2_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x803E */ 152 } BITER2; 153 uint8_t RESERVED_5[16320]; 154 __IO uint32_t CH3_CSR; /**< Channel Control and Status, offset: 0xC000 */ 155 __IO uint32_t CH3_ES; /**< Channel Error Status, offset: 0xC004 */ 156 __IO uint32_t CH3_INT; /**< Channel Interrupt Status, offset: 0xC008 */ 157 __IO uint32_t CH3_SBR; /**< Channel System Bus, offset: 0xC00C */ 158 __IO uint32_t CH3_PRI; /**< Channel Priority, offset: 0xC010 */ 159 uint8_t RESERVED_6[12]; 160 __IO uint32_t TCD3_SADDR; /**< TCD Source Address, offset: 0xC020 */ 161 __IO uint16_t TCD3_SOFF; /**< TCD Signed Source Address Offset, offset: 0xC024 */ 162 __IO uint16_t TCD3_ATTR; /**< TCD Transfer Attributes, offset: 0xC026 */ 163 union { /* offset: 0xC028 */ 164 __IO uint32_t TCD3_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0xC028 */ 165 __IO uint32_t TCD3_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0xC028 */ 166 } NBYTES3; 167 __IO uint32_t TCD3_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0xC02C */ 168 __IO uint32_t TCD3_DADDR; /**< TCD Destination Address, offset: 0xC030 */ 169 __IO uint16_t TCD3_DOFF; /**< TCD Signed Destination Address Offset, offset: 0xC034 */ 170 union { /* offset: 0xC036 */ 171 __IO uint16_t TCD3_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0xC036 */ 172 __IO uint16_t TCD3_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0xC036 */ 173 } CITER3; 174 __IO uint32_t TCD3_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0xC038 */ 175 __IO uint16_t TCD3_CSR; /**< TCD Control and Status, offset: 0xC03C */ 176 union { /* offset: 0xC03E */ 177 __IO uint16_t TCD3_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0xC03E */ 178 __IO uint16_t TCD3_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0xC03E */ 179 } BITER3; 180 uint8_t RESERVED_7[16320]; 181 __IO uint32_t CH4_CSR; /**< Channel Control and Status, offset: 0x10000 */ 182 __IO uint32_t CH4_ES; /**< Channel Error Status, offset: 0x10004 */ 183 __IO uint32_t CH4_INT; /**< Channel Interrupt Status, offset: 0x10008 */ 184 __IO uint32_t CH4_SBR; /**< Channel System Bus, offset: 0x1000C */ 185 __IO uint32_t CH4_PRI; /**< Channel Priority, offset: 0x10010 */ 186 uint8_t RESERVED_8[12]; 187 __IO uint32_t TCD4_SADDR; /**< TCD Source Address, offset: 0x10020 */ 188 __IO uint16_t TCD4_SOFF; /**< TCD Signed Source Address Offset, offset: 0x10024 */ 189 __IO uint16_t TCD4_ATTR; /**< TCD Transfer Attributes, offset: 0x10026 */ 190 union { /* offset: 0x10028 */ 191 __IO uint32_t TCD4_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x10028 */ 192 __IO uint32_t TCD4_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x10028 */ 193 } NBYTES4; 194 __IO uint32_t TCD4_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x1002C */ 195 __IO uint32_t TCD4_DADDR; /**< TCD Destination Address, offset: 0x10030 */ 196 __IO uint16_t TCD4_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x10034 */ 197 union { /* offset: 0x10036 */ 198 __IO uint16_t TCD4_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x10036 */ 199 __IO uint16_t TCD4_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x10036 */ 200 } CITER4; 201 __IO uint32_t TCD4_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x10038 */ 202 __IO uint16_t TCD4_CSR; /**< TCD Control and Status, offset: 0x1003C */ 203 union { /* offset: 0x1003E */ 204 __IO uint16_t TCD4_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x1003E */ 205 __IO uint16_t TCD4_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x1003E */ 206 } BITER4; 207 uint8_t RESERVED_9[16320]; 208 __IO uint32_t CH5_CSR; /**< Channel Control and Status, offset: 0x14000 */ 209 __IO uint32_t CH5_ES; /**< Channel Error Status, offset: 0x14004 */ 210 __IO uint32_t CH5_INT; /**< Channel Interrupt Status, offset: 0x14008 */ 211 __IO uint32_t CH5_SBR; /**< Channel System Bus, offset: 0x1400C */ 212 __IO uint32_t CH5_PRI; /**< Channel Priority, offset: 0x14010 */ 213 uint8_t RESERVED_10[12]; 214 __IO uint32_t TCD5_SADDR; /**< TCD Source Address, offset: 0x14020 */ 215 __IO uint16_t TCD5_SOFF; /**< TCD Signed Source Address Offset, offset: 0x14024 */ 216 __IO uint16_t TCD5_ATTR; /**< TCD Transfer Attributes, offset: 0x14026 */ 217 union { /* offset: 0x14028 */ 218 __IO uint32_t TCD5_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x14028 */ 219 __IO uint32_t TCD5_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x14028 */ 220 } NBYTES5; 221 __IO uint32_t TCD5_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x1402C */ 222 __IO uint32_t TCD5_DADDR; /**< TCD Destination Address, offset: 0x14030 */ 223 __IO uint16_t TCD5_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x14034 */ 224 union { /* offset: 0x14036 */ 225 __IO uint16_t TCD5_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x14036 */ 226 __IO uint16_t TCD5_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x14036 */ 227 } CITER5; 228 __IO uint32_t TCD5_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x14038 */ 229 __IO uint16_t TCD5_CSR; /**< TCD Control and Status, offset: 0x1403C */ 230 union { /* offset: 0x1403E */ 231 __IO uint16_t TCD5_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x1403E */ 232 __IO uint16_t TCD5_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x1403E */ 233 } BITER5; 234 uint8_t RESERVED_11[16320]; 235 __IO uint32_t CH6_CSR; /**< Channel Control and Status, offset: 0x18000 */ 236 __IO uint32_t CH6_ES; /**< Channel Error Status, offset: 0x18004 */ 237 __IO uint32_t CH6_INT; /**< Channel Interrupt Status, offset: 0x18008 */ 238 __IO uint32_t CH6_SBR; /**< Channel System Bus, offset: 0x1800C */ 239 __IO uint32_t CH6_PRI; /**< Channel Priority, offset: 0x18010 */ 240 uint8_t RESERVED_12[12]; 241 __IO uint32_t TCD6_SADDR; /**< TCD Source Address, offset: 0x18020 */ 242 __IO uint16_t TCD6_SOFF; /**< TCD Signed Source Address Offset, offset: 0x18024 */ 243 __IO uint16_t TCD6_ATTR; /**< TCD Transfer Attributes, offset: 0x18026 */ 244 union { /* offset: 0x18028 */ 245 __IO uint32_t TCD6_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x18028 */ 246 __IO uint32_t TCD6_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x18028 */ 247 } NBYTES6; 248 __IO uint32_t TCD6_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x1802C */ 249 __IO uint32_t TCD6_DADDR; /**< TCD Destination Address, offset: 0x18030 */ 250 __IO uint16_t TCD6_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x18034 */ 251 union { /* offset: 0x18036 */ 252 __IO uint16_t TCD6_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x18036 */ 253 __IO uint16_t TCD6_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x18036 */ 254 } CITER6; 255 __IO uint32_t TCD6_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x18038 */ 256 __IO uint16_t TCD6_CSR; /**< TCD Control and Status, offset: 0x1803C */ 257 union { /* offset: 0x1803E */ 258 __IO uint16_t TCD6_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x1803E */ 259 __IO uint16_t TCD6_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x1803E */ 260 } BITER6; 261 uint8_t RESERVED_13[16320]; 262 __IO uint32_t CH7_CSR; /**< Channel Control and Status, offset: 0x1C000 */ 263 __IO uint32_t CH7_ES; /**< Channel Error Status, offset: 0x1C004 */ 264 __IO uint32_t CH7_INT; /**< Channel Interrupt Status, offset: 0x1C008 */ 265 __IO uint32_t CH7_SBR; /**< Channel System Bus, offset: 0x1C00C */ 266 __IO uint32_t CH7_PRI; /**< Channel Priority, offset: 0x1C010 */ 267 uint8_t RESERVED_14[12]; 268 __IO uint32_t TCD7_SADDR; /**< TCD Source Address, offset: 0x1C020 */ 269 __IO uint16_t TCD7_SOFF; /**< TCD Signed Source Address Offset, offset: 0x1C024 */ 270 __IO uint16_t TCD7_ATTR; /**< TCD Transfer Attributes, offset: 0x1C026 */ 271 union { /* offset: 0x1C028 */ 272 __IO uint32_t TCD7_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x1C028 */ 273 __IO uint32_t TCD7_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x1C028 */ 274 } NBYTES7; 275 __IO uint32_t TCD7_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x1C02C */ 276 __IO uint32_t TCD7_DADDR; /**< TCD Destination Address, offset: 0x1C030 */ 277 __IO uint16_t TCD7_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x1C034 */ 278 union { /* offset: 0x1C036 */ 279 __IO uint16_t TCD7_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x1C036 */ 280 __IO uint16_t TCD7_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x1C036 */ 281 } CITER7; 282 __IO uint32_t TCD7_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x1C038 */ 283 __IO uint16_t TCD7_CSR; /**< TCD Control and Status, offset: 0x1C03C */ 284 union { /* offset: 0x1C03E */ 285 __IO uint16_t TCD7_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x1C03E */ 286 __IO uint16_t TCD7_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x1C03E */ 287 } BITER7; 288 uint8_t RESERVED_15[16320]; 289 __IO uint32_t CH8_CSR; /**< Channel Control and Status, offset: 0x20000 */ 290 __IO uint32_t CH8_ES; /**< Channel Error Status, offset: 0x20004 */ 291 __IO uint32_t CH8_INT; /**< Channel Interrupt Status, offset: 0x20008 */ 292 __IO uint32_t CH8_SBR; /**< Channel System Bus, offset: 0x2000C */ 293 __IO uint32_t CH8_PRI; /**< Channel Priority, offset: 0x20010 */ 294 uint8_t RESERVED_16[12]; 295 __IO uint32_t TCD8_SADDR; /**< TCD Source Address, offset: 0x20020 */ 296 __IO uint16_t TCD8_SOFF; /**< TCD Signed Source Address Offset, offset: 0x20024 */ 297 __IO uint16_t TCD8_ATTR; /**< TCD Transfer Attributes, offset: 0x20026 */ 298 union { /* offset: 0x20028 */ 299 __IO uint32_t TCD8_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x20028 */ 300 __IO uint32_t TCD8_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x20028 */ 301 } NBYTES8; 302 __IO uint32_t TCD8_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x2002C */ 303 __IO uint32_t TCD8_DADDR; /**< TCD Destination Address, offset: 0x20030 */ 304 __IO uint16_t TCD8_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x20034 */ 305 union { /* offset: 0x20036 */ 306 __IO uint16_t TCD8_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x20036 */ 307 __IO uint16_t TCD8_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x20036 */ 308 } CITER8; 309 __IO uint32_t TCD8_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x20038 */ 310 __IO uint16_t TCD8_CSR; /**< TCD Control and Status, offset: 0x2003C */ 311 union { /* offset: 0x2003E */ 312 __IO uint16_t TCD8_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x2003E */ 313 __IO uint16_t TCD8_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x2003E */ 314 } BITER8; 315 uint8_t RESERVED_17[16320]; 316 __IO uint32_t CH9_CSR; /**< Channel Control and Status, offset: 0x24000 */ 317 __IO uint32_t CH9_ES; /**< Channel Error Status, offset: 0x24004 */ 318 __IO uint32_t CH9_INT; /**< Channel Interrupt Status, offset: 0x24008 */ 319 __IO uint32_t CH9_SBR; /**< Channel System Bus, offset: 0x2400C */ 320 __IO uint32_t CH9_PRI; /**< Channel Priority, offset: 0x24010 */ 321 uint8_t RESERVED_18[12]; 322 __IO uint32_t TCD9_SADDR; /**< TCD Source Address, offset: 0x24020 */ 323 __IO uint16_t TCD9_SOFF; /**< TCD Signed Source Address Offset, offset: 0x24024 */ 324 __IO uint16_t TCD9_ATTR; /**< TCD Transfer Attributes, offset: 0x24026 */ 325 union { /* offset: 0x24028 */ 326 __IO uint32_t TCD9_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x24028 */ 327 __IO uint32_t TCD9_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x24028 */ 328 } NBYTES9; 329 __IO uint32_t TCD9_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x2402C */ 330 __IO uint32_t TCD9_DADDR; /**< TCD Destination Address, offset: 0x24030 */ 331 __IO uint16_t TCD9_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x24034 */ 332 union { /* offset: 0x24036 */ 333 __IO uint16_t TCD9_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x24036 */ 334 __IO uint16_t TCD9_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x24036 */ 335 } CITER9; 336 __IO uint32_t TCD9_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x24038 */ 337 __IO uint16_t TCD9_CSR; /**< TCD Control and Status, offset: 0x2403C */ 338 union { /* offset: 0x2403E */ 339 __IO uint16_t TCD9_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x2403E */ 340 __IO uint16_t TCD9_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x2403E */ 341 } BITER9; 342 uint8_t RESERVED_19[16320]; 343 __IO uint32_t CH10_CSR; /**< Channel Control and Status, offset: 0x28000 */ 344 __IO uint32_t CH10_ES; /**< Channel Error Status, offset: 0x28004 */ 345 __IO uint32_t CH10_INT; /**< Channel Interrupt Status, offset: 0x28008 */ 346 __IO uint32_t CH10_SBR; /**< Channel System Bus, offset: 0x2800C */ 347 __IO uint32_t CH10_PRI; /**< Channel Priority, offset: 0x28010 */ 348 uint8_t RESERVED_20[12]; 349 __IO uint32_t TCD10_SADDR; /**< TCD Source Address, offset: 0x28020 */ 350 __IO uint16_t TCD10_SOFF; /**< TCD Signed Source Address Offset, offset: 0x28024 */ 351 __IO uint16_t TCD10_ATTR; /**< TCD Transfer Attributes, offset: 0x28026 */ 352 union { /* offset: 0x28028 */ 353 __IO uint32_t TCD10_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x28028 */ 354 __IO uint32_t TCD10_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x28028 */ 355 } NBYTES10; 356 __IO uint32_t TCD10_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x2802C */ 357 __IO uint32_t TCD10_DADDR; /**< TCD Destination Address, offset: 0x28030 */ 358 __IO uint16_t TCD10_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x28034 */ 359 union { /* offset: 0x28036 */ 360 __IO uint16_t TCD10_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x28036 */ 361 __IO uint16_t TCD10_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x28036 */ 362 } CITER10; 363 __IO uint32_t TCD10_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x28038 */ 364 __IO uint16_t TCD10_CSR; /**< TCD Control and Status, offset: 0x2803C */ 365 union { /* offset: 0x2803E */ 366 __IO uint16_t TCD10_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x2803E */ 367 __IO uint16_t TCD10_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x2803E */ 368 } BITER10; 369 uint8_t RESERVED_21[16320]; 370 __IO uint32_t CH11_CSR; /**< Channel Control and Status, offset: 0x2C000 */ 371 __IO uint32_t CH11_ES; /**< Channel Error Status, offset: 0x2C004 */ 372 __IO uint32_t CH11_INT; /**< Channel Interrupt Status, offset: 0x2C008 */ 373 __IO uint32_t CH11_SBR; /**< Channel System Bus, offset: 0x2C00C */ 374 __IO uint32_t CH11_PRI; /**< Channel Priority, offset: 0x2C010 */ 375 uint8_t RESERVED_22[12]; 376 __IO uint32_t TCD11_SADDR; /**< TCD Source Address, offset: 0x2C020 */ 377 __IO uint16_t TCD11_SOFF; /**< TCD Signed Source Address Offset, offset: 0x2C024 */ 378 __IO uint16_t TCD11_ATTR; /**< TCD Transfer Attributes, offset: 0x2C026 */ 379 union { /* offset: 0x2C028 */ 380 __IO uint32_t TCD11_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x2C028 */ 381 __IO uint32_t TCD11_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x2C028 */ 382 } NBYTES11; 383 __IO uint32_t TCD11_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x2C02C */ 384 __IO uint32_t TCD11_DADDR; /**< TCD Destination Address, offset: 0x2C030 */ 385 __IO uint16_t TCD11_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x2C034 */ 386 union { /* offset: 0x2C036 */ 387 __IO uint16_t TCD11_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x2C036 */ 388 __IO uint16_t TCD11_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x2C036 */ 389 } CITER11; 390 __IO uint32_t TCD11_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x2C038 */ 391 __IO uint16_t TCD11_CSR; /**< TCD Control and Status, offset: 0x2C03C */ 392 union { /* offset: 0x2C03E */ 393 __IO uint16_t TCD11_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x2C03E */ 394 __IO uint16_t TCD11_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x2C03E */ 395 } BITER11; 396 uint8_t RESERVED_23[1916864]; 397 __IO uint32_t CH12_CSR; /**< Channel Control and Status, offset: 0x200000 */ 398 __IO uint32_t CH12_ES; /**< Channel Error Status, offset: 0x200004 */ 399 __IO uint32_t CH12_INT; /**< Channel Interrupt Status, offset: 0x200008 */ 400 __IO uint32_t CH12_SBR; /**< Channel System Bus, offset: 0x20000C */ 401 __IO uint32_t CH12_PRI; /**< Channel Priority, offset: 0x200010 */ 402 uint8_t RESERVED_24[12]; 403 __IO uint32_t TCD12_SADDR; /**< TCD Source Address, offset: 0x200020 */ 404 __IO uint16_t TCD12_SOFF; /**< TCD Signed Source Address Offset, offset: 0x200024 */ 405 __IO uint16_t TCD12_ATTR; /**< TCD Transfer Attributes, offset: 0x200026 */ 406 union { /* offset: 0x200028 */ 407 __IO uint32_t TCD12_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x200028 */ 408 __IO uint32_t TCD12_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x200028 */ 409 } NBYTES12; 410 __IO uint32_t TCD12_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x20002C */ 411 __IO uint32_t TCD12_DADDR; /**< TCD Destination Address, offset: 0x200030 */ 412 __IO uint16_t TCD12_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x200034 */ 413 union { /* offset: 0x200036 */ 414 __IO uint16_t TCD12_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x200036 */ 415 __IO uint16_t TCD12_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x200036 */ 416 } CITER12; 417 __IO uint32_t TCD12_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x200038 */ 418 __IO uint16_t TCD12_CSR; /**< TCD Control and Status, offset: 0x20003C */ 419 union { /* offset: 0x20003E */ 420 __IO uint16_t TCD12_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x20003E */ 421 __IO uint16_t TCD12_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x20003E */ 422 } BITER12; 423 uint8_t RESERVED_25[16320]; 424 __IO uint32_t CH13_CSR; /**< Channel Control and Status, offset: 0x204000 */ 425 __IO uint32_t CH13_ES; /**< Channel Error Status, offset: 0x204004 */ 426 __IO uint32_t CH13_INT; /**< Channel Interrupt Status, offset: 0x204008 */ 427 __IO uint32_t CH13_SBR; /**< Channel System Bus, offset: 0x20400C */ 428 __IO uint32_t CH13_PRI; /**< Channel Priority, offset: 0x204010 */ 429 uint8_t RESERVED_26[12]; 430 __IO uint32_t TCD13_SADDR; /**< TCD Source Address, offset: 0x204020 */ 431 __IO uint16_t TCD13_SOFF; /**< TCD Signed Source Address Offset, offset: 0x204024 */ 432 __IO uint16_t TCD13_ATTR; /**< TCD Transfer Attributes, offset: 0x204026 */ 433 union { /* offset: 0x204028 */ 434 __IO uint32_t TCD13_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x204028 */ 435 __IO uint32_t TCD13_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x204028 */ 436 } NBYTES13; 437 __IO uint32_t TCD13_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x20402C */ 438 __IO uint32_t TCD13_DADDR; /**< TCD Destination Address, offset: 0x204030 */ 439 __IO uint16_t TCD13_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x204034 */ 440 union { /* offset: 0x204036 */ 441 __IO uint16_t TCD13_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x204036 */ 442 __IO uint16_t TCD13_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x204036 */ 443 } CITER13; 444 __IO uint32_t TCD13_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x204038 */ 445 __IO uint16_t TCD13_CSR; /**< TCD Control and Status, offset: 0x20403C */ 446 union { /* offset: 0x20403E */ 447 __IO uint16_t TCD13_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x20403E */ 448 __IO uint16_t TCD13_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x20403E */ 449 } BITER13; 450 uint8_t RESERVED_27[16320]; 451 __IO uint32_t CH14_CSR; /**< Channel Control and Status, offset: 0x208000 */ 452 __IO uint32_t CH14_ES; /**< Channel Error Status, offset: 0x208004 */ 453 __IO uint32_t CH14_INT; /**< Channel Interrupt Status, offset: 0x208008 */ 454 __IO uint32_t CH14_SBR; /**< Channel System Bus, offset: 0x20800C */ 455 __IO uint32_t CH14_PRI; /**< Channel Priority, offset: 0x208010 */ 456 uint8_t RESERVED_28[12]; 457 __IO uint32_t TCD14_SADDR; /**< TCD Source Address, offset: 0x208020 */ 458 __IO uint16_t TCD14_SOFF; /**< TCD Signed Source Address Offset, offset: 0x208024 */ 459 __IO uint16_t TCD14_ATTR; /**< TCD Transfer Attributes, offset: 0x208026 */ 460 union { /* offset: 0x208028 */ 461 __IO uint32_t TCD14_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x208028 */ 462 __IO uint32_t TCD14_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x208028 */ 463 } NBYTES14; 464 __IO uint32_t TCD14_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x20802C */ 465 __IO uint32_t TCD14_DADDR; /**< TCD Destination Address, offset: 0x208030 */ 466 __IO uint16_t TCD14_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x208034 */ 467 union { /* offset: 0x208036 */ 468 __IO uint16_t TCD14_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x208036 */ 469 __IO uint16_t TCD14_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x208036 */ 470 } CITER14; 471 __IO uint32_t TCD14_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x208038 */ 472 __IO uint16_t TCD14_CSR; /**< TCD Control and Status, offset: 0x20803C */ 473 union { /* offset: 0x20803E */ 474 __IO uint16_t TCD14_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x20803E */ 475 __IO uint16_t TCD14_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x20803E */ 476 } BITER14; 477 uint8_t RESERVED_29[16320]; 478 __IO uint32_t CH15_CSR; /**< Channel Control and Status, offset: 0x20C000 */ 479 __IO uint32_t CH15_ES; /**< Channel Error Status, offset: 0x20C004 */ 480 __IO uint32_t CH15_INT; /**< Channel Interrupt Status, offset: 0x20C008 */ 481 __IO uint32_t CH15_SBR; /**< Channel System Bus, offset: 0x20C00C */ 482 __IO uint32_t CH15_PRI; /**< Channel Priority, offset: 0x20C010 */ 483 uint8_t RESERVED_30[12]; 484 __IO uint32_t TCD15_SADDR; /**< TCD Source Address, offset: 0x20C020 */ 485 __IO uint16_t TCD15_SOFF; /**< TCD Signed Source Address Offset, offset: 0x20C024 */ 486 __IO uint16_t TCD15_ATTR; /**< TCD Transfer Attributes, offset: 0x20C026 */ 487 union { /* offset: 0x20C028 */ 488 __IO uint32_t TCD15_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x20C028 */ 489 __IO uint32_t TCD15_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x20C028 */ 490 } NBYTES15; 491 __IO uint32_t TCD15_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x20C02C */ 492 __IO uint32_t TCD15_DADDR; /**< TCD Destination Address, offset: 0x20C030 */ 493 __IO uint16_t TCD15_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x20C034 */ 494 union { /* offset: 0x20C036 */ 495 __IO uint16_t TCD15_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x20C036 */ 496 __IO uint16_t TCD15_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x20C036 */ 497 } CITER15; 498 __IO uint32_t TCD15_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x20C038 */ 499 __IO uint16_t TCD15_CSR; /**< TCD Control and Status, offset: 0x20C03C */ 500 union { /* offset: 0x20C03E */ 501 __IO uint16_t TCD15_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x20C03E */ 502 __IO uint16_t TCD15_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x20C03E */ 503 } BITER15; 504 uint8_t RESERVED_31[16320]; 505 __IO uint32_t CH16_CSR; /**< Channel Control and Status, offset: 0x210000 */ 506 __IO uint32_t CH16_ES; /**< Channel Error Status, offset: 0x210004 */ 507 __IO uint32_t CH16_INT; /**< Channel Interrupt Status, offset: 0x210008 */ 508 __IO uint32_t CH16_SBR; /**< Channel System Bus, offset: 0x21000C */ 509 __IO uint32_t CH16_PRI; /**< Channel Priority, offset: 0x210010 */ 510 uint8_t RESERVED_32[12]; 511 __IO uint32_t TCD16_SADDR; /**< TCD Source Address, offset: 0x210020 */ 512 __IO uint16_t TCD16_SOFF; /**< TCD Signed Source Address Offset, offset: 0x210024 */ 513 __IO uint16_t TCD16_ATTR; /**< TCD Transfer Attributes, offset: 0x210026 */ 514 union { /* offset: 0x210028 */ 515 __IO uint32_t TCD16_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x210028 */ 516 __IO uint32_t TCD16_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x210028 */ 517 } NBYTES16; 518 __IO uint32_t TCD16_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x21002C */ 519 __IO uint32_t TCD16_DADDR; /**< TCD Destination Address, offset: 0x210030 */ 520 __IO uint16_t TCD16_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x210034 */ 521 union { /* offset: 0x210036 */ 522 __IO uint16_t TCD16_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x210036 */ 523 __IO uint16_t TCD16_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x210036 */ 524 } CITER16; 525 __IO uint32_t TCD16_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x210038 */ 526 __IO uint16_t TCD16_CSR; /**< TCD Control and Status, offset: 0x21003C */ 527 union { /* offset: 0x21003E */ 528 __IO uint16_t TCD16_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x21003E */ 529 __IO uint16_t TCD16_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x21003E */ 530 } BITER16; 531 uint8_t RESERVED_33[16320]; 532 __IO uint32_t CH17_CSR; /**< Channel Control and Status, offset: 0x214000 */ 533 __IO uint32_t CH17_ES; /**< Channel Error Status, offset: 0x214004 */ 534 __IO uint32_t CH17_INT; /**< Channel Interrupt Status, offset: 0x214008 */ 535 __IO uint32_t CH17_SBR; /**< Channel System Bus, offset: 0x21400C */ 536 __IO uint32_t CH17_PRI; /**< Channel Priority, offset: 0x214010 */ 537 uint8_t RESERVED_34[12]; 538 __IO uint32_t TCD17_SADDR; /**< TCD Source Address, offset: 0x214020 */ 539 __IO uint16_t TCD17_SOFF; /**< TCD Signed Source Address Offset, offset: 0x214024 */ 540 __IO uint16_t TCD17_ATTR; /**< TCD Transfer Attributes, offset: 0x214026 */ 541 union { /* offset: 0x214028 */ 542 __IO uint32_t TCD17_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x214028 */ 543 __IO uint32_t TCD17_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x214028 */ 544 } NBYTES17; 545 __IO uint32_t TCD17_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x21402C */ 546 __IO uint32_t TCD17_DADDR; /**< TCD Destination Address, offset: 0x214030 */ 547 __IO uint16_t TCD17_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x214034 */ 548 union { /* offset: 0x214036 */ 549 __IO uint16_t TCD17_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x214036 */ 550 __IO uint16_t TCD17_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x214036 */ 551 } CITER17; 552 __IO uint32_t TCD17_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x214038 */ 553 __IO uint16_t TCD17_CSR; /**< TCD Control and Status, offset: 0x21403C */ 554 union { /* offset: 0x21403E */ 555 __IO uint16_t TCD17_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x21403E */ 556 __IO uint16_t TCD17_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x21403E */ 557 } BITER17; 558 uint8_t RESERVED_35[16320]; 559 __IO uint32_t CH18_CSR; /**< Channel Control and Status, offset: 0x218000 */ 560 __IO uint32_t CH18_ES; /**< Channel Error Status, offset: 0x218004 */ 561 __IO uint32_t CH18_INT; /**< Channel Interrupt Status, offset: 0x218008 */ 562 __IO uint32_t CH18_SBR; /**< Channel System Bus, offset: 0x21800C */ 563 __IO uint32_t CH18_PRI; /**< Channel Priority, offset: 0x218010 */ 564 uint8_t RESERVED_36[12]; 565 __IO uint32_t TCD18_SADDR; /**< TCD Source Address, offset: 0x218020 */ 566 __IO uint16_t TCD18_SOFF; /**< TCD Signed Source Address Offset, offset: 0x218024 */ 567 __IO uint16_t TCD18_ATTR; /**< TCD Transfer Attributes, offset: 0x218026 */ 568 union { /* offset: 0x218028 */ 569 __IO uint32_t TCD18_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x218028 */ 570 __IO uint32_t TCD18_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x218028 */ 571 } NBYTES18; 572 __IO uint32_t TCD18_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x21802C */ 573 __IO uint32_t TCD18_DADDR; /**< TCD Destination Address, offset: 0x218030 */ 574 __IO uint16_t TCD18_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x218034 */ 575 union { /* offset: 0x218036 */ 576 __IO uint16_t TCD18_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x218036 */ 577 __IO uint16_t TCD18_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x218036 */ 578 } CITER18; 579 __IO uint32_t TCD18_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x218038 */ 580 __IO uint16_t TCD18_CSR; /**< TCD Control and Status, offset: 0x21803C */ 581 union { /* offset: 0x21803E */ 582 __IO uint16_t TCD18_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x21803E */ 583 __IO uint16_t TCD18_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x21803E */ 584 } BITER18; 585 uint8_t RESERVED_37[16320]; 586 __IO uint32_t CH19_CSR; /**< Channel Control and Status, offset: 0x21C000 */ 587 __IO uint32_t CH19_ES; /**< Channel Error Status, offset: 0x21C004 */ 588 __IO uint32_t CH19_INT; /**< Channel Interrupt Status, offset: 0x21C008 */ 589 __IO uint32_t CH19_SBR; /**< Channel System Bus, offset: 0x21C00C */ 590 __IO uint32_t CH19_PRI; /**< Channel Priority, offset: 0x21C010 */ 591 uint8_t RESERVED_38[12]; 592 __IO uint32_t TCD19_SADDR; /**< TCD Source Address, offset: 0x21C020 */ 593 __IO uint16_t TCD19_SOFF; /**< TCD Signed Source Address Offset, offset: 0x21C024 */ 594 __IO uint16_t TCD19_ATTR; /**< TCD Transfer Attributes, offset: 0x21C026 */ 595 union { /* offset: 0x21C028 */ 596 __IO uint32_t TCD19_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x21C028 */ 597 __IO uint32_t TCD19_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x21C028 */ 598 } NBYTES19; 599 __IO uint32_t TCD19_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x21C02C */ 600 __IO uint32_t TCD19_DADDR; /**< TCD Destination Address, offset: 0x21C030 */ 601 __IO uint16_t TCD19_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x21C034 */ 602 union { /* offset: 0x21C036 */ 603 __IO uint16_t TCD19_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x21C036 */ 604 __IO uint16_t TCD19_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x21C036 */ 605 } CITER19; 606 __IO uint32_t TCD19_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x21C038 */ 607 __IO uint16_t TCD19_CSR; /**< TCD Control and Status, offset: 0x21C03C */ 608 union { /* offset: 0x21C03E */ 609 __IO uint16_t TCD19_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x21C03E */ 610 __IO uint16_t TCD19_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x21C03E */ 611 } BITER19; 612 uint8_t RESERVED_39[16320]; 613 __IO uint32_t CH20_CSR; /**< Channel Control and Status, offset: 0x220000 */ 614 __IO uint32_t CH20_ES; /**< Channel Error Status, offset: 0x220004 */ 615 __IO uint32_t CH20_INT; /**< Channel Interrupt Status, offset: 0x220008 */ 616 __IO uint32_t CH20_SBR; /**< Channel System Bus, offset: 0x22000C */ 617 __IO uint32_t CH20_PRI; /**< Channel Priority, offset: 0x220010 */ 618 uint8_t RESERVED_40[12]; 619 __IO uint32_t TCD20_SADDR; /**< TCD Source Address, offset: 0x220020 */ 620 __IO uint16_t TCD20_SOFF; /**< TCD Signed Source Address Offset, offset: 0x220024 */ 621 __IO uint16_t TCD20_ATTR; /**< TCD Transfer Attributes, offset: 0x220026 */ 622 union { /* offset: 0x220028 */ 623 __IO uint32_t TCD20_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x220028 */ 624 __IO uint32_t TCD20_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x220028 */ 625 } NBYTES20; 626 __IO uint32_t TCD20_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x22002C */ 627 __IO uint32_t TCD20_DADDR; /**< TCD Destination Address, offset: 0x220030 */ 628 __IO uint16_t TCD20_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x220034 */ 629 union { /* offset: 0x220036 */ 630 __IO uint16_t TCD20_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x220036 */ 631 __IO uint16_t TCD20_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x220036 */ 632 } CITER20; 633 __IO uint32_t TCD20_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x220038 */ 634 __IO uint16_t TCD20_CSR; /**< TCD Control and Status, offset: 0x22003C */ 635 union { /* offset: 0x22003E */ 636 __IO uint16_t TCD20_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x22003E */ 637 __IO uint16_t TCD20_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x22003E */ 638 } BITER20; 639 uint8_t RESERVED_41[16320]; 640 __IO uint32_t CH21_CSR; /**< Channel Control and Status, offset: 0x224000 */ 641 __IO uint32_t CH21_ES; /**< Channel Error Status, offset: 0x224004 */ 642 __IO uint32_t CH21_INT; /**< Channel Interrupt Status, offset: 0x224008 */ 643 __IO uint32_t CH21_SBR; /**< Channel System Bus, offset: 0x22400C */ 644 __IO uint32_t CH21_PRI; /**< Channel Priority, offset: 0x224010 */ 645 uint8_t RESERVED_42[12]; 646 __IO uint32_t TCD21_SADDR; /**< TCD Source Address, offset: 0x224020 */ 647 __IO uint16_t TCD21_SOFF; /**< TCD Signed Source Address Offset, offset: 0x224024 */ 648 __IO uint16_t TCD21_ATTR; /**< TCD Transfer Attributes, offset: 0x224026 */ 649 union { /* offset: 0x224028 */ 650 __IO uint32_t TCD21_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x224028 */ 651 __IO uint32_t TCD21_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x224028 */ 652 } NBYTES21; 653 __IO uint32_t TCD21_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x22402C */ 654 __IO uint32_t TCD21_DADDR; /**< TCD Destination Address, offset: 0x224030 */ 655 __IO uint16_t TCD21_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x224034 */ 656 union { /* offset: 0x224036 */ 657 __IO uint16_t TCD21_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x224036 */ 658 __IO uint16_t TCD21_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x224036 */ 659 } CITER21; 660 __IO uint32_t TCD21_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x224038 */ 661 __IO uint16_t TCD21_CSR; /**< TCD Control and Status, offset: 0x22403C */ 662 union { /* offset: 0x22403E */ 663 __IO uint16_t TCD21_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x22403E */ 664 __IO uint16_t TCD21_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x22403E */ 665 } BITER21; 666 uint8_t RESERVED_43[16320]; 667 __IO uint32_t CH22_CSR; /**< Channel Control and Status, offset: 0x228000 */ 668 __IO uint32_t CH22_ES; /**< Channel Error Status, offset: 0x228004 */ 669 __IO uint32_t CH22_INT; /**< Channel Interrupt Status, offset: 0x228008 */ 670 __IO uint32_t CH22_SBR; /**< Channel System Bus, offset: 0x22800C */ 671 __IO uint32_t CH22_PRI; /**< Channel Priority, offset: 0x228010 */ 672 uint8_t RESERVED_44[12]; 673 __IO uint32_t TCD22_SADDR; /**< TCD Source Address, offset: 0x228020 */ 674 __IO uint16_t TCD22_SOFF; /**< TCD Signed Source Address Offset, offset: 0x228024 */ 675 __IO uint16_t TCD22_ATTR; /**< TCD Transfer Attributes, offset: 0x228026 */ 676 union { /* offset: 0x228028 */ 677 __IO uint32_t TCD22_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x228028 */ 678 __IO uint32_t TCD22_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x228028 */ 679 } NBYTES22; 680 __IO uint32_t TCD22_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x22802C */ 681 __IO uint32_t TCD22_DADDR; /**< TCD Destination Address, offset: 0x228030 */ 682 __IO uint16_t TCD22_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x228034 */ 683 union { /* offset: 0x228036 */ 684 __IO uint16_t TCD22_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x228036 */ 685 __IO uint16_t TCD22_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x228036 */ 686 } CITER22; 687 __IO uint32_t TCD22_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x228038 */ 688 __IO uint16_t TCD22_CSR; /**< TCD Control and Status, offset: 0x22803C */ 689 union { /* offset: 0x22803E */ 690 __IO uint16_t TCD22_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x22803E */ 691 __IO uint16_t TCD22_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x22803E */ 692 } BITER22; 693 uint8_t RESERVED_45[16320]; 694 __IO uint32_t CH23_CSR; /**< Channel Control and Status, offset: 0x22C000 */ 695 __IO uint32_t CH23_ES; /**< Channel Error Status, offset: 0x22C004 */ 696 __IO uint32_t CH23_INT; /**< Channel Interrupt Status, offset: 0x22C008 */ 697 __IO uint32_t CH23_SBR; /**< Channel System Bus, offset: 0x22C00C */ 698 __IO uint32_t CH23_PRI; /**< Channel Priority, offset: 0x22C010 */ 699 uint8_t RESERVED_46[12]; 700 __IO uint32_t TCD23_SADDR; /**< TCD Source Address, offset: 0x22C020 */ 701 __IO uint16_t TCD23_SOFF; /**< TCD Signed Source Address Offset, offset: 0x22C024 */ 702 __IO uint16_t TCD23_ATTR; /**< TCD Transfer Attributes, offset: 0x22C026 */ 703 union { /* offset: 0x22C028 */ 704 __IO uint32_t TCD23_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x22C028 */ 705 __IO uint32_t TCD23_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x22C028 */ 706 } NBYTES23; 707 __IO uint32_t TCD23_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x22C02C */ 708 __IO uint32_t TCD23_DADDR; /**< TCD Destination Address, offset: 0x22C030 */ 709 __IO uint16_t TCD23_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x22C034 */ 710 union { /* offset: 0x22C036 */ 711 __IO uint16_t TCD23_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x22C036 */ 712 __IO uint16_t TCD23_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x22C036 */ 713 } CITER23; 714 __IO uint32_t TCD23_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x22C038 */ 715 __IO uint16_t TCD23_CSR; /**< TCD Control and Status, offset: 0x22C03C */ 716 union { /* offset: 0x22C03E */ 717 __IO uint16_t TCD23_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x22C03E */ 718 __IO uint16_t TCD23_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x22C03E */ 719 } BITER23; 720 uint8_t RESERVED_47[16320]; 721 __IO uint32_t CH24_CSR; /**< Channel Control and Status, offset: 0x230000 */ 722 __IO uint32_t CH24_ES; /**< Channel Error Status, offset: 0x230004 */ 723 __IO uint32_t CH24_INT; /**< Channel Interrupt Status, offset: 0x230008 */ 724 __IO uint32_t CH24_SBR; /**< Channel System Bus, offset: 0x23000C */ 725 __IO uint32_t CH24_PRI; /**< Channel Priority, offset: 0x230010 */ 726 uint8_t RESERVED_48[12]; 727 __IO uint32_t TCD24_SADDR; /**< TCD Source Address, offset: 0x230020 */ 728 __IO uint16_t TCD24_SOFF; /**< TCD Signed Source Address Offset, offset: 0x230024 */ 729 __IO uint16_t TCD24_ATTR; /**< TCD Transfer Attributes, offset: 0x230026 */ 730 union { /* offset: 0x230028 */ 731 __IO uint32_t TCD24_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x230028 */ 732 __IO uint32_t TCD24_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x230028 */ 733 } NBYTES24; 734 __IO uint32_t TCD24_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x23002C */ 735 __IO uint32_t TCD24_DADDR; /**< TCD Destination Address, offset: 0x230030 */ 736 __IO uint16_t TCD24_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x230034 */ 737 union { /* offset: 0x230036 */ 738 __IO uint16_t TCD24_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x230036 */ 739 __IO uint16_t TCD24_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x230036 */ 740 } CITER24; 741 __IO uint32_t TCD24_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x230038 */ 742 __IO uint16_t TCD24_CSR; /**< TCD Control and Status, offset: 0x23003C */ 743 union { /* offset: 0x23003E */ 744 __IO uint16_t TCD24_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x23003E */ 745 __IO uint16_t TCD24_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x23003E */ 746 } BITER24; 747 uint8_t RESERVED_49[16320]; 748 __IO uint32_t CH25_CSR; /**< Channel Control and Status, offset: 0x234000 */ 749 __IO uint32_t CH25_ES; /**< Channel Error Status, offset: 0x234004 */ 750 __IO uint32_t CH25_INT; /**< Channel Interrupt Status, offset: 0x234008 */ 751 __IO uint32_t CH25_SBR; /**< Channel System Bus, offset: 0x23400C */ 752 __IO uint32_t CH25_PRI; /**< Channel Priority, offset: 0x234010 */ 753 uint8_t RESERVED_50[12]; 754 __IO uint32_t TCD25_SADDR; /**< TCD Source Address, offset: 0x234020 */ 755 __IO uint16_t TCD25_SOFF; /**< TCD Signed Source Address Offset, offset: 0x234024 */ 756 __IO uint16_t TCD25_ATTR; /**< TCD Transfer Attributes, offset: 0x234026 */ 757 union { /* offset: 0x234028 */ 758 __IO uint32_t TCD25_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x234028 */ 759 __IO uint32_t TCD25_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x234028 */ 760 } NBYTES25; 761 __IO uint32_t TCD25_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x23402C */ 762 __IO uint32_t TCD25_DADDR; /**< TCD Destination Address, offset: 0x234030 */ 763 __IO uint16_t TCD25_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x234034 */ 764 union { /* offset: 0x234036 */ 765 __IO uint16_t TCD25_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x234036 */ 766 __IO uint16_t TCD25_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x234036 */ 767 } CITER25; 768 __IO uint32_t TCD25_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x234038 */ 769 __IO uint16_t TCD25_CSR; /**< TCD Control and Status, offset: 0x23403C */ 770 union { /* offset: 0x23403E */ 771 __IO uint16_t TCD25_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x23403E */ 772 __IO uint16_t TCD25_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x23403E */ 773 } BITER25; 774 uint8_t RESERVED_51[16320]; 775 __IO uint32_t CH26_CSR; /**< Channel Control and Status, offset: 0x238000 */ 776 __IO uint32_t CH26_ES; /**< Channel Error Status, offset: 0x238004 */ 777 __IO uint32_t CH26_INT; /**< Channel Interrupt Status, offset: 0x238008 */ 778 __IO uint32_t CH26_SBR; /**< Channel System Bus, offset: 0x23800C */ 779 __IO uint32_t CH26_PRI; /**< Channel Priority, offset: 0x238010 */ 780 uint8_t RESERVED_52[12]; 781 __IO uint32_t TCD26_SADDR; /**< TCD Source Address, offset: 0x238020 */ 782 __IO uint16_t TCD26_SOFF; /**< TCD Signed Source Address Offset, offset: 0x238024 */ 783 __IO uint16_t TCD26_ATTR; /**< TCD Transfer Attributes, offset: 0x238026 */ 784 union { /* offset: 0x238028 */ 785 __IO uint32_t TCD26_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x238028 */ 786 __IO uint32_t TCD26_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x238028 */ 787 } NBYTES26; 788 __IO uint32_t TCD26_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x23802C */ 789 __IO uint32_t TCD26_DADDR; /**< TCD Destination Address, offset: 0x238030 */ 790 __IO uint16_t TCD26_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x238034 */ 791 union { /* offset: 0x238036 */ 792 __IO uint16_t TCD26_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x238036 */ 793 __IO uint16_t TCD26_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x238036 */ 794 } CITER26; 795 __IO uint32_t TCD26_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x238038 */ 796 __IO uint16_t TCD26_CSR; /**< TCD Control and Status, offset: 0x23803C */ 797 union { /* offset: 0x23803E */ 798 __IO uint16_t TCD26_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x23803E */ 799 __IO uint16_t TCD26_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x23803E */ 800 } BITER26; 801 uint8_t RESERVED_53[16320]; 802 __IO uint32_t CH27_CSR; /**< Channel Control and Status, offset: 0x23C000 */ 803 __IO uint32_t CH27_ES; /**< Channel Error Status, offset: 0x23C004 */ 804 __IO uint32_t CH27_INT; /**< Channel Interrupt Status, offset: 0x23C008 */ 805 __IO uint32_t CH27_SBR; /**< Channel System Bus, offset: 0x23C00C */ 806 __IO uint32_t CH27_PRI; /**< Channel Priority, offset: 0x23C010 */ 807 uint8_t RESERVED_54[12]; 808 __IO uint32_t TCD27_SADDR; /**< TCD Source Address, offset: 0x23C020 */ 809 __IO uint16_t TCD27_SOFF; /**< TCD Signed Source Address Offset, offset: 0x23C024 */ 810 __IO uint16_t TCD27_ATTR; /**< TCD Transfer Attributes, offset: 0x23C026 */ 811 union { /* offset: 0x23C028 */ 812 __IO uint32_t TCD27_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x23C028 */ 813 __IO uint32_t TCD27_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x23C028 */ 814 } NBYTES27; 815 __IO uint32_t TCD27_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x23C02C */ 816 __IO uint32_t TCD27_DADDR; /**< TCD Destination Address, offset: 0x23C030 */ 817 __IO uint16_t TCD27_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x23C034 */ 818 union { /* offset: 0x23C036 */ 819 __IO uint16_t TCD27_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x23C036 */ 820 __IO uint16_t TCD27_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x23C036 */ 821 } CITER27; 822 __IO uint32_t TCD27_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x23C038 */ 823 __IO uint16_t TCD27_CSR; /**< TCD Control and Status, offset: 0x23C03C */ 824 union { /* offset: 0x23C03E */ 825 __IO uint16_t TCD27_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x23C03E */ 826 __IO uint16_t TCD27_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x23C03E */ 827 } BITER27; 828 uint8_t RESERVED_55[16320]; 829 __IO uint32_t CH28_CSR; /**< Channel Control and Status, offset: 0x240000 */ 830 __IO uint32_t CH28_ES; /**< Channel Error Status, offset: 0x240004 */ 831 __IO uint32_t CH28_INT; /**< Channel Interrupt Status, offset: 0x240008 */ 832 __IO uint32_t CH28_SBR; /**< Channel System Bus, offset: 0x24000C */ 833 __IO uint32_t CH28_PRI; /**< Channel Priority, offset: 0x240010 */ 834 uint8_t RESERVED_56[12]; 835 __IO uint32_t TCD28_SADDR; /**< TCD Source Address, offset: 0x240020 */ 836 __IO uint16_t TCD28_SOFF; /**< TCD Signed Source Address Offset, offset: 0x240024 */ 837 __IO uint16_t TCD28_ATTR; /**< TCD Transfer Attributes, offset: 0x240026 */ 838 union { /* offset: 0x240028 */ 839 __IO uint32_t TCD28_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x240028 */ 840 __IO uint32_t TCD28_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x240028 */ 841 } NBYTES28; 842 __IO uint32_t TCD28_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x24002C */ 843 __IO uint32_t TCD28_DADDR; /**< TCD Destination Address, offset: 0x240030 */ 844 __IO uint16_t TCD28_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x240034 */ 845 union { /* offset: 0x240036 */ 846 __IO uint16_t TCD28_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x240036 */ 847 __IO uint16_t TCD28_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x240036 */ 848 } CITER28; 849 __IO uint32_t TCD28_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x240038 */ 850 __IO uint16_t TCD28_CSR; /**< TCD Control and Status, offset: 0x24003C */ 851 union { /* offset: 0x24003E */ 852 __IO uint16_t TCD28_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x24003E */ 853 __IO uint16_t TCD28_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x24003E */ 854 } BITER28; 855 uint8_t RESERVED_57[16320]; 856 __IO uint32_t CH29_CSR; /**< Channel Control and Status, offset: 0x244000 */ 857 __IO uint32_t CH29_ES; /**< Channel Error Status, offset: 0x244004 */ 858 __IO uint32_t CH29_INT; /**< Channel Interrupt Status, offset: 0x244008 */ 859 __IO uint32_t CH29_SBR; /**< Channel System Bus, offset: 0x24400C */ 860 __IO uint32_t CH29_PRI; /**< Channel Priority, offset: 0x244010 */ 861 uint8_t RESERVED_58[12]; 862 __IO uint32_t TCD29_SADDR; /**< TCD Source Address, offset: 0x244020 */ 863 __IO uint16_t TCD29_SOFF; /**< TCD Signed Source Address Offset, offset: 0x244024 */ 864 __IO uint16_t TCD29_ATTR; /**< TCD Transfer Attributes, offset: 0x244026 */ 865 union { /* offset: 0x244028 */ 866 __IO uint32_t TCD29_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x244028 */ 867 __IO uint32_t TCD29_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x244028 */ 868 } NBYTES29; 869 __IO uint32_t TCD29_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x24402C */ 870 __IO uint32_t TCD29_DADDR; /**< TCD Destination Address, offset: 0x244030 */ 871 __IO uint16_t TCD29_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x244034 */ 872 union { /* offset: 0x244036 */ 873 __IO uint16_t TCD29_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x244036 */ 874 __IO uint16_t TCD29_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x244036 */ 875 } CITER29; 876 __IO uint32_t TCD29_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x244038 */ 877 __IO uint16_t TCD29_CSR; /**< TCD Control and Status, offset: 0x24403C */ 878 union { /* offset: 0x24403E */ 879 __IO uint16_t TCD29_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x24403E */ 880 __IO uint16_t TCD29_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x24403E */ 881 } BITER29; 882 uint8_t RESERVED_59[16320]; 883 __IO uint32_t CH30_CSR; /**< Channel Control and Status, offset: 0x248000 */ 884 __IO uint32_t CH30_ES; /**< Channel Error Status, offset: 0x248004 */ 885 __IO uint32_t CH30_INT; /**< Channel Interrupt Status, offset: 0x248008 */ 886 __IO uint32_t CH30_SBR; /**< Channel System Bus, offset: 0x24800C */ 887 __IO uint32_t CH30_PRI; /**< Channel Priority, offset: 0x248010 */ 888 uint8_t RESERVED_60[12]; 889 __IO uint32_t TCD30_SADDR; /**< TCD Source Address, offset: 0x248020 */ 890 __IO uint16_t TCD30_SOFF; /**< TCD Signed Source Address Offset, offset: 0x248024 */ 891 __IO uint16_t TCD30_ATTR; /**< TCD Transfer Attributes, offset: 0x248026 */ 892 union { /* offset: 0x248028 */ 893 __IO uint32_t TCD30_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x248028 */ 894 __IO uint32_t TCD30_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x248028 */ 895 } NBYTES30; 896 __IO uint32_t TCD30_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x24802C */ 897 __IO uint32_t TCD30_DADDR; /**< TCD Destination Address, offset: 0x248030 */ 898 __IO uint16_t TCD30_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x248034 */ 899 union { /* offset: 0x248036 */ 900 __IO uint16_t TCD30_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x248036 */ 901 __IO uint16_t TCD30_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x248036 */ 902 } CITER30; 903 __IO uint32_t TCD30_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x248038 */ 904 __IO uint16_t TCD30_CSR; /**< TCD Control and Status, offset: 0x24803C */ 905 union { /* offset: 0x24803E */ 906 __IO uint16_t TCD30_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x24803E */ 907 __IO uint16_t TCD30_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x24803E */ 908 } BITER30; 909 uint8_t RESERVED_61[16320]; 910 __IO uint32_t CH31_CSR; /**< Channel Control and Status, offset: 0x24C000 */ 911 __IO uint32_t CH31_ES; /**< Channel Error Status, offset: 0x24C004 */ 912 __IO uint32_t CH31_INT; /**< Channel Interrupt Status, offset: 0x24C008 */ 913 __IO uint32_t CH31_SBR; /**< Channel System Bus, offset: 0x24C00C */ 914 __IO uint32_t CH31_PRI; /**< Channel Priority, offset: 0x24C010 */ 915 uint8_t RESERVED_62[12]; 916 __IO uint32_t TCD31_SADDR; /**< TCD Source Address, offset: 0x24C020 */ 917 __IO uint16_t TCD31_SOFF; /**< TCD Signed Source Address Offset, offset: 0x24C024 */ 918 __IO uint16_t TCD31_ATTR; /**< TCD Transfer Attributes, offset: 0x24C026 */ 919 union { /* offset: 0x24C028 */ 920 __IO uint32_t TCD31_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, offset: 0x24C028 */ 921 __IO uint32_t TCD31_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, offset: 0x24C028 */ 922 } NBYTES31; 923 __IO uint32_t TCD31_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, offset: 0x24C02C */ 924 __IO uint32_t TCD31_DADDR; /**< TCD Destination Address, offset: 0x24C030 */ 925 __IO uint16_t TCD31_DOFF; /**< TCD Signed Destination Address Offset, offset: 0x24C034 */ 926 union { /* offset: 0x24C036 */ 927 __IO uint16_t TCD31_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x24C036 */ 928 __IO uint16_t TCD31_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x24C036 */ 929 } CITER31; 930 __IO uint32_t TCD31_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, offset: 0x24C038 */ 931 __IO uint16_t TCD31_CSR; /**< TCD Control and Status, offset: 0x24C03C */ 932 union { /* offset: 0x24C03E */ 933 __IO uint16_t TCD31_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), offset: 0x24C03E */ 934 __IO uint16_t TCD31_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), offset: 0x24C03E */ 935 } BITER31; 936 } DMA_TCD_Type, *DMA_TCD_MemMapPtr; 937 938 /** Number of instances of the DMA_TCD module. */ 939 #define DMA_TCD_INSTANCE_COUNT (1u) 940 941 /* DMA_TCD - Peripheral instance base addresses */ 942 /** Peripheral TCD base address */ 943 #define IP_TCD_BASE (0x40210000u) 944 /** Peripheral TCD base pointer */ 945 #define IP_TCD ((DMA_TCD_Type *)IP_TCD_BASE) 946 /** Array initializer of DMA_TCD peripheral base addresses */ 947 #define IP_DMA_TCD_BASE_ADDRS { IP_TCD_BASE } 948 /** Array initializer of DMA_TCD peripheral base pointers */ 949 #define IP_DMA_TCD_BASE_PTRS { IP_TCD } 950 951 /* ---------------------------------------------------------------------------- 952 -- DMA_TCD Register Masks 953 ---------------------------------------------------------------------------- */ 954 955 /*! 956 * @addtogroup DMA_TCD_Register_Masks DMA_TCD Register Masks 957 * @{ 958 */ 959 960 /*! @name CH0_CSR - Channel Control and Status */ 961 /*! @{ */ 962 963 #define DMA_TCD_CH0_CSR_ERQ_MASK (0x1U) 964 #define DMA_TCD_CH0_CSR_ERQ_SHIFT (0U) 965 #define DMA_TCD_CH0_CSR_ERQ_WIDTH (1U) 966 #define DMA_TCD_CH0_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_CSR_ERQ_SHIFT)) & DMA_TCD_CH0_CSR_ERQ_MASK) 967 968 #define DMA_TCD_CH0_CSR_EARQ_MASK (0x2U) 969 #define DMA_TCD_CH0_CSR_EARQ_SHIFT (1U) 970 #define DMA_TCD_CH0_CSR_EARQ_WIDTH (1U) 971 #define DMA_TCD_CH0_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_CSR_EARQ_SHIFT)) & DMA_TCD_CH0_CSR_EARQ_MASK) 972 973 #define DMA_TCD_CH0_CSR_EEI_MASK (0x4U) 974 #define DMA_TCD_CH0_CSR_EEI_SHIFT (2U) 975 #define DMA_TCD_CH0_CSR_EEI_WIDTH (1U) 976 #define DMA_TCD_CH0_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_CSR_EEI_SHIFT)) & DMA_TCD_CH0_CSR_EEI_MASK) 977 978 #define DMA_TCD_CH0_CSR_EBW_MASK (0x8U) 979 #define DMA_TCD_CH0_CSR_EBW_SHIFT (3U) 980 #define DMA_TCD_CH0_CSR_EBW_WIDTH (1U) 981 #define DMA_TCD_CH0_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_CSR_EBW_SHIFT)) & DMA_TCD_CH0_CSR_EBW_MASK) 982 983 #define DMA_TCD_CH0_CSR_DONE_MASK (0x40000000U) 984 #define DMA_TCD_CH0_CSR_DONE_SHIFT (30U) 985 #define DMA_TCD_CH0_CSR_DONE_WIDTH (1U) 986 #define DMA_TCD_CH0_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_CSR_DONE_SHIFT)) & DMA_TCD_CH0_CSR_DONE_MASK) 987 988 #define DMA_TCD_CH0_CSR_ACTIVE_MASK (0x80000000U) 989 #define DMA_TCD_CH0_CSR_ACTIVE_SHIFT (31U) 990 #define DMA_TCD_CH0_CSR_ACTIVE_WIDTH (1U) 991 #define DMA_TCD_CH0_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH0_CSR_ACTIVE_MASK) 992 /*! @} */ 993 994 /*! @name CH0_ES - Channel Error Status */ 995 /*! @{ */ 996 997 #define DMA_TCD_CH0_ES_DBE_MASK (0x1U) 998 #define DMA_TCD_CH0_ES_DBE_SHIFT (0U) 999 #define DMA_TCD_CH0_ES_DBE_WIDTH (1U) 1000 #define DMA_TCD_CH0_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_ES_DBE_SHIFT)) & DMA_TCD_CH0_ES_DBE_MASK) 1001 1002 #define DMA_TCD_CH0_ES_SBE_MASK (0x2U) 1003 #define DMA_TCD_CH0_ES_SBE_SHIFT (1U) 1004 #define DMA_TCD_CH0_ES_SBE_WIDTH (1U) 1005 #define DMA_TCD_CH0_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_ES_SBE_SHIFT)) & DMA_TCD_CH0_ES_SBE_MASK) 1006 1007 #define DMA_TCD_CH0_ES_SGE_MASK (0x4U) 1008 #define DMA_TCD_CH0_ES_SGE_SHIFT (2U) 1009 #define DMA_TCD_CH0_ES_SGE_WIDTH (1U) 1010 #define DMA_TCD_CH0_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_ES_SGE_SHIFT)) & DMA_TCD_CH0_ES_SGE_MASK) 1011 1012 #define DMA_TCD_CH0_ES_NCE_MASK (0x8U) 1013 #define DMA_TCD_CH0_ES_NCE_SHIFT (3U) 1014 #define DMA_TCD_CH0_ES_NCE_WIDTH (1U) 1015 #define DMA_TCD_CH0_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_ES_NCE_SHIFT)) & DMA_TCD_CH0_ES_NCE_MASK) 1016 1017 #define DMA_TCD_CH0_ES_DOE_MASK (0x10U) 1018 #define DMA_TCD_CH0_ES_DOE_SHIFT (4U) 1019 #define DMA_TCD_CH0_ES_DOE_WIDTH (1U) 1020 #define DMA_TCD_CH0_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_ES_DOE_SHIFT)) & DMA_TCD_CH0_ES_DOE_MASK) 1021 1022 #define DMA_TCD_CH0_ES_DAE_MASK (0x20U) 1023 #define DMA_TCD_CH0_ES_DAE_SHIFT (5U) 1024 #define DMA_TCD_CH0_ES_DAE_WIDTH (1U) 1025 #define DMA_TCD_CH0_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_ES_DAE_SHIFT)) & DMA_TCD_CH0_ES_DAE_MASK) 1026 1027 #define DMA_TCD_CH0_ES_SOE_MASK (0x40U) 1028 #define DMA_TCD_CH0_ES_SOE_SHIFT (6U) 1029 #define DMA_TCD_CH0_ES_SOE_WIDTH (1U) 1030 #define DMA_TCD_CH0_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_ES_SOE_SHIFT)) & DMA_TCD_CH0_ES_SOE_MASK) 1031 1032 #define DMA_TCD_CH0_ES_SAE_MASK (0x80U) 1033 #define DMA_TCD_CH0_ES_SAE_SHIFT (7U) 1034 #define DMA_TCD_CH0_ES_SAE_WIDTH (1U) 1035 #define DMA_TCD_CH0_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_ES_SAE_SHIFT)) & DMA_TCD_CH0_ES_SAE_MASK) 1036 1037 #define DMA_TCD_CH0_ES_ERR_MASK (0x80000000U) 1038 #define DMA_TCD_CH0_ES_ERR_SHIFT (31U) 1039 #define DMA_TCD_CH0_ES_ERR_WIDTH (1U) 1040 #define DMA_TCD_CH0_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_ES_ERR_SHIFT)) & DMA_TCD_CH0_ES_ERR_MASK) 1041 /*! @} */ 1042 1043 /*! @name CH0_INT - Channel Interrupt Status */ 1044 /*! @{ */ 1045 1046 #define DMA_TCD_CH0_INT_INT_MASK (0x1U) 1047 #define DMA_TCD_CH0_INT_INT_SHIFT (0U) 1048 #define DMA_TCD_CH0_INT_INT_WIDTH (1U) 1049 #define DMA_TCD_CH0_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_INT_INT_SHIFT)) & DMA_TCD_CH0_INT_INT_MASK) 1050 /*! @} */ 1051 1052 /*! @name CH0_SBR - Channel System Bus */ 1053 /*! @{ */ 1054 1055 #define DMA_TCD_CH0_SBR_MID_MASK (0xFU) 1056 #define DMA_TCD_CH0_SBR_MID_SHIFT (0U) 1057 #define DMA_TCD_CH0_SBR_MID_WIDTH (4U) 1058 #define DMA_TCD_CH0_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_SBR_MID_SHIFT)) & DMA_TCD_CH0_SBR_MID_MASK) 1059 1060 #define DMA_TCD_CH0_SBR_PAL_MASK (0x8000U) 1061 #define DMA_TCD_CH0_SBR_PAL_SHIFT (15U) 1062 #define DMA_TCD_CH0_SBR_PAL_WIDTH (1U) 1063 #define DMA_TCD_CH0_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_SBR_PAL_SHIFT)) & DMA_TCD_CH0_SBR_PAL_MASK) 1064 1065 #define DMA_TCD_CH0_SBR_EMI_MASK (0x10000U) 1066 #define DMA_TCD_CH0_SBR_EMI_SHIFT (16U) 1067 #define DMA_TCD_CH0_SBR_EMI_WIDTH (1U) 1068 #define DMA_TCD_CH0_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_SBR_EMI_SHIFT)) & DMA_TCD_CH0_SBR_EMI_MASK) 1069 1070 #define DMA_TCD_CH0_SBR_ATTR_MASK (0xE0000U) 1071 #define DMA_TCD_CH0_SBR_ATTR_SHIFT (17U) 1072 #define DMA_TCD_CH0_SBR_ATTR_WIDTH (3U) 1073 #define DMA_TCD_CH0_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_SBR_ATTR_SHIFT)) & DMA_TCD_CH0_SBR_ATTR_MASK) 1074 /*! @} */ 1075 1076 /*! @name CH0_PRI - Channel Priority */ 1077 /*! @{ */ 1078 1079 #define DMA_TCD_CH0_PRI_APL_MASK (0x7U) 1080 #define DMA_TCD_CH0_PRI_APL_SHIFT (0U) 1081 #define DMA_TCD_CH0_PRI_APL_WIDTH (3U) 1082 #define DMA_TCD_CH0_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_PRI_APL_SHIFT)) & DMA_TCD_CH0_PRI_APL_MASK) 1083 1084 #define DMA_TCD_CH0_PRI_DPA_MASK (0x40000000U) 1085 #define DMA_TCD_CH0_PRI_DPA_SHIFT (30U) 1086 #define DMA_TCD_CH0_PRI_DPA_WIDTH (1U) 1087 #define DMA_TCD_CH0_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_PRI_DPA_SHIFT)) & DMA_TCD_CH0_PRI_DPA_MASK) 1088 1089 #define DMA_TCD_CH0_PRI_ECP_MASK (0x80000000U) 1090 #define DMA_TCD_CH0_PRI_ECP_SHIFT (31U) 1091 #define DMA_TCD_CH0_PRI_ECP_WIDTH (1U) 1092 #define DMA_TCD_CH0_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH0_PRI_ECP_SHIFT)) & DMA_TCD_CH0_PRI_ECP_MASK) 1093 /*! @} */ 1094 1095 /*! @name TCD0_SADDR - TCD Source Address */ 1096 /*! @{ */ 1097 1098 #define DMA_TCD_TCD0_SADDR_SADDR_MASK (0xFFFFFFFFU) 1099 #define DMA_TCD_TCD0_SADDR_SADDR_SHIFT (0U) 1100 #define DMA_TCD_TCD0_SADDR_SADDR_WIDTH (32U) 1101 #define DMA_TCD_TCD0_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD0_SADDR_SADDR_MASK) 1102 /*! @} */ 1103 1104 /*! @name TCD0_SOFF - TCD Signed Source Address Offset */ 1105 /*! @{ */ 1106 1107 #define DMA_TCD_TCD0_SOFF_SOFF_MASK (0xFFFFU) 1108 #define DMA_TCD_TCD0_SOFF_SOFF_SHIFT (0U) 1109 #define DMA_TCD_TCD0_SOFF_SOFF_WIDTH (16U) 1110 #define DMA_TCD_TCD0_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD0_SOFF_SOFF_MASK) 1111 /*! @} */ 1112 1113 /*! @name TCD0_ATTR - TCD Transfer Attributes */ 1114 /*! @{ */ 1115 1116 #define DMA_TCD_TCD0_ATTR_DSIZE_MASK (0x7U) 1117 #define DMA_TCD_TCD0_ATTR_DSIZE_SHIFT (0U) 1118 #define DMA_TCD_TCD0_ATTR_DSIZE_WIDTH (3U) 1119 #define DMA_TCD_TCD0_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD0_ATTR_DSIZE_MASK) 1120 1121 #define DMA_TCD_TCD0_ATTR_DMOD_MASK (0xF8U) 1122 #define DMA_TCD_TCD0_ATTR_DMOD_SHIFT (3U) 1123 #define DMA_TCD_TCD0_ATTR_DMOD_WIDTH (5U) 1124 #define DMA_TCD_TCD0_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD0_ATTR_DMOD_MASK) 1125 1126 #define DMA_TCD_TCD0_ATTR_SSIZE_MASK (0x700U) 1127 #define DMA_TCD_TCD0_ATTR_SSIZE_SHIFT (8U) 1128 #define DMA_TCD_TCD0_ATTR_SSIZE_WIDTH (3U) 1129 #define DMA_TCD_TCD0_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD0_ATTR_SSIZE_MASK) 1130 1131 #define DMA_TCD_TCD0_ATTR_SMOD_MASK (0xF800U) 1132 #define DMA_TCD_TCD0_ATTR_SMOD_SHIFT (11U) 1133 #define DMA_TCD_TCD0_ATTR_SMOD_WIDTH (5U) 1134 #define DMA_TCD_TCD0_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD0_ATTR_SMOD_MASK) 1135 /*! @} */ 1136 1137 /*! @name TCD0_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 1138 /*! @{ */ 1139 1140 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 1141 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 1142 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 1143 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD0_NBYTES_MLOFFNO_NBYTES_MASK) 1144 1145 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 1146 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 1147 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 1148 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD0_NBYTES_MLOFFNO_DMLOE_MASK) 1149 1150 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 1151 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 1152 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 1153 #define DMA_TCD_TCD0_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD0_NBYTES_MLOFFNO_SMLOE_MASK) 1154 /*! @} */ 1155 1156 /*! @name TCD0_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 1157 /*! @{ */ 1158 1159 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 1160 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 1161 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 1162 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD0_NBYTES_MLOFFYES_NBYTES_MASK) 1163 1164 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 1165 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 1166 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 1167 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD0_NBYTES_MLOFFYES_MLOFF_MASK) 1168 1169 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 1170 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 1171 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 1172 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD0_NBYTES_MLOFFYES_DMLOE_MASK) 1173 1174 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 1175 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 1176 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 1177 #define DMA_TCD_TCD0_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD0_NBYTES_MLOFFYES_SMLOE_MASK) 1178 /*! @} */ 1179 1180 /*! @name TCD0_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 1181 /*! @{ */ 1182 1183 #define DMA_TCD_TCD0_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 1184 #define DMA_TCD_TCD0_SLAST_SDA_SLAST_SDA_SHIFT (0U) 1185 #define DMA_TCD_TCD0_SLAST_SDA_SLAST_SDA_WIDTH (32U) 1186 #define DMA_TCD_TCD0_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD0_SLAST_SDA_SLAST_SDA_MASK) 1187 /*! @} */ 1188 1189 /*! @name TCD0_DADDR - TCD Destination Address */ 1190 /*! @{ */ 1191 1192 #define DMA_TCD_TCD0_DADDR_DADDR_MASK (0xFFFFFFFFU) 1193 #define DMA_TCD_TCD0_DADDR_DADDR_SHIFT (0U) 1194 #define DMA_TCD_TCD0_DADDR_DADDR_WIDTH (32U) 1195 #define DMA_TCD_TCD0_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD0_DADDR_DADDR_MASK) 1196 /*! @} */ 1197 1198 /*! @name TCD0_DOFF - TCD Signed Destination Address Offset */ 1199 /*! @{ */ 1200 1201 #define DMA_TCD_TCD0_DOFF_DOFF_MASK (0xFFFFU) 1202 #define DMA_TCD_TCD0_DOFF_DOFF_SHIFT (0U) 1203 #define DMA_TCD_TCD0_DOFF_DOFF_WIDTH (16U) 1204 #define DMA_TCD_TCD0_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD0_DOFF_DOFF_MASK) 1205 /*! @} */ 1206 1207 /*! @name TCD0_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 1208 /*! @{ */ 1209 1210 #define DMA_TCD_TCD0_CITER_ELINKNO_CITER_MASK (0x7FFFU) 1211 #define DMA_TCD_TCD0_CITER_ELINKNO_CITER_SHIFT (0U) 1212 #define DMA_TCD_TCD0_CITER_ELINKNO_CITER_WIDTH (15U) 1213 #define DMA_TCD_TCD0_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD0_CITER_ELINKNO_CITER_MASK) 1214 1215 #define DMA_TCD_TCD0_CITER_ELINKNO_ELINK_MASK (0x8000U) 1216 #define DMA_TCD_TCD0_CITER_ELINKNO_ELINK_SHIFT (15U) 1217 #define DMA_TCD_TCD0_CITER_ELINKNO_ELINK_WIDTH (1U) 1218 #define DMA_TCD_TCD0_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD0_CITER_ELINKNO_ELINK_MASK) 1219 /*! @} */ 1220 1221 /*! @name TCD0_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 1222 /*! @{ */ 1223 1224 #define DMA_TCD_TCD0_CITER_ELINKYES_CITER_MASK (0x1FFU) 1225 #define DMA_TCD_TCD0_CITER_ELINKYES_CITER_SHIFT (0U) 1226 #define DMA_TCD_TCD0_CITER_ELINKYES_CITER_WIDTH (9U) 1227 #define DMA_TCD_TCD0_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD0_CITER_ELINKYES_CITER_MASK) 1228 1229 #define DMA_TCD_TCD0_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 1230 #define DMA_TCD_TCD0_CITER_ELINKYES_LINKCH_SHIFT (9U) 1231 #define DMA_TCD_TCD0_CITER_ELINKYES_LINKCH_WIDTH (5U) 1232 #define DMA_TCD_TCD0_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD0_CITER_ELINKYES_LINKCH_MASK) 1233 1234 #define DMA_TCD_TCD0_CITER_ELINKYES_ELINK_MASK (0x8000U) 1235 #define DMA_TCD_TCD0_CITER_ELINKYES_ELINK_SHIFT (15U) 1236 #define DMA_TCD_TCD0_CITER_ELINKYES_ELINK_WIDTH (1U) 1237 #define DMA_TCD_TCD0_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD0_CITER_ELINKYES_ELINK_MASK) 1238 /*! @} */ 1239 1240 /*! @name TCD0_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 1241 /*! @{ */ 1242 1243 #define DMA_TCD_TCD0_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 1244 #define DMA_TCD_TCD0_DLAST_SGA_DLAST_SGA_SHIFT (0U) 1245 #define DMA_TCD_TCD0_DLAST_SGA_DLAST_SGA_WIDTH (32U) 1246 #define DMA_TCD_TCD0_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD0_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD0_DLAST_SGA_DLAST_SGA_MASK) 1247 /*! @} */ 1248 1249 /*! @name TCD0_CSR - TCD Control and Status */ 1250 /*! @{ */ 1251 1252 #define DMA_TCD_TCD0_CSR_START_MASK (0x1U) 1253 #define DMA_TCD_TCD0_CSR_START_SHIFT (0U) 1254 #define DMA_TCD_TCD0_CSR_START_WIDTH (1U) 1255 #define DMA_TCD_TCD0_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CSR_START_SHIFT)) & DMA_TCD_TCD0_CSR_START_MASK) 1256 1257 #define DMA_TCD_TCD0_CSR_INTMAJOR_MASK (0x2U) 1258 #define DMA_TCD_TCD0_CSR_INTMAJOR_SHIFT (1U) 1259 #define DMA_TCD_TCD0_CSR_INTMAJOR_WIDTH (1U) 1260 #define DMA_TCD_TCD0_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD0_CSR_INTMAJOR_MASK) 1261 1262 #define DMA_TCD_TCD0_CSR_INTHALF_MASK (0x4U) 1263 #define DMA_TCD_TCD0_CSR_INTHALF_SHIFT (2U) 1264 #define DMA_TCD_TCD0_CSR_INTHALF_WIDTH (1U) 1265 #define DMA_TCD_TCD0_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD0_CSR_INTHALF_MASK) 1266 1267 #define DMA_TCD_TCD0_CSR_DREQ_MASK (0x8U) 1268 #define DMA_TCD_TCD0_CSR_DREQ_SHIFT (3U) 1269 #define DMA_TCD_TCD0_CSR_DREQ_WIDTH (1U) 1270 #define DMA_TCD_TCD0_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CSR_DREQ_SHIFT)) & DMA_TCD_TCD0_CSR_DREQ_MASK) 1271 1272 #define DMA_TCD_TCD0_CSR_ESG_MASK (0x10U) 1273 #define DMA_TCD_TCD0_CSR_ESG_SHIFT (4U) 1274 #define DMA_TCD_TCD0_CSR_ESG_WIDTH (1U) 1275 #define DMA_TCD_TCD0_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CSR_ESG_SHIFT)) & DMA_TCD_TCD0_CSR_ESG_MASK) 1276 1277 #define DMA_TCD_TCD0_CSR_MAJORELINK_MASK (0x20U) 1278 #define DMA_TCD_TCD0_CSR_MAJORELINK_SHIFT (5U) 1279 #define DMA_TCD_TCD0_CSR_MAJORELINK_WIDTH (1U) 1280 #define DMA_TCD_TCD0_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD0_CSR_MAJORELINK_MASK) 1281 1282 #define DMA_TCD_TCD0_CSR_EEOP_MASK (0x40U) 1283 #define DMA_TCD_TCD0_CSR_EEOP_SHIFT (6U) 1284 #define DMA_TCD_TCD0_CSR_EEOP_WIDTH (1U) 1285 #define DMA_TCD_TCD0_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CSR_EEOP_SHIFT)) & DMA_TCD_TCD0_CSR_EEOP_MASK) 1286 1287 #define DMA_TCD_TCD0_CSR_ESDA_MASK (0x80U) 1288 #define DMA_TCD_TCD0_CSR_ESDA_SHIFT (7U) 1289 #define DMA_TCD_TCD0_CSR_ESDA_WIDTH (1U) 1290 #define DMA_TCD_TCD0_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CSR_ESDA_SHIFT)) & DMA_TCD_TCD0_CSR_ESDA_MASK) 1291 1292 #define DMA_TCD_TCD0_CSR_MAJORLINKCH_MASK (0x1F00U) 1293 #define DMA_TCD_TCD0_CSR_MAJORLINKCH_SHIFT (8U) 1294 #define DMA_TCD_TCD0_CSR_MAJORLINKCH_WIDTH (5U) 1295 #define DMA_TCD_TCD0_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD0_CSR_MAJORLINKCH_MASK) 1296 1297 #define DMA_TCD_TCD0_CSR_BWC_MASK (0xC000U) 1298 #define DMA_TCD_TCD0_CSR_BWC_SHIFT (14U) 1299 #define DMA_TCD_TCD0_CSR_BWC_WIDTH (2U) 1300 #define DMA_TCD_TCD0_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_CSR_BWC_SHIFT)) & DMA_TCD_TCD0_CSR_BWC_MASK) 1301 /*! @} */ 1302 1303 /*! @name TCD0_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 1304 /*! @{ */ 1305 1306 #define DMA_TCD_TCD0_BITER_ELINKNO_BITER_MASK (0x7FFFU) 1307 #define DMA_TCD_TCD0_BITER_ELINKNO_BITER_SHIFT (0U) 1308 #define DMA_TCD_TCD0_BITER_ELINKNO_BITER_WIDTH (15U) 1309 #define DMA_TCD_TCD0_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD0_BITER_ELINKNO_BITER_MASK) 1310 1311 #define DMA_TCD_TCD0_BITER_ELINKNO_ELINK_MASK (0x8000U) 1312 #define DMA_TCD_TCD0_BITER_ELINKNO_ELINK_SHIFT (15U) 1313 #define DMA_TCD_TCD0_BITER_ELINKNO_ELINK_WIDTH (1U) 1314 #define DMA_TCD_TCD0_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD0_BITER_ELINKNO_ELINK_MASK) 1315 /*! @} */ 1316 1317 /*! @name TCD0_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 1318 /*! @{ */ 1319 1320 #define DMA_TCD_TCD0_BITER_ELINKYES_BITER_MASK (0x1FFU) 1321 #define DMA_TCD_TCD0_BITER_ELINKYES_BITER_SHIFT (0U) 1322 #define DMA_TCD_TCD0_BITER_ELINKYES_BITER_WIDTH (9U) 1323 #define DMA_TCD_TCD0_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD0_BITER_ELINKYES_BITER_MASK) 1324 1325 #define DMA_TCD_TCD0_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 1326 #define DMA_TCD_TCD0_BITER_ELINKYES_LINKCH_SHIFT (9U) 1327 #define DMA_TCD_TCD0_BITER_ELINKYES_LINKCH_WIDTH (5U) 1328 #define DMA_TCD_TCD0_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD0_BITER_ELINKYES_LINKCH_MASK) 1329 1330 #define DMA_TCD_TCD0_BITER_ELINKYES_ELINK_MASK (0x8000U) 1331 #define DMA_TCD_TCD0_BITER_ELINKYES_ELINK_SHIFT (15U) 1332 #define DMA_TCD_TCD0_BITER_ELINKYES_ELINK_WIDTH (1U) 1333 #define DMA_TCD_TCD0_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD0_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD0_BITER_ELINKYES_ELINK_MASK) 1334 /*! @} */ 1335 1336 /*! @name CH1_CSR - Channel Control and Status */ 1337 /*! @{ */ 1338 1339 #define DMA_TCD_CH1_CSR_ERQ_MASK (0x1U) 1340 #define DMA_TCD_CH1_CSR_ERQ_SHIFT (0U) 1341 #define DMA_TCD_CH1_CSR_ERQ_WIDTH (1U) 1342 #define DMA_TCD_CH1_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_CSR_ERQ_SHIFT)) & DMA_TCD_CH1_CSR_ERQ_MASK) 1343 1344 #define DMA_TCD_CH1_CSR_EARQ_MASK (0x2U) 1345 #define DMA_TCD_CH1_CSR_EARQ_SHIFT (1U) 1346 #define DMA_TCD_CH1_CSR_EARQ_WIDTH (1U) 1347 #define DMA_TCD_CH1_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_CSR_EARQ_SHIFT)) & DMA_TCD_CH1_CSR_EARQ_MASK) 1348 1349 #define DMA_TCD_CH1_CSR_EEI_MASK (0x4U) 1350 #define DMA_TCD_CH1_CSR_EEI_SHIFT (2U) 1351 #define DMA_TCD_CH1_CSR_EEI_WIDTH (1U) 1352 #define DMA_TCD_CH1_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_CSR_EEI_SHIFT)) & DMA_TCD_CH1_CSR_EEI_MASK) 1353 1354 #define DMA_TCD_CH1_CSR_EBW_MASK (0x8U) 1355 #define DMA_TCD_CH1_CSR_EBW_SHIFT (3U) 1356 #define DMA_TCD_CH1_CSR_EBW_WIDTH (1U) 1357 #define DMA_TCD_CH1_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_CSR_EBW_SHIFT)) & DMA_TCD_CH1_CSR_EBW_MASK) 1358 1359 #define DMA_TCD_CH1_CSR_DONE_MASK (0x40000000U) 1360 #define DMA_TCD_CH1_CSR_DONE_SHIFT (30U) 1361 #define DMA_TCD_CH1_CSR_DONE_WIDTH (1U) 1362 #define DMA_TCD_CH1_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_CSR_DONE_SHIFT)) & DMA_TCD_CH1_CSR_DONE_MASK) 1363 1364 #define DMA_TCD_CH1_CSR_ACTIVE_MASK (0x80000000U) 1365 #define DMA_TCD_CH1_CSR_ACTIVE_SHIFT (31U) 1366 #define DMA_TCD_CH1_CSR_ACTIVE_WIDTH (1U) 1367 #define DMA_TCD_CH1_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH1_CSR_ACTIVE_MASK) 1368 /*! @} */ 1369 1370 /*! @name CH1_ES - Channel Error Status */ 1371 /*! @{ */ 1372 1373 #define DMA_TCD_CH1_ES_DBE_MASK (0x1U) 1374 #define DMA_TCD_CH1_ES_DBE_SHIFT (0U) 1375 #define DMA_TCD_CH1_ES_DBE_WIDTH (1U) 1376 #define DMA_TCD_CH1_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_ES_DBE_SHIFT)) & DMA_TCD_CH1_ES_DBE_MASK) 1377 1378 #define DMA_TCD_CH1_ES_SBE_MASK (0x2U) 1379 #define DMA_TCD_CH1_ES_SBE_SHIFT (1U) 1380 #define DMA_TCD_CH1_ES_SBE_WIDTH (1U) 1381 #define DMA_TCD_CH1_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_ES_SBE_SHIFT)) & DMA_TCD_CH1_ES_SBE_MASK) 1382 1383 #define DMA_TCD_CH1_ES_SGE_MASK (0x4U) 1384 #define DMA_TCD_CH1_ES_SGE_SHIFT (2U) 1385 #define DMA_TCD_CH1_ES_SGE_WIDTH (1U) 1386 #define DMA_TCD_CH1_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_ES_SGE_SHIFT)) & DMA_TCD_CH1_ES_SGE_MASK) 1387 1388 #define DMA_TCD_CH1_ES_NCE_MASK (0x8U) 1389 #define DMA_TCD_CH1_ES_NCE_SHIFT (3U) 1390 #define DMA_TCD_CH1_ES_NCE_WIDTH (1U) 1391 #define DMA_TCD_CH1_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_ES_NCE_SHIFT)) & DMA_TCD_CH1_ES_NCE_MASK) 1392 1393 #define DMA_TCD_CH1_ES_DOE_MASK (0x10U) 1394 #define DMA_TCD_CH1_ES_DOE_SHIFT (4U) 1395 #define DMA_TCD_CH1_ES_DOE_WIDTH (1U) 1396 #define DMA_TCD_CH1_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_ES_DOE_SHIFT)) & DMA_TCD_CH1_ES_DOE_MASK) 1397 1398 #define DMA_TCD_CH1_ES_DAE_MASK (0x20U) 1399 #define DMA_TCD_CH1_ES_DAE_SHIFT (5U) 1400 #define DMA_TCD_CH1_ES_DAE_WIDTH (1U) 1401 #define DMA_TCD_CH1_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_ES_DAE_SHIFT)) & DMA_TCD_CH1_ES_DAE_MASK) 1402 1403 #define DMA_TCD_CH1_ES_SOE_MASK (0x40U) 1404 #define DMA_TCD_CH1_ES_SOE_SHIFT (6U) 1405 #define DMA_TCD_CH1_ES_SOE_WIDTH (1U) 1406 #define DMA_TCD_CH1_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_ES_SOE_SHIFT)) & DMA_TCD_CH1_ES_SOE_MASK) 1407 1408 #define DMA_TCD_CH1_ES_SAE_MASK (0x80U) 1409 #define DMA_TCD_CH1_ES_SAE_SHIFT (7U) 1410 #define DMA_TCD_CH1_ES_SAE_WIDTH (1U) 1411 #define DMA_TCD_CH1_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_ES_SAE_SHIFT)) & DMA_TCD_CH1_ES_SAE_MASK) 1412 1413 #define DMA_TCD_CH1_ES_ERR_MASK (0x80000000U) 1414 #define DMA_TCD_CH1_ES_ERR_SHIFT (31U) 1415 #define DMA_TCD_CH1_ES_ERR_WIDTH (1U) 1416 #define DMA_TCD_CH1_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_ES_ERR_SHIFT)) & DMA_TCD_CH1_ES_ERR_MASK) 1417 /*! @} */ 1418 1419 /*! @name CH1_INT - Channel Interrupt Status */ 1420 /*! @{ */ 1421 1422 #define DMA_TCD_CH1_INT_INT_MASK (0x1U) 1423 #define DMA_TCD_CH1_INT_INT_SHIFT (0U) 1424 #define DMA_TCD_CH1_INT_INT_WIDTH (1U) 1425 #define DMA_TCD_CH1_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_INT_INT_SHIFT)) & DMA_TCD_CH1_INT_INT_MASK) 1426 /*! @} */ 1427 1428 /*! @name CH1_SBR - Channel System Bus */ 1429 /*! @{ */ 1430 1431 #define DMA_TCD_CH1_SBR_MID_MASK (0xFU) 1432 #define DMA_TCD_CH1_SBR_MID_SHIFT (0U) 1433 #define DMA_TCD_CH1_SBR_MID_WIDTH (4U) 1434 #define DMA_TCD_CH1_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_SBR_MID_SHIFT)) & DMA_TCD_CH1_SBR_MID_MASK) 1435 1436 #define DMA_TCD_CH1_SBR_PAL_MASK (0x8000U) 1437 #define DMA_TCD_CH1_SBR_PAL_SHIFT (15U) 1438 #define DMA_TCD_CH1_SBR_PAL_WIDTH (1U) 1439 #define DMA_TCD_CH1_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_SBR_PAL_SHIFT)) & DMA_TCD_CH1_SBR_PAL_MASK) 1440 1441 #define DMA_TCD_CH1_SBR_EMI_MASK (0x10000U) 1442 #define DMA_TCD_CH1_SBR_EMI_SHIFT (16U) 1443 #define DMA_TCD_CH1_SBR_EMI_WIDTH (1U) 1444 #define DMA_TCD_CH1_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_SBR_EMI_SHIFT)) & DMA_TCD_CH1_SBR_EMI_MASK) 1445 1446 #define DMA_TCD_CH1_SBR_ATTR_MASK (0xE0000U) 1447 #define DMA_TCD_CH1_SBR_ATTR_SHIFT (17U) 1448 #define DMA_TCD_CH1_SBR_ATTR_WIDTH (3U) 1449 #define DMA_TCD_CH1_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_SBR_ATTR_SHIFT)) & DMA_TCD_CH1_SBR_ATTR_MASK) 1450 /*! @} */ 1451 1452 /*! @name CH1_PRI - Channel Priority */ 1453 /*! @{ */ 1454 1455 #define DMA_TCD_CH1_PRI_APL_MASK (0x7U) 1456 #define DMA_TCD_CH1_PRI_APL_SHIFT (0U) 1457 #define DMA_TCD_CH1_PRI_APL_WIDTH (3U) 1458 #define DMA_TCD_CH1_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_PRI_APL_SHIFT)) & DMA_TCD_CH1_PRI_APL_MASK) 1459 1460 #define DMA_TCD_CH1_PRI_DPA_MASK (0x40000000U) 1461 #define DMA_TCD_CH1_PRI_DPA_SHIFT (30U) 1462 #define DMA_TCD_CH1_PRI_DPA_WIDTH (1U) 1463 #define DMA_TCD_CH1_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_PRI_DPA_SHIFT)) & DMA_TCD_CH1_PRI_DPA_MASK) 1464 1465 #define DMA_TCD_CH1_PRI_ECP_MASK (0x80000000U) 1466 #define DMA_TCD_CH1_PRI_ECP_SHIFT (31U) 1467 #define DMA_TCD_CH1_PRI_ECP_WIDTH (1U) 1468 #define DMA_TCD_CH1_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH1_PRI_ECP_SHIFT)) & DMA_TCD_CH1_PRI_ECP_MASK) 1469 /*! @} */ 1470 1471 /*! @name TCD1_SADDR - TCD Source Address */ 1472 /*! @{ */ 1473 1474 #define DMA_TCD_TCD1_SADDR_SADDR_MASK (0xFFFFFFFFU) 1475 #define DMA_TCD_TCD1_SADDR_SADDR_SHIFT (0U) 1476 #define DMA_TCD_TCD1_SADDR_SADDR_WIDTH (32U) 1477 #define DMA_TCD_TCD1_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD1_SADDR_SADDR_MASK) 1478 /*! @} */ 1479 1480 /*! @name TCD1_SOFF - TCD Signed Source Address Offset */ 1481 /*! @{ */ 1482 1483 #define DMA_TCD_TCD1_SOFF_SOFF_MASK (0xFFFFU) 1484 #define DMA_TCD_TCD1_SOFF_SOFF_SHIFT (0U) 1485 #define DMA_TCD_TCD1_SOFF_SOFF_WIDTH (16U) 1486 #define DMA_TCD_TCD1_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD1_SOFF_SOFF_MASK) 1487 /*! @} */ 1488 1489 /*! @name TCD1_ATTR - TCD Transfer Attributes */ 1490 /*! @{ */ 1491 1492 #define DMA_TCD_TCD1_ATTR_DSIZE_MASK (0x7U) 1493 #define DMA_TCD_TCD1_ATTR_DSIZE_SHIFT (0U) 1494 #define DMA_TCD_TCD1_ATTR_DSIZE_WIDTH (3U) 1495 #define DMA_TCD_TCD1_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD1_ATTR_DSIZE_MASK) 1496 1497 #define DMA_TCD_TCD1_ATTR_DMOD_MASK (0xF8U) 1498 #define DMA_TCD_TCD1_ATTR_DMOD_SHIFT (3U) 1499 #define DMA_TCD_TCD1_ATTR_DMOD_WIDTH (5U) 1500 #define DMA_TCD_TCD1_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD1_ATTR_DMOD_MASK) 1501 1502 #define DMA_TCD_TCD1_ATTR_SSIZE_MASK (0x700U) 1503 #define DMA_TCD_TCD1_ATTR_SSIZE_SHIFT (8U) 1504 #define DMA_TCD_TCD1_ATTR_SSIZE_WIDTH (3U) 1505 #define DMA_TCD_TCD1_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD1_ATTR_SSIZE_MASK) 1506 1507 #define DMA_TCD_TCD1_ATTR_SMOD_MASK (0xF800U) 1508 #define DMA_TCD_TCD1_ATTR_SMOD_SHIFT (11U) 1509 #define DMA_TCD_TCD1_ATTR_SMOD_WIDTH (5U) 1510 #define DMA_TCD_TCD1_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD1_ATTR_SMOD_MASK) 1511 /*! @} */ 1512 1513 /*! @name TCD1_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 1514 /*! @{ */ 1515 1516 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 1517 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 1518 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 1519 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD1_NBYTES_MLOFFNO_NBYTES_MASK) 1520 1521 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 1522 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 1523 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 1524 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD1_NBYTES_MLOFFNO_DMLOE_MASK) 1525 1526 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 1527 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 1528 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 1529 #define DMA_TCD_TCD1_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD1_NBYTES_MLOFFNO_SMLOE_MASK) 1530 /*! @} */ 1531 1532 /*! @name TCD1_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 1533 /*! @{ */ 1534 1535 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 1536 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 1537 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 1538 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD1_NBYTES_MLOFFYES_NBYTES_MASK) 1539 1540 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 1541 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 1542 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 1543 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD1_NBYTES_MLOFFYES_MLOFF_MASK) 1544 1545 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 1546 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 1547 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 1548 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD1_NBYTES_MLOFFYES_DMLOE_MASK) 1549 1550 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 1551 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 1552 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 1553 #define DMA_TCD_TCD1_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD1_NBYTES_MLOFFYES_SMLOE_MASK) 1554 /*! @} */ 1555 1556 /*! @name TCD1_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 1557 /*! @{ */ 1558 1559 #define DMA_TCD_TCD1_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 1560 #define DMA_TCD_TCD1_SLAST_SDA_SLAST_SDA_SHIFT (0U) 1561 #define DMA_TCD_TCD1_SLAST_SDA_SLAST_SDA_WIDTH (32U) 1562 #define DMA_TCD_TCD1_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD1_SLAST_SDA_SLAST_SDA_MASK) 1563 /*! @} */ 1564 1565 /*! @name TCD1_DADDR - TCD Destination Address */ 1566 /*! @{ */ 1567 1568 #define DMA_TCD_TCD1_DADDR_DADDR_MASK (0xFFFFFFFFU) 1569 #define DMA_TCD_TCD1_DADDR_DADDR_SHIFT (0U) 1570 #define DMA_TCD_TCD1_DADDR_DADDR_WIDTH (32U) 1571 #define DMA_TCD_TCD1_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD1_DADDR_DADDR_MASK) 1572 /*! @} */ 1573 1574 /*! @name TCD1_DOFF - TCD Signed Destination Address Offset */ 1575 /*! @{ */ 1576 1577 #define DMA_TCD_TCD1_DOFF_DOFF_MASK (0xFFFFU) 1578 #define DMA_TCD_TCD1_DOFF_DOFF_SHIFT (0U) 1579 #define DMA_TCD_TCD1_DOFF_DOFF_WIDTH (16U) 1580 #define DMA_TCD_TCD1_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD1_DOFF_DOFF_MASK) 1581 /*! @} */ 1582 1583 /*! @name TCD1_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 1584 /*! @{ */ 1585 1586 #define DMA_TCD_TCD1_CITER_ELINKNO_CITER_MASK (0x7FFFU) 1587 #define DMA_TCD_TCD1_CITER_ELINKNO_CITER_SHIFT (0U) 1588 #define DMA_TCD_TCD1_CITER_ELINKNO_CITER_WIDTH (15U) 1589 #define DMA_TCD_TCD1_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD1_CITER_ELINKNO_CITER_MASK) 1590 1591 #define DMA_TCD_TCD1_CITER_ELINKNO_ELINK_MASK (0x8000U) 1592 #define DMA_TCD_TCD1_CITER_ELINKNO_ELINK_SHIFT (15U) 1593 #define DMA_TCD_TCD1_CITER_ELINKNO_ELINK_WIDTH (1U) 1594 #define DMA_TCD_TCD1_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD1_CITER_ELINKNO_ELINK_MASK) 1595 /*! @} */ 1596 1597 /*! @name TCD1_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 1598 /*! @{ */ 1599 1600 #define DMA_TCD_TCD1_CITER_ELINKYES_CITER_MASK (0x1FFU) 1601 #define DMA_TCD_TCD1_CITER_ELINKYES_CITER_SHIFT (0U) 1602 #define DMA_TCD_TCD1_CITER_ELINKYES_CITER_WIDTH (9U) 1603 #define DMA_TCD_TCD1_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD1_CITER_ELINKYES_CITER_MASK) 1604 1605 #define DMA_TCD_TCD1_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 1606 #define DMA_TCD_TCD1_CITER_ELINKYES_LINKCH_SHIFT (9U) 1607 #define DMA_TCD_TCD1_CITER_ELINKYES_LINKCH_WIDTH (5U) 1608 #define DMA_TCD_TCD1_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD1_CITER_ELINKYES_LINKCH_MASK) 1609 1610 #define DMA_TCD_TCD1_CITER_ELINKYES_ELINK_MASK (0x8000U) 1611 #define DMA_TCD_TCD1_CITER_ELINKYES_ELINK_SHIFT (15U) 1612 #define DMA_TCD_TCD1_CITER_ELINKYES_ELINK_WIDTH (1U) 1613 #define DMA_TCD_TCD1_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD1_CITER_ELINKYES_ELINK_MASK) 1614 /*! @} */ 1615 1616 /*! @name TCD1_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 1617 /*! @{ */ 1618 1619 #define DMA_TCD_TCD1_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 1620 #define DMA_TCD_TCD1_DLAST_SGA_DLAST_SGA_SHIFT (0U) 1621 #define DMA_TCD_TCD1_DLAST_SGA_DLAST_SGA_WIDTH (32U) 1622 #define DMA_TCD_TCD1_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD1_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD1_DLAST_SGA_DLAST_SGA_MASK) 1623 /*! @} */ 1624 1625 /*! @name TCD1_CSR - TCD Control and Status */ 1626 /*! @{ */ 1627 1628 #define DMA_TCD_TCD1_CSR_START_MASK (0x1U) 1629 #define DMA_TCD_TCD1_CSR_START_SHIFT (0U) 1630 #define DMA_TCD_TCD1_CSR_START_WIDTH (1U) 1631 #define DMA_TCD_TCD1_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CSR_START_SHIFT)) & DMA_TCD_TCD1_CSR_START_MASK) 1632 1633 #define DMA_TCD_TCD1_CSR_INTMAJOR_MASK (0x2U) 1634 #define DMA_TCD_TCD1_CSR_INTMAJOR_SHIFT (1U) 1635 #define DMA_TCD_TCD1_CSR_INTMAJOR_WIDTH (1U) 1636 #define DMA_TCD_TCD1_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD1_CSR_INTMAJOR_MASK) 1637 1638 #define DMA_TCD_TCD1_CSR_INTHALF_MASK (0x4U) 1639 #define DMA_TCD_TCD1_CSR_INTHALF_SHIFT (2U) 1640 #define DMA_TCD_TCD1_CSR_INTHALF_WIDTH (1U) 1641 #define DMA_TCD_TCD1_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD1_CSR_INTHALF_MASK) 1642 1643 #define DMA_TCD_TCD1_CSR_DREQ_MASK (0x8U) 1644 #define DMA_TCD_TCD1_CSR_DREQ_SHIFT (3U) 1645 #define DMA_TCD_TCD1_CSR_DREQ_WIDTH (1U) 1646 #define DMA_TCD_TCD1_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CSR_DREQ_SHIFT)) & DMA_TCD_TCD1_CSR_DREQ_MASK) 1647 1648 #define DMA_TCD_TCD1_CSR_ESG_MASK (0x10U) 1649 #define DMA_TCD_TCD1_CSR_ESG_SHIFT (4U) 1650 #define DMA_TCD_TCD1_CSR_ESG_WIDTH (1U) 1651 #define DMA_TCD_TCD1_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CSR_ESG_SHIFT)) & DMA_TCD_TCD1_CSR_ESG_MASK) 1652 1653 #define DMA_TCD_TCD1_CSR_MAJORELINK_MASK (0x20U) 1654 #define DMA_TCD_TCD1_CSR_MAJORELINK_SHIFT (5U) 1655 #define DMA_TCD_TCD1_CSR_MAJORELINK_WIDTH (1U) 1656 #define DMA_TCD_TCD1_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD1_CSR_MAJORELINK_MASK) 1657 1658 #define DMA_TCD_TCD1_CSR_EEOP_MASK (0x40U) 1659 #define DMA_TCD_TCD1_CSR_EEOP_SHIFT (6U) 1660 #define DMA_TCD_TCD1_CSR_EEOP_WIDTH (1U) 1661 #define DMA_TCD_TCD1_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CSR_EEOP_SHIFT)) & DMA_TCD_TCD1_CSR_EEOP_MASK) 1662 1663 #define DMA_TCD_TCD1_CSR_ESDA_MASK (0x80U) 1664 #define DMA_TCD_TCD1_CSR_ESDA_SHIFT (7U) 1665 #define DMA_TCD_TCD1_CSR_ESDA_WIDTH (1U) 1666 #define DMA_TCD_TCD1_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CSR_ESDA_SHIFT)) & DMA_TCD_TCD1_CSR_ESDA_MASK) 1667 1668 #define DMA_TCD_TCD1_CSR_MAJORLINKCH_MASK (0x1F00U) 1669 #define DMA_TCD_TCD1_CSR_MAJORLINKCH_SHIFT (8U) 1670 #define DMA_TCD_TCD1_CSR_MAJORLINKCH_WIDTH (5U) 1671 #define DMA_TCD_TCD1_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD1_CSR_MAJORLINKCH_MASK) 1672 1673 #define DMA_TCD_TCD1_CSR_BWC_MASK (0xC000U) 1674 #define DMA_TCD_TCD1_CSR_BWC_SHIFT (14U) 1675 #define DMA_TCD_TCD1_CSR_BWC_WIDTH (2U) 1676 #define DMA_TCD_TCD1_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_CSR_BWC_SHIFT)) & DMA_TCD_TCD1_CSR_BWC_MASK) 1677 /*! @} */ 1678 1679 /*! @name TCD1_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 1680 /*! @{ */ 1681 1682 #define DMA_TCD_TCD1_BITER_ELINKNO_BITER_MASK (0x7FFFU) 1683 #define DMA_TCD_TCD1_BITER_ELINKNO_BITER_SHIFT (0U) 1684 #define DMA_TCD_TCD1_BITER_ELINKNO_BITER_WIDTH (15U) 1685 #define DMA_TCD_TCD1_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD1_BITER_ELINKNO_BITER_MASK) 1686 1687 #define DMA_TCD_TCD1_BITER_ELINKNO_ELINK_MASK (0x8000U) 1688 #define DMA_TCD_TCD1_BITER_ELINKNO_ELINK_SHIFT (15U) 1689 #define DMA_TCD_TCD1_BITER_ELINKNO_ELINK_WIDTH (1U) 1690 #define DMA_TCD_TCD1_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD1_BITER_ELINKNO_ELINK_MASK) 1691 /*! @} */ 1692 1693 /*! @name TCD1_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 1694 /*! @{ */ 1695 1696 #define DMA_TCD_TCD1_BITER_ELINKYES_BITER_MASK (0x1FFU) 1697 #define DMA_TCD_TCD1_BITER_ELINKYES_BITER_SHIFT (0U) 1698 #define DMA_TCD_TCD1_BITER_ELINKYES_BITER_WIDTH (9U) 1699 #define DMA_TCD_TCD1_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD1_BITER_ELINKYES_BITER_MASK) 1700 1701 #define DMA_TCD_TCD1_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 1702 #define DMA_TCD_TCD1_BITER_ELINKYES_LINKCH_SHIFT (9U) 1703 #define DMA_TCD_TCD1_BITER_ELINKYES_LINKCH_WIDTH (5U) 1704 #define DMA_TCD_TCD1_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD1_BITER_ELINKYES_LINKCH_MASK) 1705 1706 #define DMA_TCD_TCD1_BITER_ELINKYES_ELINK_MASK (0x8000U) 1707 #define DMA_TCD_TCD1_BITER_ELINKYES_ELINK_SHIFT (15U) 1708 #define DMA_TCD_TCD1_BITER_ELINKYES_ELINK_WIDTH (1U) 1709 #define DMA_TCD_TCD1_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD1_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD1_BITER_ELINKYES_ELINK_MASK) 1710 /*! @} */ 1711 1712 /*! @name CH2_CSR - Channel Control and Status */ 1713 /*! @{ */ 1714 1715 #define DMA_TCD_CH2_CSR_ERQ_MASK (0x1U) 1716 #define DMA_TCD_CH2_CSR_ERQ_SHIFT (0U) 1717 #define DMA_TCD_CH2_CSR_ERQ_WIDTH (1U) 1718 #define DMA_TCD_CH2_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_CSR_ERQ_SHIFT)) & DMA_TCD_CH2_CSR_ERQ_MASK) 1719 1720 #define DMA_TCD_CH2_CSR_EARQ_MASK (0x2U) 1721 #define DMA_TCD_CH2_CSR_EARQ_SHIFT (1U) 1722 #define DMA_TCD_CH2_CSR_EARQ_WIDTH (1U) 1723 #define DMA_TCD_CH2_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_CSR_EARQ_SHIFT)) & DMA_TCD_CH2_CSR_EARQ_MASK) 1724 1725 #define DMA_TCD_CH2_CSR_EEI_MASK (0x4U) 1726 #define DMA_TCD_CH2_CSR_EEI_SHIFT (2U) 1727 #define DMA_TCD_CH2_CSR_EEI_WIDTH (1U) 1728 #define DMA_TCD_CH2_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_CSR_EEI_SHIFT)) & DMA_TCD_CH2_CSR_EEI_MASK) 1729 1730 #define DMA_TCD_CH2_CSR_EBW_MASK (0x8U) 1731 #define DMA_TCD_CH2_CSR_EBW_SHIFT (3U) 1732 #define DMA_TCD_CH2_CSR_EBW_WIDTH (1U) 1733 #define DMA_TCD_CH2_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_CSR_EBW_SHIFT)) & DMA_TCD_CH2_CSR_EBW_MASK) 1734 1735 #define DMA_TCD_CH2_CSR_DONE_MASK (0x40000000U) 1736 #define DMA_TCD_CH2_CSR_DONE_SHIFT (30U) 1737 #define DMA_TCD_CH2_CSR_DONE_WIDTH (1U) 1738 #define DMA_TCD_CH2_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_CSR_DONE_SHIFT)) & DMA_TCD_CH2_CSR_DONE_MASK) 1739 1740 #define DMA_TCD_CH2_CSR_ACTIVE_MASK (0x80000000U) 1741 #define DMA_TCD_CH2_CSR_ACTIVE_SHIFT (31U) 1742 #define DMA_TCD_CH2_CSR_ACTIVE_WIDTH (1U) 1743 #define DMA_TCD_CH2_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH2_CSR_ACTIVE_MASK) 1744 /*! @} */ 1745 1746 /*! @name CH2_ES - Channel Error Status */ 1747 /*! @{ */ 1748 1749 #define DMA_TCD_CH2_ES_DBE_MASK (0x1U) 1750 #define DMA_TCD_CH2_ES_DBE_SHIFT (0U) 1751 #define DMA_TCD_CH2_ES_DBE_WIDTH (1U) 1752 #define DMA_TCD_CH2_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_ES_DBE_SHIFT)) & DMA_TCD_CH2_ES_DBE_MASK) 1753 1754 #define DMA_TCD_CH2_ES_SBE_MASK (0x2U) 1755 #define DMA_TCD_CH2_ES_SBE_SHIFT (1U) 1756 #define DMA_TCD_CH2_ES_SBE_WIDTH (1U) 1757 #define DMA_TCD_CH2_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_ES_SBE_SHIFT)) & DMA_TCD_CH2_ES_SBE_MASK) 1758 1759 #define DMA_TCD_CH2_ES_SGE_MASK (0x4U) 1760 #define DMA_TCD_CH2_ES_SGE_SHIFT (2U) 1761 #define DMA_TCD_CH2_ES_SGE_WIDTH (1U) 1762 #define DMA_TCD_CH2_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_ES_SGE_SHIFT)) & DMA_TCD_CH2_ES_SGE_MASK) 1763 1764 #define DMA_TCD_CH2_ES_NCE_MASK (0x8U) 1765 #define DMA_TCD_CH2_ES_NCE_SHIFT (3U) 1766 #define DMA_TCD_CH2_ES_NCE_WIDTH (1U) 1767 #define DMA_TCD_CH2_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_ES_NCE_SHIFT)) & DMA_TCD_CH2_ES_NCE_MASK) 1768 1769 #define DMA_TCD_CH2_ES_DOE_MASK (0x10U) 1770 #define DMA_TCD_CH2_ES_DOE_SHIFT (4U) 1771 #define DMA_TCD_CH2_ES_DOE_WIDTH (1U) 1772 #define DMA_TCD_CH2_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_ES_DOE_SHIFT)) & DMA_TCD_CH2_ES_DOE_MASK) 1773 1774 #define DMA_TCD_CH2_ES_DAE_MASK (0x20U) 1775 #define DMA_TCD_CH2_ES_DAE_SHIFT (5U) 1776 #define DMA_TCD_CH2_ES_DAE_WIDTH (1U) 1777 #define DMA_TCD_CH2_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_ES_DAE_SHIFT)) & DMA_TCD_CH2_ES_DAE_MASK) 1778 1779 #define DMA_TCD_CH2_ES_SOE_MASK (0x40U) 1780 #define DMA_TCD_CH2_ES_SOE_SHIFT (6U) 1781 #define DMA_TCD_CH2_ES_SOE_WIDTH (1U) 1782 #define DMA_TCD_CH2_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_ES_SOE_SHIFT)) & DMA_TCD_CH2_ES_SOE_MASK) 1783 1784 #define DMA_TCD_CH2_ES_SAE_MASK (0x80U) 1785 #define DMA_TCD_CH2_ES_SAE_SHIFT (7U) 1786 #define DMA_TCD_CH2_ES_SAE_WIDTH (1U) 1787 #define DMA_TCD_CH2_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_ES_SAE_SHIFT)) & DMA_TCD_CH2_ES_SAE_MASK) 1788 1789 #define DMA_TCD_CH2_ES_ERR_MASK (0x80000000U) 1790 #define DMA_TCD_CH2_ES_ERR_SHIFT (31U) 1791 #define DMA_TCD_CH2_ES_ERR_WIDTH (1U) 1792 #define DMA_TCD_CH2_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_ES_ERR_SHIFT)) & DMA_TCD_CH2_ES_ERR_MASK) 1793 /*! @} */ 1794 1795 /*! @name CH2_INT - Channel Interrupt Status */ 1796 /*! @{ */ 1797 1798 #define DMA_TCD_CH2_INT_INT_MASK (0x1U) 1799 #define DMA_TCD_CH2_INT_INT_SHIFT (0U) 1800 #define DMA_TCD_CH2_INT_INT_WIDTH (1U) 1801 #define DMA_TCD_CH2_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_INT_INT_SHIFT)) & DMA_TCD_CH2_INT_INT_MASK) 1802 /*! @} */ 1803 1804 /*! @name CH2_SBR - Channel System Bus */ 1805 /*! @{ */ 1806 1807 #define DMA_TCD_CH2_SBR_MID_MASK (0xFU) 1808 #define DMA_TCD_CH2_SBR_MID_SHIFT (0U) 1809 #define DMA_TCD_CH2_SBR_MID_WIDTH (4U) 1810 #define DMA_TCD_CH2_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_SBR_MID_SHIFT)) & DMA_TCD_CH2_SBR_MID_MASK) 1811 1812 #define DMA_TCD_CH2_SBR_PAL_MASK (0x8000U) 1813 #define DMA_TCD_CH2_SBR_PAL_SHIFT (15U) 1814 #define DMA_TCD_CH2_SBR_PAL_WIDTH (1U) 1815 #define DMA_TCD_CH2_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_SBR_PAL_SHIFT)) & DMA_TCD_CH2_SBR_PAL_MASK) 1816 1817 #define DMA_TCD_CH2_SBR_EMI_MASK (0x10000U) 1818 #define DMA_TCD_CH2_SBR_EMI_SHIFT (16U) 1819 #define DMA_TCD_CH2_SBR_EMI_WIDTH (1U) 1820 #define DMA_TCD_CH2_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_SBR_EMI_SHIFT)) & DMA_TCD_CH2_SBR_EMI_MASK) 1821 1822 #define DMA_TCD_CH2_SBR_ATTR_MASK (0xE0000U) 1823 #define DMA_TCD_CH2_SBR_ATTR_SHIFT (17U) 1824 #define DMA_TCD_CH2_SBR_ATTR_WIDTH (3U) 1825 #define DMA_TCD_CH2_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_SBR_ATTR_SHIFT)) & DMA_TCD_CH2_SBR_ATTR_MASK) 1826 /*! @} */ 1827 1828 /*! @name CH2_PRI - Channel Priority */ 1829 /*! @{ */ 1830 1831 #define DMA_TCD_CH2_PRI_APL_MASK (0x7U) 1832 #define DMA_TCD_CH2_PRI_APL_SHIFT (0U) 1833 #define DMA_TCD_CH2_PRI_APL_WIDTH (3U) 1834 #define DMA_TCD_CH2_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_PRI_APL_SHIFT)) & DMA_TCD_CH2_PRI_APL_MASK) 1835 1836 #define DMA_TCD_CH2_PRI_DPA_MASK (0x40000000U) 1837 #define DMA_TCD_CH2_PRI_DPA_SHIFT (30U) 1838 #define DMA_TCD_CH2_PRI_DPA_WIDTH (1U) 1839 #define DMA_TCD_CH2_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_PRI_DPA_SHIFT)) & DMA_TCD_CH2_PRI_DPA_MASK) 1840 1841 #define DMA_TCD_CH2_PRI_ECP_MASK (0x80000000U) 1842 #define DMA_TCD_CH2_PRI_ECP_SHIFT (31U) 1843 #define DMA_TCD_CH2_PRI_ECP_WIDTH (1U) 1844 #define DMA_TCD_CH2_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH2_PRI_ECP_SHIFT)) & DMA_TCD_CH2_PRI_ECP_MASK) 1845 /*! @} */ 1846 1847 /*! @name TCD2_SADDR - TCD Source Address */ 1848 /*! @{ */ 1849 1850 #define DMA_TCD_TCD2_SADDR_SADDR_MASK (0xFFFFFFFFU) 1851 #define DMA_TCD_TCD2_SADDR_SADDR_SHIFT (0U) 1852 #define DMA_TCD_TCD2_SADDR_SADDR_WIDTH (32U) 1853 #define DMA_TCD_TCD2_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD2_SADDR_SADDR_MASK) 1854 /*! @} */ 1855 1856 /*! @name TCD2_SOFF - TCD Signed Source Address Offset */ 1857 /*! @{ */ 1858 1859 #define DMA_TCD_TCD2_SOFF_SOFF_MASK (0xFFFFU) 1860 #define DMA_TCD_TCD2_SOFF_SOFF_SHIFT (0U) 1861 #define DMA_TCD_TCD2_SOFF_SOFF_WIDTH (16U) 1862 #define DMA_TCD_TCD2_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD2_SOFF_SOFF_MASK) 1863 /*! @} */ 1864 1865 /*! @name TCD2_ATTR - TCD Transfer Attributes */ 1866 /*! @{ */ 1867 1868 #define DMA_TCD_TCD2_ATTR_DSIZE_MASK (0x7U) 1869 #define DMA_TCD_TCD2_ATTR_DSIZE_SHIFT (0U) 1870 #define DMA_TCD_TCD2_ATTR_DSIZE_WIDTH (3U) 1871 #define DMA_TCD_TCD2_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD2_ATTR_DSIZE_MASK) 1872 1873 #define DMA_TCD_TCD2_ATTR_DMOD_MASK (0xF8U) 1874 #define DMA_TCD_TCD2_ATTR_DMOD_SHIFT (3U) 1875 #define DMA_TCD_TCD2_ATTR_DMOD_WIDTH (5U) 1876 #define DMA_TCD_TCD2_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD2_ATTR_DMOD_MASK) 1877 1878 #define DMA_TCD_TCD2_ATTR_SSIZE_MASK (0x700U) 1879 #define DMA_TCD_TCD2_ATTR_SSIZE_SHIFT (8U) 1880 #define DMA_TCD_TCD2_ATTR_SSIZE_WIDTH (3U) 1881 #define DMA_TCD_TCD2_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD2_ATTR_SSIZE_MASK) 1882 1883 #define DMA_TCD_TCD2_ATTR_SMOD_MASK (0xF800U) 1884 #define DMA_TCD_TCD2_ATTR_SMOD_SHIFT (11U) 1885 #define DMA_TCD_TCD2_ATTR_SMOD_WIDTH (5U) 1886 #define DMA_TCD_TCD2_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD2_ATTR_SMOD_MASK) 1887 /*! @} */ 1888 1889 /*! @name TCD2_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 1890 /*! @{ */ 1891 1892 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 1893 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 1894 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 1895 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD2_NBYTES_MLOFFNO_NBYTES_MASK) 1896 1897 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 1898 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 1899 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 1900 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD2_NBYTES_MLOFFNO_DMLOE_MASK) 1901 1902 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 1903 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 1904 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 1905 #define DMA_TCD_TCD2_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD2_NBYTES_MLOFFNO_SMLOE_MASK) 1906 /*! @} */ 1907 1908 /*! @name TCD2_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 1909 /*! @{ */ 1910 1911 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 1912 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 1913 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 1914 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD2_NBYTES_MLOFFYES_NBYTES_MASK) 1915 1916 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 1917 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 1918 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 1919 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD2_NBYTES_MLOFFYES_MLOFF_MASK) 1920 1921 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 1922 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 1923 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 1924 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD2_NBYTES_MLOFFYES_DMLOE_MASK) 1925 1926 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 1927 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 1928 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 1929 #define DMA_TCD_TCD2_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD2_NBYTES_MLOFFYES_SMLOE_MASK) 1930 /*! @} */ 1931 1932 /*! @name TCD2_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 1933 /*! @{ */ 1934 1935 #define DMA_TCD_TCD2_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 1936 #define DMA_TCD_TCD2_SLAST_SDA_SLAST_SDA_SHIFT (0U) 1937 #define DMA_TCD_TCD2_SLAST_SDA_SLAST_SDA_WIDTH (32U) 1938 #define DMA_TCD_TCD2_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD2_SLAST_SDA_SLAST_SDA_MASK) 1939 /*! @} */ 1940 1941 /*! @name TCD2_DADDR - TCD Destination Address */ 1942 /*! @{ */ 1943 1944 #define DMA_TCD_TCD2_DADDR_DADDR_MASK (0xFFFFFFFFU) 1945 #define DMA_TCD_TCD2_DADDR_DADDR_SHIFT (0U) 1946 #define DMA_TCD_TCD2_DADDR_DADDR_WIDTH (32U) 1947 #define DMA_TCD_TCD2_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD2_DADDR_DADDR_MASK) 1948 /*! @} */ 1949 1950 /*! @name TCD2_DOFF - TCD Signed Destination Address Offset */ 1951 /*! @{ */ 1952 1953 #define DMA_TCD_TCD2_DOFF_DOFF_MASK (0xFFFFU) 1954 #define DMA_TCD_TCD2_DOFF_DOFF_SHIFT (0U) 1955 #define DMA_TCD_TCD2_DOFF_DOFF_WIDTH (16U) 1956 #define DMA_TCD_TCD2_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD2_DOFF_DOFF_MASK) 1957 /*! @} */ 1958 1959 /*! @name TCD2_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 1960 /*! @{ */ 1961 1962 #define DMA_TCD_TCD2_CITER_ELINKNO_CITER_MASK (0x7FFFU) 1963 #define DMA_TCD_TCD2_CITER_ELINKNO_CITER_SHIFT (0U) 1964 #define DMA_TCD_TCD2_CITER_ELINKNO_CITER_WIDTH (15U) 1965 #define DMA_TCD_TCD2_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD2_CITER_ELINKNO_CITER_MASK) 1966 1967 #define DMA_TCD_TCD2_CITER_ELINKNO_ELINK_MASK (0x8000U) 1968 #define DMA_TCD_TCD2_CITER_ELINKNO_ELINK_SHIFT (15U) 1969 #define DMA_TCD_TCD2_CITER_ELINKNO_ELINK_WIDTH (1U) 1970 #define DMA_TCD_TCD2_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD2_CITER_ELINKNO_ELINK_MASK) 1971 /*! @} */ 1972 1973 /*! @name TCD2_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 1974 /*! @{ */ 1975 1976 #define DMA_TCD_TCD2_CITER_ELINKYES_CITER_MASK (0x1FFU) 1977 #define DMA_TCD_TCD2_CITER_ELINKYES_CITER_SHIFT (0U) 1978 #define DMA_TCD_TCD2_CITER_ELINKYES_CITER_WIDTH (9U) 1979 #define DMA_TCD_TCD2_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD2_CITER_ELINKYES_CITER_MASK) 1980 1981 #define DMA_TCD_TCD2_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 1982 #define DMA_TCD_TCD2_CITER_ELINKYES_LINKCH_SHIFT (9U) 1983 #define DMA_TCD_TCD2_CITER_ELINKYES_LINKCH_WIDTH (5U) 1984 #define DMA_TCD_TCD2_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD2_CITER_ELINKYES_LINKCH_MASK) 1985 1986 #define DMA_TCD_TCD2_CITER_ELINKYES_ELINK_MASK (0x8000U) 1987 #define DMA_TCD_TCD2_CITER_ELINKYES_ELINK_SHIFT (15U) 1988 #define DMA_TCD_TCD2_CITER_ELINKYES_ELINK_WIDTH (1U) 1989 #define DMA_TCD_TCD2_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD2_CITER_ELINKYES_ELINK_MASK) 1990 /*! @} */ 1991 1992 /*! @name TCD2_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 1993 /*! @{ */ 1994 1995 #define DMA_TCD_TCD2_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 1996 #define DMA_TCD_TCD2_DLAST_SGA_DLAST_SGA_SHIFT (0U) 1997 #define DMA_TCD_TCD2_DLAST_SGA_DLAST_SGA_WIDTH (32U) 1998 #define DMA_TCD_TCD2_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD2_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD2_DLAST_SGA_DLAST_SGA_MASK) 1999 /*! @} */ 2000 2001 /*! @name TCD2_CSR - TCD Control and Status */ 2002 /*! @{ */ 2003 2004 #define DMA_TCD_TCD2_CSR_START_MASK (0x1U) 2005 #define DMA_TCD_TCD2_CSR_START_SHIFT (0U) 2006 #define DMA_TCD_TCD2_CSR_START_WIDTH (1U) 2007 #define DMA_TCD_TCD2_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CSR_START_SHIFT)) & DMA_TCD_TCD2_CSR_START_MASK) 2008 2009 #define DMA_TCD_TCD2_CSR_INTMAJOR_MASK (0x2U) 2010 #define DMA_TCD_TCD2_CSR_INTMAJOR_SHIFT (1U) 2011 #define DMA_TCD_TCD2_CSR_INTMAJOR_WIDTH (1U) 2012 #define DMA_TCD_TCD2_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD2_CSR_INTMAJOR_MASK) 2013 2014 #define DMA_TCD_TCD2_CSR_INTHALF_MASK (0x4U) 2015 #define DMA_TCD_TCD2_CSR_INTHALF_SHIFT (2U) 2016 #define DMA_TCD_TCD2_CSR_INTHALF_WIDTH (1U) 2017 #define DMA_TCD_TCD2_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD2_CSR_INTHALF_MASK) 2018 2019 #define DMA_TCD_TCD2_CSR_DREQ_MASK (0x8U) 2020 #define DMA_TCD_TCD2_CSR_DREQ_SHIFT (3U) 2021 #define DMA_TCD_TCD2_CSR_DREQ_WIDTH (1U) 2022 #define DMA_TCD_TCD2_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CSR_DREQ_SHIFT)) & DMA_TCD_TCD2_CSR_DREQ_MASK) 2023 2024 #define DMA_TCD_TCD2_CSR_ESG_MASK (0x10U) 2025 #define DMA_TCD_TCD2_CSR_ESG_SHIFT (4U) 2026 #define DMA_TCD_TCD2_CSR_ESG_WIDTH (1U) 2027 #define DMA_TCD_TCD2_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CSR_ESG_SHIFT)) & DMA_TCD_TCD2_CSR_ESG_MASK) 2028 2029 #define DMA_TCD_TCD2_CSR_MAJORELINK_MASK (0x20U) 2030 #define DMA_TCD_TCD2_CSR_MAJORELINK_SHIFT (5U) 2031 #define DMA_TCD_TCD2_CSR_MAJORELINK_WIDTH (1U) 2032 #define DMA_TCD_TCD2_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD2_CSR_MAJORELINK_MASK) 2033 2034 #define DMA_TCD_TCD2_CSR_EEOP_MASK (0x40U) 2035 #define DMA_TCD_TCD2_CSR_EEOP_SHIFT (6U) 2036 #define DMA_TCD_TCD2_CSR_EEOP_WIDTH (1U) 2037 #define DMA_TCD_TCD2_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CSR_EEOP_SHIFT)) & DMA_TCD_TCD2_CSR_EEOP_MASK) 2038 2039 #define DMA_TCD_TCD2_CSR_ESDA_MASK (0x80U) 2040 #define DMA_TCD_TCD2_CSR_ESDA_SHIFT (7U) 2041 #define DMA_TCD_TCD2_CSR_ESDA_WIDTH (1U) 2042 #define DMA_TCD_TCD2_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CSR_ESDA_SHIFT)) & DMA_TCD_TCD2_CSR_ESDA_MASK) 2043 2044 #define DMA_TCD_TCD2_CSR_MAJORLINKCH_MASK (0x1F00U) 2045 #define DMA_TCD_TCD2_CSR_MAJORLINKCH_SHIFT (8U) 2046 #define DMA_TCD_TCD2_CSR_MAJORLINKCH_WIDTH (5U) 2047 #define DMA_TCD_TCD2_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD2_CSR_MAJORLINKCH_MASK) 2048 2049 #define DMA_TCD_TCD2_CSR_BWC_MASK (0xC000U) 2050 #define DMA_TCD_TCD2_CSR_BWC_SHIFT (14U) 2051 #define DMA_TCD_TCD2_CSR_BWC_WIDTH (2U) 2052 #define DMA_TCD_TCD2_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_CSR_BWC_SHIFT)) & DMA_TCD_TCD2_CSR_BWC_MASK) 2053 /*! @} */ 2054 2055 /*! @name TCD2_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 2056 /*! @{ */ 2057 2058 #define DMA_TCD_TCD2_BITER_ELINKNO_BITER_MASK (0x7FFFU) 2059 #define DMA_TCD_TCD2_BITER_ELINKNO_BITER_SHIFT (0U) 2060 #define DMA_TCD_TCD2_BITER_ELINKNO_BITER_WIDTH (15U) 2061 #define DMA_TCD_TCD2_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD2_BITER_ELINKNO_BITER_MASK) 2062 2063 #define DMA_TCD_TCD2_BITER_ELINKNO_ELINK_MASK (0x8000U) 2064 #define DMA_TCD_TCD2_BITER_ELINKNO_ELINK_SHIFT (15U) 2065 #define DMA_TCD_TCD2_BITER_ELINKNO_ELINK_WIDTH (1U) 2066 #define DMA_TCD_TCD2_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD2_BITER_ELINKNO_ELINK_MASK) 2067 /*! @} */ 2068 2069 /*! @name TCD2_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 2070 /*! @{ */ 2071 2072 #define DMA_TCD_TCD2_BITER_ELINKYES_BITER_MASK (0x1FFU) 2073 #define DMA_TCD_TCD2_BITER_ELINKYES_BITER_SHIFT (0U) 2074 #define DMA_TCD_TCD2_BITER_ELINKYES_BITER_WIDTH (9U) 2075 #define DMA_TCD_TCD2_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD2_BITER_ELINKYES_BITER_MASK) 2076 2077 #define DMA_TCD_TCD2_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 2078 #define DMA_TCD_TCD2_BITER_ELINKYES_LINKCH_SHIFT (9U) 2079 #define DMA_TCD_TCD2_BITER_ELINKYES_LINKCH_WIDTH (5U) 2080 #define DMA_TCD_TCD2_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD2_BITER_ELINKYES_LINKCH_MASK) 2081 2082 #define DMA_TCD_TCD2_BITER_ELINKYES_ELINK_MASK (0x8000U) 2083 #define DMA_TCD_TCD2_BITER_ELINKYES_ELINK_SHIFT (15U) 2084 #define DMA_TCD_TCD2_BITER_ELINKYES_ELINK_WIDTH (1U) 2085 #define DMA_TCD_TCD2_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD2_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD2_BITER_ELINKYES_ELINK_MASK) 2086 /*! @} */ 2087 2088 /*! @name CH3_CSR - Channel Control and Status */ 2089 /*! @{ */ 2090 2091 #define DMA_TCD_CH3_CSR_ERQ_MASK (0x1U) 2092 #define DMA_TCD_CH3_CSR_ERQ_SHIFT (0U) 2093 #define DMA_TCD_CH3_CSR_ERQ_WIDTH (1U) 2094 #define DMA_TCD_CH3_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_CSR_ERQ_SHIFT)) & DMA_TCD_CH3_CSR_ERQ_MASK) 2095 2096 #define DMA_TCD_CH3_CSR_EARQ_MASK (0x2U) 2097 #define DMA_TCD_CH3_CSR_EARQ_SHIFT (1U) 2098 #define DMA_TCD_CH3_CSR_EARQ_WIDTH (1U) 2099 #define DMA_TCD_CH3_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_CSR_EARQ_SHIFT)) & DMA_TCD_CH3_CSR_EARQ_MASK) 2100 2101 #define DMA_TCD_CH3_CSR_EEI_MASK (0x4U) 2102 #define DMA_TCD_CH3_CSR_EEI_SHIFT (2U) 2103 #define DMA_TCD_CH3_CSR_EEI_WIDTH (1U) 2104 #define DMA_TCD_CH3_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_CSR_EEI_SHIFT)) & DMA_TCD_CH3_CSR_EEI_MASK) 2105 2106 #define DMA_TCD_CH3_CSR_EBW_MASK (0x8U) 2107 #define DMA_TCD_CH3_CSR_EBW_SHIFT (3U) 2108 #define DMA_TCD_CH3_CSR_EBW_WIDTH (1U) 2109 #define DMA_TCD_CH3_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_CSR_EBW_SHIFT)) & DMA_TCD_CH3_CSR_EBW_MASK) 2110 2111 #define DMA_TCD_CH3_CSR_DONE_MASK (0x40000000U) 2112 #define DMA_TCD_CH3_CSR_DONE_SHIFT (30U) 2113 #define DMA_TCD_CH3_CSR_DONE_WIDTH (1U) 2114 #define DMA_TCD_CH3_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_CSR_DONE_SHIFT)) & DMA_TCD_CH3_CSR_DONE_MASK) 2115 2116 #define DMA_TCD_CH3_CSR_ACTIVE_MASK (0x80000000U) 2117 #define DMA_TCD_CH3_CSR_ACTIVE_SHIFT (31U) 2118 #define DMA_TCD_CH3_CSR_ACTIVE_WIDTH (1U) 2119 #define DMA_TCD_CH3_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH3_CSR_ACTIVE_MASK) 2120 /*! @} */ 2121 2122 /*! @name CH3_ES - Channel Error Status */ 2123 /*! @{ */ 2124 2125 #define DMA_TCD_CH3_ES_DBE_MASK (0x1U) 2126 #define DMA_TCD_CH3_ES_DBE_SHIFT (0U) 2127 #define DMA_TCD_CH3_ES_DBE_WIDTH (1U) 2128 #define DMA_TCD_CH3_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_ES_DBE_SHIFT)) & DMA_TCD_CH3_ES_DBE_MASK) 2129 2130 #define DMA_TCD_CH3_ES_SBE_MASK (0x2U) 2131 #define DMA_TCD_CH3_ES_SBE_SHIFT (1U) 2132 #define DMA_TCD_CH3_ES_SBE_WIDTH (1U) 2133 #define DMA_TCD_CH3_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_ES_SBE_SHIFT)) & DMA_TCD_CH3_ES_SBE_MASK) 2134 2135 #define DMA_TCD_CH3_ES_SGE_MASK (0x4U) 2136 #define DMA_TCD_CH3_ES_SGE_SHIFT (2U) 2137 #define DMA_TCD_CH3_ES_SGE_WIDTH (1U) 2138 #define DMA_TCD_CH3_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_ES_SGE_SHIFT)) & DMA_TCD_CH3_ES_SGE_MASK) 2139 2140 #define DMA_TCD_CH3_ES_NCE_MASK (0x8U) 2141 #define DMA_TCD_CH3_ES_NCE_SHIFT (3U) 2142 #define DMA_TCD_CH3_ES_NCE_WIDTH (1U) 2143 #define DMA_TCD_CH3_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_ES_NCE_SHIFT)) & DMA_TCD_CH3_ES_NCE_MASK) 2144 2145 #define DMA_TCD_CH3_ES_DOE_MASK (0x10U) 2146 #define DMA_TCD_CH3_ES_DOE_SHIFT (4U) 2147 #define DMA_TCD_CH3_ES_DOE_WIDTH (1U) 2148 #define DMA_TCD_CH3_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_ES_DOE_SHIFT)) & DMA_TCD_CH3_ES_DOE_MASK) 2149 2150 #define DMA_TCD_CH3_ES_DAE_MASK (0x20U) 2151 #define DMA_TCD_CH3_ES_DAE_SHIFT (5U) 2152 #define DMA_TCD_CH3_ES_DAE_WIDTH (1U) 2153 #define DMA_TCD_CH3_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_ES_DAE_SHIFT)) & DMA_TCD_CH3_ES_DAE_MASK) 2154 2155 #define DMA_TCD_CH3_ES_SOE_MASK (0x40U) 2156 #define DMA_TCD_CH3_ES_SOE_SHIFT (6U) 2157 #define DMA_TCD_CH3_ES_SOE_WIDTH (1U) 2158 #define DMA_TCD_CH3_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_ES_SOE_SHIFT)) & DMA_TCD_CH3_ES_SOE_MASK) 2159 2160 #define DMA_TCD_CH3_ES_SAE_MASK (0x80U) 2161 #define DMA_TCD_CH3_ES_SAE_SHIFT (7U) 2162 #define DMA_TCD_CH3_ES_SAE_WIDTH (1U) 2163 #define DMA_TCD_CH3_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_ES_SAE_SHIFT)) & DMA_TCD_CH3_ES_SAE_MASK) 2164 2165 #define DMA_TCD_CH3_ES_ERR_MASK (0x80000000U) 2166 #define DMA_TCD_CH3_ES_ERR_SHIFT (31U) 2167 #define DMA_TCD_CH3_ES_ERR_WIDTH (1U) 2168 #define DMA_TCD_CH3_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_ES_ERR_SHIFT)) & DMA_TCD_CH3_ES_ERR_MASK) 2169 /*! @} */ 2170 2171 /*! @name CH3_INT - Channel Interrupt Status */ 2172 /*! @{ */ 2173 2174 #define DMA_TCD_CH3_INT_INT_MASK (0x1U) 2175 #define DMA_TCD_CH3_INT_INT_SHIFT (0U) 2176 #define DMA_TCD_CH3_INT_INT_WIDTH (1U) 2177 #define DMA_TCD_CH3_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_INT_INT_SHIFT)) & DMA_TCD_CH3_INT_INT_MASK) 2178 /*! @} */ 2179 2180 /*! @name CH3_SBR - Channel System Bus */ 2181 /*! @{ */ 2182 2183 #define DMA_TCD_CH3_SBR_MID_MASK (0xFU) 2184 #define DMA_TCD_CH3_SBR_MID_SHIFT (0U) 2185 #define DMA_TCD_CH3_SBR_MID_WIDTH (4U) 2186 #define DMA_TCD_CH3_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_SBR_MID_SHIFT)) & DMA_TCD_CH3_SBR_MID_MASK) 2187 2188 #define DMA_TCD_CH3_SBR_PAL_MASK (0x8000U) 2189 #define DMA_TCD_CH3_SBR_PAL_SHIFT (15U) 2190 #define DMA_TCD_CH3_SBR_PAL_WIDTH (1U) 2191 #define DMA_TCD_CH3_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_SBR_PAL_SHIFT)) & DMA_TCD_CH3_SBR_PAL_MASK) 2192 2193 #define DMA_TCD_CH3_SBR_EMI_MASK (0x10000U) 2194 #define DMA_TCD_CH3_SBR_EMI_SHIFT (16U) 2195 #define DMA_TCD_CH3_SBR_EMI_WIDTH (1U) 2196 #define DMA_TCD_CH3_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_SBR_EMI_SHIFT)) & DMA_TCD_CH3_SBR_EMI_MASK) 2197 2198 #define DMA_TCD_CH3_SBR_ATTR_MASK (0xE0000U) 2199 #define DMA_TCD_CH3_SBR_ATTR_SHIFT (17U) 2200 #define DMA_TCD_CH3_SBR_ATTR_WIDTH (3U) 2201 #define DMA_TCD_CH3_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_SBR_ATTR_SHIFT)) & DMA_TCD_CH3_SBR_ATTR_MASK) 2202 /*! @} */ 2203 2204 /*! @name CH3_PRI - Channel Priority */ 2205 /*! @{ */ 2206 2207 #define DMA_TCD_CH3_PRI_APL_MASK (0x7U) 2208 #define DMA_TCD_CH3_PRI_APL_SHIFT (0U) 2209 #define DMA_TCD_CH3_PRI_APL_WIDTH (3U) 2210 #define DMA_TCD_CH3_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_PRI_APL_SHIFT)) & DMA_TCD_CH3_PRI_APL_MASK) 2211 2212 #define DMA_TCD_CH3_PRI_DPA_MASK (0x40000000U) 2213 #define DMA_TCD_CH3_PRI_DPA_SHIFT (30U) 2214 #define DMA_TCD_CH3_PRI_DPA_WIDTH (1U) 2215 #define DMA_TCD_CH3_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_PRI_DPA_SHIFT)) & DMA_TCD_CH3_PRI_DPA_MASK) 2216 2217 #define DMA_TCD_CH3_PRI_ECP_MASK (0x80000000U) 2218 #define DMA_TCD_CH3_PRI_ECP_SHIFT (31U) 2219 #define DMA_TCD_CH3_PRI_ECP_WIDTH (1U) 2220 #define DMA_TCD_CH3_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH3_PRI_ECP_SHIFT)) & DMA_TCD_CH3_PRI_ECP_MASK) 2221 /*! @} */ 2222 2223 /*! @name TCD3_SADDR - TCD Source Address */ 2224 /*! @{ */ 2225 2226 #define DMA_TCD_TCD3_SADDR_SADDR_MASK (0xFFFFFFFFU) 2227 #define DMA_TCD_TCD3_SADDR_SADDR_SHIFT (0U) 2228 #define DMA_TCD_TCD3_SADDR_SADDR_WIDTH (32U) 2229 #define DMA_TCD_TCD3_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD3_SADDR_SADDR_MASK) 2230 /*! @} */ 2231 2232 /*! @name TCD3_SOFF - TCD Signed Source Address Offset */ 2233 /*! @{ */ 2234 2235 #define DMA_TCD_TCD3_SOFF_SOFF_MASK (0xFFFFU) 2236 #define DMA_TCD_TCD3_SOFF_SOFF_SHIFT (0U) 2237 #define DMA_TCD_TCD3_SOFF_SOFF_WIDTH (16U) 2238 #define DMA_TCD_TCD3_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD3_SOFF_SOFF_MASK) 2239 /*! @} */ 2240 2241 /*! @name TCD3_ATTR - TCD Transfer Attributes */ 2242 /*! @{ */ 2243 2244 #define DMA_TCD_TCD3_ATTR_DSIZE_MASK (0x7U) 2245 #define DMA_TCD_TCD3_ATTR_DSIZE_SHIFT (0U) 2246 #define DMA_TCD_TCD3_ATTR_DSIZE_WIDTH (3U) 2247 #define DMA_TCD_TCD3_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD3_ATTR_DSIZE_MASK) 2248 2249 #define DMA_TCD_TCD3_ATTR_DMOD_MASK (0xF8U) 2250 #define DMA_TCD_TCD3_ATTR_DMOD_SHIFT (3U) 2251 #define DMA_TCD_TCD3_ATTR_DMOD_WIDTH (5U) 2252 #define DMA_TCD_TCD3_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD3_ATTR_DMOD_MASK) 2253 2254 #define DMA_TCD_TCD3_ATTR_SSIZE_MASK (0x700U) 2255 #define DMA_TCD_TCD3_ATTR_SSIZE_SHIFT (8U) 2256 #define DMA_TCD_TCD3_ATTR_SSIZE_WIDTH (3U) 2257 #define DMA_TCD_TCD3_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD3_ATTR_SSIZE_MASK) 2258 2259 #define DMA_TCD_TCD3_ATTR_SMOD_MASK (0xF800U) 2260 #define DMA_TCD_TCD3_ATTR_SMOD_SHIFT (11U) 2261 #define DMA_TCD_TCD3_ATTR_SMOD_WIDTH (5U) 2262 #define DMA_TCD_TCD3_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD3_ATTR_SMOD_MASK) 2263 /*! @} */ 2264 2265 /*! @name TCD3_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 2266 /*! @{ */ 2267 2268 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 2269 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 2270 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 2271 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD3_NBYTES_MLOFFNO_NBYTES_MASK) 2272 2273 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 2274 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 2275 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 2276 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD3_NBYTES_MLOFFNO_DMLOE_MASK) 2277 2278 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 2279 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 2280 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 2281 #define DMA_TCD_TCD3_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD3_NBYTES_MLOFFNO_SMLOE_MASK) 2282 /*! @} */ 2283 2284 /*! @name TCD3_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 2285 /*! @{ */ 2286 2287 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 2288 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 2289 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 2290 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD3_NBYTES_MLOFFYES_NBYTES_MASK) 2291 2292 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 2293 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 2294 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 2295 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD3_NBYTES_MLOFFYES_MLOFF_MASK) 2296 2297 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 2298 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 2299 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 2300 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD3_NBYTES_MLOFFYES_DMLOE_MASK) 2301 2302 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 2303 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 2304 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 2305 #define DMA_TCD_TCD3_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD3_NBYTES_MLOFFYES_SMLOE_MASK) 2306 /*! @} */ 2307 2308 /*! @name TCD3_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 2309 /*! @{ */ 2310 2311 #define DMA_TCD_TCD3_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 2312 #define DMA_TCD_TCD3_SLAST_SDA_SLAST_SDA_SHIFT (0U) 2313 #define DMA_TCD_TCD3_SLAST_SDA_SLAST_SDA_WIDTH (32U) 2314 #define DMA_TCD_TCD3_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD3_SLAST_SDA_SLAST_SDA_MASK) 2315 /*! @} */ 2316 2317 /*! @name TCD3_DADDR - TCD Destination Address */ 2318 /*! @{ */ 2319 2320 #define DMA_TCD_TCD3_DADDR_DADDR_MASK (0xFFFFFFFFU) 2321 #define DMA_TCD_TCD3_DADDR_DADDR_SHIFT (0U) 2322 #define DMA_TCD_TCD3_DADDR_DADDR_WIDTH (32U) 2323 #define DMA_TCD_TCD3_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD3_DADDR_DADDR_MASK) 2324 /*! @} */ 2325 2326 /*! @name TCD3_DOFF - TCD Signed Destination Address Offset */ 2327 /*! @{ */ 2328 2329 #define DMA_TCD_TCD3_DOFF_DOFF_MASK (0xFFFFU) 2330 #define DMA_TCD_TCD3_DOFF_DOFF_SHIFT (0U) 2331 #define DMA_TCD_TCD3_DOFF_DOFF_WIDTH (16U) 2332 #define DMA_TCD_TCD3_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD3_DOFF_DOFF_MASK) 2333 /*! @} */ 2334 2335 /*! @name TCD3_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 2336 /*! @{ */ 2337 2338 #define DMA_TCD_TCD3_CITER_ELINKNO_CITER_MASK (0x7FFFU) 2339 #define DMA_TCD_TCD3_CITER_ELINKNO_CITER_SHIFT (0U) 2340 #define DMA_TCD_TCD3_CITER_ELINKNO_CITER_WIDTH (15U) 2341 #define DMA_TCD_TCD3_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD3_CITER_ELINKNO_CITER_MASK) 2342 2343 #define DMA_TCD_TCD3_CITER_ELINKNO_ELINK_MASK (0x8000U) 2344 #define DMA_TCD_TCD3_CITER_ELINKNO_ELINK_SHIFT (15U) 2345 #define DMA_TCD_TCD3_CITER_ELINKNO_ELINK_WIDTH (1U) 2346 #define DMA_TCD_TCD3_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD3_CITER_ELINKNO_ELINK_MASK) 2347 /*! @} */ 2348 2349 /*! @name TCD3_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 2350 /*! @{ */ 2351 2352 #define DMA_TCD_TCD3_CITER_ELINKYES_CITER_MASK (0x1FFU) 2353 #define DMA_TCD_TCD3_CITER_ELINKYES_CITER_SHIFT (0U) 2354 #define DMA_TCD_TCD3_CITER_ELINKYES_CITER_WIDTH (9U) 2355 #define DMA_TCD_TCD3_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD3_CITER_ELINKYES_CITER_MASK) 2356 2357 #define DMA_TCD_TCD3_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 2358 #define DMA_TCD_TCD3_CITER_ELINKYES_LINKCH_SHIFT (9U) 2359 #define DMA_TCD_TCD3_CITER_ELINKYES_LINKCH_WIDTH (5U) 2360 #define DMA_TCD_TCD3_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD3_CITER_ELINKYES_LINKCH_MASK) 2361 2362 #define DMA_TCD_TCD3_CITER_ELINKYES_ELINK_MASK (0x8000U) 2363 #define DMA_TCD_TCD3_CITER_ELINKYES_ELINK_SHIFT (15U) 2364 #define DMA_TCD_TCD3_CITER_ELINKYES_ELINK_WIDTH (1U) 2365 #define DMA_TCD_TCD3_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD3_CITER_ELINKYES_ELINK_MASK) 2366 /*! @} */ 2367 2368 /*! @name TCD3_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 2369 /*! @{ */ 2370 2371 #define DMA_TCD_TCD3_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 2372 #define DMA_TCD_TCD3_DLAST_SGA_DLAST_SGA_SHIFT (0U) 2373 #define DMA_TCD_TCD3_DLAST_SGA_DLAST_SGA_WIDTH (32U) 2374 #define DMA_TCD_TCD3_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD3_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD3_DLAST_SGA_DLAST_SGA_MASK) 2375 /*! @} */ 2376 2377 /*! @name TCD3_CSR - TCD Control and Status */ 2378 /*! @{ */ 2379 2380 #define DMA_TCD_TCD3_CSR_START_MASK (0x1U) 2381 #define DMA_TCD_TCD3_CSR_START_SHIFT (0U) 2382 #define DMA_TCD_TCD3_CSR_START_WIDTH (1U) 2383 #define DMA_TCD_TCD3_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CSR_START_SHIFT)) & DMA_TCD_TCD3_CSR_START_MASK) 2384 2385 #define DMA_TCD_TCD3_CSR_INTMAJOR_MASK (0x2U) 2386 #define DMA_TCD_TCD3_CSR_INTMAJOR_SHIFT (1U) 2387 #define DMA_TCD_TCD3_CSR_INTMAJOR_WIDTH (1U) 2388 #define DMA_TCD_TCD3_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD3_CSR_INTMAJOR_MASK) 2389 2390 #define DMA_TCD_TCD3_CSR_INTHALF_MASK (0x4U) 2391 #define DMA_TCD_TCD3_CSR_INTHALF_SHIFT (2U) 2392 #define DMA_TCD_TCD3_CSR_INTHALF_WIDTH (1U) 2393 #define DMA_TCD_TCD3_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD3_CSR_INTHALF_MASK) 2394 2395 #define DMA_TCD_TCD3_CSR_DREQ_MASK (0x8U) 2396 #define DMA_TCD_TCD3_CSR_DREQ_SHIFT (3U) 2397 #define DMA_TCD_TCD3_CSR_DREQ_WIDTH (1U) 2398 #define DMA_TCD_TCD3_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CSR_DREQ_SHIFT)) & DMA_TCD_TCD3_CSR_DREQ_MASK) 2399 2400 #define DMA_TCD_TCD3_CSR_ESG_MASK (0x10U) 2401 #define DMA_TCD_TCD3_CSR_ESG_SHIFT (4U) 2402 #define DMA_TCD_TCD3_CSR_ESG_WIDTH (1U) 2403 #define DMA_TCD_TCD3_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CSR_ESG_SHIFT)) & DMA_TCD_TCD3_CSR_ESG_MASK) 2404 2405 #define DMA_TCD_TCD3_CSR_MAJORELINK_MASK (0x20U) 2406 #define DMA_TCD_TCD3_CSR_MAJORELINK_SHIFT (5U) 2407 #define DMA_TCD_TCD3_CSR_MAJORELINK_WIDTH (1U) 2408 #define DMA_TCD_TCD3_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD3_CSR_MAJORELINK_MASK) 2409 2410 #define DMA_TCD_TCD3_CSR_EEOP_MASK (0x40U) 2411 #define DMA_TCD_TCD3_CSR_EEOP_SHIFT (6U) 2412 #define DMA_TCD_TCD3_CSR_EEOP_WIDTH (1U) 2413 #define DMA_TCD_TCD3_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CSR_EEOP_SHIFT)) & DMA_TCD_TCD3_CSR_EEOP_MASK) 2414 2415 #define DMA_TCD_TCD3_CSR_ESDA_MASK (0x80U) 2416 #define DMA_TCD_TCD3_CSR_ESDA_SHIFT (7U) 2417 #define DMA_TCD_TCD3_CSR_ESDA_WIDTH (1U) 2418 #define DMA_TCD_TCD3_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CSR_ESDA_SHIFT)) & DMA_TCD_TCD3_CSR_ESDA_MASK) 2419 2420 #define DMA_TCD_TCD3_CSR_MAJORLINKCH_MASK (0x1F00U) 2421 #define DMA_TCD_TCD3_CSR_MAJORLINKCH_SHIFT (8U) 2422 #define DMA_TCD_TCD3_CSR_MAJORLINKCH_WIDTH (5U) 2423 #define DMA_TCD_TCD3_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD3_CSR_MAJORLINKCH_MASK) 2424 2425 #define DMA_TCD_TCD3_CSR_BWC_MASK (0xC000U) 2426 #define DMA_TCD_TCD3_CSR_BWC_SHIFT (14U) 2427 #define DMA_TCD_TCD3_CSR_BWC_WIDTH (2U) 2428 #define DMA_TCD_TCD3_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_CSR_BWC_SHIFT)) & DMA_TCD_TCD3_CSR_BWC_MASK) 2429 /*! @} */ 2430 2431 /*! @name TCD3_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 2432 /*! @{ */ 2433 2434 #define DMA_TCD_TCD3_BITER_ELINKNO_BITER_MASK (0x7FFFU) 2435 #define DMA_TCD_TCD3_BITER_ELINKNO_BITER_SHIFT (0U) 2436 #define DMA_TCD_TCD3_BITER_ELINKNO_BITER_WIDTH (15U) 2437 #define DMA_TCD_TCD3_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD3_BITER_ELINKNO_BITER_MASK) 2438 2439 #define DMA_TCD_TCD3_BITER_ELINKNO_ELINK_MASK (0x8000U) 2440 #define DMA_TCD_TCD3_BITER_ELINKNO_ELINK_SHIFT (15U) 2441 #define DMA_TCD_TCD3_BITER_ELINKNO_ELINK_WIDTH (1U) 2442 #define DMA_TCD_TCD3_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD3_BITER_ELINKNO_ELINK_MASK) 2443 /*! @} */ 2444 2445 /*! @name TCD3_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 2446 /*! @{ */ 2447 2448 #define DMA_TCD_TCD3_BITER_ELINKYES_BITER_MASK (0x1FFU) 2449 #define DMA_TCD_TCD3_BITER_ELINKYES_BITER_SHIFT (0U) 2450 #define DMA_TCD_TCD3_BITER_ELINKYES_BITER_WIDTH (9U) 2451 #define DMA_TCD_TCD3_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD3_BITER_ELINKYES_BITER_MASK) 2452 2453 #define DMA_TCD_TCD3_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 2454 #define DMA_TCD_TCD3_BITER_ELINKYES_LINKCH_SHIFT (9U) 2455 #define DMA_TCD_TCD3_BITER_ELINKYES_LINKCH_WIDTH (5U) 2456 #define DMA_TCD_TCD3_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD3_BITER_ELINKYES_LINKCH_MASK) 2457 2458 #define DMA_TCD_TCD3_BITER_ELINKYES_ELINK_MASK (0x8000U) 2459 #define DMA_TCD_TCD3_BITER_ELINKYES_ELINK_SHIFT (15U) 2460 #define DMA_TCD_TCD3_BITER_ELINKYES_ELINK_WIDTH (1U) 2461 #define DMA_TCD_TCD3_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD3_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD3_BITER_ELINKYES_ELINK_MASK) 2462 /*! @} */ 2463 2464 /*! @name CH4_CSR - Channel Control and Status */ 2465 /*! @{ */ 2466 2467 #define DMA_TCD_CH4_CSR_ERQ_MASK (0x1U) 2468 #define DMA_TCD_CH4_CSR_ERQ_SHIFT (0U) 2469 #define DMA_TCD_CH4_CSR_ERQ_WIDTH (1U) 2470 #define DMA_TCD_CH4_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_CSR_ERQ_SHIFT)) & DMA_TCD_CH4_CSR_ERQ_MASK) 2471 2472 #define DMA_TCD_CH4_CSR_EARQ_MASK (0x2U) 2473 #define DMA_TCD_CH4_CSR_EARQ_SHIFT (1U) 2474 #define DMA_TCD_CH4_CSR_EARQ_WIDTH (1U) 2475 #define DMA_TCD_CH4_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_CSR_EARQ_SHIFT)) & DMA_TCD_CH4_CSR_EARQ_MASK) 2476 2477 #define DMA_TCD_CH4_CSR_EEI_MASK (0x4U) 2478 #define DMA_TCD_CH4_CSR_EEI_SHIFT (2U) 2479 #define DMA_TCD_CH4_CSR_EEI_WIDTH (1U) 2480 #define DMA_TCD_CH4_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_CSR_EEI_SHIFT)) & DMA_TCD_CH4_CSR_EEI_MASK) 2481 2482 #define DMA_TCD_CH4_CSR_EBW_MASK (0x8U) 2483 #define DMA_TCD_CH4_CSR_EBW_SHIFT (3U) 2484 #define DMA_TCD_CH4_CSR_EBW_WIDTH (1U) 2485 #define DMA_TCD_CH4_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_CSR_EBW_SHIFT)) & DMA_TCD_CH4_CSR_EBW_MASK) 2486 2487 #define DMA_TCD_CH4_CSR_DONE_MASK (0x40000000U) 2488 #define DMA_TCD_CH4_CSR_DONE_SHIFT (30U) 2489 #define DMA_TCD_CH4_CSR_DONE_WIDTH (1U) 2490 #define DMA_TCD_CH4_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_CSR_DONE_SHIFT)) & DMA_TCD_CH4_CSR_DONE_MASK) 2491 2492 #define DMA_TCD_CH4_CSR_ACTIVE_MASK (0x80000000U) 2493 #define DMA_TCD_CH4_CSR_ACTIVE_SHIFT (31U) 2494 #define DMA_TCD_CH4_CSR_ACTIVE_WIDTH (1U) 2495 #define DMA_TCD_CH4_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH4_CSR_ACTIVE_MASK) 2496 /*! @} */ 2497 2498 /*! @name CH4_ES - Channel Error Status */ 2499 /*! @{ */ 2500 2501 #define DMA_TCD_CH4_ES_DBE_MASK (0x1U) 2502 #define DMA_TCD_CH4_ES_DBE_SHIFT (0U) 2503 #define DMA_TCD_CH4_ES_DBE_WIDTH (1U) 2504 #define DMA_TCD_CH4_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_ES_DBE_SHIFT)) & DMA_TCD_CH4_ES_DBE_MASK) 2505 2506 #define DMA_TCD_CH4_ES_SBE_MASK (0x2U) 2507 #define DMA_TCD_CH4_ES_SBE_SHIFT (1U) 2508 #define DMA_TCD_CH4_ES_SBE_WIDTH (1U) 2509 #define DMA_TCD_CH4_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_ES_SBE_SHIFT)) & DMA_TCD_CH4_ES_SBE_MASK) 2510 2511 #define DMA_TCD_CH4_ES_SGE_MASK (0x4U) 2512 #define DMA_TCD_CH4_ES_SGE_SHIFT (2U) 2513 #define DMA_TCD_CH4_ES_SGE_WIDTH (1U) 2514 #define DMA_TCD_CH4_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_ES_SGE_SHIFT)) & DMA_TCD_CH4_ES_SGE_MASK) 2515 2516 #define DMA_TCD_CH4_ES_NCE_MASK (0x8U) 2517 #define DMA_TCD_CH4_ES_NCE_SHIFT (3U) 2518 #define DMA_TCD_CH4_ES_NCE_WIDTH (1U) 2519 #define DMA_TCD_CH4_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_ES_NCE_SHIFT)) & DMA_TCD_CH4_ES_NCE_MASK) 2520 2521 #define DMA_TCD_CH4_ES_DOE_MASK (0x10U) 2522 #define DMA_TCD_CH4_ES_DOE_SHIFT (4U) 2523 #define DMA_TCD_CH4_ES_DOE_WIDTH (1U) 2524 #define DMA_TCD_CH4_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_ES_DOE_SHIFT)) & DMA_TCD_CH4_ES_DOE_MASK) 2525 2526 #define DMA_TCD_CH4_ES_DAE_MASK (0x20U) 2527 #define DMA_TCD_CH4_ES_DAE_SHIFT (5U) 2528 #define DMA_TCD_CH4_ES_DAE_WIDTH (1U) 2529 #define DMA_TCD_CH4_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_ES_DAE_SHIFT)) & DMA_TCD_CH4_ES_DAE_MASK) 2530 2531 #define DMA_TCD_CH4_ES_SOE_MASK (0x40U) 2532 #define DMA_TCD_CH4_ES_SOE_SHIFT (6U) 2533 #define DMA_TCD_CH4_ES_SOE_WIDTH (1U) 2534 #define DMA_TCD_CH4_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_ES_SOE_SHIFT)) & DMA_TCD_CH4_ES_SOE_MASK) 2535 2536 #define DMA_TCD_CH4_ES_SAE_MASK (0x80U) 2537 #define DMA_TCD_CH4_ES_SAE_SHIFT (7U) 2538 #define DMA_TCD_CH4_ES_SAE_WIDTH (1U) 2539 #define DMA_TCD_CH4_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_ES_SAE_SHIFT)) & DMA_TCD_CH4_ES_SAE_MASK) 2540 2541 #define DMA_TCD_CH4_ES_ERR_MASK (0x80000000U) 2542 #define DMA_TCD_CH4_ES_ERR_SHIFT (31U) 2543 #define DMA_TCD_CH4_ES_ERR_WIDTH (1U) 2544 #define DMA_TCD_CH4_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_ES_ERR_SHIFT)) & DMA_TCD_CH4_ES_ERR_MASK) 2545 /*! @} */ 2546 2547 /*! @name CH4_INT - Channel Interrupt Status */ 2548 /*! @{ */ 2549 2550 #define DMA_TCD_CH4_INT_INT_MASK (0x1U) 2551 #define DMA_TCD_CH4_INT_INT_SHIFT (0U) 2552 #define DMA_TCD_CH4_INT_INT_WIDTH (1U) 2553 #define DMA_TCD_CH4_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_INT_INT_SHIFT)) & DMA_TCD_CH4_INT_INT_MASK) 2554 /*! @} */ 2555 2556 /*! @name CH4_SBR - Channel System Bus */ 2557 /*! @{ */ 2558 2559 #define DMA_TCD_CH4_SBR_MID_MASK (0xFU) 2560 #define DMA_TCD_CH4_SBR_MID_SHIFT (0U) 2561 #define DMA_TCD_CH4_SBR_MID_WIDTH (4U) 2562 #define DMA_TCD_CH4_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_SBR_MID_SHIFT)) & DMA_TCD_CH4_SBR_MID_MASK) 2563 2564 #define DMA_TCD_CH4_SBR_PAL_MASK (0x8000U) 2565 #define DMA_TCD_CH4_SBR_PAL_SHIFT (15U) 2566 #define DMA_TCD_CH4_SBR_PAL_WIDTH (1U) 2567 #define DMA_TCD_CH4_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_SBR_PAL_SHIFT)) & DMA_TCD_CH4_SBR_PAL_MASK) 2568 2569 #define DMA_TCD_CH4_SBR_EMI_MASK (0x10000U) 2570 #define DMA_TCD_CH4_SBR_EMI_SHIFT (16U) 2571 #define DMA_TCD_CH4_SBR_EMI_WIDTH (1U) 2572 #define DMA_TCD_CH4_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_SBR_EMI_SHIFT)) & DMA_TCD_CH4_SBR_EMI_MASK) 2573 2574 #define DMA_TCD_CH4_SBR_ATTR_MASK (0xE0000U) 2575 #define DMA_TCD_CH4_SBR_ATTR_SHIFT (17U) 2576 #define DMA_TCD_CH4_SBR_ATTR_WIDTH (3U) 2577 #define DMA_TCD_CH4_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_SBR_ATTR_SHIFT)) & DMA_TCD_CH4_SBR_ATTR_MASK) 2578 /*! @} */ 2579 2580 /*! @name CH4_PRI - Channel Priority */ 2581 /*! @{ */ 2582 2583 #define DMA_TCD_CH4_PRI_APL_MASK (0x7U) 2584 #define DMA_TCD_CH4_PRI_APL_SHIFT (0U) 2585 #define DMA_TCD_CH4_PRI_APL_WIDTH (3U) 2586 #define DMA_TCD_CH4_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_PRI_APL_SHIFT)) & DMA_TCD_CH4_PRI_APL_MASK) 2587 2588 #define DMA_TCD_CH4_PRI_DPA_MASK (0x40000000U) 2589 #define DMA_TCD_CH4_PRI_DPA_SHIFT (30U) 2590 #define DMA_TCD_CH4_PRI_DPA_WIDTH (1U) 2591 #define DMA_TCD_CH4_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_PRI_DPA_SHIFT)) & DMA_TCD_CH4_PRI_DPA_MASK) 2592 2593 #define DMA_TCD_CH4_PRI_ECP_MASK (0x80000000U) 2594 #define DMA_TCD_CH4_PRI_ECP_SHIFT (31U) 2595 #define DMA_TCD_CH4_PRI_ECP_WIDTH (1U) 2596 #define DMA_TCD_CH4_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH4_PRI_ECP_SHIFT)) & DMA_TCD_CH4_PRI_ECP_MASK) 2597 /*! @} */ 2598 2599 /*! @name TCD4_SADDR - TCD Source Address */ 2600 /*! @{ */ 2601 2602 #define DMA_TCD_TCD4_SADDR_SADDR_MASK (0xFFFFFFFFU) 2603 #define DMA_TCD_TCD4_SADDR_SADDR_SHIFT (0U) 2604 #define DMA_TCD_TCD4_SADDR_SADDR_WIDTH (32U) 2605 #define DMA_TCD_TCD4_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD4_SADDR_SADDR_MASK) 2606 /*! @} */ 2607 2608 /*! @name TCD4_SOFF - TCD Signed Source Address Offset */ 2609 /*! @{ */ 2610 2611 #define DMA_TCD_TCD4_SOFF_SOFF_MASK (0xFFFFU) 2612 #define DMA_TCD_TCD4_SOFF_SOFF_SHIFT (0U) 2613 #define DMA_TCD_TCD4_SOFF_SOFF_WIDTH (16U) 2614 #define DMA_TCD_TCD4_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD4_SOFF_SOFF_MASK) 2615 /*! @} */ 2616 2617 /*! @name TCD4_ATTR - TCD Transfer Attributes */ 2618 /*! @{ */ 2619 2620 #define DMA_TCD_TCD4_ATTR_DSIZE_MASK (0x7U) 2621 #define DMA_TCD_TCD4_ATTR_DSIZE_SHIFT (0U) 2622 #define DMA_TCD_TCD4_ATTR_DSIZE_WIDTH (3U) 2623 #define DMA_TCD_TCD4_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD4_ATTR_DSIZE_MASK) 2624 2625 #define DMA_TCD_TCD4_ATTR_DMOD_MASK (0xF8U) 2626 #define DMA_TCD_TCD4_ATTR_DMOD_SHIFT (3U) 2627 #define DMA_TCD_TCD4_ATTR_DMOD_WIDTH (5U) 2628 #define DMA_TCD_TCD4_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD4_ATTR_DMOD_MASK) 2629 2630 #define DMA_TCD_TCD4_ATTR_SSIZE_MASK (0x700U) 2631 #define DMA_TCD_TCD4_ATTR_SSIZE_SHIFT (8U) 2632 #define DMA_TCD_TCD4_ATTR_SSIZE_WIDTH (3U) 2633 #define DMA_TCD_TCD4_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD4_ATTR_SSIZE_MASK) 2634 2635 #define DMA_TCD_TCD4_ATTR_SMOD_MASK (0xF800U) 2636 #define DMA_TCD_TCD4_ATTR_SMOD_SHIFT (11U) 2637 #define DMA_TCD_TCD4_ATTR_SMOD_WIDTH (5U) 2638 #define DMA_TCD_TCD4_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD4_ATTR_SMOD_MASK) 2639 /*! @} */ 2640 2641 /*! @name TCD4_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 2642 /*! @{ */ 2643 2644 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 2645 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 2646 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 2647 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD4_NBYTES_MLOFFNO_NBYTES_MASK) 2648 2649 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 2650 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 2651 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 2652 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD4_NBYTES_MLOFFNO_DMLOE_MASK) 2653 2654 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 2655 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 2656 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 2657 #define DMA_TCD_TCD4_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD4_NBYTES_MLOFFNO_SMLOE_MASK) 2658 /*! @} */ 2659 2660 /*! @name TCD4_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 2661 /*! @{ */ 2662 2663 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 2664 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 2665 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 2666 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD4_NBYTES_MLOFFYES_NBYTES_MASK) 2667 2668 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 2669 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 2670 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 2671 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD4_NBYTES_MLOFFYES_MLOFF_MASK) 2672 2673 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 2674 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 2675 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 2676 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD4_NBYTES_MLOFFYES_DMLOE_MASK) 2677 2678 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 2679 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 2680 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 2681 #define DMA_TCD_TCD4_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD4_NBYTES_MLOFFYES_SMLOE_MASK) 2682 /*! @} */ 2683 2684 /*! @name TCD4_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 2685 /*! @{ */ 2686 2687 #define DMA_TCD_TCD4_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 2688 #define DMA_TCD_TCD4_SLAST_SDA_SLAST_SDA_SHIFT (0U) 2689 #define DMA_TCD_TCD4_SLAST_SDA_SLAST_SDA_WIDTH (32U) 2690 #define DMA_TCD_TCD4_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD4_SLAST_SDA_SLAST_SDA_MASK) 2691 /*! @} */ 2692 2693 /*! @name TCD4_DADDR - TCD Destination Address */ 2694 /*! @{ */ 2695 2696 #define DMA_TCD_TCD4_DADDR_DADDR_MASK (0xFFFFFFFFU) 2697 #define DMA_TCD_TCD4_DADDR_DADDR_SHIFT (0U) 2698 #define DMA_TCD_TCD4_DADDR_DADDR_WIDTH (32U) 2699 #define DMA_TCD_TCD4_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD4_DADDR_DADDR_MASK) 2700 /*! @} */ 2701 2702 /*! @name TCD4_DOFF - TCD Signed Destination Address Offset */ 2703 /*! @{ */ 2704 2705 #define DMA_TCD_TCD4_DOFF_DOFF_MASK (0xFFFFU) 2706 #define DMA_TCD_TCD4_DOFF_DOFF_SHIFT (0U) 2707 #define DMA_TCD_TCD4_DOFF_DOFF_WIDTH (16U) 2708 #define DMA_TCD_TCD4_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD4_DOFF_DOFF_MASK) 2709 /*! @} */ 2710 2711 /*! @name TCD4_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 2712 /*! @{ */ 2713 2714 #define DMA_TCD_TCD4_CITER_ELINKNO_CITER_MASK (0x7FFFU) 2715 #define DMA_TCD_TCD4_CITER_ELINKNO_CITER_SHIFT (0U) 2716 #define DMA_TCD_TCD4_CITER_ELINKNO_CITER_WIDTH (15U) 2717 #define DMA_TCD_TCD4_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD4_CITER_ELINKNO_CITER_MASK) 2718 2719 #define DMA_TCD_TCD4_CITER_ELINKNO_ELINK_MASK (0x8000U) 2720 #define DMA_TCD_TCD4_CITER_ELINKNO_ELINK_SHIFT (15U) 2721 #define DMA_TCD_TCD4_CITER_ELINKNO_ELINK_WIDTH (1U) 2722 #define DMA_TCD_TCD4_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD4_CITER_ELINKNO_ELINK_MASK) 2723 /*! @} */ 2724 2725 /*! @name TCD4_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 2726 /*! @{ */ 2727 2728 #define DMA_TCD_TCD4_CITER_ELINKYES_CITER_MASK (0x1FFU) 2729 #define DMA_TCD_TCD4_CITER_ELINKYES_CITER_SHIFT (0U) 2730 #define DMA_TCD_TCD4_CITER_ELINKYES_CITER_WIDTH (9U) 2731 #define DMA_TCD_TCD4_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD4_CITER_ELINKYES_CITER_MASK) 2732 2733 #define DMA_TCD_TCD4_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 2734 #define DMA_TCD_TCD4_CITER_ELINKYES_LINKCH_SHIFT (9U) 2735 #define DMA_TCD_TCD4_CITER_ELINKYES_LINKCH_WIDTH (5U) 2736 #define DMA_TCD_TCD4_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD4_CITER_ELINKYES_LINKCH_MASK) 2737 2738 #define DMA_TCD_TCD4_CITER_ELINKYES_ELINK_MASK (0x8000U) 2739 #define DMA_TCD_TCD4_CITER_ELINKYES_ELINK_SHIFT (15U) 2740 #define DMA_TCD_TCD4_CITER_ELINKYES_ELINK_WIDTH (1U) 2741 #define DMA_TCD_TCD4_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD4_CITER_ELINKYES_ELINK_MASK) 2742 /*! @} */ 2743 2744 /*! @name TCD4_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 2745 /*! @{ */ 2746 2747 #define DMA_TCD_TCD4_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 2748 #define DMA_TCD_TCD4_DLAST_SGA_DLAST_SGA_SHIFT (0U) 2749 #define DMA_TCD_TCD4_DLAST_SGA_DLAST_SGA_WIDTH (32U) 2750 #define DMA_TCD_TCD4_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD4_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD4_DLAST_SGA_DLAST_SGA_MASK) 2751 /*! @} */ 2752 2753 /*! @name TCD4_CSR - TCD Control and Status */ 2754 /*! @{ */ 2755 2756 #define DMA_TCD_TCD4_CSR_START_MASK (0x1U) 2757 #define DMA_TCD_TCD4_CSR_START_SHIFT (0U) 2758 #define DMA_TCD_TCD4_CSR_START_WIDTH (1U) 2759 #define DMA_TCD_TCD4_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CSR_START_SHIFT)) & DMA_TCD_TCD4_CSR_START_MASK) 2760 2761 #define DMA_TCD_TCD4_CSR_INTMAJOR_MASK (0x2U) 2762 #define DMA_TCD_TCD4_CSR_INTMAJOR_SHIFT (1U) 2763 #define DMA_TCD_TCD4_CSR_INTMAJOR_WIDTH (1U) 2764 #define DMA_TCD_TCD4_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD4_CSR_INTMAJOR_MASK) 2765 2766 #define DMA_TCD_TCD4_CSR_INTHALF_MASK (0x4U) 2767 #define DMA_TCD_TCD4_CSR_INTHALF_SHIFT (2U) 2768 #define DMA_TCD_TCD4_CSR_INTHALF_WIDTH (1U) 2769 #define DMA_TCD_TCD4_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD4_CSR_INTHALF_MASK) 2770 2771 #define DMA_TCD_TCD4_CSR_DREQ_MASK (0x8U) 2772 #define DMA_TCD_TCD4_CSR_DREQ_SHIFT (3U) 2773 #define DMA_TCD_TCD4_CSR_DREQ_WIDTH (1U) 2774 #define DMA_TCD_TCD4_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CSR_DREQ_SHIFT)) & DMA_TCD_TCD4_CSR_DREQ_MASK) 2775 2776 #define DMA_TCD_TCD4_CSR_ESG_MASK (0x10U) 2777 #define DMA_TCD_TCD4_CSR_ESG_SHIFT (4U) 2778 #define DMA_TCD_TCD4_CSR_ESG_WIDTH (1U) 2779 #define DMA_TCD_TCD4_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CSR_ESG_SHIFT)) & DMA_TCD_TCD4_CSR_ESG_MASK) 2780 2781 #define DMA_TCD_TCD4_CSR_MAJORELINK_MASK (0x20U) 2782 #define DMA_TCD_TCD4_CSR_MAJORELINK_SHIFT (5U) 2783 #define DMA_TCD_TCD4_CSR_MAJORELINK_WIDTH (1U) 2784 #define DMA_TCD_TCD4_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD4_CSR_MAJORELINK_MASK) 2785 2786 #define DMA_TCD_TCD4_CSR_EEOP_MASK (0x40U) 2787 #define DMA_TCD_TCD4_CSR_EEOP_SHIFT (6U) 2788 #define DMA_TCD_TCD4_CSR_EEOP_WIDTH (1U) 2789 #define DMA_TCD_TCD4_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CSR_EEOP_SHIFT)) & DMA_TCD_TCD4_CSR_EEOP_MASK) 2790 2791 #define DMA_TCD_TCD4_CSR_ESDA_MASK (0x80U) 2792 #define DMA_TCD_TCD4_CSR_ESDA_SHIFT (7U) 2793 #define DMA_TCD_TCD4_CSR_ESDA_WIDTH (1U) 2794 #define DMA_TCD_TCD4_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CSR_ESDA_SHIFT)) & DMA_TCD_TCD4_CSR_ESDA_MASK) 2795 2796 #define DMA_TCD_TCD4_CSR_MAJORLINKCH_MASK (0x1F00U) 2797 #define DMA_TCD_TCD4_CSR_MAJORLINKCH_SHIFT (8U) 2798 #define DMA_TCD_TCD4_CSR_MAJORLINKCH_WIDTH (5U) 2799 #define DMA_TCD_TCD4_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD4_CSR_MAJORLINKCH_MASK) 2800 2801 #define DMA_TCD_TCD4_CSR_BWC_MASK (0xC000U) 2802 #define DMA_TCD_TCD4_CSR_BWC_SHIFT (14U) 2803 #define DMA_TCD_TCD4_CSR_BWC_WIDTH (2U) 2804 #define DMA_TCD_TCD4_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_CSR_BWC_SHIFT)) & DMA_TCD_TCD4_CSR_BWC_MASK) 2805 /*! @} */ 2806 2807 /*! @name TCD4_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 2808 /*! @{ */ 2809 2810 #define DMA_TCD_TCD4_BITER_ELINKNO_BITER_MASK (0x7FFFU) 2811 #define DMA_TCD_TCD4_BITER_ELINKNO_BITER_SHIFT (0U) 2812 #define DMA_TCD_TCD4_BITER_ELINKNO_BITER_WIDTH (15U) 2813 #define DMA_TCD_TCD4_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD4_BITER_ELINKNO_BITER_MASK) 2814 2815 #define DMA_TCD_TCD4_BITER_ELINKNO_ELINK_MASK (0x8000U) 2816 #define DMA_TCD_TCD4_BITER_ELINKNO_ELINK_SHIFT (15U) 2817 #define DMA_TCD_TCD4_BITER_ELINKNO_ELINK_WIDTH (1U) 2818 #define DMA_TCD_TCD4_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD4_BITER_ELINKNO_ELINK_MASK) 2819 /*! @} */ 2820 2821 /*! @name TCD4_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 2822 /*! @{ */ 2823 2824 #define DMA_TCD_TCD4_BITER_ELINKYES_BITER_MASK (0x1FFU) 2825 #define DMA_TCD_TCD4_BITER_ELINKYES_BITER_SHIFT (0U) 2826 #define DMA_TCD_TCD4_BITER_ELINKYES_BITER_WIDTH (9U) 2827 #define DMA_TCD_TCD4_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD4_BITER_ELINKYES_BITER_MASK) 2828 2829 #define DMA_TCD_TCD4_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 2830 #define DMA_TCD_TCD4_BITER_ELINKYES_LINKCH_SHIFT (9U) 2831 #define DMA_TCD_TCD4_BITER_ELINKYES_LINKCH_WIDTH (5U) 2832 #define DMA_TCD_TCD4_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD4_BITER_ELINKYES_LINKCH_MASK) 2833 2834 #define DMA_TCD_TCD4_BITER_ELINKYES_ELINK_MASK (0x8000U) 2835 #define DMA_TCD_TCD4_BITER_ELINKYES_ELINK_SHIFT (15U) 2836 #define DMA_TCD_TCD4_BITER_ELINKYES_ELINK_WIDTH (1U) 2837 #define DMA_TCD_TCD4_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD4_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD4_BITER_ELINKYES_ELINK_MASK) 2838 /*! @} */ 2839 2840 /*! @name CH5_CSR - Channel Control and Status */ 2841 /*! @{ */ 2842 2843 #define DMA_TCD_CH5_CSR_ERQ_MASK (0x1U) 2844 #define DMA_TCD_CH5_CSR_ERQ_SHIFT (0U) 2845 #define DMA_TCD_CH5_CSR_ERQ_WIDTH (1U) 2846 #define DMA_TCD_CH5_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_CSR_ERQ_SHIFT)) & DMA_TCD_CH5_CSR_ERQ_MASK) 2847 2848 #define DMA_TCD_CH5_CSR_EARQ_MASK (0x2U) 2849 #define DMA_TCD_CH5_CSR_EARQ_SHIFT (1U) 2850 #define DMA_TCD_CH5_CSR_EARQ_WIDTH (1U) 2851 #define DMA_TCD_CH5_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_CSR_EARQ_SHIFT)) & DMA_TCD_CH5_CSR_EARQ_MASK) 2852 2853 #define DMA_TCD_CH5_CSR_EEI_MASK (0x4U) 2854 #define DMA_TCD_CH5_CSR_EEI_SHIFT (2U) 2855 #define DMA_TCD_CH5_CSR_EEI_WIDTH (1U) 2856 #define DMA_TCD_CH5_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_CSR_EEI_SHIFT)) & DMA_TCD_CH5_CSR_EEI_MASK) 2857 2858 #define DMA_TCD_CH5_CSR_EBW_MASK (0x8U) 2859 #define DMA_TCD_CH5_CSR_EBW_SHIFT (3U) 2860 #define DMA_TCD_CH5_CSR_EBW_WIDTH (1U) 2861 #define DMA_TCD_CH5_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_CSR_EBW_SHIFT)) & DMA_TCD_CH5_CSR_EBW_MASK) 2862 2863 #define DMA_TCD_CH5_CSR_DONE_MASK (0x40000000U) 2864 #define DMA_TCD_CH5_CSR_DONE_SHIFT (30U) 2865 #define DMA_TCD_CH5_CSR_DONE_WIDTH (1U) 2866 #define DMA_TCD_CH5_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_CSR_DONE_SHIFT)) & DMA_TCD_CH5_CSR_DONE_MASK) 2867 2868 #define DMA_TCD_CH5_CSR_ACTIVE_MASK (0x80000000U) 2869 #define DMA_TCD_CH5_CSR_ACTIVE_SHIFT (31U) 2870 #define DMA_TCD_CH5_CSR_ACTIVE_WIDTH (1U) 2871 #define DMA_TCD_CH5_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH5_CSR_ACTIVE_MASK) 2872 /*! @} */ 2873 2874 /*! @name CH5_ES - Channel Error Status */ 2875 /*! @{ */ 2876 2877 #define DMA_TCD_CH5_ES_DBE_MASK (0x1U) 2878 #define DMA_TCD_CH5_ES_DBE_SHIFT (0U) 2879 #define DMA_TCD_CH5_ES_DBE_WIDTH (1U) 2880 #define DMA_TCD_CH5_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_ES_DBE_SHIFT)) & DMA_TCD_CH5_ES_DBE_MASK) 2881 2882 #define DMA_TCD_CH5_ES_SBE_MASK (0x2U) 2883 #define DMA_TCD_CH5_ES_SBE_SHIFT (1U) 2884 #define DMA_TCD_CH5_ES_SBE_WIDTH (1U) 2885 #define DMA_TCD_CH5_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_ES_SBE_SHIFT)) & DMA_TCD_CH5_ES_SBE_MASK) 2886 2887 #define DMA_TCD_CH5_ES_SGE_MASK (0x4U) 2888 #define DMA_TCD_CH5_ES_SGE_SHIFT (2U) 2889 #define DMA_TCD_CH5_ES_SGE_WIDTH (1U) 2890 #define DMA_TCD_CH5_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_ES_SGE_SHIFT)) & DMA_TCD_CH5_ES_SGE_MASK) 2891 2892 #define DMA_TCD_CH5_ES_NCE_MASK (0x8U) 2893 #define DMA_TCD_CH5_ES_NCE_SHIFT (3U) 2894 #define DMA_TCD_CH5_ES_NCE_WIDTH (1U) 2895 #define DMA_TCD_CH5_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_ES_NCE_SHIFT)) & DMA_TCD_CH5_ES_NCE_MASK) 2896 2897 #define DMA_TCD_CH5_ES_DOE_MASK (0x10U) 2898 #define DMA_TCD_CH5_ES_DOE_SHIFT (4U) 2899 #define DMA_TCD_CH5_ES_DOE_WIDTH (1U) 2900 #define DMA_TCD_CH5_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_ES_DOE_SHIFT)) & DMA_TCD_CH5_ES_DOE_MASK) 2901 2902 #define DMA_TCD_CH5_ES_DAE_MASK (0x20U) 2903 #define DMA_TCD_CH5_ES_DAE_SHIFT (5U) 2904 #define DMA_TCD_CH5_ES_DAE_WIDTH (1U) 2905 #define DMA_TCD_CH5_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_ES_DAE_SHIFT)) & DMA_TCD_CH5_ES_DAE_MASK) 2906 2907 #define DMA_TCD_CH5_ES_SOE_MASK (0x40U) 2908 #define DMA_TCD_CH5_ES_SOE_SHIFT (6U) 2909 #define DMA_TCD_CH5_ES_SOE_WIDTH (1U) 2910 #define DMA_TCD_CH5_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_ES_SOE_SHIFT)) & DMA_TCD_CH5_ES_SOE_MASK) 2911 2912 #define DMA_TCD_CH5_ES_SAE_MASK (0x80U) 2913 #define DMA_TCD_CH5_ES_SAE_SHIFT (7U) 2914 #define DMA_TCD_CH5_ES_SAE_WIDTH (1U) 2915 #define DMA_TCD_CH5_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_ES_SAE_SHIFT)) & DMA_TCD_CH5_ES_SAE_MASK) 2916 2917 #define DMA_TCD_CH5_ES_ERR_MASK (0x80000000U) 2918 #define DMA_TCD_CH5_ES_ERR_SHIFT (31U) 2919 #define DMA_TCD_CH5_ES_ERR_WIDTH (1U) 2920 #define DMA_TCD_CH5_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_ES_ERR_SHIFT)) & DMA_TCD_CH5_ES_ERR_MASK) 2921 /*! @} */ 2922 2923 /*! @name CH5_INT - Channel Interrupt Status */ 2924 /*! @{ */ 2925 2926 #define DMA_TCD_CH5_INT_INT_MASK (0x1U) 2927 #define DMA_TCD_CH5_INT_INT_SHIFT (0U) 2928 #define DMA_TCD_CH5_INT_INT_WIDTH (1U) 2929 #define DMA_TCD_CH5_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_INT_INT_SHIFT)) & DMA_TCD_CH5_INT_INT_MASK) 2930 /*! @} */ 2931 2932 /*! @name CH5_SBR - Channel System Bus */ 2933 /*! @{ */ 2934 2935 #define DMA_TCD_CH5_SBR_MID_MASK (0xFU) 2936 #define DMA_TCD_CH5_SBR_MID_SHIFT (0U) 2937 #define DMA_TCD_CH5_SBR_MID_WIDTH (4U) 2938 #define DMA_TCD_CH5_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_SBR_MID_SHIFT)) & DMA_TCD_CH5_SBR_MID_MASK) 2939 2940 #define DMA_TCD_CH5_SBR_PAL_MASK (0x8000U) 2941 #define DMA_TCD_CH5_SBR_PAL_SHIFT (15U) 2942 #define DMA_TCD_CH5_SBR_PAL_WIDTH (1U) 2943 #define DMA_TCD_CH5_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_SBR_PAL_SHIFT)) & DMA_TCD_CH5_SBR_PAL_MASK) 2944 2945 #define DMA_TCD_CH5_SBR_EMI_MASK (0x10000U) 2946 #define DMA_TCD_CH5_SBR_EMI_SHIFT (16U) 2947 #define DMA_TCD_CH5_SBR_EMI_WIDTH (1U) 2948 #define DMA_TCD_CH5_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_SBR_EMI_SHIFT)) & DMA_TCD_CH5_SBR_EMI_MASK) 2949 2950 #define DMA_TCD_CH5_SBR_ATTR_MASK (0xE0000U) 2951 #define DMA_TCD_CH5_SBR_ATTR_SHIFT (17U) 2952 #define DMA_TCD_CH5_SBR_ATTR_WIDTH (3U) 2953 #define DMA_TCD_CH5_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_SBR_ATTR_SHIFT)) & DMA_TCD_CH5_SBR_ATTR_MASK) 2954 /*! @} */ 2955 2956 /*! @name CH5_PRI - Channel Priority */ 2957 /*! @{ */ 2958 2959 #define DMA_TCD_CH5_PRI_APL_MASK (0x7U) 2960 #define DMA_TCD_CH5_PRI_APL_SHIFT (0U) 2961 #define DMA_TCD_CH5_PRI_APL_WIDTH (3U) 2962 #define DMA_TCD_CH5_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_PRI_APL_SHIFT)) & DMA_TCD_CH5_PRI_APL_MASK) 2963 2964 #define DMA_TCD_CH5_PRI_DPA_MASK (0x40000000U) 2965 #define DMA_TCD_CH5_PRI_DPA_SHIFT (30U) 2966 #define DMA_TCD_CH5_PRI_DPA_WIDTH (1U) 2967 #define DMA_TCD_CH5_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_PRI_DPA_SHIFT)) & DMA_TCD_CH5_PRI_DPA_MASK) 2968 2969 #define DMA_TCD_CH5_PRI_ECP_MASK (0x80000000U) 2970 #define DMA_TCD_CH5_PRI_ECP_SHIFT (31U) 2971 #define DMA_TCD_CH5_PRI_ECP_WIDTH (1U) 2972 #define DMA_TCD_CH5_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH5_PRI_ECP_SHIFT)) & DMA_TCD_CH5_PRI_ECP_MASK) 2973 /*! @} */ 2974 2975 /*! @name TCD5_SADDR - TCD Source Address */ 2976 /*! @{ */ 2977 2978 #define DMA_TCD_TCD5_SADDR_SADDR_MASK (0xFFFFFFFFU) 2979 #define DMA_TCD_TCD5_SADDR_SADDR_SHIFT (0U) 2980 #define DMA_TCD_TCD5_SADDR_SADDR_WIDTH (32U) 2981 #define DMA_TCD_TCD5_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD5_SADDR_SADDR_MASK) 2982 /*! @} */ 2983 2984 /*! @name TCD5_SOFF - TCD Signed Source Address Offset */ 2985 /*! @{ */ 2986 2987 #define DMA_TCD_TCD5_SOFF_SOFF_MASK (0xFFFFU) 2988 #define DMA_TCD_TCD5_SOFF_SOFF_SHIFT (0U) 2989 #define DMA_TCD_TCD5_SOFF_SOFF_WIDTH (16U) 2990 #define DMA_TCD_TCD5_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD5_SOFF_SOFF_MASK) 2991 /*! @} */ 2992 2993 /*! @name TCD5_ATTR - TCD Transfer Attributes */ 2994 /*! @{ */ 2995 2996 #define DMA_TCD_TCD5_ATTR_DSIZE_MASK (0x7U) 2997 #define DMA_TCD_TCD5_ATTR_DSIZE_SHIFT (0U) 2998 #define DMA_TCD_TCD5_ATTR_DSIZE_WIDTH (3U) 2999 #define DMA_TCD_TCD5_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD5_ATTR_DSIZE_MASK) 3000 3001 #define DMA_TCD_TCD5_ATTR_DMOD_MASK (0xF8U) 3002 #define DMA_TCD_TCD5_ATTR_DMOD_SHIFT (3U) 3003 #define DMA_TCD_TCD5_ATTR_DMOD_WIDTH (5U) 3004 #define DMA_TCD_TCD5_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD5_ATTR_DMOD_MASK) 3005 3006 #define DMA_TCD_TCD5_ATTR_SSIZE_MASK (0x700U) 3007 #define DMA_TCD_TCD5_ATTR_SSIZE_SHIFT (8U) 3008 #define DMA_TCD_TCD5_ATTR_SSIZE_WIDTH (3U) 3009 #define DMA_TCD_TCD5_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD5_ATTR_SSIZE_MASK) 3010 3011 #define DMA_TCD_TCD5_ATTR_SMOD_MASK (0xF800U) 3012 #define DMA_TCD_TCD5_ATTR_SMOD_SHIFT (11U) 3013 #define DMA_TCD_TCD5_ATTR_SMOD_WIDTH (5U) 3014 #define DMA_TCD_TCD5_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD5_ATTR_SMOD_MASK) 3015 /*! @} */ 3016 3017 /*! @name TCD5_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 3018 /*! @{ */ 3019 3020 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 3021 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 3022 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 3023 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD5_NBYTES_MLOFFNO_NBYTES_MASK) 3024 3025 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 3026 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 3027 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 3028 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD5_NBYTES_MLOFFNO_DMLOE_MASK) 3029 3030 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 3031 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 3032 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 3033 #define DMA_TCD_TCD5_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD5_NBYTES_MLOFFNO_SMLOE_MASK) 3034 /*! @} */ 3035 3036 /*! @name TCD5_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 3037 /*! @{ */ 3038 3039 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 3040 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 3041 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 3042 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD5_NBYTES_MLOFFYES_NBYTES_MASK) 3043 3044 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 3045 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 3046 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 3047 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD5_NBYTES_MLOFFYES_MLOFF_MASK) 3048 3049 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 3050 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 3051 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 3052 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD5_NBYTES_MLOFFYES_DMLOE_MASK) 3053 3054 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 3055 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 3056 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 3057 #define DMA_TCD_TCD5_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD5_NBYTES_MLOFFYES_SMLOE_MASK) 3058 /*! @} */ 3059 3060 /*! @name TCD5_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 3061 /*! @{ */ 3062 3063 #define DMA_TCD_TCD5_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 3064 #define DMA_TCD_TCD5_SLAST_SDA_SLAST_SDA_SHIFT (0U) 3065 #define DMA_TCD_TCD5_SLAST_SDA_SLAST_SDA_WIDTH (32U) 3066 #define DMA_TCD_TCD5_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD5_SLAST_SDA_SLAST_SDA_MASK) 3067 /*! @} */ 3068 3069 /*! @name TCD5_DADDR - TCD Destination Address */ 3070 /*! @{ */ 3071 3072 #define DMA_TCD_TCD5_DADDR_DADDR_MASK (0xFFFFFFFFU) 3073 #define DMA_TCD_TCD5_DADDR_DADDR_SHIFT (0U) 3074 #define DMA_TCD_TCD5_DADDR_DADDR_WIDTH (32U) 3075 #define DMA_TCD_TCD5_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD5_DADDR_DADDR_MASK) 3076 /*! @} */ 3077 3078 /*! @name TCD5_DOFF - TCD Signed Destination Address Offset */ 3079 /*! @{ */ 3080 3081 #define DMA_TCD_TCD5_DOFF_DOFF_MASK (0xFFFFU) 3082 #define DMA_TCD_TCD5_DOFF_DOFF_SHIFT (0U) 3083 #define DMA_TCD_TCD5_DOFF_DOFF_WIDTH (16U) 3084 #define DMA_TCD_TCD5_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD5_DOFF_DOFF_MASK) 3085 /*! @} */ 3086 3087 /*! @name TCD5_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 3088 /*! @{ */ 3089 3090 #define DMA_TCD_TCD5_CITER_ELINKNO_CITER_MASK (0x7FFFU) 3091 #define DMA_TCD_TCD5_CITER_ELINKNO_CITER_SHIFT (0U) 3092 #define DMA_TCD_TCD5_CITER_ELINKNO_CITER_WIDTH (15U) 3093 #define DMA_TCD_TCD5_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD5_CITER_ELINKNO_CITER_MASK) 3094 3095 #define DMA_TCD_TCD5_CITER_ELINKNO_ELINK_MASK (0x8000U) 3096 #define DMA_TCD_TCD5_CITER_ELINKNO_ELINK_SHIFT (15U) 3097 #define DMA_TCD_TCD5_CITER_ELINKNO_ELINK_WIDTH (1U) 3098 #define DMA_TCD_TCD5_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD5_CITER_ELINKNO_ELINK_MASK) 3099 /*! @} */ 3100 3101 /*! @name TCD5_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 3102 /*! @{ */ 3103 3104 #define DMA_TCD_TCD5_CITER_ELINKYES_CITER_MASK (0x1FFU) 3105 #define DMA_TCD_TCD5_CITER_ELINKYES_CITER_SHIFT (0U) 3106 #define DMA_TCD_TCD5_CITER_ELINKYES_CITER_WIDTH (9U) 3107 #define DMA_TCD_TCD5_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD5_CITER_ELINKYES_CITER_MASK) 3108 3109 #define DMA_TCD_TCD5_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 3110 #define DMA_TCD_TCD5_CITER_ELINKYES_LINKCH_SHIFT (9U) 3111 #define DMA_TCD_TCD5_CITER_ELINKYES_LINKCH_WIDTH (5U) 3112 #define DMA_TCD_TCD5_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD5_CITER_ELINKYES_LINKCH_MASK) 3113 3114 #define DMA_TCD_TCD5_CITER_ELINKYES_ELINK_MASK (0x8000U) 3115 #define DMA_TCD_TCD5_CITER_ELINKYES_ELINK_SHIFT (15U) 3116 #define DMA_TCD_TCD5_CITER_ELINKYES_ELINK_WIDTH (1U) 3117 #define DMA_TCD_TCD5_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD5_CITER_ELINKYES_ELINK_MASK) 3118 /*! @} */ 3119 3120 /*! @name TCD5_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 3121 /*! @{ */ 3122 3123 #define DMA_TCD_TCD5_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 3124 #define DMA_TCD_TCD5_DLAST_SGA_DLAST_SGA_SHIFT (0U) 3125 #define DMA_TCD_TCD5_DLAST_SGA_DLAST_SGA_WIDTH (32U) 3126 #define DMA_TCD_TCD5_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD5_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD5_DLAST_SGA_DLAST_SGA_MASK) 3127 /*! @} */ 3128 3129 /*! @name TCD5_CSR - TCD Control and Status */ 3130 /*! @{ */ 3131 3132 #define DMA_TCD_TCD5_CSR_START_MASK (0x1U) 3133 #define DMA_TCD_TCD5_CSR_START_SHIFT (0U) 3134 #define DMA_TCD_TCD5_CSR_START_WIDTH (1U) 3135 #define DMA_TCD_TCD5_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CSR_START_SHIFT)) & DMA_TCD_TCD5_CSR_START_MASK) 3136 3137 #define DMA_TCD_TCD5_CSR_INTMAJOR_MASK (0x2U) 3138 #define DMA_TCD_TCD5_CSR_INTMAJOR_SHIFT (1U) 3139 #define DMA_TCD_TCD5_CSR_INTMAJOR_WIDTH (1U) 3140 #define DMA_TCD_TCD5_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD5_CSR_INTMAJOR_MASK) 3141 3142 #define DMA_TCD_TCD5_CSR_INTHALF_MASK (0x4U) 3143 #define DMA_TCD_TCD5_CSR_INTHALF_SHIFT (2U) 3144 #define DMA_TCD_TCD5_CSR_INTHALF_WIDTH (1U) 3145 #define DMA_TCD_TCD5_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD5_CSR_INTHALF_MASK) 3146 3147 #define DMA_TCD_TCD5_CSR_DREQ_MASK (0x8U) 3148 #define DMA_TCD_TCD5_CSR_DREQ_SHIFT (3U) 3149 #define DMA_TCD_TCD5_CSR_DREQ_WIDTH (1U) 3150 #define DMA_TCD_TCD5_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CSR_DREQ_SHIFT)) & DMA_TCD_TCD5_CSR_DREQ_MASK) 3151 3152 #define DMA_TCD_TCD5_CSR_ESG_MASK (0x10U) 3153 #define DMA_TCD_TCD5_CSR_ESG_SHIFT (4U) 3154 #define DMA_TCD_TCD5_CSR_ESG_WIDTH (1U) 3155 #define DMA_TCD_TCD5_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CSR_ESG_SHIFT)) & DMA_TCD_TCD5_CSR_ESG_MASK) 3156 3157 #define DMA_TCD_TCD5_CSR_MAJORELINK_MASK (0x20U) 3158 #define DMA_TCD_TCD5_CSR_MAJORELINK_SHIFT (5U) 3159 #define DMA_TCD_TCD5_CSR_MAJORELINK_WIDTH (1U) 3160 #define DMA_TCD_TCD5_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD5_CSR_MAJORELINK_MASK) 3161 3162 #define DMA_TCD_TCD5_CSR_EEOP_MASK (0x40U) 3163 #define DMA_TCD_TCD5_CSR_EEOP_SHIFT (6U) 3164 #define DMA_TCD_TCD5_CSR_EEOP_WIDTH (1U) 3165 #define DMA_TCD_TCD5_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CSR_EEOP_SHIFT)) & DMA_TCD_TCD5_CSR_EEOP_MASK) 3166 3167 #define DMA_TCD_TCD5_CSR_ESDA_MASK (0x80U) 3168 #define DMA_TCD_TCD5_CSR_ESDA_SHIFT (7U) 3169 #define DMA_TCD_TCD5_CSR_ESDA_WIDTH (1U) 3170 #define DMA_TCD_TCD5_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CSR_ESDA_SHIFT)) & DMA_TCD_TCD5_CSR_ESDA_MASK) 3171 3172 #define DMA_TCD_TCD5_CSR_MAJORLINKCH_MASK (0x1F00U) 3173 #define DMA_TCD_TCD5_CSR_MAJORLINKCH_SHIFT (8U) 3174 #define DMA_TCD_TCD5_CSR_MAJORLINKCH_WIDTH (5U) 3175 #define DMA_TCD_TCD5_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD5_CSR_MAJORLINKCH_MASK) 3176 3177 #define DMA_TCD_TCD5_CSR_BWC_MASK (0xC000U) 3178 #define DMA_TCD_TCD5_CSR_BWC_SHIFT (14U) 3179 #define DMA_TCD_TCD5_CSR_BWC_WIDTH (2U) 3180 #define DMA_TCD_TCD5_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_CSR_BWC_SHIFT)) & DMA_TCD_TCD5_CSR_BWC_MASK) 3181 /*! @} */ 3182 3183 /*! @name TCD5_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 3184 /*! @{ */ 3185 3186 #define DMA_TCD_TCD5_BITER_ELINKNO_BITER_MASK (0x7FFFU) 3187 #define DMA_TCD_TCD5_BITER_ELINKNO_BITER_SHIFT (0U) 3188 #define DMA_TCD_TCD5_BITER_ELINKNO_BITER_WIDTH (15U) 3189 #define DMA_TCD_TCD5_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD5_BITER_ELINKNO_BITER_MASK) 3190 3191 #define DMA_TCD_TCD5_BITER_ELINKNO_ELINK_MASK (0x8000U) 3192 #define DMA_TCD_TCD5_BITER_ELINKNO_ELINK_SHIFT (15U) 3193 #define DMA_TCD_TCD5_BITER_ELINKNO_ELINK_WIDTH (1U) 3194 #define DMA_TCD_TCD5_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD5_BITER_ELINKNO_ELINK_MASK) 3195 /*! @} */ 3196 3197 /*! @name TCD5_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 3198 /*! @{ */ 3199 3200 #define DMA_TCD_TCD5_BITER_ELINKYES_BITER_MASK (0x1FFU) 3201 #define DMA_TCD_TCD5_BITER_ELINKYES_BITER_SHIFT (0U) 3202 #define DMA_TCD_TCD5_BITER_ELINKYES_BITER_WIDTH (9U) 3203 #define DMA_TCD_TCD5_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD5_BITER_ELINKYES_BITER_MASK) 3204 3205 #define DMA_TCD_TCD5_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 3206 #define DMA_TCD_TCD5_BITER_ELINKYES_LINKCH_SHIFT (9U) 3207 #define DMA_TCD_TCD5_BITER_ELINKYES_LINKCH_WIDTH (5U) 3208 #define DMA_TCD_TCD5_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD5_BITER_ELINKYES_LINKCH_MASK) 3209 3210 #define DMA_TCD_TCD5_BITER_ELINKYES_ELINK_MASK (0x8000U) 3211 #define DMA_TCD_TCD5_BITER_ELINKYES_ELINK_SHIFT (15U) 3212 #define DMA_TCD_TCD5_BITER_ELINKYES_ELINK_WIDTH (1U) 3213 #define DMA_TCD_TCD5_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD5_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD5_BITER_ELINKYES_ELINK_MASK) 3214 /*! @} */ 3215 3216 /*! @name CH6_CSR - Channel Control and Status */ 3217 /*! @{ */ 3218 3219 #define DMA_TCD_CH6_CSR_ERQ_MASK (0x1U) 3220 #define DMA_TCD_CH6_CSR_ERQ_SHIFT (0U) 3221 #define DMA_TCD_CH6_CSR_ERQ_WIDTH (1U) 3222 #define DMA_TCD_CH6_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_CSR_ERQ_SHIFT)) & DMA_TCD_CH6_CSR_ERQ_MASK) 3223 3224 #define DMA_TCD_CH6_CSR_EARQ_MASK (0x2U) 3225 #define DMA_TCD_CH6_CSR_EARQ_SHIFT (1U) 3226 #define DMA_TCD_CH6_CSR_EARQ_WIDTH (1U) 3227 #define DMA_TCD_CH6_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_CSR_EARQ_SHIFT)) & DMA_TCD_CH6_CSR_EARQ_MASK) 3228 3229 #define DMA_TCD_CH6_CSR_EEI_MASK (0x4U) 3230 #define DMA_TCD_CH6_CSR_EEI_SHIFT (2U) 3231 #define DMA_TCD_CH6_CSR_EEI_WIDTH (1U) 3232 #define DMA_TCD_CH6_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_CSR_EEI_SHIFT)) & DMA_TCD_CH6_CSR_EEI_MASK) 3233 3234 #define DMA_TCD_CH6_CSR_EBW_MASK (0x8U) 3235 #define DMA_TCD_CH6_CSR_EBW_SHIFT (3U) 3236 #define DMA_TCD_CH6_CSR_EBW_WIDTH (1U) 3237 #define DMA_TCD_CH6_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_CSR_EBW_SHIFT)) & DMA_TCD_CH6_CSR_EBW_MASK) 3238 3239 #define DMA_TCD_CH6_CSR_DONE_MASK (0x40000000U) 3240 #define DMA_TCD_CH6_CSR_DONE_SHIFT (30U) 3241 #define DMA_TCD_CH6_CSR_DONE_WIDTH (1U) 3242 #define DMA_TCD_CH6_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_CSR_DONE_SHIFT)) & DMA_TCD_CH6_CSR_DONE_MASK) 3243 3244 #define DMA_TCD_CH6_CSR_ACTIVE_MASK (0x80000000U) 3245 #define DMA_TCD_CH6_CSR_ACTIVE_SHIFT (31U) 3246 #define DMA_TCD_CH6_CSR_ACTIVE_WIDTH (1U) 3247 #define DMA_TCD_CH6_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH6_CSR_ACTIVE_MASK) 3248 /*! @} */ 3249 3250 /*! @name CH6_ES - Channel Error Status */ 3251 /*! @{ */ 3252 3253 #define DMA_TCD_CH6_ES_DBE_MASK (0x1U) 3254 #define DMA_TCD_CH6_ES_DBE_SHIFT (0U) 3255 #define DMA_TCD_CH6_ES_DBE_WIDTH (1U) 3256 #define DMA_TCD_CH6_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_ES_DBE_SHIFT)) & DMA_TCD_CH6_ES_DBE_MASK) 3257 3258 #define DMA_TCD_CH6_ES_SBE_MASK (0x2U) 3259 #define DMA_TCD_CH6_ES_SBE_SHIFT (1U) 3260 #define DMA_TCD_CH6_ES_SBE_WIDTH (1U) 3261 #define DMA_TCD_CH6_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_ES_SBE_SHIFT)) & DMA_TCD_CH6_ES_SBE_MASK) 3262 3263 #define DMA_TCD_CH6_ES_SGE_MASK (0x4U) 3264 #define DMA_TCD_CH6_ES_SGE_SHIFT (2U) 3265 #define DMA_TCD_CH6_ES_SGE_WIDTH (1U) 3266 #define DMA_TCD_CH6_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_ES_SGE_SHIFT)) & DMA_TCD_CH6_ES_SGE_MASK) 3267 3268 #define DMA_TCD_CH6_ES_NCE_MASK (0x8U) 3269 #define DMA_TCD_CH6_ES_NCE_SHIFT (3U) 3270 #define DMA_TCD_CH6_ES_NCE_WIDTH (1U) 3271 #define DMA_TCD_CH6_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_ES_NCE_SHIFT)) & DMA_TCD_CH6_ES_NCE_MASK) 3272 3273 #define DMA_TCD_CH6_ES_DOE_MASK (0x10U) 3274 #define DMA_TCD_CH6_ES_DOE_SHIFT (4U) 3275 #define DMA_TCD_CH6_ES_DOE_WIDTH (1U) 3276 #define DMA_TCD_CH6_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_ES_DOE_SHIFT)) & DMA_TCD_CH6_ES_DOE_MASK) 3277 3278 #define DMA_TCD_CH6_ES_DAE_MASK (0x20U) 3279 #define DMA_TCD_CH6_ES_DAE_SHIFT (5U) 3280 #define DMA_TCD_CH6_ES_DAE_WIDTH (1U) 3281 #define DMA_TCD_CH6_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_ES_DAE_SHIFT)) & DMA_TCD_CH6_ES_DAE_MASK) 3282 3283 #define DMA_TCD_CH6_ES_SOE_MASK (0x40U) 3284 #define DMA_TCD_CH6_ES_SOE_SHIFT (6U) 3285 #define DMA_TCD_CH6_ES_SOE_WIDTH (1U) 3286 #define DMA_TCD_CH6_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_ES_SOE_SHIFT)) & DMA_TCD_CH6_ES_SOE_MASK) 3287 3288 #define DMA_TCD_CH6_ES_SAE_MASK (0x80U) 3289 #define DMA_TCD_CH6_ES_SAE_SHIFT (7U) 3290 #define DMA_TCD_CH6_ES_SAE_WIDTH (1U) 3291 #define DMA_TCD_CH6_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_ES_SAE_SHIFT)) & DMA_TCD_CH6_ES_SAE_MASK) 3292 3293 #define DMA_TCD_CH6_ES_ERR_MASK (0x80000000U) 3294 #define DMA_TCD_CH6_ES_ERR_SHIFT (31U) 3295 #define DMA_TCD_CH6_ES_ERR_WIDTH (1U) 3296 #define DMA_TCD_CH6_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_ES_ERR_SHIFT)) & DMA_TCD_CH6_ES_ERR_MASK) 3297 /*! @} */ 3298 3299 /*! @name CH6_INT - Channel Interrupt Status */ 3300 /*! @{ */ 3301 3302 #define DMA_TCD_CH6_INT_INT_MASK (0x1U) 3303 #define DMA_TCD_CH6_INT_INT_SHIFT (0U) 3304 #define DMA_TCD_CH6_INT_INT_WIDTH (1U) 3305 #define DMA_TCD_CH6_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_INT_INT_SHIFT)) & DMA_TCD_CH6_INT_INT_MASK) 3306 /*! @} */ 3307 3308 /*! @name CH6_SBR - Channel System Bus */ 3309 /*! @{ */ 3310 3311 #define DMA_TCD_CH6_SBR_MID_MASK (0xFU) 3312 #define DMA_TCD_CH6_SBR_MID_SHIFT (0U) 3313 #define DMA_TCD_CH6_SBR_MID_WIDTH (4U) 3314 #define DMA_TCD_CH6_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_SBR_MID_SHIFT)) & DMA_TCD_CH6_SBR_MID_MASK) 3315 3316 #define DMA_TCD_CH6_SBR_PAL_MASK (0x8000U) 3317 #define DMA_TCD_CH6_SBR_PAL_SHIFT (15U) 3318 #define DMA_TCD_CH6_SBR_PAL_WIDTH (1U) 3319 #define DMA_TCD_CH6_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_SBR_PAL_SHIFT)) & DMA_TCD_CH6_SBR_PAL_MASK) 3320 3321 #define DMA_TCD_CH6_SBR_EMI_MASK (0x10000U) 3322 #define DMA_TCD_CH6_SBR_EMI_SHIFT (16U) 3323 #define DMA_TCD_CH6_SBR_EMI_WIDTH (1U) 3324 #define DMA_TCD_CH6_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_SBR_EMI_SHIFT)) & DMA_TCD_CH6_SBR_EMI_MASK) 3325 3326 #define DMA_TCD_CH6_SBR_ATTR_MASK (0xE0000U) 3327 #define DMA_TCD_CH6_SBR_ATTR_SHIFT (17U) 3328 #define DMA_TCD_CH6_SBR_ATTR_WIDTH (3U) 3329 #define DMA_TCD_CH6_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_SBR_ATTR_SHIFT)) & DMA_TCD_CH6_SBR_ATTR_MASK) 3330 /*! @} */ 3331 3332 /*! @name CH6_PRI - Channel Priority */ 3333 /*! @{ */ 3334 3335 #define DMA_TCD_CH6_PRI_APL_MASK (0x7U) 3336 #define DMA_TCD_CH6_PRI_APL_SHIFT (0U) 3337 #define DMA_TCD_CH6_PRI_APL_WIDTH (3U) 3338 #define DMA_TCD_CH6_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_PRI_APL_SHIFT)) & DMA_TCD_CH6_PRI_APL_MASK) 3339 3340 #define DMA_TCD_CH6_PRI_DPA_MASK (0x40000000U) 3341 #define DMA_TCD_CH6_PRI_DPA_SHIFT (30U) 3342 #define DMA_TCD_CH6_PRI_DPA_WIDTH (1U) 3343 #define DMA_TCD_CH6_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_PRI_DPA_SHIFT)) & DMA_TCD_CH6_PRI_DPA_MASK) 3344 3345 #define DMA_TCD_CH6_PRI_ECP_MASK (0x80000000U) 3346 #define DMA_TCD_CH6_PRI_ECP_SHIFT (31U) 3347 #define DMA_TCD_CH6_PRI_ECP_WIDTH (1U) 3348 #define DMA_TCD_CH6_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH6_PRI_ECP_SHIFT)) & DMA_TCD_CH6_PRI_ECP_MASK) 3349 /*! @} */ 3350 3351 /*! @name TCD6_SADDR - TCD Source Address */ 3352 /*! @{ */ 3353 3354 #define DMA_TCD_TCD6_SADDR_SADDR_MASK (0xFFFFFFFFU) 3355 #define DMA_TCD_TCD6_SADDR_SADDR_SHIFT (0U) 3356 #define DMA_TCD_TCD6_SADDR_SADDR_WIDTH (32U) 3357 #define DMA_TCD_TCD6_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD6_SADDR_SADDR_MASK) 3358 /*! @} */ 3359 3360 /*! @name TCD6_SOFF - TCD Signed Source Address Offset */ 3361 /*! @{ */ 3362 3363 #define DMA_TCD_TCD6_SOFF_SOFF_MASK (0xFFFFU) 3364 #define DMA_TCD_TCD6_SOFF_SOFF_SHIFT (0U) 3365 #define DMA_TCD_TCD6_SOFF_SOFF_WIDTH (16U) 3366 #define DMA_TCD_TCD6_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD6_SOFF_SOFF_MASK) 3367 /*! @} */ 3368 3369 /*! @name TCD6_ATTR - TCD Transfer Attributes */ 3370 /*! @{ */ 3371 3372 #define DMA_TCD_TCD6_ATTR_DSIZE_MASK (0x7U) 3373 #define DMA_TCD_TCD6_ATTR_DSIZE_SHIFT (0U) 3374 #define DMA_TCD_TCD6_ATTR_DSIZE_WIDTH (3U) 3375 #define DMA_TCD_TCD6_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD6_ATTR_DSIZE_MASK) 3376 3377 #define DMA_TCD_TCD6_ATTR_DMOD_MASK (0xF8U) 3378 #define DMA_TCD_TCD6_ATTR_DMOD_SHIFT (3U) 3379 #define DMA_TCD_TCD6_ATTR_DMOD_WIDTH (5U) 3380 #define DMA_TCD_TCD6_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD6_ATTR_DMOD_MASK) 3381 3382 #define DMA_TCD_TCD6_ATTR_SSIZE_MASK (0x700U) 3383 #define DMA_TCD_TCD6_ATTR_SSIZE_SHIFT (8U) 3384 #define DMA_TCD_TCD6_ATTR_SSIZE_WIDTH (3U) 3385 #define DMA_TCD_TCD6_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD6_ATTR_SSIZE_MASK) 3386 3387 #define DMA_TCD_TCD6_ATTR_SMOD_MASK (0xF800U) 3388 #define DMA_TCD_TCD6_ATTR_SMOD_SHIFT (11U) 3389 #define DMA_TCD_TCD6_ATTR_SMOD_WIDTH (5U) 3390 #define DMA_TCD_TCD6_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD6_ATTR_SMOD_MASK) 3391 /*! @} */ 3392 3393 /*! @name TCD6_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 3394 /*! @{ */ 3395 3396 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 3397 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 3398 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 3399 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD6_NBYTES_MLOFFNO_NBYTES_MASK) 3400 3401 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 3402 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 3403 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 3404 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD6_NBYTES_MLOFFNO_DMLOE_MASK) 3405 3406 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 3407 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 3408 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 3409 #define DMA_TCD_TCD6_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD6_NBYTES_MLOFFNO_SMLOE_MASK) 3410 /*! @} */ 3411 3412 /*! @name TCD6_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 3413 /*! @{ */ 3414 3415 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 3416 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 3417 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 3418 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD6_NBYTES_MLOFFYES_NBYTES_MASK) 3419 3420 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 3421 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 3422 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 3423 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD6_NBYTES_MLOFFYES_MLOFF_MASK) 3424 3425 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 3426 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 3427 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 3428 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD6_NBYTES_MLOFFYES_DMLOE_MASK) 3429 3430 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 3431 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 3432 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 3433 #define DMA_TCD_TCD6_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD6_NBYTES_MLOFFYES_SMLOE_MASK) 3434 /*! @} */ 3435 3436 /*! @name TCD6_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 3437 /*! @{ */ 3438 3439 #define DMA_TCD_TCD6_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 3440 #define DMA_TCD_TCD6_SLAST_SDA_SLAST_SDA_SHIFT (0U) 3441 #define DMA_TCD_TCD6_SLAST_SDA_SLAST_SDA_WIDTH (32U) 3442 #define DMA_TCD_TCD6_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD6_SLAST_SDA_SLAST_SDA_MASK) 3443 /*! @} */ 3444 3445 /*! @name TCD6_DADDR - TCD Destination Address */ 3446 /*! @{ */ 3447 3448 #define DMA_TCD_TCD6_DADDR_DADDR_MASK (0xFFFFFFFFU) 3449 #define DMA_TCD_TCD6_DADDR_DADDR_SHIFT (0U) 3450 #define DMA_TCD_TCD6_DADDR_DADDR_WIDTH (32U) 3451 #define DMA_TCD_TCD6_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD6_DADDR_DADDR_MASK) 3452 /*! @} */ 3453 3454 /*! @name TCD6_DOFF - TCD Signed Destination Address Offset */ 3455 /*! @{ */ 3456 3457 #define DMA_TCD_TCD6_DOFF_DOFF_MASK (0xFFFFU) 3458 #define DMA_TCD_TCD6_DOFF_DOFF_SHIFT (0U) 3459 #define DMA_TCD_TCD6_DOFF_DOFF_WIDTH (16U) 3460 #define DMA_TCD_TCD6_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD6_DOFF_DOFF_MASK) 3461 /*! @} */ 3462 3463 /*! @name TCD6_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 3464 /*! @{ */ 3465 3466 #define DMA_TCD_TCD6_CITER_ELINKNO_CITER_MASK (0x7FFFU) 3467 #define DMA_TCD_TCD6_CITER_ELINKNO_CITER_SHIFT (0U) 3468 #define DMA_TCD_TCD6_CITER_ELINKNO_CITER_WIDTH (15U) 3469 #define DMA_TCD_TCD6_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD6_CITER_ELINKNO_CITER_MASK) 3470 3471 #define DMA_TCD_TCD6_CITER_ELINKNO_ELINK_MASK (0x8000U) 3472 #define DMA_TCD_TCD6_CITER_ELINKNO_ELINK_SHIFT (15U) 3473 #define DMA_TCD_TCD6_CITER_ELINKNO_ELINK_WIDTH (1U) 3474 #define DMA_TCD_TCD6_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD6_CITER_ELINKNO_ELINK_MASK) 3475 /*! @} */ 3476 3477 /*! @name TCD6_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 3478 /*! @{ */ 3479 3480 #define DMA_TCD_TCD6_CITER_ELINKYES_CITER_MASK (0x1FFU) 3481 #define DMA_TCD_TCD6_CITER_ELINKYES_CITER_SHIFT (0U) 3482 #define DMA_TCD_TCD6_CITER_ELINKYES_CITER_WIDTH (9U) 3483 #define DMA_TCD_TCD6_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD6_CITER_ELINKYES_CITER_MASK) 3484 3485 #define DMA_TCD_TCD6_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 3486 #define DMA_TCD_TCD6_CITER_ELINKYES_LINKCH_SHIFT (9U) 3487 #define DMA_TCD_TCD6_CITER_ELINKYES_LINKCH_WIDTH (5U) 3488 #define DMA_TCD_TCD6_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD6_CITER_ELINKYES_LINKCH_MASK) 3489 3490 #define DMA_TCD_TCD6_CITER_ELINKYES_ELINK_MASK (0x8000U) 3491 #define DMA_TCD_TCD6_CITER_ELINKYES_ELINK_SHIFT (15U) 3492 #define DMA_TCD_TCD6_CITER_ELINKYES_ELINK_WIDTH (1U) 3493 #define DMA_TCD_TCD6_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD6_CITER_ELINKYES_ELINK_MASK) 3494 /*! @} */ 3495 3496 /*! @name TCD6_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 3497 /*! @{ */ 3498 3499 #define DMA_TCD_TCD6_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 3500 #define DMA_TCD_TCD6_DLAST_SGA_DLAST_SGA_SHIFT (0U) 3501 #define DMA_TCD_TCD6_DLAST_SGA_DLAST_SGA_WIDTH (32U) 3502 #define DMA_TCD_TCD6_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD6_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD6_DLAST_SGA_DLAST_SGA_MASK) 3503 /*! @} */ 3504 3505 /*! @name TCD6_CSR - TCD Control and Status */ 3506 /*! @{ */ 3507 3508 #define DMA_TCD_TCD6_CSR_START_MASK (0x1U) 3509 #define DMA_TCD_TCD6_CSR_START_SHIFT (0U) 3510 #define DMA_TCD_TCD6_CSR_START_WIDTH (1U) 3511 #define DMA_TCD_TCD6_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CSR_START_SHIFT)) & DMA_TCD_TCD6_CSR_START_MASK) 3512 3513 #define DMA_TCD_TCD6_CSR_INTMAJOR_MASK (0x2U) 3514 #define DMA_TCD_TCD6_CSR_INTMAJOR_SHIFT (1U) 3515 #define DMA_TCD_TCD6_CSR_INTMAJOR_WIDTH (1U) 3516 #define DMA_TCD_TCD6_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD6_CSR_INTMAJOR_MASK) 3517 3518 #define DMA_TCD_TCD6_CSR_INTHALF_MASK (0x4U) 3519 #define DMA_TCD_TCD6_CSR_INTHALF_SHIFT (2U) 3520 #define DMA_TCD_TCD6_CSR_INTHALF_WIDTH (1U) 3521 #define DMA_TCD_TCD6_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD6_CSR_INTHALF_MASK) 3522 3523 #define DMA_TCD_TCD6_CSR_DREQ_MASK (0x8U) 3524 #define DMA_TCD_TCD6_CSR_DREQ_SHIFT (3U) 3525 #define DMA_TCD_TCD6_CSR_DREQ_WIDTH (1U) 3526 #define DMA_TCD_TCD6_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CSR_DREQ_SHIFT)) & DMA_TCD_TCD6_CSR_DREQ_MASK) 3527 3528 #define DMA_TCD_TCD6_CSR_ESG_MASK (0x10U) 3529 #define DMA_TCD_TCD6_CSR_ESG_SHIFT (4U) 3530 #define DMA_TCD_TCD6_CSR_ESG_WIDTH (1U) 3531 #define DMA_TCD_TCD6_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CSR_ESG_SHIFT)) & DMA_TCD_TCD6_CSR_ESG_MASK) 3532 3533 #define DMA_TCD_TCD6_CSR_MAJORELINK_MASK (0x20U) 3534 #define DMA_TCD_TCD6_CSR_MAJORELINK_SHIFT (5U) 3535 #define DMA_TCD_TCD6_CSR_MAJORELINK_WIDTH (1U) 3536 #define DMA_TCD_TCD6_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD6_CSR_MAJORELINK_MASK) 3537 3538 #define DMA_TCD_TCD6_CSR_EEOP_MASK (0x40U) 3539 #define DMA_TCD_TCD6_CSR_EEOP_SHIFT (6U) 3540 #define DMA_TCD_TCD6_CSR_EEOP_WIDTH (1U) 3541 #define DMA_TCD_TCD6_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CSR_EEOP_SHIFT)) & DMA_TCD_TCD6_CSR_EEOP_MASK) 3542 3543 #define DMA_TCD_TCD6_CSR_ESDA_MASK (0x80U) 3544 #define DMA_TCD_TCD6_CSR_ESDA_SHIFT (7U) 3545 #define DMA_TCD_TCD6_CSR_ESDA_WIDTH (1U) 3546 #define DMA_TCD_TCD6_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CSR_ESDA_SHIFT)) & DMA_TCD_TCD6_CSR_ESDA_MASK) 3547 3548 #define DMA_TCD_TCD6_CSR_MAJORLINKCH_MASK (0x1F00U) 3549 #define DMA_TCD_TCD6_CSR_MAJORLINKCH_SHIFT (8U) 3550 #define DMA_TCD_TCD6_CSR_MAJORLINKCH_WIDTH (5U) 3551 #define DMA_TCD_TCD6_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD6_CSR_MAJORLINKCH_MASK) 3552 3553 #define DMA_TCD_TCD6_CSR_BWC_MASK (0xC000U) 3554 #define DMA_TCD_TCD6_CSR_BWC_SHIFT (14U) 3555 #define DMA_TCD_TCD6_CSR_BWC_WIDTH (2U) 3556 #define DMA_TCD_TCD6_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_CSR_BWC_SHIFT)) & DMA_TCD_TCD6_CSR_BWC_MASK) 3557 /*! @} */ 3558 3559 /*! @name TCD6_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 3560 /*! @{ */ 3561 3562 #define DMA_TCD_TCD6_BITER_ELINKNO_BITER_MASK (0x7FFFU) 3563 #define DMA_TCD_TCD6_BITER_ELINKNO_BITER_SHIFT (0U) 3564 #define DMA_TCD_TCD6_BITER_ELINKNO_BITER_WIDTH (15U) 3565 #define DMA_TCD_TCD6_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD6_BITER_ELINKNO_BITER_MASK) 3566 3567 #define DMA_TCD_TCD6_BITER_ELINKNO_ELINK_MASK (0x8000U) 3568 #define DMA_TCD_TCD6_BITER_ELINKNO_ELINK_SHIFT (15U) 3569 #define DMA_TCD_TCD6_BITER_ELINKNO_ELINK_WIDTH (1U) 3570 #define DMA_TCD_TCD6_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD6_BITER_ELINKNO_ELINK_MASK) 3571 /*! @} */ 3572 3573 /*! @name TCD6_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 3574 /*! @{ */ 3575 3576 #define DMA_TCD_TCD6_BITER_ELINKYES_BITER_MASK (0x1FFU) 3577 #define DMA_TCD_TCD6_BITER_ELINKYES_BITER_SHIFT (0U) 3578 #define DMA_TCD_TCD6_BITER_ELINKYES_BITER_WIDTH (9U) 3579 #define DMA_TCD_TCD6_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD6_BITER_ELINKYES_BITER_MASK) 3580 3581 #define DMA_TCD_TCD6_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 3582 #define DMA_TCD_TCD6_BITER_ELINKYES_LINKCH_SHIFT (9U) 3583 #define DMA_TCD_TCD6_BITER_ELINKYES_LINKCH_WIDTH (5U) 3584 #define DMA_TCD_TCD6_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD6_BITER_ELINKYES_LINKCH_MASK) 3585 3586 #define DMA_TCD_TCD6_BITER_ELINKYES_ELINK_MASK (0x8000U) 3587 #define DMA_TCD_TCD6_BITER_ELINKYES_ELINK_SHIFT (15U) 3588 #define DMA_TCD_TCD6_BITER_ELINKYES_ELINK_WIDTH (1U) 3589 #define DMA_TCD_TCD6_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD6_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD6_BITER_ELINKYES_ELINK_MASK) 3590 /*! @} */ 3591 3592 /*! @name CH7_CSR - Channel Control and Status */ 3593 /*! @{ */ 3594 3595 #define DMA_TCD_CH7_CSR_ERQ_MASK (0x1U) 3596 #define DMA_TCD_CH7_CSR_ERQ_SHIFT (0U) 3597 #define DMA_TCD_CH7_CSR_ERQ_WIDTH (1U) 3598 #define DMA_TCD_CH7_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_CSR_ERQ_SHIFT)) & DMA_TCD_CH7_CSR_ERQ_MASK) 3599 3600 #define DMA_TCD_CH7_CSR_EARQ_MASK (0x2U) 3601 #define DMA_TCD_CH7_CSR_EARQ_SHIFT (1U) 3602 #define DMA_TCD_CH7_CSR_EARQ_WIDTH (1U) 3603 #define DMA_TCD_CH7_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_CSR_EARQ_SHIFT)) & DMA_TCD_CH7_CSR_EARQ_MASK) 3604 3605 #define DMA_TCD_CH7_CSR_EEI_MASK (0x4U) 3606 #define DMA_TCD_CH7_CSR_EEI_SHIFT (2U) 3607 #define DMA_TCD_CH7_CSR_EEI_WIDTH (1U) 3608 #define DMA_TCD_CH7_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_CSR_EEI_SHIFT)) & DMA_TCD_CH7_CSR_EEI_MASK) 3609 3610 #define DMA_TCD_CH7_CSR_EBW_MASK (0x8U) 3611 #define DMA_TCD_CH7_CSR_EBW_SHIFT (3U) 3612 #define DMA_TCD_CH7_CSR_EBW_WIDTH (1U) 3613 #define DMA_TCD_CH7_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_CSR_EBW_SHIFT)) & DMA_TCD_CH7_CSR_EBW_MASK) 3614 3615 #define DMA_TCD_CH7_CSR_DONE_MASK (0x40000000U) 3616 #define DMA_TCD_CH7_CSR_DONE_SHIFT (30U) 3617 #define DMA_TCD_CH7_CSR_DONE_WIDTH (1U) 3618 #define DMA_TCD_CH7_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_CSR_DONE_SHIFT)) & DMA_TCD_CH7_CSR_DONE_MASK) 3619 3620 #define DMA_TCD_CH7_CSR_ACTIVE_MASK (0x80000000U) 3621 #define DMA_TCD_CH7_CSR_ACTIVE_SHIFT (31U) 3622 #define DMA_TCD_CH7_CSR_ACTIVE_WIDTH (1U) 3623 #define DMA_TCD_CH7_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH7_CSR_ACTIVE_MASK) 3624 /*! @} */ 3625 3626 /*! @name CH7_ES - Channel Error Status */ 3627 /*! @{ */ 3628 3629 #define DMA_TCD_CH7_ES_DBE_MASK (0x1U) 3630 #define DMA_TCD_CH7_ES_DBE_SHIFT (0U) 3631 #define DMA_TCD_CH7_ES_DBE_WIDTH (1U) 3632 #define DMA_TCD_CH7_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_ES_DBE_SHIFT)) & DMA_TCD_CH7_ES_DBE_MASK) 3633 3634 #define DMA_TCD_CH7_ES_SBE_MASK (0x2U) 3635 #define DMA_TCD_CH7_ES_SBE_SHIFT (1U) 3636 #define DMA_TCD_CH7_ES_SBE_WIDTH (1U) 3637 #define DMA_TCD_CH7_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_ES_SBE_SHIFT)) & DMA_TCD_CH7_ES_SBE_MASK) 3638 3639 #define DMA_TCD_CH7_ES_SGE_MASK (0x4U) 3640 #define DMA_TCD_CH7_ES_SGE_SHIFT (2U) 3641 #define DMA_TCD_CH7_ES_SGE_WIDTH (1U) 3642 #define DMA_TCD_CH7_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_ES_SGE_SHIFT)) & DMA_TCD_CH7_ES_SGE_MASK) 3643 3644 #define DMA_TCD_CH7_ES_NCE_MASK (0x8U) 3645 #define DMA_TCD_CH7_ES_NCE_SHIFT (3U) 3646 #define DMA_TCD_CH7_ES_NCE_WIDTH (1U) 3647 #define DMA_TCD_CH7_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_ES_NCE_SHIFT)) & DMA_TCD_CH7_ES_NCE_MASK) 3648 3649 #define DMA_TCD_CH7_ES_DOE_MASK (0x10U) 3650 #define DMA_TCD_CH7_ES_DOE_SHIFT (4U) 3651 #define DMA_TCD_CH7_ES_DOE_WIDTH (1U) 3652 #define DMA_TCD_CH7_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_ES_DOE_SHIFT)) & DMA_TCD_CH7_ES_DOE_MASK) 3653 3654 #define DMA_TCD_CH7_ES_DAE_MASK (0x20U) 3655 #define DMA_TCD_CH7_ES_DAE_SHIFT (5U) 3656 #define DMA_TCD_CH7_ES_DAE_WIDTH (1U) 3657 #define DMA_TCD_CH7_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_ES_DAE_SHIFT)) & DMA_TCD_CH7_ES_DAE_MASK) 3658 3659 #define DMA_TCD_CH7_ES_SOE_MASK (0x40U) 3660 #define DMA_TCD_CH7_ES_SOE_SHIFT (6U) 3661 #define DMA_TCD_CH7_ES_SOE_WIDTH (1U) 3662 #define DMA_TCD_CH7_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_ES_SOE_SHIFT)) & DMA_TCD_CH7_ES_SOE_MASK) 3663 3664 #define DMA_TCD_CH7_ES_SAE_MASK (0x80U) 3665 #define DMA_TCD_CH7_ES_SAE_SHIFT (7U) 3666 #define DMA_TCD_CH7_ES_SAE_WIDTH (1U) 3667 #define DMA_TCD_CH7_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_ES_SAE_SHIFT)) & DMA_TCD_CH7_ES_SAE_MASK) 3668 3669 #define DMA_TCD_CH7_ES_ERR_MASK (0x80000000U) 3670 #define DMA_TCD_CH7_ES_ERR_SHIFT (31U) 3671 #define DMA_TCD_CH7_ES_ERR_WIDTH (1U) 3672 #define DMA_TCD_CH7_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_ES_ERR_SHIFT)) & DMA_TCD_CH7_ES_ERR_MASK) 3673 /*! @} */ 3674 3675 /*! @name CH7_INT - Channel Interrupt Status */ 3676 /*! @{ */ 3677 3678 #define DMA_TCD_CH7_INT_INT_MASK (0x1U) 3679 #define DMA_TCD_CH7_INT_INT_SHIFT (0U) 3680 #define DMA_TCD_CH7_INT_INT_WIDTH (1U) 3681 #define DMA_TCD_CH7_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_INT_INT_SHIFT)) & DMA_TCD_CH7_INT_INT_MASK) 3682 /*! @} */ 3683 3684 /*! @name CH7_SBR - Channel System Bus */ 3685 /*! @{ */ 3686 3687 #define DMA_TCD_CH7_SBR_MID_MASK (0xFU) 3688 #define DMA_TCD_CH7_SBR_MID_SHIFT (0U) 3689 #define DMA_TCD_CH7_SBR_MID_WIDTH (4U) 3690 #define DMA_TCD_CH7_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_SBR_MID_SHIFT)) & DMA_TCD_CH7_SBR_MID_MASK) 3691 3692 #define DMA_TCD_CH7_SBR_PAL_MASK (0x8000U) 3693 #define DMA_TCD_CH7_SBR_PAL_SHIFT (15U) 3694 #define DMA_TCD_CH7_SBR_PAL_WIDTH (1U) 3695 #define DMA_TCD_CH7_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_SBR_PAL_SHIFT)) & DMA_TCD_CH7_SBR_PAL_MASK) 3696 3697 #define DMA_TCD_CH7_SBR_EMI_MASK (0x10000U) 3698 #define DMA_TCD_CH7_SBR_EMI_SHIFT (16U) 3699 #define DMA_TCD_CH7_SBR_EMI_WIDTH (1U) 3700 #define DMA_TCD_CH7_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_SBR_EMI_SHIFT)) & DMA_TCD_CH7_SBR_EMI_MASK) 3701 3702 #define DMA_TCD_CH7_SBR_ATTR_MASK (0xE0000U) 3703 #define DMA_TCD_CH7_SBR_ATTR_SHIFT (17U) 3704 #define DMA_TCD_CH7_SBR_ATTR_WIDTH (3U) 3705 #define DMA_TCD_CH7_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_SBR_ATTR_SHIFT)) & DMA_TCD_CH7_SBR_ATTR_MASK) 3706 /*! @} */ 3707 3708 /*! @name CH7_PRI - Channel Priority */ 3709 /*! @{ */ 3710 3711 #define DMA_TCD_CH7_PRI_APL_MASK (0x7U) 3712 #define DMA_TCD_CH7_PRI_APL_SHIFT (0U) 3713 #define DMA_TCD_CH7_PRI_APL_WIDTH (3U) 3714 #define DMA_TCD_CH7_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_PRI_APL_SHIFT)) & DMA_TCD_CH7_PRI_APL_MASK) 3715 3716 #define DMA_TCD_CH7_PRI_DPA_MASK (0x40000000U) 3717 #define DMA_TCD_CH7_PRI_DPA_SHIFT (30U) 3718 #define DMA_TCD_CH7_PRI_DPA_WIDTH (1U) 3719 #define DMA_TCD_CH7_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_PRI_DPA_SHIFT)) & DMA_TCD_CH7_PRI_DPA_MASK) 3720 3721 #define DMA_TCD_CH7_PRI_ECP_MASK (0x80000000U) 3722 #define DMA_TCD_CH7_PRI_ECP_SHIFT (31U) 3723 #define DMA_TCD_CH7_PRI_ECP_WIDTH (1U) 3724 #define DMA_TCD_CH7_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH7_PRI_ECP_SHIFT)) & DMA_TCD_CH7_PRI_ECP_MASK) 3725 /*! @} */ 3726 3727 /*! @name TCD7_SADDR - TCD Source Address */ 3728 /*! @{ */ 3729 3730 #define DMA_TCD_TCD7_SADDR_SADDR_MASK (0xFFFFFFFFU) 3731 #define DMA_TCD_TCD7_SADDR_SADDR_SHIFT (0U) 3732 #define DMA_TCD_TCD7_SADDR_SADDR_WIDTH (32U) 3733 #define DMA_TCD_TCD7_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD7_SADDR_SADDR_MASK) 3734 /*! @} */ 3735 3736 /*! @name TCD7_SOFF - TCD Signed Source Address Offset */ 3737 /*! @{ */ 3738 3739 #define DMA_TCD_TCD7_SOFF_SOFF_MASK (0xFFFFU) 3740 #define DMA_TCD_TCD7_SOFF_SOFF_SHIFT (0U) 3741 #define DMA_TCD_TCD7_SOFF_SOFF_WIDTH (16U) 3742 #define DMA_TCD_TCD7_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD7_SOFF_SOFF_MASK) 3743 /*! @} */ 3744 3745 /*! @name TCD7_ATTR - TCD Transfer Attributes */ 3746 /*! @{ */ 3747 3748 #define DMA_TCD_TCD7_ATTR_DSIZE_MASK (0x7U) 3749 #define DMA_TCD_TCD7_ATTR_DSIZE_SHIFT (0U) 3750 #define DMA_TCD_TCD7_ATTR_DSIZE_WIDTH (3U) 3751 #define DMA_TCD_TCD7_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD7_ATTR_DSIZE_MASK) 3752 3753 #define DMA_TCD_TCD7_ATTR_DMOD_MASK (0xF8U) 3754 #define DMA_TCD_TCD7_ATTR_DMOD_SHIFT (3U) 3755 #define DMA_TCD_TCD7_ATTR_DMOD_WIDTH (5U) 3756 #define DMA_TCD_TCD7_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD7_ATTR_DMOD_MASK) 3757 3758 #define DMA_TCD_TCD7_ATTR_SSIZE_MASK (0x700U) 3759 #define DMA_TCD_TCD7_ATTR_SSIZE_SHIFT (8U) 3760 #define DMA_TCD_TCD7_ATTR_SSIZE_WIDTH (3U) 3761 #define DMA_TCD_TCD7_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD7_ATTR_SSIZE_MASK) 3762 3763 #define DMA_TCD_TCD7_ATTR_SMOD_MASK (0xF800U) 3764 #define DMA_TCD_TCD7_ATTR_SMOD_SHIFT (11U) 3765 #define DMA_TCD_TCD7_ATTR_SMOD_WIDTH (5U) 3766 #define DMA_TCD_TCD7_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD7_ATTR_SMOD_MASK) 3767 /*! @} */ 3768 3769 /*! @name TCD7_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 3770 /*! @{ */ 3771 3772 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 3773 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 3774 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 3775 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD7_NBYTES_MLOFFNO_NBYTES_MASK) 3776 3777 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 3778 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 3779 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 3780 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD7_NBYTES_MLOFFNO_DMLOE_MASK) 3781 3782 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 3783 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 3784 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 3785 #define DMA_TCD_TCD7_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD7_NBYTES_MLOFFNO_SMLOE_MASK) 3786 /*! @} */ 3787 3788 /*! @name TCD7_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 3789 /*! @{ */ 3790 3791 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 3792 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 3793 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 3794 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD7_NBYTES_MLOFFYES_NBYTES_MASK) 3795 3796 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 3797 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 3798 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 3799 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD7_NBYTES_MLOFFYES_MLOFF_MASK) 3800 3801 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 3802 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 3803 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 3804 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD7_NBYTES_MLOFFYES_DMLOE_MASK) 3805 3806 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 3807 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 3808 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 3809 #define DMA_TCD_TCD7_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD7_NBYTES_MLOFFYES_SMLOE_MASK) 3810 /*! @} */ 3811 3812 /*! @name TCD7_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 3813 /*! @{ */ 3814 3815 #define DMA_TCD_TCD7_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 3816 #define DMA_TCD_TCD7_SLAST_SDA_SLAST_SDA_SHIFT (0U) 3817 #define DMA_TCD_TCD7_SLAST_SDA_SLAST_SDA_WIDTH (32U) 3818 #define DMA_TCD_TCD7_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD7_SLAST_SDA_SLAST_SDA_MASK) 3819 /*! @} */ 3820 3821 /*! @name TCD7_DADDR - TCD Destination Address */ 3822 /*! @{ */ 3823 3824 #define DMA_TCD_TCD7_DADDR_DADDR_MASK (0xFFFFFFFFU) 3825 #define DMA_TCD_TCD7_DADDR_DADDR_SHIFT (0U) 3826 #define DMA_TCD_TCD7_DADDR_DADDR_WIDTH (32U) 3827 #define DMA_TCD_TCD7_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD7_DADDR_DADDR_MASK) 3828 /*! @} */ 3829 3830 /*! @name TCD7_DOFF - TCD Signed Destination Address Offset */ 3831 /*! @{ */ 3832 3833 #define DMA_TCD_TCD7_DOFF_DOFF_MASK (0xFFFFU) 3834 #define DMA_TCD_TCD7_DOFF_DOFF_SHIFT (0U) 3835 #define DMA_TCD_TCD7_DOFF_DOFF_WIDTH (16U) 3836 #define DMA_TCD_TCD7_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD7_DOFF_DOFF_MASK) 3837 /*! @} */ 3838 3839 /*! @name TCD7_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 3840 /*! @{ */ 3841 3842 #define DMA_TCD_TCD7_CITER_ELINKNO_CITER_MASK (0x7FFFU) 3843 #define DMA_TCD_TCD7_CITER_ELINKNO_CITER_SHIFT (0U) 3844 #define DMA_TCD_TCD7_CITER_ELINKNO_CITER_WIDTH (15U) 3845 #define DMA_TCD_TCD7_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD7_CITER_ELINKNO_CITER_MASK) 3846 3847 #define DMA_TCD_TCD7_CITER_ELINKNO_ELINK_MASK (0x8000U) 3848 #define DMA_TCD_TCD7_CITER_ELINKNO_ELINK_SHIFT (15U) 3849 #define DMA_TCD_TCD7_CITER_ELINKNO_ELINK_WIDTH (1U) 3850 #define DMA_TCD_TCD7_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD7_CITER_ELINKNO_ELINK_MASK) 3851 /*! @} */ 3852 3853 /*! @name TCD7_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 3854 /*! @{ */ 3855 3856 #define DMA_TCD_TCD7_CITER_ELINKYES_CITER_MASK (0x1FFU) 3857 #define DMA_TCD_TCD7_CITER_ELINKYES_CITER_SHIFT (0U) 3858 #define DMA_TCD_TCD7_CITER_ELINKYES_CITER_WIDTH (9U) 3859 #define DMA_TCD_TCD7_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD7_CITER_ELINKYES_CITER_MASK) 3860 3861 #define DMA_TCD_TCD7_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 3862 #define DMA_TCD_TCD7_CITER_ELINKYES_LINKCH_SHIFT (9U) 3863 #define DMA_TCD_TCD7_CITER_ELINKYES_LINKCH_WIDTH (5U) 3864 #define DMA_TCD_TCD7_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD7_CITER_ELINKYES_LINKCH_MASK) 3865 3866 #define DMA_TCD_TCD7_CITER_ELINKYES_ELINK_MASK (0x8000U) 3867 #define DMA_TCD_TCD7_CITER_ELINKYES_ELINK_SHIFT (15U) 3868 #define DMA_TCD_TCD7_CITER_ELINKYES_ELINK_WIDTH (1U) 3869 #define DMA_TCD_TCD7_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD7_CITER_ELINKYES_ELINK_MASK) 3870 /*! @} */ 3871 3872 /*! @name TCD7_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 3873 /*! @{ */ 3874 3875 #define DMA_TCD_TCD7_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 3876 #define DMA_TCD_TCD7_DLAST_SGA_DLAST_SGA_SHIFT (0U) 3877 #define DMA_TCD_TCD7_DLAST_SGA_DLAST_SGA_WIDTH (32U) 3878 #define DMA_TCD_TCD7_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD7_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD7_DLAST_SGA_DLAST_SGA_MASK) 3879 /*! @} */ 3880 3881 /*! @name TCD7_CSR - TCD Control and Status */ 3882 /*! @{ */ 3883 3884 #define DMA_TCD_TCD7_CSR_START_MASK (0x1U) 3885 #define DMA_TCD_TCD7_CSR_START_SHIFT (0U) 3886 #define DMA_TCD_TCD7_CSR_START_WIDTH (1U) 3887 #define DMA_TCD_TCD7_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CSR_START_SHIFT)) & DMA_TCD_TCD7_CSR_START_MASK) 3888 3889 #define DMA_TCD_TCD7_CSR_INTMAJOR_MASK (0x2U) 3890 #define DMA_TCD_TCD7_CSR_INTMAJOR_SHIFT (1U) 3891 #define DMA_TCD_TCD7_CSR_INTMAJOR_WIDTH (1U) 3892 #define DMA_TCD_TCD7_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD7_CSR_INTMAJOR_MASK) 3893 3894 #define DMA_TCD_TCD7_CSR_INTHALF_MASK (0x4U) 3895 #define DMA_TCD_TCD7_CSR_INTHALF_SHIFT (2U) 3896 #define DMA_TCD_TCD7_CSR_INTHALF_WIDTH (1U) 3897 #define DMA_TCD_TCD7_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD7_CSR_INTHALF_MASK) 3898 3899 #define DMA_TCD_TCD7_CSR_DREQ_MASK (0x8U) 3900 #define DMA_TCD_TCD7_CSR_DREQ_SHIFT (3U) 3901 #define DMA_TCD_TCD7_CSR_DREQ_WIDTH (1U) 3902 #define DMA_TCD_TCD7_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CSR_DREQ_SHIFT)) & DMA_TCD_TCD7_CSR_DREQ_MASK) 3903 3904 #define DMA_TCD_TCD7_CSR_ESG_MASK (0x10U) 3905 #define DMA_TCD_TCD7_CSR_ESG_SHIFT (4U) 3906 #define DMA_TCD_TCD7_CSR_ESG_WIDTH (1U) 3907 #define DMA_TCD_TCD7_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CSR_ESG_SHIFT)) & DMA_TCD_TCD7_CSR_ESG_MASK) 3908 3909 #define DMA_TCD_TCD7_CSR_MAJORELINK_MASK (0x20U) 3910 #define DMA_TCD_TCD7_CSR_MAJORELINK_SHIFT (5U) 3911 #define DMA_TCD_TCD7_CSR_MAJORELINK_WIDTH (1U) 3912 #define DMA_TCD_TCD7_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD7_CSR_MAJORELINK_MASK) 3913 3914 #define DMA_TCD_TCD7_CSR_EEOP_MASK (0x40U) 3915 #define DMA_TCD_TCD7_CSR_EEOP_SHIFT (6U) 3916 #define DMA_TCD_TCD7_CSR_EEOP_WIDTH (1U) 3917 #define DMA_TCD_TCD7_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CSR_EEOP_SHIFT)) & DMA_TCD_TCD7_CSR_EEOP_MASK) 3918 3919 #define DMA_TCD_TCD7_CSR_ESDA_MASK (0x80U) 3920 #define DMA_TCD_TCD7_CSR_ESDA_SHIFT (7U) 3921 #define DMA_TCD_TCD7_CSR_ESDA_WIDTH (1U) 3922 #define DMA_TCD_TCD7_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CSR_ESDA_SHIFT)) & DMA_TCD_TCD7_CSR_ESDA_MASK) 3923 3924 #define DMA_TCD_TCD7_CSR_MAJORLINKCH_MASK (0x1F00U) 3925 #define DMA_TCD_TCD7_CSR_MAJORLINKCH_SHIFT (8U) 3926 #define DMA_TCD_TCD7_CSR_MAJORLINKCH_WIDTH (5U) 3927 #define DMA_TCD_TCD7_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD7_CSR_MAJORLINKCH_MASK) 3928 3929 #define DMA_TCD_TCD7_CSR_BWC_MASK (0xC000U) 3930 #define DMA_TCD_TCD7_CSR_BWC_SHIFT (14U) 3931 #define DMA_TCD_TCD7_CSR_BWC_WIDTH (2U) 3932 #define DMA_TCD_TCD7_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_CSR_BWC_SHIFT)) & DMA_TCD_TCD7_CSR_BWC_MASK) 3933 /*! @} */ 3934 3935 /*! @name TCD7_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 3936 /*! @{ */ 3937 3938 #define DMA_TCD_TCD7_BITER_ELINKNO_BITER_MASK (0x7FFFU) 3939 #define DMA_TCD_TCD7_BITER_ELINKNO_BITER_SHIFT (0U) 3940 #define DMA_TCD_TCD7_BITER_ELINKNO_BITER_WIDTH (15U) 3941 #define DMA_TCD_TCD7_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD7_BITER_ELINKNO_BITER_MASK) 3942 3943 #define DMA_TCD_TCD7_BITER_ELINKNO_ELINK_MASK (0x8000U) 3944 #define DMA_TCD_TCD7_BITER_ELINKNO_ELINK_SHIFT (15U) 3945 #define DMA_TCD_TCD7_BITER_ELINKNO_ELINK_WIDTH (1U) 3946 #define DMA_TCD_TCD7_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD7_BITER_ELINKNO_ELINK_MASK) 3947 /*! @} */ 3948 3949 /*! @name TCD7_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 3950 /*! @{ */ 3951 3952 #define DMA_TCD_TCD7_BITER_ELINKYES_BITER_MASK (0x1FFU) 3953 #define DMA_TCD_TCD7_BITER_ELINKYES_BITER_SHIFT (0U) 3954 #define DMA_TCD_TCD7_BITER_ELINKYES_BITER_WIDTH (9U) 3955 #define DMA_TCD_TCD7_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD7_BITER_ELINKYES_BITER_MASK) 3956 3957 #define DMA_TCD_TCD7_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 3958 #define DMA_TCD_TCD7_BITER_ELINKYES_LINKCH_SHIFT (9U) 3959 #define DMA_TCD_TCD7_BITER_ELINKYES_LINKCH_WIDTH (5U) 3960 #define DMA_TCD_TCD7_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD7_BITER_ELINKYES_LINKCH_MASK) 3961 3962 #define DMA_TCD_TCD7_BITER_ELINKYES_ELINK_MASK (0x8000U) 3963 #define DMA_TCD_TCD7_BITER_ELINKYES_ELINK_SHIFT (15U) 3964 #define DMA_TCD_TCD7_BITER_ELINKYES_ELINK_WIDTH (1U) 3965 #define DMA_TCD_TCD7_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD7_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD7_BITER_ELINKYES_ELINK_MASK) 3966 /*! @} */ 3967 3968 /*! @name CH8_CSR - Channel Control and Status */ 3969 /*! @{ */ 3970 3971 #define DMA_TCD_CH8_CSR_ERQ_MASK (0x1U) 3972 #define DMA_TCD_CH8_CSR_ERQ_SHIFT (0U) 3973 #define DMA_TCD_CH8_CSR_ERQ_WIDTH (1U) 3974 #define DMA_TCD_CH8_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_CSR_ERQ_SHIFT)) & DMA_TCD_CH8_CSR_ERQ_MASK) 3975 3976 #define DMA_TCD_CH8_CSR_EARQ_MASK (0x2U) 3977 #define DMA_TCD_CH8_CSR_EARQ_SHIFT (1U) 3978 #define DMA_TCD_CH8_CSR_EARQ_WIDTH (1U) 3979 #define DMA_TCD_CH8_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_CSR_EARQ_SHIFT)) & DMA_TCD_CH8_CSR_EARQ_MASK) 3980 3981 #define DMA_TCD_CH8_CSR_EEI_MASK (0x4U) 3982 #define DMA_TCD_CH8_CSR_EEI_SHIFT (2U) 3983 #define DMA_TCD_CH8_CSR_EEI_WIDTH (1U) 3984 #define DMA_TCD_CH8_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_CSR_EEI_SHIFT)) & DMA_TCD_CH8_CSR_EEI_MASK) 3985 3986 #define DMA_TCD_CH8_CSR_EBW_MASK (0x8U) 3987 #define DMA_TCD_CH8_CSR_EBW_SHIFT (3U) 3988 #define DMA_TCD_CH8_CSR_EBW_WIDTH (1U) 3989 #define DMA_TCD_CH8_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_CSR_EBW_SHIFT)) & DMA_TCD_CH8_CSR_EBW_MASK) 3990 3991 #define DMA_TCD_CH8_CSR_DONE_MASK (0x40000000U) 3992 #define DMA_TCD_CH8_CSR_DONE_SHIFT (30U) 3993 #define DMA_TCD_CH8_CSR_DONE_WIDTH (1U) 3994 #define DMA_TCD_CH8_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_CSR_DONE_SHIFT)) & DMA_TCD_CH8_CSR_DONE_MASK) 3995 3996 #define DMA_TCD_CH8_CSR_ACTIVE_MASK (0x80000000U) 3997 #define DMA_TCD_CH8_CSR_ACTIVE_SHIFT (31U) 3998 #define DMA_TCD_CH8_CSR_ACTIVE_WIDTH (1U) 3999 #define DMA_TCD_CH8_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH8_CSR_ACTIVE_MASK) 4000 /*! @} */ 4001 4002 /*! @name CH8_ES - Channel Error Status */ 4003 /*! @{ */ 4004 4005 #define DMA_TCD_CH8_ES_DBE_MASK (0x1U) 4006 #define DMA_TCD_CH8_ES_DBE_SHIFT (0U) 4007 #define DMA_TCD_CH8_ES_DBE_WIDTH (1U) 4008 #define DMA_TCD_CH8_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_ES_DBE_SHIFT)) & DMA_TCD_CH8_ES_DBE_MASK) 4009 4010 #define DMA_TCD_CH8_ES_SBE_MASK (0x2U) 4011 #define DMA_TCD_CH8_ES_SBE_SHIFT (1U) 4012 #define DMA_TCD_CH8_ES_SBE_WIDTH (1U) 4013 #define DMA_TCD_CH8_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_ES_SBE_SHIFT)) & DMA_TCD_CH8_ES_SBE_MASK) 4014 4015 #define DMA_TCD_CH8_ES_SGE_MASK (0x4U) 4016 #define DMA_TCD_CH8_ES_SGE_SHIFT (2U) 4017 #define DMA_TCD_CH8_ES_SGE_WIDTH (1U) 4018 #define DMA_TCD_CH8_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_ES_SGE_SHIFT)) & DMA_TCD_CH8_ES_SGE_MASK) 4019 4020 #define DMA_TCD_CH8_ES_NCE_MASK (0x8U) 4021 #define DMA_TCD_CH8_ES_NCE_SHIFT (3U) 4022 #define DMA_TCD_CH8_ES_NCE_WIDTH (1U) 4023 #define DMA_TCD_CH8_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_ES_NCE_SHIFT)) & DMA_TCD_CH8_ES_NCE_MASK) 4024 4025 #define DMA_TCD_CH8_ES_DOE_MASK (0x10U) 4026 #define DMA_TCD_CH8_ES_DOE_SHIFT (4U) 4027 #define DMA_TCD_CH8_ES_DOE_WIDTH (1U) 4028 #define DMA_TCD_CH8_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_ES_DOE_SHIFT)) & DMA_TCD_CH8_ES_DOE_MASK) 4029 4030 #define DMA_TCD_CH8_ES_DAE_MASK (0x20U) 4031 #define DMA_TCD_CH8_ES_DAE_SHIFT (5U) 4032 #define DMA_TCD_CH8_ES_DAE_WIDTH (1U) 4033 #define DMA_TCD_CH8_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_ES_DAE_SHIFT)) & DMA_TCD_CH8_ES_DAE_MASK) 4034 4035 #define DMA_TCD_CH8_ES_SOE_MASK (0x40U) 4036 #define DMA_TCD_CH8_ES_SOE_SHIFT (6U) 4037 #define DMA_TCD_CH8_ES_SOE_WIDTH (1U) 4038 #define DMA_TCD_CH8_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_ES_SOE_SHIFT)) & DMA_TCD_CH8_ES_SOE_MASK) 4039 4040 #define DMA_TCD_CH8_ES_SAE_MASK (0x80U) 4041 #define DMA_TCD_CH8_ES_SAE_SHIFT (7U) 4042 #define DMA_TCD_CH8_ES_SAE_WIDTH (1U) 4043 #define DMA_TCD_CH8_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_ES_SAE_SHIFT)) & DMA_TCD_CH8_ES_SAE_MASK) 4044 4045 #define DMA_TCD_CH8_ES_ERR_MASK (0x80000000U) 4046 #define DMA_TCD_CH8_ES_ERR_SHIFT (31U) 4047 #define DMA_TCD_CH8_ES_ERR_WIDTH (1U) 4048 #define DMA_TCD_CH8_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_ES_ERR_SHIFT)) & DMA_TCD_CH8_ES_ERR_MASK) 4049 /*! @} */ 4050 4051 /*! @name CH8_INT - Channel Interrupt Status */ 4052 /*! @{ */ 4053 4054 #define DMA_TCD_CH8_INT_INT_MASK (0x1U) 4055 #define DMA_TCD_CH8_INT_INT_SHIFT (0U) 4056 #define DMA_TCD_CH8_INT_INT_WIDTH (1U) 4057 #define DMA_TCD_CH8_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_INT_INT_SHIFT)) & DMA_TCD_CH8_INT_INT_MASK) 4058 /*! @} */ 4059 4060 /*! @name CH8_SBR - Channel System Bus */ 4061 /*! @{ */ 4062 4063 #define DMA_TCD_CH8_SBR_MID_MASK (0xFU) 4064 #define DMA_TCD_CH8_SBR_MID_SHIFT (0U) 4065 #define DMA_TCD_CH8_SBR_MID_WIDTH (4U) 4066 #define DMA_TCD_CH8_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_SBR_MID_SHIFT)) & DMA_TCD_CH8_SBR_MID_MASK) 4067 4068 #define DMA_TCD_CH8_SBR_PAL_MASK (0x8000U) 4069 #define DMA_TCD_CH8_SBR_PAL_SHIFT (15U) 4070 #define DMA_TCD_CH8_SBR_PAL_WIDTH (1U) 4071 #define DMA_TCD_CH8_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_SBR_PAL_SHIFT)) & DMA_TCD_CH8_SBR_PAL_MASK) 4072 4073 #define DMA_TCD_CH8_SBR_EMI_MASK (0x10000U) 4074 #define DMA_TCD_CH8_SBR_EMI_SHIFT (16U) 4075 #define DMA_TCD_CH8_SBR_EMI_WIDTH (1U) 4076 #define DMA_TCD_CH8_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_SBR_EMI_SHIFT)) & DMA_TCD_CH8_SBR_EMI_MASK) 4077 4078 #define DMA_TCD_CH8_SBR_ATTR_MASK (0xE0000U) 4079 #define DMA_TCD_CH8_SBR_ATTR_SHIFT (17U) 4080 #define DMA_TCD_CH8_SBR_ATTR_WIDTH (3U) 4081 #define DMA_TCD_CH8_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_SBR_ATTR_SHIFT)) & DMA_TCD_CH8_SBR_ATTR_MASK) 4082 /*! @} */ 4083 4084 /*! @name CH8_PRI - Channel Priority */ 4085 /*! @{ */ 4086 4087 #define DMA_TCD_CH8_PRI_APL_MASK (0x7U) 4088 #define DMA_TCD_CH8_PRI_APL_SHIFT (0U) 4089 #define DMA_TCD_CH8_PRI_APL_WIDTH (3U) 4090 #define DMA_TCD_CH8_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_PRI_APL_SHIFT)) & DMA_TCD_CH8_PRI_APL_MASK) 4091 4092 #define DMA_TCD_CH8_PRI_DPA_MASK (0x40000000U) 4093 #define DMA_TCD_CH8_PRI_DPA_SHIFT (30U) 4094 #define DMA_TCD_CH8_PRI_DPA_WIDTH (1U) 4095 #define DMA_TCD_CH8_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_PRI_DPA_SHIFT)) & DMA_TCD_CH8_PRI_DPA_MASK) 4096 4097 #define DMA_TCD_CH8_PRI_ECP_MASK (0x80000000U) 4098 #define DMA_TCD_CH8_PRI_ECP_SHIFT (31U) 4099 #define DMA_TCD_CH8_PRI_ECP_WIDTH (1U) 4100 #define DMA_TCD_CH8_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH8_PRI_ECP_SHIFT)) & DMA_TCD_CH8_PRI_ECP_MASK) 4101 /*! @} */ 4102 4103 /*! @name TCD8_SADDR - TCD Source Address */ 4104 /*! @{ */ 4105 4106 #define DMA_TCD_TCD8_SADDR_SADDR_MASK (0xFFFFFFFFU) 4107 #define DMA_TCD_TCD8_SADDR_SADDR_SHIFT (0U) 4108 #define DMA_TCD_TCD8_SADDR_SADDR_WIDTH (32U) 4109 #define DMA_TCD_TCD8_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD8_SADDR_SADDR_MASK) 4110 /*! @} */ 4111 4112 /*! @name TCD8_SOFF - TCD Signed Source Address Offset */ 4113 /*! @{ */ 4114 4115 #define DMA_TCD_TCD8_SOFF_SOFF_MASK (0xFFFFU) 4116 #define DMA_TCD_TCD8_SOFF_SOFF_SHIFT (0U) 4117 #define DMA_TCD_TCD8_SOFF_SOFF_WIDTH (16U) 4118 #define DMA_TCD_TCD8_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD8_SOFF_SOFF_MASK) 4119 /*! @} */ 4120 4121 /*! @name TCD8_ATTR - TCD Transfer Attributes */ 4122 /*! @{ */ 4123 4124 #define DMA_TCD_TCD8_ATTR_DSIZE_MASK (0x7U) 4125 #define DMA_TCD_TCD8_ATTR_DSIZE_SHIFT (0U) 4126 #define DMA_TCD_TCD8_ATTR_DSIZE_WIDTH (3U) 4127 #define DMA_TCD_TCD8_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD8_ATTR_DSIZE_MASK) 4128 4129 #define DMA_TCD_TCD8_ATTR_DMOD_MASK (0xF8U) 4130 #define DMA_TCD_TCD8_ATTR_DMOD_SHIFT (3U) 4131 #define DMA_TCD_TCD8_ATTR_DMOD_WIDTH (5U) 4132 #define DMA_TCD_TCD8_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD8_ATTR_DMOD_MASK) 4133 4134 #define DMA_TCD_TCD8_ATTR_SSIZE_MASK (0x700U) 4135 #define DMA_TCD_TCD8_ATTR_SSIZE_SHIFT (8U) 4136 #define DMA_TCD_TCD8_ATTR_SSIZE_WIDTH (3U) 4137 #define DMA_TCD_TCD8_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD8_ATTR_SSIZE_MASK) 4138 4139 #define DMA_TCD_TCD8_ATTR_SMOD_MASK (0xF800U) 4140 #define DMA_TCD_TCD8_ATTR_SMOD_SHIFT (11U) 4141 #define DMA_TCD_TCD8_ATTR_SMOD_WIDTH (5U) 4142 #define DMA_TCD_TCD8_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD8_ATTR_SMOD_MASK) 4143 /*! @} */ 4144 4145 /*! @name TCD8_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 4146 /*! @{ */ 4147 4148 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 4149 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 4150 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 4151 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD8_NBYTES_MLOFFNO_NBYTES_MASK) 4152 4153 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 4154 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 4155 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 4156 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD8_NBYTES_MLOFFNO_DMLOE_MASK) 4157 4158 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 4159 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 4160 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 4161 #define DMA_TCD_TCD8_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD8_NBYTES_MLOFFNO_SMLOE_MASK) 4162 /*! @} */ 4163 4164 /*! @name TCD8_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 4165 /*! @{ */ 4166 4167 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 4168 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 4169 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 4170 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD8_NBYTES_MLOFFYES_NBYTES_MASK) 4171 4172 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 4173 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 4174 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 4175 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD8_NBYTES_MLOFFYES_MLOFF_MASK) 4176 4177 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 4178 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 4179 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 4180 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD8_NBYTES_MLOFFYES_DMLOE_MASK) 4181 4182 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 4183 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 4184 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 4185 #define DMA_TCD_TCD8_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD8_NBYTES_MLOFFYES_SMLOE_MASK) 4186 /*! @} */ 4187 4188 /*! @name TCD8_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 4189 /*! @{ */ 4190 4191 #define DMA_TCD_TCD8_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 4192 #define DMA_TCD_TCD8_SLAST_SDA_SLAST_SDA_SHIFT (0U) 4193 #define DMA_TCD_TCD8_SLAST_SDA_SLAST_SDA_WIDTH (32U) 4194 #define DMA_TCD_TCD8_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD8_SLAST_SDA_SLAST_SDA_MASK) 4195 /*! @} */ 4196 4197 /*! @name TCD8_DADDR - TCD Destination Address */ 4198 /*! @{ */ 4199 4200 #define DMA_TCD_TCD8_DADDR_DADDR_MASK (0xFFFFFFFFU) 4201 #define DMA_TCD_TCD8_DADDR_DADDR_SHIFT (0U) 4202 #define DMA_TCD_TCD8_DADDR_DADDR_WIDTH (32U) 4203 #define DMA_TCD_TCD8_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD8_DADDR_DADDR_MASK) 4204 /*! @} */ 4205 4206 /*! @name TCD8_DOFF - TCD Signed Destination Address Offset */ 4207 /*! @{ */ 4208 4209 #define DMA_TCD_TCD8_DOFF_DOFF_MASK (0xFFFFU) 4210 #define DMA_TCD_TCD8_DOFF_DOFF_SHIFT (0U) 4211 #define DMA_TCD_TCD8_DOFF_DOFF_WIDTH (16U) 4212 #define DMA_TCD_TCD8_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD8_DOFF_DOFF_MASK) 4213 /*! @} */ 4214 4215 /*! @name TCD8_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 4216 /*! @{ */ 4217 4218 #define DMA_TCD_TCD8_CITER_ELINKNO_CITER_MASK (0x7FFFU) 4219 #define DMA_TCD_TCD8_CITER_ELINKNO_CITER_SHIFT (0U) 4220 #define DMA_TCD_TCD8_CITER_ELINKNO_CITER_WIDTH (15U) 4221 #define DMA_TCD_TCD8_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD8_CITER_ELINKNO_CITER_MASK) 4222 4223 #define DMA_TCD_TCD8_CITER_ELINKNO_ELINK_MASK (0x8000U) 4224 #define DMA_TCD_TCD8_CITER_ELINKNO_ELINK_SHIFT (15U) 4225 #define DMA_TCD_TCD8_CITER_ELINKNO_ELINK_WIDTH (1U) 4226 #define DMA_TCD_TCD8_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD8_CITER_ELINKNO_ELINK_MASK) 4227 /*! @} */ 4228 4229 /*! @name TCD8_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 4230 /*! @{ */ 4231 4232 #define DMA_TCD_TCD8_CITER_ELINKYES_CITER_MASK (0x1FFU) 4233 #define DMA_TCD_TCD8_CITER_ELINKYES_CITER_SHIFT (0U) 4234 #define DMA_TCD_TCD8_CITER_ELINKYES_CITER_WIDTH (9U) 4235 #define DMA_TCD_TCD8_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD8_CITER_ELINKYES_CITER_MASK) 4236 4237 #define DMA_TCD_TCD8_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 4238 #define DMA_TCD_TCD8_CITER_ELINKYES_LINKCH_SHIFT (9U) 4239 #define DMA_TCD_TCD8_CITER_ELINKYES_LINKCH_WIDTH (5U) 4240 #define DMA_TCD_TCD8_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD8_CITER_ELINKYES_LINKCH_MASK) 4241 4242 #define DMA_TCD_TCD8_CITER_ELINKYES_ELINK_MASK (0x8000U) 4243 #define DMA_TCD_TCD8_CITER_ELINKYES_ELINK_SHIFT (15U) 4244 #define DMA_TCD_TCD8_CITER_ELINKYES_ELINK_WIDTH (1U) 4245 #define DMA_TCD_TCD8_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD8_CITER_ELINKYES_ELINK_MASK) 4246 /*! @} */ 4247 4248 /*! @name TCD8_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 4249 /*! @{ */ 4250 4251 #define DMA_TCD_TCD8_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 4252 #define DMA_TCD_TCD8_DLAST_SGA_DLAST_SGA_SHIFT (0U) 4253 #define DMA_TCD_TCD8_DLAST_SGA_DLAST_SGA_WIDTH (32U) 4254 #define DMA_TCD_TCD8_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD8_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD8_DLAST_SGA_DLAST_SGA_MASK) 4255 /*! @} */ 4256 4257 /*! @name TCD8_CSR - TCD Control and Status */ 4258 /*! @{ */ 4259 4260 #define DMA_TCD_TCD8_CSR_START_MASK (0x1U) 4261 #define DMA_TCD_TCD8_CSR_START_SHIFT (0U) 4262 #define DMA_TCD_TCD8_CSR_START_WIDTH (1U) 4263 #define DMA_TCD_TCD8_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CSR_START_SHIFT)) & DMA_TCD_TCD8_CSR_START_MASK) 4264 4265 #define DMA_TCD_TCD8_CSR_INTMAJOR_MASK (0x2U) 4266 #define DMA_TCD_TCD8_CSR_INTMAJOR_SHIFT (1U) 4267 #define DMA_TCD_TCD8_CSR_INTMAJOR_WIDTH (1U) 4268 #define DMA_TCD_TCD8_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD8_CSR_INTMAJOR_MASK) 4269 4270 #define DMA_TCD_TCD8_CSR_INTHALF_MASK (0x4U) 4271 #define DMA_TCD_TCD8_CSR_INTHALF_SHIFT (2U) 4272 #define DMA_TCD_TCD8_CSR_INTHALF_WIDTH (1U) 4273 #define DMA_TCD_TCD8_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD8_CSR_INTHALF_MASK) 4274 4275 #define DMA_TCD_TCD8_CSR_DREQ_MASK (0x8U) 4276 #define DMA_TCD_TCD8_CSR_DREQ_SHIFT (3U) 4277 #define DMA_TCD_TCD8_CSR_DREQ_WIDTH (1U) 4278 #define DMA_TCD_TCD8_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CSR_DREQ_SHIFT)) & DMA_TCD_TCD8_CSR_DREQ_MASK) 4279 4280 #define DMA_TCD_TCD8_CSR_ESG_MASK (0x10U) 4281 #define DMA_TCD_TCD8_CSR_ESG_SHIFT (4U) 4282 #define DMA_TCD_TCD8_CSR_ESG_WIDTH (1U) 4283 #define DMA_TCD_TCD8_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CSR_ESG_SHIFT)) & DMA_TCD_TCD8_CSR_ESG_MASK) 4284 4285 #define DMA_TCD_TCD8_CSR_MAJORELINK_MASK (0x20U) 4286 #define DMA_TCD_TCD8_CSR_MAJORELINK_SHIFT (5U) 4287 #define DMA_TCD_TCD8_CSR_MAJORELINK_WIDTH (1U) 4288 #define DMA_TCD_TCD8_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD8_CSR_MAJORELINK_MASK) 4289 4290 #define DMA_TCD_TCD8_CSR_EEOP_MASK (0x40U) 4291 #define DMA_TCD_TCD8_CSR_EEOP_SHIFT (6U) 4292 #define DMA_TCD_TCD8_CSR_EEOP_WIDTH (1U) 4293 #define DMA_TCD_TCD8_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CSR_EEOP_SHIFT)) & DMA_TCD_TCD8_CSR_EEOP_MASK) 4294 4295 #define DMA_TCD_TCD8_CSR_ESDA_MASK (0x80U) 4296 #define DMA_TCD_TCD8_CSR_ESDA_SHIFT (7U) 4297 #define DMA_TCD_TCD8_CSR_ESDA_WIDTH (1U) 4298 #define DMA_TCD_TCD8_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CSR_ESDA_SHIFT)) & DMA_TCD_TCD8_CSR_ESDA_MASK) 4299 4300 #define DMA_TCD_TCD8_CSR_MAJORLINKCH_MASK (0x1F00U) 4301 #define DMA_TCD_TCD8_CSR_MAJORLINKCH_SHIFT (8U) 4302 #define DMA_TCD_TCD8_CSR_MAJORLINKCH_WIDTH (5U) 4303 #define DMA_TCD_TCD8_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD8_CSR_MAJORLINKCH_MASK) 4304 4305 #define DMA_TCD_TCD8_CSR_BWC_MASK (0xC000U) 4306 #define DMA_TCD_TCD8_CSR_BWC_SHIFT (14U) 4307 #define DMA_TCD_TCD8_CSR_BWC_WIDTH (2U) 4308 #define DMA_TCD_TCD8_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_CSR_BWC_SHIFT)) & DMA_TCD_TCD8_CSR_BWC_MASK) 4309 /*! @} */ 4310 4311 /*! @name TCD8_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 4312 /*! @{ */ 4313 4314 #define DMA_TCD_TCD8_BITER_ELINKNO_BITER_MASK (0x7FFFU) 4315 #define DMA_TCD_TCD8_BITER_ELINKNO_BITER_SHIFT (0U) 4316 #define DMA_TCD_TCD8_BITER_ELINKNO_BITER_WIDTH (15U) 4317 #define DMA_TCD_TCD8_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD8_BITER_ELINKNO_BITER_MASK) 4318 4319 #define DMA_TCD_TCD8_BITER_ELINKNO_ELINK_MASK (0x8000U) 4320 #define DMA_TCD_TCD8_BITER_ELINKNO_ELINK_SHIFT (15U) 4321 #define DMA_TCD_TCD8_BITER_ELINKNO_ELINK_WIDTH (1U) 4322 #define DMA_TCD_TCD8_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD8_BITER_ELINKNO_ELINK_MASK) 4323 /*! @} */ 4324 4325 /*! @name TCD8_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 4326 /*! @{ */ 4327 4328 #define DMA_TCD_TCD8_BITER_ELINKYES_BITER_MASK (0x1FFU) 4329 #define DMA_TCD_TCD8_BITER_ELINKYES_BITER_SHIFT (0U) 4330 #define DMA_TCD_TCD8_BITER_ELINKYES_BITER_WIDTH (9U) 4331 #define DMA_TCD_TCD8_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD8_BITER_ELINKYES_BITER_MASK) 4332 4333 #define DMA_TCD_TCD8_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 4334 #define DMA_TCD_TCD8_BITER_ELINKYES_LINKCH_SHIFT (9U) 4335 #define DMA_TCD_TCD8_BITER_ELINKYES_LINKCH_WIDTH (5U) 4336 #define DMA_TCD_TCD8_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD8_BITER_ELINKYES_LINKCH_MASK) 4337 4338 #define DMA_TCD_TCD8_BITER_ELINKYES_ELINK_MASK (0x8000U) 4339 #define DMA_TCD_TCD8_BITER_ELINKYES_ELINK_SHIFT (15U) 4340 #define DMA_TCD_TCD8_BITER_ELINKYES_ELINK_WIDTH (1U) 4341 #define DMA_TCD_TCD8_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD8_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD8_BITER_ELINKYES_ELINK_MASK) 4342 /*! @} */ 4343 4344 /*! @name CH9_CSR - Channel Control and Status */ 4345 /*! @{ */ 4346 4347 #define DMA_TCD_CH9_CSR_ERQ_MASK (0x1U) 4348 #define DMA_TCD_CH9_CSR_ERQ_SHIFT (0U) 4349 #define DMA_TCD_CH9_CSR_ERQ_WIDTH (1U) 4350 #define DMA_TCD_CH9_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_CSR_ERQ_SHIFT)) & DMA_TCD_CH9_CSR_ERQ_MASK) 4351 4352 #define DMA_TCD_CH9_CSR_EARQ_MASK (0x2U) 4353 #define DMA_TCD_CH9_CSR_EARQ_SHIFT (1U) 4354 #define DMA_TCD_CH9_CSR_EARQ_WIDTH (1U) 4355 #define DMA_TCD_CH9_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_CSR_EARQ_SHIFT)) & DMA_TCD_CH9_CSR_EARQ_MASK) 4356 4357 #define DMA_TCD_CH9_CSR_EEI_MASK (0x4U) 4358 #define DMA_TCD_CH9_CSR_EEI_SHIFT (2U) 4359 #define DMA_TCD_CH9_CSR_EEI_WIDTH (1U) 4360 #define DMA_TCD_CH9_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_CSR_EEI_SHIFT)) & DMA_TCD_CH9_CSR_EEI_MASK) 4361 4362 #define DMA_TCD_CH9_CSR_EBW_MASK (0x8U) 4363 #define DMA_TCD_CH9_CSR_EBW_SHIFT (3U) 4364 #define DMA_TCD_CH9_CSR_EBW_WIDTH (1U) 4365 #define DMA_TCD_CH9_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_CSR_EBW_SHIFT)) & DMA_TCD_CH9_CSR_EBW_MASK) 4366 4367 #define DMA_TCD_CH9_CSR_DONE_MASK (0x40000000U) 4368 #define DMA_TCD_CH9_CSR_DONE_SHIFT (30U) 4369 #define DMA_TCD_CH9_CSR_DONE_WIDTH (1U) 4370 #define DMA_TCD_CH9_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_CSR_DONE_SHIFT)) & DMA_TCD_CH9_CSR_DONE_MASK) 4371 4372 #define DMA_TCD_CH9_CSR_ACTIVE_MASK (0x80000000U) 4373 #define DMA_TCD_CH9_CSR_ACTIVE_SHIFT (31U) 4374 #define DMA_TCD_CH9_CSR_ACTIVE_WIDTH (1U) 4375 #define DMA_TCD_CH9_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH9_CSR_ACTIVE_MASK) 4376 /*! @} */ 4377 4378 /*! @name CH9_ES - Channel Error Status */ 4379 /*! @{ */ 4380 4381 #define DMA_TCD_CH9_ES_DBE_MASK (0x1U) 4382 #define DMA_TCD_CH9_ES_DBE_SHIFT (0U) 4383 #define DMA_TCD_CH9_ES_DBE_WIDTH (1U) 4384 #define DMA_TCD_CH9_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_ES_DBE_SHIFT)) & DMA_TCD_CH9_ES_DBE_MASK) 4385 4386 #define DMA_TCD_CH9_ES_SBE_MASK (0x2U) 4387 #define DMA_TCD_CH9_ES_SBE_SHIFT (1U) 4388 #define DMA_TCD_CH9_ES_SBE_WIDTH (1U) 4389 #define DMA_TCD_CH9_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_ES_SBE_SHIFT)) & DMA_TCD_CH9_ES_SBE_MASK) 4390 4391 #define DMA_TCD_CH9_ES_SGE_MASK (0x4U) 4392 #define DMA_TCD_CH9_ES_SGE_SHIFT (2U) 4393 #define DMA_TCD_CH9_ES_SGE_WIDTH (1U) 4394 #define DMA_TCD_CH9_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_ES_SGE_SHIFT)) & DMA_TCD_CH9_ES_SGE_MASK) 4395 4396 #define DMA_TCD_CH9_ES_NCE_MASK (0x8U) 4397 #define DMA_TCD_CH9_ES_NCE_SHIFT (3U) 4398 #define DMA_TCD_CH9_ES_NCE_WIDTH (1U) 4399 #define DMA_TCD_CH9_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_ES_NCE_SHIFT)) & DMA_TCD_CH9_ES_NCE_MASK) 4400 4401 #define DMA_TCD_CH9_ES_DOE_MASK (0x10U) 4402 #define DMA_TCD_CH9_ES_DOE_SHIFT (4U) 4403 #define DMA_TCD_CH9_ES_DOE_WIDTH (1U) 4404 #define DMA_TCD_CH9_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_ES_DOE_SHIFT)) & DMA_TCD_CH9_ES_DOE_MASK) 4405 4406 #define DMA_TCD_CH9_ES_DAE_MASK (0x20U) 4407 #define DMA_TCD_CH9_ES_DAE_SHIFT (5U) 4408 #define DMA_TCD_CH9_ES_DAE_WIDTH (1U) 4409 #define DMA_TCD_CH9_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_ES_DAE_SHIFT)) & DMA_TCD_CH9_ES_DAE_MASK) 4410 4411 #define DMA_TCD_CH9_ES_SOE_MASK (0x40U) 4412 #define DMA_TCD_CH9_ES_SOE_SHIFT (6U) 4413 #define DMA_TCD_CH9_ES_SOE_WIDTH (1U) 4414 #define DMA_TCD_CH9_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_ES_SOE_SHIFT)) & DMA_TCD_CH9_ES_SOE_MASK) 4415 4416 #define DMA_TCD_CH9_ES_SAE_MASK (0x80U) 4417 #define DMA_TCD_CH9_ES_SAE_SHIFT (7U) 4418 #define DMA_TCD_CH9_ES_SAE_WIDTH (1U) 4419 #define DMA_TCD_CH9_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_ES_SAE_SHIFT)) & DMA_TCD_CH9_ES_SAE_MASK) 4420 4421 #define DMA_TCD_CH9_ES_ERR_MASK (0x80000000U) 4422 #define DMA_TCD_CH9_ES_ERR_SHIFT (31U) 4423 #define DMA_TCD_CH9_ES_ERR_WIDTH (1U) 4424 #define DMA_TCD_CH9_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_ES_ERR_SHIFT)) & DMA_TCD_CH9_ES_ERR_MASK) 4425 /*! @} */ 4426 4427 /*! @name CH9_INT - Channel Interrupt Status */ 4428 /*! @{ */ 4429 4430 #define DMA_TCD_CH9_INT_INT_MASK (0x1U) 4431 #define DMA_TCD_CH9_INT_INT_SHIFT (0U) 4432 #define DMA_TCD_CH9_INT_INT_WIDTH (1U) 4433 #define DMA_TCD_CH9_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_INT_INT_SHIFT)) & DMA_TCD_CH9_INT_INT_MASK) 4434 /*! @} */ 4435 4436 /*! @name CH9_SBR - Channel System Bus */ 4437 /*! @{ */ 4438 4439 #define DMA_TCD_CH9_SBR_MID_MASK (0xFU) 4440 #define DMA_TCD_CH9_SBR_MID_SHIFT (0U) 4441 #define DMA_TCD_CH9_SBR_MID_WIDTH (4U) 4442 #define DMA_TCD_CH9_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_SBR_MID_SHIFT)) & DMA_TCD_CH9_SBR_MID_MASK) 4443 4444 #define DMA_TCD_CH9_SBR_PAL_MASK (0x8000U) 4445 #define DMA_TCD_CH9_SBR_PAL_SHIFT (15U) 4446 #define DMA_TCD_CH9_SBR_PAL_WIDTH (1U) 4447 #define DMA_TCD_CH9_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_SBR_PAL_SHIFT)) & DMA_TCD_CH9_SBR_PAL_MASK) 4448 4449 #define DMA_TCD_CH9_SBR_EMI_MASK (0x10000U) 4450 #define DMA_TCD_CH9_SBR_EMI_SHIFT (16U) 4451 #define DMA_TCD_CH9_SBR_EMI_WIDTH (1U) 4452 #define DMA_TCD_CH9_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_SBR_EMI_SHIFT)) & DMA_TCD_CH9_SBR_EMI_MASK) 4453 4454 #define DMA_TCD_CH9_SBR_ATTR_MASK (0xE0000U) 4455 #define DMA_TCD_CH9_SBR_ATTR_SHIFT (17U) 4456 #define DMA_TCD_CH9_SBR_ATTR_WIDTH (3U) 4457 #define DMA_TCD_CH9_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_SBR_ATTR_SHIFT)) & DMA_TCD_CH9_SBR_ATTR_MASK) 4458 /*! @} */ 4459 4460 /*! @name CH9_PRI - Channel Priority */ 4461 /*! @{ */ 4462 4463 #define DMA_TCD_CH9_PRI_APL_MASK (0x7U) 4464 #define DMA_TCD_CH9_PRI_APL_SHIFT (0U) 4465 #define DMA_TCD_CH9_PRI_APL_WIDTH (3U) 4466 #define DMA_TCD_CH9_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_PRI_APL_SHIFT)) & DMA_TCD_CH9_PRI_APL_MASK) 4467 4468 #define DMA_TCD_CH9_PRI_DPA_MASK (0x40000000U) 4469 #define DMA_TCD_CH9_PRI_DPA_SHIFT (30U) 4470 #define DMA_TCD_CH9_PRI_DPA_WIDTH (1U) 4471 #define DMA_TCD_CH9_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_PRI_DPA_SHIFT)) & DMA_TCD_CH9_PRI_DPA_MASK) 4472 4473 #define DMA_TCD_CH9_PRI_ECP_MASK (0x80000000U) 4474 #define DMA_TCD_CH9_PRI_ECP_SHIFT (31U) 4475 #define DMA_TCD_CH9_PRI_ECP_WIDTH (1U) 4476 #define DMA_TCD_CH9_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH9_PRI_ECP_SHIFT)) & DMA_TCD_CH9_PRI_ECP_MASK) 4477 /*! @} */ 4478 4479 /*! @name TCD9_SADDR - TCD Source Address */ 4480 /*! @{ */ 4481 4482 #define DMA_TCD_TCD9_SADDR_SADDR_MASK (0xFFFFFFFFU) 4483 #define DMA_TCD_TCD9_SADDR_SADDR_SHIFT (0U) 4484 #define DMA_TCD_TCD9_SADDR_SADDR_WIDTH (32U) 4485 #define DMA_TCD_TCD9_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD9_SADDR_SADDR_MASK) 4486 /*! @} */ 4487 4488 /*! @name TCD9_SOFF - TCD Signed Source Address Offset */ 4489 /*! @{ */ 4490 4491 #define DMA_TCD_TCD9_SOFF_SOFF_MASK (0xFFFFU) 4492 #define DMA_TCD_TCD9_SOFF_SOFF_SHIFT (0U) 4493 #define DMA_TCD_TCD9_SOFF_SOFF_WIDTH (16U) 4494 #define DMA_TCD_TCD9_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD9_SOFF_SOFF_MASK) 4495 /*! @} */ 4496 4497 /*! @name TCD9_ATTR - TCD Transfer Attributes */ 4498 /*! @{ */ 4499 4500 #define DMA_TCD_TCD9_ATTR_DSIZE_MASK (0x7U) 4501 #define DMA_TCD_TCD9_ATTR_DSIZE_SHIFT (0U) 4502 #define DMA_TCD_TCD9_ATTR_DSIZE_WIDTH (3U) 4503 #define DMA_TCD_TCD9_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD9_ATTR_DSIZE_MASK) 4504 4505 #define DMA_TCD_TCD9_ATTR_DMOD_MASK (0xF8U) 4506 #define DMA_TCD_TCD9_ATTR_DMOD_SHIFT (3U) 4507 #define DMA_TCD_TCD9_ATTR_DMOD_WIDTH (5U) 4508 #define DMA_TCD_TCD9_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD9_ATTR_DMOD_MASK) 4509 4510 #define DMA_TCD_TCD9_ATTR_SSIZE_MASK (0x700U) 4511 #define DMA_TCD_TCD9_ATTR_SSIZE_SHIFT (8U) 4512 #define DMA_TCD_TCD9_ATTR_SSIZE_WIDTH (3U) 4513 #define DMA_TCD_TCD9_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD9_ATTR_SSIZE_MASK) 4514 4515 #define DMA_TCD_TCD9_ATTR_SMOD_MASK (0xF800U) 4516 #define DMA_TCD_TCD9_ATTR_SMOD_SHIFT (11U) 4517 #define DMA_TCD_TCD9_ATTR_SMOD_WIDTH (5U) 4518 #define DMA_TCD_TCD9_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD9_ATTR_SMOD_MASK) 4519 /*! @} */ 4520 4521 /*! @name TCD9_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 4522 /*! @{ */ 4523 4524 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 4525 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 4526 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 4527 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD9_NBYTES_MLOFFNO_NBYTES_MASK) 4528 4529 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 4530 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 4531 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 4532 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD9_NBYTES_MLOFFNO_DMLOE_MASK) 4533 4534 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 4535 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 4536 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 4537 #define DMA_TCD_TCD9_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD9_NBYTES_MLOFFNO_SMLOE_MASK) 4538 /*! @} */ 4539 4540 /*! @name TCD9_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 4541 /*! @{ */ 4542 4543 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 4544 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 4545 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 4546 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD9_NBYTES_MLOFFYES_NBYTES_MASK) 4547 4548 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 4549 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 4550 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 4551 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD9_NBYTES_MLOFFYES_MLOFF_MASK) 4552 4553 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 4554 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 4555 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 4556 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD9_NBYTES_MLOFFYES_DMLOE_MASK) 4557 4558 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 4559 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 4560 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 4561 #define DMA_TCD_TCD9_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD9_NBYTES_MLOFFYES_SMLOE_MASK) 4562 /*! @} */ 4563 4564 /*! @name TCD9_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 4565 /*! @{ */ 4566 4567 #define DMA_TCD_TCD9_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 4568 #define DMA_TCD_TCD9_SLAST_SDA_SLAST_SDA_SHIFT (0U) 4569 #define DMA_TCD_TCD9_SLAST_SDA_SLAST_SDA_WIDTH (32U) 4570 #define DMA_TCD_TCD9_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD9_SLAST_SDA_SLAST_SDA_MASK) 4571 /*! @} */ 4572 4573 /*! @name TCD9_DADDR - TCD Destination Address */ 4574 /*! @{ */ 4575 4576 #define DMA_TCD_TCD9_DADDR_DADDR_MASK (0xFFFFFFFFU) 4577 #define DMA_TCD_TCD9_DADDR_DADDR_SHIFT (0U) 4578 #define DMA_TCD_TCD9_DADDR_DADDR_WIDTH (32U) 4579 #define DMA_TCD_TCD9_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD9_DADDR_DADDR_MASK) 4580 /*! @} */ 4581 4582 /*! @name TCD9_DOFF - TCD Signed Destination Address Offset */ 4583 /*! @{ */ 4584 4585 #define DMA_TCD_TCD9_DOFF_DOFF_MASK (0xFFFFU) 4586 #define DMA_TCD_TCD9_DOFF_DOFF_SHIFT (0U) 4587 #define DMA_TCD_TCD9_DOFF_DOFF_WIDTH (16U) 4588 #define DMA_TCD_TCD9_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD9_DOFF_DOFF_MASK) 4589 /*! @} */ 4590 4591 /*! @name TCD9_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 4592 /*! @{ */ 4593 4594 #define DMA_TCD_TCD9_CITER_ELINKNO_CITER_MASK (0x7FFFU) 4595 #define DMA_TCD_TCD9_CITER_ELINKNO_CITER_SHIFT (0U) 4596 #define DMA_TCD_TCD9_CITER_ELINKNO_CITER_WIDTH (15U) 4597 #define DMA_TCD_TCD9_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD9_CITER_ELINKNO_CITER_MASK) 4598 4599 #define DMA_TCD_TCD9_CITER_ELINKNO_ELINK_MASK (0x8000U) 4600 #define DMA_TCD_TCD9_CITER_ELINKNO_ELINK_SHIFT (15U) 4601 #define DMA_TCD_TCD9_CITER_ELINKNO_ELINK_WIDTH (1U) 4602 #define DMA_TCD_TCD9_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD9_CITER_ELINKNO_ELINK_MASK) 4603 /*! @} */ 4604 4605 /*! @name TCD9_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 4606 /*! @{ */ 4607 4608 #define DMA_TCD_TCD9_CITER_ELINKYES_CITER_MASK (0x1FFU) 4609 #define DMA_TCD_TCD9_CITER_ELINKYES_CITER_SHIFT (0U) 4610 #define DMA_TCD_TCD9_CITER_ELINKYES_CITER_WIDTH (9U) 4611 #define DMA_TCD_TCD9_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD9_CITER_ELINKYES_CITER_MASK) 4612 4613 #define DMA_TCD_TCD9_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 4614 #define DMA_TCD_TCD9_CITER_ELINKYES_LINKCH_SHIFT (9U) 4615 #define DMA_TCD_TCD9_CITER_ELINKYES_LINKCH_WIDTH (5U) 4616 #define DMA_TCD_TCD9_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD9_CITER_ELINKYES_LINKCH_MASK) 4617 4618 #define DMA_TCD_TCD9_CITER_ELINKYES_ELINK_MASK (0x8000U) 4619 #define DMA_TCD_TCD9_CITER_ELINKYES_ELINK_SHIFT (15U) 4620 #define DMA_TCD_TCD9_CITER_ELINKYES_ELINK_WIDTH (1U) 4621 #define DMA_TCD_TCD9_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD9_CITER_ELINKYES_ELINK_MASK) 4622 /*! @} */ 4623 4624 /*! @name TCD9_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 4625 /*! @{ */ 4626 4627 #define DMA_TCD_TCD9_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 4628 #define DMA_TCD_TCD9_DLAST_SGA_DLAST_SGA_SHIFT (0U) 4629 #define DMA_TCD_TCD9_DLAST_SGA_DLAST_SGA_WIDTH (32U) 4630 #define DMA_TCD_TCD9_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD9_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD9_DLAST_SGA_DLAST_SGA_MASK) 4631 /*! @} */ 4632 4633 /*! @name TCD9_CSR - TCD Control and Status */ 4634 /*! @{ */ 4635 4636 #define DMA_TCD_TCD9_CSR_START_MASK (0x1U) 4637 #define DMA_TCD_TCD9_CSR_START_SHIFT (0U) 4638 #define DMA_TCD_TCD9_CSR_START_WIDTH (1U) 4639 #define DMA_TCD_TCD9_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CSR_START_SHIFT)) & DMA_TCD_TCD9_CSR_START_MASK) 4640 4641 #define DMA_TCD_TCD9_CSR_INTMAJOR_MASK (0x2U) 4642 #define DMA_TCD_TCD9_CSR_INTMAJOR_SHIFT (1U) 4643 #define DMA_TCD_TCD9_CSR_INTMAJOR_WIDTH (1U) 4644 #define DMA_TCD_TCD9_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD9_CSR_INTMAJOR_MASK) 4645 4646 #define DMA_TCD_TCD9_CSR_INTHALF_MASK (0x4U) 4647 #define DMA_TCD_TCD9_CSR_INTHALF_SHIFT (2U) 4648 #define DMA_TCD_TCD9_CSR_INTHALF_WIDTH (1U) 4649 #define DMA_TCD_TCD9_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD9_CSR_INTHALF_MASK) 4650 4651 #define DMA_TCD_TCD9_CSR_DREQ_MASK (0x8U) 4652 #define DMA_TCD_TCD9_CSR_DREQ_SHIFT (3U) 4653 #define DMA_TCD_TCD9_CSR_DREQ_WIDTH (1U) 4654 #define DMA_TCD_TCD9_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CSR_DREQ_SHIFT)) & DMA_TCD_TCD9_CSR_DREQ_MASK) 4655 4656 #define DMA_TCD_TCD9_CSR_ESG_MASK (0x10U) 4657 #define DMA_TCD_TCD9_CSR_ESG_SHIFT (4U) 4658 #define DMA_TCD_TCD9_CSR_ESG_WIDTH (1U) 4659 #define DMA_TCD_TCD9_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CSR_ESG_SHIFT)) & DMA_TCD_TCD9_CSR_ESG_MASK) 4660 4661 #define DMA_TCD_TCD9_CSR_MAJORELINK_MASK (0x20U) 4662 #define DMA_TCD_TCD9_CSR_MAJORELINK_SHIFT (5U) 4663 #define DMA_TCD_TCD9_CSR_MAJORELINK_WIDTH (1U) 4664 #define DMA_TCD_TCD9_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD9_CSR_MAJORELINK_MASK) 4665 4666 #define DMA_TCD_TCD9_CSR_EEOP_MASK (0x40U) 4667 #define DMA_TCD_TCD9_CSR_EEOP_SHIFT (6U) 4668 #define DMA_TCD_TCD9_CSR_EEOP_WIDTH (1U) 4669 #define DMA_TCD_TCD9_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CSR_EEOP_SHIFT)) & DMA_TCD_TCD9_CSR_EEOP_MASK) 4670 4671 #define DMA_TCD_TCD9_CSR_ESDA_MASK (0x80U) 4672 #define DMA_TCD_TCD9_CSR_ESDA_SHIFT (7U) 4673 #define DMA_TCD_TCD9_CSR_ESDA_WIDTH (1U) 4674 #define DMA_TCD_TCD9_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CSR_ESDA_SHIFT)) & DMA_TCD_TCD9_CSR_ESDA_MASK) 4675 4676 #define DMA_TCD_TCD9_CSR_MAJORLINKCH_MASK (0x1F00U) 4677 #define DMA_TCD_TCD9_CSR_MAJORLINKCH_SHIFT (8U) 4678 #define DMA_TCD_TCD9_CSR_MAJORLINKCH_WIDTH (5U) 4679 #define DMA_TCD_TCD9_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD9_CSR_MAJORLINKCH_MASK) 4680 4681 #define DMA_TCD_TCD9_CSR_BWC_MASK (0xC000U) 4682 #define DMA_TCD_TCD9_CSR_BWC_SHIFT (14U) 4683 #define DMA_TCD_TCD9_CSR_BWC_WIDTH (2U) 4684 #define DMA_TCD_TCD9_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_CSR_BWC_SHIFT)) & DMA_TCD_TCD9_CSR_BWC_MASK) 4685 /*! @} */ 4686 4687 /*! @name TCD9_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 4688 /*! @{ */ 4689 4690 #define DMA_TCD_TCD9_BITER_ELINKNO_BITER_MASK (0x7FFFU) 4691 #define DMA_TCD_TCD9_BITER_ELINKNO_BITER_SHIFT (0U) 4692 #define DMA_TCD_TCD9_BITER_ELINKNO_BITER_WIDTH (15U) 4693 #define DMA_TCD_TCD9_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD9_BITER_ELINKNO_BITER_MASK) 4694 4695 #define DMA_TCD_TCD9_BITER_ELINKNO_ELINK_MASK (0x8000U) 4696 #define DMA_TCD_TCD9_BITER_ELINKNO_ELINK_SHIFT (15U) 4697 #define DMA_TCD_TCD9_BITER_ELINKNO_ELINK_WIDTH (1U) 4698 #define DMA_TCD_TCD9_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD9_BITER_ELINKNO_ELINK_MASK) 4699 /*! @} */ 4700 4701 /*! @name TCD9_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 4702 /*! @{ */ 4703 4704 #define DMA_TCD_TCD9_BITER_ELINKYES_BITER_MASK (0x1FFU) 4705 #define DMA_TCD_TCD9_BITER_ELINKYES_BITER_SHIFT (0U) 4706 #define DMA_TCD_TCD9_BITER_ELINKYES_BITER_WIDTH (9U) 4707 #define DMA_TCD_TCD9_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD9_BITER_ELINKYES_BITER_MASK) 4708 4709 #define DMA_TCD_TCD9_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 4710 #define DMA_TCD_TCD9_BITER_ELINKYES_LINKCH_SHIFT (9U) 4711 #define DMA_TCD_TCD9_BITER_ELINKYES_LINKCH_WIDTH (5U) 4712 #define DMA_TCD_TCD9_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD9_BITER_ELINKYES_LINKCH_MASK) 4713 4714 #define DMA_TCD_TCD9_BITER_ELINKYES_ELINK_MASK (0x8000U) 4715 #define DMA_TCD_TCD9_BITER_ELINKYES_ELINK_SHIFT (15U) 4716 #define DMA_TCD_TCD9_BITER_ELINKYES_ELINK_WIDTH (1U) 4717 #define DMA_TCD_TCD9_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD9_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD9_BITER_ELINKYES_ELINK_MASK) 4718 /*! @} */ 4719 4720 /*! @name CH10_CSR - Channel Control and Status */ 4721 /*! @{ */ 4722 4723 #define DMA_TCD_CH10_CSR_ERQ_MASK (0x1U) 4724 #define DMA_TCD_CH10_CSR_ERQ_SHIFT (0U) 4725 #define DMA_TCD_CH10_CSR_ERQ_WIDTH (1U) 4726 #define DMA_TCD_CH10_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_CSR_ERQ_SHIFT)) & DMA_TCD_CH10_CSR_ERQ_MASK) 4727 4728 #define DMA_TCD_CH10_CSR_EARQ_MASK (0x2U) 4729 #define DMA_TCD_CH10_CSR_EARQ_SHIFT (1U) 4730 #define DMA_TCD_CH10_CSR_EARQ_WIDTH (1U) 4731 #define DMA_TCD_CH10_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_CSR_EARQ_SHIFT)) & DMA_TCD_CH10_CSR_EARQ_MASK) 4732 4733 #define DMA_TCD_CH10_CSR_EEI_MASK (0x4U) 4734 #define DMA_TCD_CH10_CSR_EEI_SHIFT (2U) 4735 #define DMA_TCD_CH10_CSR_EEI_WIDTH (1U) 4736 #define DMA_TCD_CH10_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_CSR_EEI_SHIFT)) & DMA_TCD_CH10_CSR_EEI_MASK) 4737 4738 #define DMA_TCD_CH10_CSR_EBW_MASK (0x8U) 4739 #define DMA_TCD_CH10_CSR_EBW_SHIFT (3U) 4740 #define DMA_TCD_CH10_CSR_EBW_WIDTH (1U) 4741 #define DMA_TCD_CH10_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_CSR_EBW_SHIFT)) & DMA_TCD_CH10_CSR_EBW_MASK) 4742 4743 #define DMA_TCD_CH10_CSR_DONE_MASK (0x40000000U) 4744 #define DMA_TCD_CH10_CSR_DONE_SHIFT (30U) 4745 #define DMA_TCD_CH10_CSR_DONE_WIDTH (1U) 4746 #define DMA_TCD_CH10_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_CSR_DONE_SHIFT)) & DMA_TCD_CH10_CSR_DONE_MASK) 4747 4748 #define DMA_TCD_CH10_CSR_ACTIVE_MASK (0x80000000U) 4749 #define DMA_TCD_CH10_CSR_ACTIVE_SHIFT (31U) 4750 #define DMA_TCD_CH10_CSR_ACTIVE_WIDTH (1U) 4751 #define DMA_TCD_CH10_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH10_CSR_ACTIVE_MASK) 4752 /*! @} */ 4753 4754 /*! @name CH10_ES - Channel Error Status */ 4755 /*! @{ */ 4756 4757 #define DMA_TCD_CH10_ES_DBE_MASK (0x1U) 4758 #define DMA_TCD_CH10_ES_DBE_SHIFT (0U) 4759 #define DMA_TCD_CH10_ES_DBE_WIDTH (1U) 4760 #define DMA_TCD_CH10_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_ES_DBE_SHIFT)) & DMA_TCD_CH10_ES_DBE_MASK) 4761 4762 #define DMA_TCD_CH10_ES_SBE_MASK (0x2U) 4763 #define DMA_TCD_CH10_ES_SBE_SHIFT (1U) 4764 #define DMA_TCD_CH10_ES_SBE_WIDTH (1U) 4765 #define DMA_TCD_CH10_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_ES_SBE_SHIFT)) & DMA_TCD_CH10_ES_SBE_MASK) 4766 4767 #define DMA_TCD_CH10_ES_SGE_MASK (0x4U) 4768 #define DMA_TCD_CH10_ES_SGE_SHIFT (2U) 4769 #define DMA_TCD_CH10_ES_SGE_WIDTH (1U) 4770 #define DMA_TCD_CH10_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_ES_SGE_SHIFT)) & DMA_TCD_CH10_ES_SGE_MASK) 4771 4772 #define DMA_TCD_CH10_ES_NCE_MASK (0x8U) 4773 #define DMA_TCD_CH10_ES_NCE_SHIFT (3U) 4774 #define DMA_TCD_CH10_ES_NCE_WIDTH (1U) 4775 #define DMA_TCD_CH10_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_ES_NCE_SHIFT)) & DMA_TCD_CH10_ES_NCE_MASK) 4776 4777 #define DMA_TCD_CH10_ES_DOE_MASK (0x10U) 4778 #define DMA_TCD_CH10_ES_DOE_SHIFT (4U) 4779 #define DMA_TCD_CH10_ES_DOE_WIDTH (1U) 4780 #define DMA_TCD_CH10_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_ES_DOE_SHIFT)) & DMA_TCD_CH10_ES_DOE_MASK) 4781 4782 #define DMA_TCD_CH10_ES_DAE_MASK (0x20U) 4783 #define DMA_TCD_CH10_ES_DAE_SHIFT (5U) 4784 #define DMA_TCD_CH10_ES_DAE_WIDTH (1U) 4785 #define DMA_TCD_CH10_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_ES_DAE_SHIFT)) & DMA_TCD_CH10_ES_DAE_MASK) 4786 4787 #define DMA_TCD_CH10_ES_SOE_MASK (0x40U) 4788 #define DMA_TCD_CH10_ES_SOE_SHIFT (6U) 4789 #define DMA_TCD_CH10_ES_SOE_WIDTH (1U) 4790 #define DMA_TCD_CH10_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_ES_SOE_SHIFT)) & DMA_TCD_CH10_ES_SOE_MASK) 4791 4792 #define DMA_TCD_CH10_ES_SAE_MASK (0x80U) 4793 #define DMA_TCD_CH10_ES_SAE_SHIFT (7U) 4794 #define DMA_TCD_CH10_ES_SAE_WIDTH (1U) 4795 #define DMA_TCD_CH10_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_ES_SAE_SHIFT)) & DMA_TCD_CH10_ES_SAE_MASK) 4796 4797 #define DMA_TCD_CH10_ES_ERR_MASK (0x80000000U) 4798 #define DMA_TCD_CH10_ES_ERR_SHIFT (31U) 4799 #define DMA_TCD_CH10_ES_ERR_WIDTH (1U) 4800 #define DMA_TCD_CH10_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_ES_ERR_SHIFT)) & DMA_TCD_CH10_ES_ERR_MASK) 4801 /*! @} */ 4802 4803 /*! @name CH10_INT - Channel Interrupt Status */ 4804 /*! @{ */ 4805 4806 #define DMA_TCD_CH10_INT_INT_MASK (0x1U) 4807 #define DMA_TCD_CH10_INT_INT_SHIFT (0U) 4808 #define DMA_TCD_CH10_INT_INT_WIDTH (1U) 4809 #define DMA_TCD_CH10_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_INT_INT_SHIFT)) & DMA_TCD_CH10_INT_INT_MASK) 4810 /*! @} */ 4811 4812 /*! @name CH10_SBR - Channel System Bus */ 4813 /*! @{ */ 4814 4815 #define DMA_TCD_CH10_SBR_MID_MASK (0xFU) 4816 #define DMA_TCD_CH10_SBR_MID_SHIFT (0U) 4817 #define DMA_TCD_CH10_SBR_MID_WIDTH (4U) 4818 #define DMA_TCD_CH10_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_SBR_MID_SHIFT)) & DMA_TCD_CH10_SBR_MID_MASK) 4819 4820 #define DMA_TCD_CH10_SBR_PAL_MASK (0x8000U) 4821 #define DMA_TCD_CH10_SBR_PAL_SHIFT (15U) 4822 #define DMA_TCD_CH10_SBR_PAL_WIDTH (1U) 4823 #define DMA_TCD_CH10_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_SBR_PAL_SHIFT)) & DMA_TCD_CH10_SBR_PAL_MASK) 4824 4825 #define DMA_TCD_CH10_SBR_EMI_MASK (0x10000U) 4826 #define DMA_TCD_CH10_SBR_EMI_SHIFT (16U) 4827 #define DMA_TCD_CH10_SBR_EMI_WIDTH (1U) 4828 #define DMA_TCD_CH10_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_SBR_EMI_SHIFT)) & DMA_TCD_CH10_SBR_EMI_MASK) 4829 4830 #define DMA_TCD_CH10_SBR_ATTR_MASK (0xE0000U) 4831 #define DMA_TCD_CH10_SBR_ATTR_SHIFT (17U) 4832 #define DMA_TCD_CH10_SBR_ATTR_WIDTH (3U) 4833 #define DMA_TCD_CH10_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_SBR_ATTR_SHIFT)) & DMA_TCD_CH10_SBR_ATTR_MASK) 4834 /*! @} */ 4835 4836 /*! @name CH10_PRI - Channel Priority */ 4837 /*! @{ */ 4838 4839 #define DMA_TCD_CH10_PRI_APL_MASK (0x7U) 4840 #define DMA_TCD_CH10_PRI_APL_SHIFT (0U) 4841 #define DMA_TCD_CH10_PRI_APL_WIDTH (3U) 4842 #define DMA_TCD_CH10_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_PRI_APL_SHIFT)) & DMA_TCD_CH10_PRI_APL_MASK) 4843 4844 #define DMA_TCD_CH10_PRI_DPA_MASK (0x40000000U) 4845 #define DMA_TCD_CH10_PRI_DPA_SHIFT (30U) 4846 #define DMA_TCD_CH10_PRI_DPA_WIDTH (1U) 4847 #define DMA_TCD_CH10_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_PRI_DPA_SHIFT)) & DMA_TCD_CH10_PRI_DPA_MASK) 4848 4849 #define DMA_TCD_CH10_PRI_ECP_MASK (0x80000000U) 4850 #define DMA_TCD_CH10_PRI_ECP_SHIFT (31U) 4851 #define DMA_TCD_CH10_PRI_ECP_WIDTH (1U) 4852 #define DMA_TCD_CH10_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH10_PRI_ECP_SHIFT)) & DMA_TCD_CH10_PRI_ECP_MASK) 4853 /*! @} */ 4854 4855 /*! @name TCD10_SADDR - TCD Source Address */ 4856 /*! @{ */ 4857 4858 #define DMA_TCD_TCD10_SADDR_SADDR_MASK (0xFFFFFFFFU) 4859 #define DMA_TCD_TCD10_SADDR_SADDR_SHIFT (0U) 4860 #define DMA_TCD_TCD10_SADDR_SADDR_WIDTH (32U) 4861 #define DMA_TCD_TCD10_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD10_SADDR_SADDR_MASK) 4862 /*! @} */ 4863 4864 /*! @name TCD10_SOFF - TCD Signed Source Address Offset */ 4865 /*! @{ */ 4866 4867 #define DMA_TCD_TCD10_SOFF_SOFF_MASK (0xFFFFU) 4868 #define DMA_TCD_TCD10_SOFF_SOFF_SHIFT (0U) 4869 #define DMA_TCD_TCD10_SOFF_SOFF_WIDTH (16U) 4870 #define DMA_TCD_TCD10_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD10_SOFF_SOFF_MASK) 4871 /*! @} */ 4872 4873 /*! @name TCD10_ATTR - TCD Transfer Attributes */ 4874 /*! @{ */ 4875 4876 #define DMA_TCD_TCD10_ATTR_DSIZE_MASK (0x7U) 4877 #define DMA_TCD_TCD10_ATTR_DSIZE_SHIFT (0U) 4878 #define DMA_TCD_TCD10_ATTR_DSIZE_WIDTH (3U) 4879 #define DMA_TCD_TCD10_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD10_ATTR_DSIZE_MASK) 4880 4881 #define DMA_TCD_TCD10_ATTR_DMOD_MASK (0xF8U) 4882 #define DMA_TCD_TCD10_ATTR_DMOD_SHIFT (3U) 4883 #define DMA_TCD_TCD10_ATTR_DMOD_WIDTH (5U) 4884 #define DMA_TCD_TCD10_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD10_ATTR_DMOD_MASK) 4885 4886 #define DMA_TCD_TCD10_ATTR_SSIZE_MASK (0x700U) 4887 #define DMA_TCD_TCD10_ATTR_SSIZE_SHIFT (8U) 4888 #define DMA_TCD_TCD10_ATTR_SSIZE_WIDTH (3U) 4889 #define DMA_TCD_TCD10_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD10_ATTR_SSIZE_MASK) 4890 4891 #define DMA_TCD_TCD10_ATTR_SMOD_MASK (0xF800U) 4892 #define DMA_TCD_TCD10_ATTR_SMOD_SHIFT (11U) 4893 #define DMA_TCD_TCD10_ATTR_SMOD_WIDTH (5U) 4894 #define DMA_TCD_TCD10_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD10_ATTR_SMOD_MASK) 4895 /*! @} */ 4896 4897 /*! @name TCD10_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 4898 /*! @{ */ 4899 4900 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 4901 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 4902 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 4903 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD10_NBYTES_MLOFFNO_NBYTES_MASK) 4904 4905 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 4906 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 4907 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 4908 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD10_NBYTES_MLOFFNO_DMLOE_MASK) 4909 4910 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 4911 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 4912 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 4913 #define DMA_TCD_TCD10_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD10_NBYTES_MLOFFNO_SMLOE_MASK) 4914 /*! @} */ 4915 4916 /*! @name TCD10_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 4917 /*! @{ */ 4918 4919 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 4920 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 4921 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 4922 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD10_NBYTES_MLOFFYES_NBYTES_MASK) 4923 4924 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 4925 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 4926 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 4927 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD10_NBYTES_MLOFFYES_MLOFF_MASK) 4928 4929 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 4930 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 4931 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 4932 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD10_NBYTES_MLOFFYES_DMLOE_MASK) 4933 4934 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 4935 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 4936 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 4937 #define DMA_TCD_TCD10_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD10_NBYTES_MLOFFYES_SMLOE_MASK) 4938 /*! @} */ 4939 4940 /*! @name TCD10_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 4941 /*! @{ */ 4942 4943 #define DMA_TCD_TCD10_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 4944 #define DMA_TCD_TCD10_SLAST_SDA_SLAST_SDA_SHIFT (0U) 4945 #define DMA_TCD_TCD10_SLAST_SDA_SLAST_SDA_WIDTH (32U) 4946 #define DMA_TCD_TCD10_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD10_SLAST_SDA_SLAST_SDA_MASK) 4947 /*! @} */ 4948 4949 /*! @name TCD10_DADDR - TCD Destination Address */ 4950 /*! @{ */ 4951 4952 #define DMA_TCD_TCD10_DADDR_DADDR_MASK (0xFFFFFFFFU) 4953 #define DMA_TCD_TCD10_DADDR_DADDR_SHIFT (0U) 4954 #define DMA_TCD_TCD10_DADDR_DADDR_WIDTH (32U) 4955 #define DMA_TCD_TCD10_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD10_DADDR_DADDR_MASK) 4956 /*! @} */ 4957 4958 /*! @name TCD10_DOFF - TCD Signed Destination Address Offset */ 4959 /*! @{ */ 4960 4961 #define DMA_TCD_TCD10_DOFF_DOFF_MASK (0xFFFFU) 4962 #define DMA_TCD_TCD10_DOFF_DOFF_SHIFT (0U) 4963 #define DMA_TCD_TCD10_DOFF_DOFF_WIDTH (16U) 4964 #define DMA_TCD_TCD10_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD10_DOFF_DOFF_MASK) 4965 /*! @} */ 4966 4967 /*! @name TCD10_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 4968 /*! @{ */ 4969 4970 #define DMA_TCD_TCD10_CITER_ELINKNO_CITER_MASK (0x7FFFU) 4971 #define DMA_TCD_TCD10_CITER_ELINKNO_CITER_SHIFT (0U) 4972 #define DMA_TCD_TCD10_CITER_ELINKNO_CITER_WIDTH (15U) 4973 #define DMA_TCD_TCD10_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD10_CITER_ELINKNO_CITER_MASK) 4974 4975 #define DMA_TCD_TCD10_CITER_ELINKNO_ELINK_MASK (0x8000U) 4976 #define DMA_TCD_TCD10_CITER_ELINKNO_ELINK_SHIFT (15U) 4977 #define DMA_TCD_TCD10_CITER_ELINKNO_ELINK_WIDTH (1U) 4978 #define DMA_TCD_TCD10_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD10_CITER_ELINKNO_ELINK_MASK) 4979 /*! @} */ 4980 4981 /*! @name TCD10_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 4982 /*! @{ */ 4983 4984 #define DMA_TCD_TCD10_CITER_ELINKYES_CITER_MASK (0x1FFU) 4985 #define DMA_TCD_TCD10_CITER_ELINKYES_CITER_SHIFT (0U) 4986 #define DMA_TCD_TCD10_CITER_ELINKYES_CITER_WIDTH (9U) 4987 #define DMA_TCD_TCD10_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD10_CITER_ELINKYES_CITER_MASK) 4988 4989 #define DMA_TCD_TCD10_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 4990 #define DMA_TCD_TCD10_CITER_ELINKYES_LINKCH_SHIFT (9U) 4991 #define DMA_TCD_TCD10_CITER_ELINKYES_LINKCH_WIDTH (5U) 4992 #define DMA_TCD_TCD10_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD10_CITER_ELINKYES_LINKCH_MASK) 4993 4994 #define DMA_TCD_TCD10_CITER_ELINKYES_ELINK_MASK (0x8000U) 4995 #define DMA_TCD_TCD10_CITER_ELINKYES_ELINK_SHIFT (15U) 4996 #define DMA_TCD_TCD10_CITER_ELINKYES_ELINK_WIDTH (1U) 4997 #define DMA_TCD_TCD10_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD10_CITER_ELINKYES_ELINK_MASK) 4998 /*! @} */ 4999 5000 /*! @name TCD10_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 5001 /*! @{ */ 5002 5003 #define DMA_TCD_TCD10_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 5004 #define DMA_TCD_TCD10_DLAST_SGA_DLAST_SGA_SHIFT (0U) 5005 #define DMA_TCD_TCD10_DLAST_SGA_DLAST_SGA_WIDTH (32U) 5006 #define DMA_TCD_TCD10_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD10_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD10_DLAST_SGA_DLAST_SGA_MASK) 5007 /*! @} */ 5008 5009 /*! @name TCD10_CSR - TCD Control and Status */ 5010 /*! @{ */ 5011 5012 #define DMA_TCD_TCD10_CSR_START_MASK (0x1U) 5013 #define DMA_TCD_TCD10_CSR_START_SHIFT (0U) 5014 #define DMA_TCD_TCD10_CSR_START_WIDTH (1U) 5015 #define DMA_TCD_TCD10_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CSR_START_SHIFT)) & DMA_TCD_TCD10_CSR_START_MASK) 5016 5017 #define DMA_TCD_TCD10_CSR_INTMAJOR_MASK (0x2U) 5018 #define DMA_TCD_TCD10_CSR_INTMAJOR_SHIFT (1U) 5019 #define DMA_TCD_TCD10_CSR_INTMAJOR_WIDTH (1U) 5020 #define DMA_TCD_TCD10_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD10_CSR_INTMAJOR_MASK) 5021 5022 #define DMA_TCD_TCD10_CSR_INTHALF_MASK (0x4U) 5023 #define DMA_TCD_TCD10_CSR_INTHALF_SHIFT (2U) 5024 #define DMA_TCD_TCD10_CSR_INTHALF_WIDTH (1U) 5025 #define DMA_TCD_TCD10_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD10_CSR_INTHALF_MASK) 5026 5027 #define DMA_TCD_TCD10_CSR_DREQ_MASK (0x8U) 5028 #define DMA_TCD_TCD10_CSR_DREQ_SHIFT (3U) 5029 #define DMA_TCD_TCD10_CSR_DREQ_WIDTH (1U) 5030 #define DMA_TCD_TCD10_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CSR_DREQ_SHIFT)) & DMA_TCD_TCD10_CSR_DREQ_MASK) 5031 5032 #define DMA_TCD_TCD10_CSR_ESG_MASK (0x10U) 5033 #define DMA_TCD_TCD10_CSR_ESG_SHIFT (4U) 5034 #define DMA_TCD_TCD10_CSR_ESG_WIDTH (1U) 5035 #define DMA_TCD_TCD10_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CSR_ESG_SHIFT)) & DMA_TCD_TCD10_CSR_ESG_MASK) 5036 5037 #define DMA_TCD_TCD10_CSR_MAJORELINK_MASK (0x20U) 5038 #define DMA_TCD_TCD10_CSR_MAJORELINK_SHIFT (5U) 5039 #define DMA_TCD_TCD10_CSR_MAJORELINK_WIDTH (1U) 5040 #define DMA_TCD_TCD10_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD10_CSR_MAJORELINK_MASK) 5041 5042 #define DMA_TCD_TCD10_CSR_EEOP_MASK (0x40U) 5043 #define DMA_TCD_TCD10_CSR_EEOP_SHIFT (6U) 5044 #define DMA_TCD_TCD10_CSR_EEOP_WIDTH (1U) 5045 #define DMA_TCD_TCD10_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CSR_EEOP_SHIFT)) & DMA_TCD_TCD10_CSR_EEOP_MASK) 5046 5047 #define DMA_TCD_TCD10_CSR_ESDA_MASK (0x80U) 5048 #define DMA_TCD_TCD10_CSR_ESDA_SHIFT (7U) 5049 #define DMA_TCD_TCD10_CSR_ESDA_WIDTH (1U) 5050 #define DMA_TCD_TCD10_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CSR_ESDA_SHIFT)) & DMA_TCD_TCD10_CSR_ESDA_MASK) 5051 5052 #define DMA_TCD_TCD10_CSR_MAJORLINKCH_MASK (0x1F00U) 5053 #define DMA_TCD_TCD10_CSR_MAJORLINKCH_SHIFT (8U) 5054 #define DMA_TCD_TCD10_CSR_MAJORLINKCH_WIDTH (5U) 5055 #define DMA_TCD_TCD10_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD10_CSR_MAJORLINKCH_MASK) 5056 5057 #define DMA_TCD_TCD10_CSR_BWC_MASK (0xC000U) 5058 #define DMA_TCD_TCD10_CSR_BWC_SHIFT (14U) 5059 #define DMA_TCD_TCD10_CSR_BWC_WIDTH (2U) 5060 #define DMA_TCD_TCD10_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_CSR_BWC_SHIFT)) & DMA_TCD_TCD10_CSR_BWC_MASK) 5061 /*! @} */ 5062 5063 /*! @name TCD10_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 5064 /*! @{ */ 5065 5066 #define DMA_TCD_TCD10_BITER_ELINKNO_BITER_MASK (0x7FFFU) 5067 #define DMA_TCD_TCD10_BITER_ELINKNO_BITER_SHIFT (0U) 5068 #define DMA_TCD_TCD10_BITER_ELINKNO_BITER_WIDTH (15U) 5069 #define DMA_TCD_TCD10_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD10_BITER_ELINKNO_BITER_MASK) 5070 5071 #define DMA_TCD_TCD10_BITER_ELINKNO_ELINK_MASK (0x8000U) 5072 #define DMA_TCD_TCD10_BITER_ELINKNO_ELINK_SHIFT (15U) 5073 #define DMA_TCD_TCD10_BITER_ELINKNO_ELINK_WIDTH (1U) 5074 #define DMA_TCD_TCD10_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD10_BITER_ELINKNO_ELINK_MASK) 5075 /*! @} */ 5076 5077 /*! @name TCD10_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 5078 /*! @{ */ 5079 5080 #define DMA_TCD_TCD10_BITER_ELINKYES_BITER_MASK (0x1FFU) 5081 #define DMA_TCD_TCD10_BITER_ELINKYES_BITER_SHIFT (0U) 5082 #define DMA_TCD_TCD10_BITER_ELINKYES_BITER_WIDTH (9U) 5083 #define DMA_TCD_TCD10_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD10_BITER_ELINKYES_BITER_MASK) 5084 5085 #define DMA_TCD_TCD10_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 5086 #define DMA_TCD_TCD10_BITER_ELINKYES_LINKCH_SHIFT (9U) 5087 #define DMA_TCD_TCD10_BITER_ELINKYES_LINKCH_WIDTH (5U) 5088 #define DMA_TCD_TCD10_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD10_BITER_ELINKYES_LINKCH_MASK) 5089 5090 #define DMA_TCD_TCD10_BITER_ELINKYES_ELINK_MASK (0x8000U) 5091 #define DMA_TCD_TCD10_BITER_ELINKYES_ELINK_SHIFT (15U) 5092 #define DMA_TCD_TCD10_BITER_ELINKYES_ELINK_WIDTH (1U) 5093 #define DMA_TCD_TCD10_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD10_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD10_BITER_ELINKYES_ELINK_MASK) 5094 /*! @} */ 5095 5096 /*! @name CH11_CSR - Channel Control and Status */ 5097 /*! @{ */ 5098 5099 #define DMA_TCD_CH11_CSR_ERQ_MASK (0x1U) 5100 #define DMA_TCD_CH11_CSR_ERQ_SHIFT (0U) 5101 #define DMA_TCD_CH11_CSR_ERQ_WIDTH (1U) 5102 #define DMA_TCD_CH11_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_CSR_ERQ_SHIFT)) & DMA_TCD_CH11_CSR_ERQ_MASK) 5103 5104 #define DMA_TCD_CH11_CSR_EARQ_MASK (0x2U) 5105 #define DMA_TCD_CH11_CSR_EARQ_SHIFT (1U) 5106 #define DMA_TCD_CH11_CSR_EARQ_WIDTH (1U) 5107 #define DMA_TCD_CH11_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_CSR_EARQ_SHIFT)) & DMA_TCD_CH11_CSR_EARQ_MASK) 5108 5109 #define DMA_TCD_CH11_CSR_EEI_MASK (0x4U) 5110 #define DMA_TCD_CH11_CSR_EEI_SHIFT (2U) 5111 #define DMA_TCD_CH11_CSR_EEI_WIDTH (1U) 5112 #define DMA_TCD_CH11_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_CSR_EEI_SHIFT)) & DMA_TCD_CH11_CSR_EEI_MASK) 5113 5114 #define DMA_TCD_CH11_CSR_EBW_MASK (0x8U) 5115 #define DMA_TCD_CH11_CSR_EBW_SHIFT (3U) 5116 #define DMA_TCD_CH11_CSR_EBW_WIDTH (1U) 5117 #define DMA_TCD_CH11_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_CSR_EBW_SHIFT)) & DMA_TCD_CH11_CSR_EBW_MASK) 5118 5119 #define DMA_TCD_CH11_CSR_DONE_MASK (0x40000000U) 5120 #define DMA_TCD_CH11_CSR_DONE_SHIFT (30U) 5121 #define DMA_TCD_CH11_CSR_DONE_WIDTH (1U) 5122 #define DMA_TCD_CH11_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_CSR_DONE_SHIFT)) & DMA_TCD_CH11_CSR_DONE_MASK) 5123 5124 #define DMA_TCD_CH11_CSR_ACTIVE_MASK (0x80000000U) 5125 #define DMA_TCD_CH11_CSR_ACTIVE_SHIFT (31U) 5126 #define DMA_TCD_CH11_CSR_ACTIVE_WIDTH (1U) 5127 #define DMA_TCD_CH11_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH11_CSR_ACTIVE_MASK) 5128 /*! @} */ 5129 5130 /*! @name CH11_ES - Channel Error Status */ 5131 /*! @{ */ 5132 5133 #define DMA_TCD_CH11_ES_DBE_MASK (0x1U) 5134 #define DMA_TCD_CH11_ES_DBE_SHIFT (0U) 5135 #define DMA_TCD_CH11_ES_DBE_WIDTH (1U) 5136 #define DMA_TCD_CH11_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_ES_DBE_SHIFT)) & DMA_TCD_CH11_ES_DBE_MASK) 5137 5138 #define DMA_TCD_CH11_ES_SBE_MASK (0x2U) 5139 #define DMA_TCD_CH11_ES_SBE_SHIFT (1U) 5140 #define DMA_TCD_CH11_ES_SBE_WIDTH (1U) 5141 #define DMA_TCD_CH11_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_ES_SBE_SHIFT)) & DMA_TCD_CH11_ES_SBE_MASK) 5142 5143 #define DMA_TCD_CH11_ES_SGE_MASK (0x4U) 5144 #define DMA_TCD_CH11_ES_SGE_SHIFT (2U) 5145 #define DMA_TCD_CH11_ES_SGE_WIDTH (1U) 5146 #define DMA_TCD_CH11_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_ES_SGE_SHIFT)) & DMA_TCD_CH11_ES_SGE_MASK) 5147 5148 #define DMA_TCD_CH11_ES_NCE_MASK (0x8U) 5149 #define DMA_TCD_CH11_ES_NCE_SHIFT (3U) 5150 #define DMA_TCD_CH11_ES_NCE_WIDTH (1U) 5151 #define DMA_TCD_CH11_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_ES_NCE_SHIFT)) & DMA_TCD_CH11_ES_NCE_MASK) 5152 5153 #define DMA_TCD_CH11_ES_DOE_MASK (0x10U) 5154 #define DMA_TCD_CH11_ES_DOE_SHIFT (4U) 5155 #define DMA_TCD_CH11_ES_DOE_WIDTH (1U) 5156 #define DMA_TCD_CH11_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_ES_DOE_SHIFT)) & DMA_TCD_CH11_ES_DOE_MASK) 5157 5158 #define DMA_TCD_CH11_ES_DAE_MASK (0x20U) 5159 #define DMA_TCD_CH11_ES_DAE_SHIFT (5U) 5160 #define DMA_TCD_CH11_ES_DAE_WIDTH (1U) 5161 #define DMA_TCD_CH11_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_ES_DAE_SHIFT)) & DMA_TCD_CH11_ES_DAE_MASK) 5162 5163 #define DMA_TCD_CH11_ES_SOE_MASK (0x40U) 5164 #define DMA_TCD_CH11_ES_SOE_SHIFT (6U) 5165 #define DMA_TCD_CH11_ES_SOE_WIDTH (1U) 5166 #define DMA_TCD_CH11_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_ES_SOE_SHIFT)) & DMA_TCD_CH11_ES_SOE_MASK) 5167 5168 #define DMA_TCD_CH11_ES_SAE_MASK (0x80U) 5169 #define DMA_TCD_CH11_ES_SAE_SHIFT (7U) 5170 #define DMA_TCD_CH11_ES_SAE_WIDTH (1U) 5171 #define DMA_TCD_CH11_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_ES_SAE_SHIFT)) & DMA_TCD_CH11_ES_SAE_MASK) 5172 5173 #define DMA_TCD_CH11_ES_ERR_MASK (0x80000000U) 5174 #define DMA_TCD_CH11_ES_ERR_SHIFT (31U) 5175 #define DMA_TCD_CH11_ES_ERR_WIDTH (1U) 5176 #define DMA_TCD_CH11_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_ES_ERR_SHIFT)) & DMA_TCD_CH11_ES_ERR_MASK) 5177 /*! @} */ 5178 5179 /*! @name CH11_INT - Channel Interrupt Status */ 5180 /*! @{ */ 5181 5182 #define DMA_TCD_CH11_INT_INT_MASK (0x1U) 5183 #define DMA_TCD_CH11_INT_INT_SHIFT (0U) 5184 #define DMA_TCD_CH11_INT_INT_WIDTH (1U) 5185 #define DMA_TCD_CH11_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_INT_INT_SHIFT)) & DMA_TCD_CH11_INT_INT_MASK) 5186 /*! @} */ 5187 5188 /*! @name CH11_SBR - Channel System Bus */ 5189 /*! @{ */ 5190 5191 #define DMA_TCD_CH11_SBR_MID_MASK (0xFU) 5192 #define DMA_TCD_CH11_SBR_MID_SHIFT (0U) 5193 #define DMA_TCD_CH11_SBR_MID_WIDTH (4U) 5194 #define DMA_TCD_CH11_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_SBR_MID_SHIFT)) & DMA_TCD_CH11_SBR_MID_MASK) 5195 5196 #define DMA_TCD_CH11_SBR_PAL_MASK (0x8000U) 5197 #define DMA_TCD_CH11_SBR_PAL_SHIFT (15U) 5198 #define DMA_TCD_CH11_SBR_PAL_WIDTH (1U) 5199 #define DMA_TCD_CH11_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_SBR_PAL_SHIFT)) & DMA_TCD_CH11_SBR_PAL_MASK) 5200 5201 #define DMA_TCD_CH11_SBR_EMI_MASK (0x10000U) 5202 #define DMA_TCD_CH11_SBR_EMI_SHIFT (16U) 5203 #define DMA_TCD_CH11_SBR_EMI_WIDTH (1U) 5204 #define DMA_TCD_CH11_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_SBR_EMI_SHIFT)) & DMA_TCD_CH11_SBR_EMI_MASK) 5205 5206 #define DMA_TCD_CH11_SBR_ATTR_MASK (0xE0000U) 5207 #define DMA_TCD_CH11_SBR_ATTR_SHIFT (17U) 5208 #define DMA_TCD_CH11_SBR_ATTR_WIDTH (3U) 5209 #define DMA_TCD_CH11_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_SBR_ATTR_SHIFT)) & DMA_TCD_CH11_SBR_ATTR_MASK) 5210 /*! @} */ 5211 5212 /*! @name CH11_PRI - Channel Priority */ 5213 /*! @{ */ 5214 5215 #define DMA_TCD_CH11_PRI_APL_MASK (0x7U) 5216 #define DMA_TCD_CH11_PRI_APL_SHIFT (0U) 5217 #define DMA_TCD_CH11_PRI_APL_WIDTH (3U) 5218 #define DMA_TCD_CH11_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_PRI_APL_SHIFT)) & DMA_TCD_CH11_PRI_APL_MASK) 5219 5220 #define DMA_TCD_CH11_PRI_DPA_MASK (0x40000000U) 5221 #define DMA_TCD_CH11_PRI_DPA_SHIFT (30U) 5222 #define DMA_TCD_CH11_PRI_DPA_WIDTH (1U) 5223 #define DMA_TCD_CH11_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_PRI_DPA_SHIFT)) & DMA_TCD_CH11_PRI_DPA_MASK) 5224 5225 #define DMA_TCD_CH11_PRI_ECP_MASK (0x80000000U) 5226 #define DMA_TCD_CH11_PRI_ECP_SHIFT (31U) 5227 #define DMA_TCD_CH11_PRI_ECP_WIDTH (1U) 5228 #define DMA_TCD_CH11_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH11_PRI_ECP_SHIFT)) & DMA_TCD_CH11_PRI_ECP_MASK) 5229 /*! @} */ 5230 5231 /*! @name TCD11_SADDR - TCD Source Address */ 5232 /*! @{ */ 5233 5234 #define DMA_TCD_TCD11_SADDR_SADDR_MASK (0xFFFFFFFFU) 5235 #define DMA_TCD_TCD11_SADDR_SADDR_SHIFT (0U) 5236 #define DMA_TCD_TCD11_SADDR_SADDR_WIDTH (32U) 5237 #define DMA_TCD_TCD11_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD11_SADDR_SADDR_MASK) 5238 /*! @} */ 5239 5240 /*! @name TCD11_SOFF - TCD Signed Source Address Offset */ 5241 /*! @{ */ 5242 5243 #define DMA_TCD_TCD11_SOFF_SOFF_MASK (0xFFFFU) 5244 #define DMA_TCD_TCD11_SOFF_SOFF_SHIFT (0U) 5245 #define DMA_TCD_TCD11_SOFF_SOFF_WIDTH (16U) 5246 #define DMA_TCD_TCD11_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD11_SOFF_SOFF_MASK) 5247 /*! @} */ 5248 5249 /*! @name TCD11_ATTR - TCD Transfer Attributes */ 5250 /*! @{ */ 5251 5252 #define DMA_TCD_TCD11_ATTR_DSIZE_MASK (0x7U) 5253 #define DMA_TCD_TCD11_ATTR_DSIZE_SHIFT (0U) 5254 #define DMA_TCD_TCD11_ATTR_DSIZE_WIDTH (3U) 5255 #define DMA_TCD_TCD11_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD11_ATTR_DSIZE_MASK) 5256 5257 #define DMA_TCD_TCD11_ATTR_DMOD_MASK (0xF8U) 5258 #define DMA_TCD_TCD11_ATTR_DMOD_SHIFT (3U) 5259 #define DMA_TCD_TCD11_ATTR_DMOD_WIDTH (5U) 5260 #define DMA_TCD_TCD11_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD11_ATTR_DMOD_MASK) 5261 5262 #define DMA_TCD_TCD11_ATTR_SSIZE_MASK (0x700U) 5263 #define DMA_TCD_TCD11_ATTR_SSIZE_SHIFT (8U) 5264 #define DMA_TCD_TCD11_ATTR_SSIZE_WIDTH (3U) 5265 #define DMA_TCD_TCD11_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD11_ATTR_SSIZE_MASK) 5266 5267 #define DMA_TCD_TCD11_ATTR_SMOD_MASK (0xF800U) 5268 #define DMA_TCD_TCD11_ATTR_SMOD_SHIFT (11U) 5269 #define DMA_TCD_TCD11_ATTR_SMOD_WIDTH (5U) 5270 #define DMA_TCD_TCD11_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD11_ATTR_SMOD_MASK) 5271 /*! @} */ 5272 5273 /*! @name TCD11_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 5274 /*! @{ */ 5275 5276 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 5277 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 5278 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 5279 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD11_NBYTES_MLOFFNO_NBYTES_MASK) 5280 5281 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 5282 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 5283 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 5284 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD11_NBYTES_MLOFFNO_DMLOE_MASK) 5285 5286 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 5287 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 5288 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 5289 #define DMA_TCD_TCD11_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD11_NBYTES_MLOFFNO_SMLOE_MASK) 5290 /*! @} */ 5291 5292 /*! @name TCD11_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 5293 /*! @{ */ 5294 5295 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 5296 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 5297 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 5298 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD11_NBYTES_MLOFFYES_NBYTES_MASK) 5299 5300 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 5301 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 5302 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 5303 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD11_NBYTES_MLOFFYES_MLOFF_MASK) 5304 5305 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 5306 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 5307 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 5308 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD11_NBYTES_MLOFFYES_DMLOE_MASK) 5309 5310 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 5311 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 5312 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 5313 #define DMA_TCD_TCD11_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD11_NBYTES_MLOFFYES_SMLOE_MASK) 5314 /*! @} */ 5315 5316 /*! @name TCD11_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 5317 /*! @{ */ 5318 5319 #define DMA_TCD_TCD11_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 5320 #define DMA_TCD_TCD11_SLAST_SDA_SLAST_SDA_SHIFT (0U) 5321 #define DMA_TCD_TCD11_SLAST_SDA_SLAST_SDA_WIDTH (32U) 5322 #define DMA_TCD_TCD11_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD11_SLAST_SDA_SLAST_SDA_MASK) 5323 /*! @} */ 5324 5325 /*! @name TCD11_DADDR - TCD Destination Address */ 5326 /*! @{ */ 5327 5328 #define DMA_TCD_TCD11_DADDR_DADDR_MASK (0xFFFFFFFFU) 5329 #define DMA_TCD_TCD11_DADDR_DADDR_SHIFT (0U) 5330 #define DMA_TCD_TCD11_DADDR_DADDR_WIDTH (32U) 5331 #define DMA_TCD_TCD11_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD11_DADDR_DADDR_MASK) 5332 /*! @} */ 5333 5334 /*! @name TCD11_DOFF - TCD Signed Destination Address Offset */ 5335 /*! @{ */ 5336 5337 #define DMA_TCD_TCD11_DOFF_DOFF_MASK (0xFFFFU) 5338 #define DMA_TCD_TCD11_DOFF_DOFF_SHIFT (0U) 5339 #define DMA_TCD_TCD11_DOFF_DOFF_WIDTH (16U) 5340 #define DMA_TCD_TCD11_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD11_DOFF_DOFF_MASK) 5341 /*! @} */ 5342 5343 /*! @name TCD11_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 5344 /*! @{ */ 5345 5346 #define DMA_TCD_TCD11_CITER_ELINKNO_CITER_MASK (0x7FFFU) 5347 #define DMA_TCD_TCD11_CITER_ELINKNO_CITER_SHIFT (0U) 5348 #define DMA_TCD_TCD11_CITER_ELINKNO_CITER_WIDTH (15U) 5349 #define DMA_TCD_TCD11_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD11_CITER_ELINKNO_CITER_MASK) 5350 5351 #define DMA_TCD_TCD11_CITER_ELINKNO_ELINK_MASK (0x8000U) 5352 #define DMA_TCD_TCD11_CITER_ELINKNO_ELINK_SHIFT (15U) 5353 #define DMA_TCD_TCD11_CITER_ELINKNO_ELINK_WIDTH (1U) 5354 #define DMA_TCD_TCD11_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD11_CITER_ELINKNO_ELINK_MASK) 5355 /*! @} */ 5356 5357 /*! @name TCD11_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 5358 /*! @{ */ 5359 5360 #define DMA_TCD_TCD11_CITER_ELINKYES_CITER_MASK (0x1FFU) 5361 #define DMA_TCD_TCD11_CITER_ELINKYES_CITER_SHIFT (0U) 5362 #define DMA_TCD_TCD11_CITER_ELINKYES_CITER_WIDTH (9U) 5363 #define DMA_TCD_TCD11_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD11_CITER_ELINKYES_CITER_MASK) 5364 5365 #define DMA_TCD_TCD11_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 5366 #define DMA_TCD_TCD11_CITER_ELINKYES_LINKCH_SHIFT (9U) 5367 #define DMA_TCD_TCD11_CITER_ELINKYES_LINKCH_WIDTH (5U) 5368 #define DMA_TCD_TCD11_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD11_CITER_ELINKYES_LINKCH_MASK) 5369 5370 #define DMA_TCD_TCD11_CITER_ELINKYES_ELINK_MASK (0x8000U) 5371 #define DMA_TCD_TCD11_CITER_ELINKYES_ELINK_SHIFT (15U) 5372 #define DMA_TCD_TCD11_CITER_ELINKYES_ELINK_WIDTH (1U) 5373 #define DMA_TCD_TCD11_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD11_CITER_ELINKYES_ELINK_MASK) 5374 /*! @} */ 5375 5376 /*! @name TCD11_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 5377 /*! @{ */ 5378 5379 #define DMA_TCD_TCD11_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 5380 #define DMA_TCD_TCD11_DLAST_SGA_DLAST_SGA_SHIFT (0U) 5381 #define DMA_TCD_TCD11_DLAST_SGA_DLAST_SGA_WIDTH (32U) 5382 #define DMA_TCD_TCD11_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD11_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD11_DLAST_SGA_DLAST_SGA_MASK) 5383 /*! @} */ 5384 5385 /*! @name TCD11_CSR - TCD Control and Status */ 5386 /*! @{ */ 5387 5388 #define DMA_TCD_TCD11_CSR_START_MASK (0x1U) 5389 #define DMA_TCD_TCD11_CSR_START_SHIFT (0U) 5390 #define DMA_TCD_TCD11_CSR_START_WIDTH (1U) 5391 #define DMA_TCD_TCD11_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CSR_START_SHIFT)) & DMA_TCD_TCD11_CSR_START_MASK) 5392 5393 #define DMA_TCD_TCD11_CSR_INTMAJOR_MASK (0x2U) 5394 #define DMA_TCD_TCD11_CSR_INTMAJOR_SHIFT (1U) 5395 #define DMA_TCD_TCD11_CSR_INTMAJOR_WIDTH (1U) 5396 #define DMA_TCD_TCD11_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD11_CSR_INTMAJOR_MASK) 5397 5398 #define DMA_TCD_TCD11_CSR_INTHALF_MASK (0x4U) 5399 #define DMA_TCD_TCD11_CSR_INTHALF_SHIFT (2U) 5400 #define DMA_TCD_TCD11_CSR_INTHALF_WIDTH (1U) 5401 #define DMA_TCD_TCD11_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD11_CSR_INTHALF_MASK) 5402 5403 #define DMA_TCD_TCD11_CSR_DREQ_MASK (0x8U) 5404 #define DMA_TCD_TCD11_CSR_DREQ_SHIFT (3U) 5405 #define DMA_TCD_TCD11_CSR_DREQ_WIDTH (1U) 5406 #define DMA_TCD_TCD11_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CSR_DREQ_SHIFT)) & DMA_TCD_TCD11_CSR_DREQ_MASK) 5407 5408 #define DMA_TCD_TCD11_CSR_ESG_MASK (0x10U) 5409 #define DMA_TCD_TCD11_CSR_ESG_SHIFT (4U) 5410 #define DMA_TCD_TCD11_CSR_ESG_WIDTH (1U) 5411 #define DMA_TCD_TCD11_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CSR_ESG_SHIFT)) & DMA_TCD_TCD11_CSR_ESG_MASK) 5412 5413 #define DMA_TCD_TCD11_CSR_MAJORELINK_MASK (0x20U) 5414 #define DMA_TCD_TCD11_CSR_MAJORELINK_SHIFT (5U) 5415 #define DMA_TCD_TCD11_CSR_MAJORELINK_WIDTH (1U) 5416 #define DMA_TCD_TCD11_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD11_CSR_MAJORELINK_MASK) 5417 5418 #define DMA_TCD_TCD11_CSR_EEOP_MASK (0x40U) 5419 #define DMA_TCD_TCD11_CSR_EEOP_SHIFT (6U) 5420 #define DMA_TCD_TCD11_CSR_EEOP_WIDTH (1U) 5421 #define DMA_TCD_TCD11_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CSR_EEOP_SHIFT)) & DMA_TCD_TCD11_CSR_EEOP_MASK) 5422 5423 #define DMA_TCD_TCD11_CSR_ESDA_MASK (0x80U) 5424 #define DMA_TCD_TCD11_CSR_ESDA_SHIFT (7U) 5425 #define DMA_TCD_TCD11_CSR_ESDA_WIDTH (1U) 5426 #define DMA_TCD_TCD11_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CSR_ESDA_SHIFT)) & DMA_TCD_TCD11_CSR_ESDA_MASK) 5427 5428 #define DMA_TCD_TCD11_CSR_MAJORLINKCH_MASK (0x1F00U) 5429 #define DMA_TCD_TCD11_CSR_MAJORLINKCH_SHIFT (8U) 5430 #define DMA_TCD_TCD11_CSR_MAJORLINKCH_WIDTH (5U) 5431 #define DMA_TCD_TCD11_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD11_CSR_MAJORLINKCH_MASK) 5432 5433 #define DMA_TCD_TCD11_CSR_BWC_MASK (0xC000U) 5434 #define DMA_TCD_TCD11_CSR_BWC_SHIFT (14U) 5435 #define DMA_TCD_TCD11_CSR_BWC_WIDTH (2U) 5436 #define DMA_TCD_TCD11_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_CSR_BWC_SHIFT)) & DMA_TCD_TCD11_CSR_BWC_MASK) 5437 /*! @} */ 5438 5439 /*! @name TCD11_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 5440 /*! @{ */ 5441 5442 #define DMA_TCD_TCD11_BITER_ELINKNO_BITER_MASK (0x7FFFU) 5443 #define DMA_TCD_TCD11_BITER_ELINKNO_BITER_SHIFT (0U) 5444 #define DMA_TCD_TCD11_BITER_ELINKNO_BITER_WIDTH (15U) 5445 #define DMA_TCD_TCD11_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD11_BITER_ELINKNO_BITER_MASK) 5446 5447 #define DMA_TCD_TCD11_BITER_ELINKNO_ELINK_MASK (0x8000U) 5448 #define DMA_TCD_TCD11_BITER_ELINKNO_ELINK_SHIFT (15U) 5449 #define DMA_TCD_TCD11_BITER_ELINKNO_ELINK_WIDTH (1U) 5450 #define DMA_TCD_TCD11_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD11_BITER_ELINKNO_ELINK_MASK) 5451 /*! @} */ 5452 5453 /*! @name TCD11_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 5454 /*! @{ */ 5455 5456 #define DMA_TCD_TCD11_BITER_ELINKYES_BITER_MASK (0x1FFU) 5457 #define DMA_TCD_TCD11_BITER_ELINKYES_BITER_SHIFT (0U) 5458 #define DMA_TCD_TCD11_BITER_ELINKYES_BITER_WIDTH (9U) 5459 #define DMA_TCD_TCD11_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD11_BITER_ELINKYES_BITER_MASK) 5460 5461 #define DMA_TCD_TCD11_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 5462 #define DMA_TCD_TCD11_BITER_ELINKYES_LINKCH_SHIFT (9U) 5463 #define DMA_TCD_TCD11_BITER_ELINKYES_LINKCH_WIDTH (5U) 5464 #define DMA_TCD_TCD11_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD11_BITER_ELINKYES_LINKCH_MASK) 5465 5466 #define DMA_TCD_TCD11_BITER_ELINKYES_ELINK_MASK (0x8000U) 5467 #define DMA_TCD_TCD11_BITER_ELINKYES_ELINK_SHIFT (15U) 5468 #define DMA_TCD_TCD11_BITER_ELINKYES_ELINK_WIDTH (1U) 5469 #define DMA_TCD_TCD11_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD11_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD11_BITER_ELINKYES_ELINK_MASK) 5470 /*! @} */ 5471 5472 /*! @name CH12_CSR - Channel Control and Status */ 5473 /*! @{ */ 5474 5475 #define DMA_TCD_CH12_CSR_ERQ_MASK (0x1U) 5476 #define DMA_TCD_CH12_CSR_ERQ_SHIFT (0U) 5477 #define DMA_TCD_CH12_CSR_ERQ_WIDTH (1U) 5478 #define DMA_TCD_CH12_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_CSR_ERQ_SHIFT)) & DMA_TCD_CH12_CSR_ERQ_MASK) 5479 5480 #define DMA_TCD_CH12_CSR_EARQ_MASK (0x2U) 5481 #define DMA_TCD_CH12_CSR_EARQ_SHIFT (1U) 5482 #define DMA_TCD_CH12_CSR_EARQ_WIDTH (1U) 5483 #define DMA_TCD_CH12_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_CSR_EARQ_SHIFT)) & DMA_TCD_CH12_CSR_EARQ_MASK) 5484 5485 #define DMA_TCD_CH12_CSR_EEI_MASK (0x4U) 5486 #define DMA_TCD_CH12_CSR_EEI_SHIFT (2U) 5487 #define DMA_TCD_CH12_CSR_EEI_WIDTH (1U) 5488 #define DMA_TCD_CH12_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_CSR_EEI_SHIFT)) & DMA_TCD_CH12_CSR_EEI_MASK) 5489 5490 #define DMA_TCD_CH12_CSR_EBW_MASK (0x8U) 5491 #define DMA_TCD_CH12_CSR_EBW_SHIFT (3U) 5492 #define DMA_TCD_CH12_CSR_EBW_WIDTH (1U) 5493 #define DMA_TCD_CH12_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_CSR_EBW_SHIFT)) & DMA_TCD_CH12_CSR_EBW_MASK) 5494 5495 #define DMA_TCD_CH12_CSR_DONE_MASK (0x40000000U) 5496 #define DMA_TCD_CH12_CSR_DONE_SHIFT (30U) 5497 #define DMA_TCD_CH12_CSR_DONE_WIDTH (1U) 5498 #define DMA_TCD_CH12_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_CSR_DONE_SHIFT)) & DMA_TCD_CH12_CSR_DONE_MASK) 5499 5500 #define DMA_TCD_CH12_CSR_ACTIVE_MASK (0x80000000U) 5501 #define DMA_TCD_CH12_CSR_ACTIVE_SHIFT (31U) 5502 #define DMA_TCD_CH12_CSR_ACTIVE_WIDTH (1U) 5503 #define DMA_TCD_CH12_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH12_CSR_ACTIVE_MASK) 5504 /*! @} */ 5505 5506 /*! @name CH12_ES - Channel Error Status */ 5507 /*! @{ */ 5508 5509 #define DMA_TCD_CH12_ES_DBE_MASK (0x1U) 5510 #define DMA_TCD_CH12_ES_DBE_SHIFT (0U) 5511 #define DMA_TCD_CH12_ES_DBE_WIDTH (1U) 5512 #define DMA_TCD_CH12_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_ES_DBE_SHIFT)) & DMA_TCD_CH12_ES_DBE_MASK) 5513 5514 #define DMA_TCD_CH12_ES_SBE_MASK (0x2U) 5515 #define DMA_TCD_CH12_ES_SBE_SHIFT (1U) 5516 #define DMA_TCD_CH12_ES_SBE_WIDTH (1U) 5517 #define DMA_TCD_CH12_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_ES_SBE_SHIFT)) & DMA_TCD_CH12_ES_SBE_MASK) 5518 5519 #define DMA_TCD_CH12_ES_SGE_MASK (0x4U) 5520 #define DMA_TCD_CH12_ES_SGE_SHIFT (2U) 5521 #define DMA_TCD_CH12_ES_SGE_WIDTH (1U) 5522 #define DMA_TCD_CH12_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_ES_SGE_SHIFT)) & DMA_TCD_CH12_ES_SGE_MASK) 5523 5524 #define DMA_TCD_CH12_ES_NCE_MASK (0x8U) 5525 #define DMA_TCD_CH12_ES_NCE_SHIFT (3U) 5526 #define DMA_TCD_CH12_ES_NCE_WIDTH (1U) 5527 #define DMA_TCD_CH12_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_ES_NCE_SHIFT)) & DMA_TCD_CH12_ES_NCE_MASK) 5528 5529 #define DMA_TCD_CH12_ES_DOE_MASK (0x10U) 5530 #define DMA_TCD_CH12_ES_DOE_SHIFT (4U) 5531 #define DMA_TCD_CH12_ES_DOE_WIDTH (1U) 5532 #define DMA_TCD_CH12_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_ES_DOE_SHIFT)) & DMA_TCD_CH12_ES_DOE_MASK) 5533 5534 #define DMA_TCD_CH12_ES_DAE_MASK (0x20U) 5535 #define DMA_TCD_CH12_ES_DAE_SHIFT (5U) 5536 #define DMA_TCD_CH12_ES_DAE_WIDTH (1U) 5537 #define DMA_TCD_CH12_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_ES_DAE_SHIFT)) & DMA_TCD_CH12_ES_DAE_MASK) 5538 5539 #define DMA_TCD_CH12_ES_SOE_MASK (0x40U) 5540 #define DMA_TCD_CH12_ES_SOE_SHIFT (6U) 5541 #define DMA_TCD_CH12_ES_SOE_WIDTH (1U) 5542 #define DMA_TCD_CH12_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_ES_SOE_SHIFT)) & DMA_TCD_CH12_ES_SOE_MASK) 5543 5544 #define DMA_TCD_CH12_ES_SAE_MASK (0x80U) 5545 #define DMA_TCD_CH12_ES_SAE_SHIFT (7U) 5546 #define DMA_TCD_CH12_ES_SAE_WIDTH (1U) 5547 #define DMA_TCD_CH12_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_ES_SAE_SHIFT)) & DMA_TCD_CH12_ES_SAE_MASK) 5548 5549 #define DMA_TCD_CH12_ES_ERR_MASK (0x80000000U) 5550 #define DMA_TCD_CH12_ES_ERR_SHIFT (31U) 5551 #define DMA_TCD_CH12_ES_ERR_WIDTH (1U) 5552 #define DMA_TCD_CH12_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_ES_ERR_SHIFT)) & DMA_TCD_CH12_ES_ERR_MASK) 5553 /*! @} */ 5554 5555 /*! @name CH12_INT - Channel Interrupt Status */ 5556 /*! @{ */ 5557 5558 #define DMA_TCD_CH12_INT_INT_MASK (0x1U) 5559 #define DMA_TCD_CH12_INT_INT_SHIFT (0U) 5560 #define DMA_TCD_CH12_INT_INT_WIDTH (1U) 5561 #define DMA_TCD_CH12_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_INT_INT_SHIFT)) & DMA_TCD_CH12_INT_INT_MASK) 5562 /*! @} */ 5563 5564 /*! @name CH12_SBR - Channel System Bus */ 5565 /*! @{ */ 5566 5567 #define DMA_TCD_CH12_SBR_MID_MASK (0xFU) 5568 #define DMA_TCD_CH12_SBR_MID_SHIFT (0U) 5569 #define DMA_TCD_CH12_SBR_MID_WIDTH (4U) 5570 #define DMA_TCD_CH12_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_SBR_MID_SHIFT)) & DMA_TCD_CH12_SBR_MID_MASK) 5571 5572 #define DMA_TCD_CH12_SBR_PAL_MASK (0x8000U) 5573 #define DMA_TCD_CH12_SBR_PAL_SHIFT (15U) 5574 #define DMA_TCD_CH12_SBR_PAL_WIDTH (1U) 5575 #define DMA_TCD_CH12_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_SBR_PAL_SHIFT)) & DMA_TCD_CH12_SBR_PAL_MASK) 5576 5577 #define DMA_TCD_CH12_SBR_EMI_MASK (0x10000U) 5578 #define DMA_TCD_CH12_SBR_EMI_SHIFT (16U) 5579 #define DMA_TCD_CH12_SBR_EMI_WIDTH (1U) 5580 #define DMA_TCD_CH12_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_SBR_EMI_SHIFT)) & DMA_TCD_CH12_SBR_EMI_MASK) 5581 5582 #define DMA_TCD_CH12_SBR_ATTR_MASK (0xE0000U) 5583 #define DMA_TCD_CH12_SBR_ATTR_SHIFT (17U) 5584 #define DMA_TCD_CH12_SBR_ATTR_WIDTH (3U) 5585 #define DMA_TCD_CH12_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_SBR_ATTR_SHIFT)) & DMA_TCD_CH12_SBR_ATTR_MASK) 5586 /*! @} */ 5587 5588 /*! @name CH12_PRI - Channel Priority */ 5589 /*! @{ */ 5590 5591 #define DMA_TCD_CH12_PRI_APL_MASK (0x7U) 5592 #define DMA_TCD_CH12_PRI_APL_SHIFT (0U) 5593 #define DMA_TCD_CH12_PRI_APL_WIDTH (3U) 5594 #define DMA_TCD_CH12_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_PRI_APL_SHIFT)) & DMA_TCD_CH12_PRI_APL_MASK) 5595 5596 #define DMA_TCD_CH12_PRI_DPA_MASK (0x40000000U) 5597 #define DMA_TCD_CH12_PRI_DPA_SHIFT (30U) 5598 #define DMA_TCD_CH12_PRI_DPA_WIDTH (1U) 5599 #define DMA_TCD_CH12_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_PRI_DPA_SHIFT)) & DMA_TCD_CH12_PRI_DPA_MASK) 5600 5601 #define DMA_TCD_CH12_PRI_ECP_MASK (0x80000000U) 5602 #define DMA_TCD_CH12_PRI_ECP_SHIFT (31U) 5603 #define DMA_TCD_CH12_PRI_ECP_WIDTH (1U) 5604 #define DMA_TCD_CH12_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH12_PRI_ECP_SHIFT)) & DMA_TCD_CH12_PRI_ECP_MASK) 5605 /*! @} */ 5606 5607 /*! @name TCD12_SADDR - TCD Source Address */ 5608 /*! @{ */ 5609 5610 #define DMA_TCD_TCD12_SADDR_SADDR_MASK (0xFFFFFFFFU) 5611 #define DMA_TCD_TCD12_SADDR_SADDR_SHIFT (0U) 5612 #define DMA_TCD_TCD12_SADDR_SADDR_WIDTH (32U) 5613 #define DMA_TCD_TCD12_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD12_SADDR_SADDR_MASK) 5614 /*! @} */ 5615 5616 /*! @name TCD12_SOFF - TCD Signed Source Address Offset */ 5617 /*! @{ */ 5618 5619 #define DMA_TCD_TCD12_SOFF_SOFF_MASK (0xFFFFU) 5620 #define DMA_TCD_TCD12_SOFF_SOFF_SHIFT (0U) 5621 #define DMA_TCD_TCD12_SOFF_SOFF_WIDTH (16U) 5622 #define DMA_TCD_TCD12_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD12_SOFF_SOFF_MASK) 5623 /*! @} */ 5624 5625 /*! @name TCD12_ATTR - TCD Transfer Attributes */ 5626 /*! @{ */ 5627 5628 #define DMA_TCD_TCD12_ATTR_DSIZE_MASK (0x7U) 5629 #define DMA_TCD_TCD12_ATTR_DSIZE_SHIFT (0U) 5630 #define DMA_TCD_TCD12_ATTR_DSIZE_WIDTH (3U) 5631 #define DMA_TCD_TCD12_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD12_ATTR_DSIZE_MASK) 5632 5633 #define DMA_TCD_TCD12_ATTR_DMOD_MASK (0xF8U) 5634 #define DMA_TCD_TCD12_ATTR_DMOD_SHIFT (3U) 5635 #define DMA_TCD_TCD12_ATTR_DMOD_WIDTH (5U) 5636 #define DMA_TCD_TCD12_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD12_ATTR_DMOD_MASK) 5637 5638 #define DMA_TCD_TCD12_ATTR_SSIZE_MASK (0x700U) 5639 #define DMA_TCD_TCD12_ATTR_SSIZE_SHIFT (8U) 5640 #define DMA_TCD_TCD12_ATTR_SSIZE_WIDTH (3U) 5641 #define DMA_TCD_TCD12_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD12_ATTR_SSIZE_MASK) 5642 5643 #define DMA_TCD_TCD12_ATTR_SMOD_MASK (0xF800U) 5644 #define DMA_TCD_TCD12_ATTR_SMOD_SHIFT (11U) 5645 #define DMA_TCD_TCD12_ATTR_SMOD_WIDTH (5U) 5646 #define DMA_TCD_TCD12_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD12_ATTR_SMOD_MASK) 5647 /*! @} */ 5648 5649 /*! @name TCD12_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 5650 /*! @{ */ 5651 5652 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 5653 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 5654 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 5655 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD12_NBYTES_MLOFFNO_NBYTES_MASK) 5656 5657 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 5658 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 5659 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 5660 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD12_NBYTES_MLOFFNO_DMLOE_MASK) 5661 5662 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 5663 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 5664 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 5665 #define DMA_TCD_TCD12_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD12_NBYTES_MLOFFNO_SMLOE_MASK) 5666 /*! @} */ 5667 5668 /*! @name TCD12_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 5669 /*! @{ */ 5670 5671 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 5672 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 5673 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 5674 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD12_NBYTES_MLOFFYES_NBYTES_MASK) 5675 5676 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 5677 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 5678 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 5679 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD12_NBYTES_MLOFFYES_MLOFF_MASK) 5680 5681 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 5682 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 5683 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 5684 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD12_NBYTES_MLOFFYES_DMLOE_MASK) 5685 5686 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 5687 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 5688 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 5689 #define DMA_TCD_TCD12_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD12_NBYTES_MLOFFYES_SMLOE_MASK) 5690 /*! @} */ 5691 5692 /*! @name TCD12_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 5693 /*! @{ */ 5694 5695 #define DMA_TCD_TCD12_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 5696 #define DMA_TCD_TCD12_SLAST_SDA_SLAST_SDA_SHIFT (0U) 5697 #define DMA_TCD_TCD12_SLAST_SDA_SLAST_SDA_WIDTH (32U) 5698 #define DMA_TCD_TCD12_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD12_SLAST_SDA_SLAST_SDA_MASK) 5699 /*! @} */ 5700 5701 /*! @name TCD12_DADDR - TCD Destination Address */ 5702 /*! @{ */ 5703 5704 #define DMA_TCD_TCD12_DADDR_DADDR_MASK (0xFFFFFFFFU) 5705 #define DMA_TCD_TCD12_DADDR_DADDR_SHIFT (0U) 5706 #define DMA_TCD_TCD12_DADDR_DADDR_WIDTH (32U) 5707 #define DMA_TCD_TCD12_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD12_DADDR_DADDR_MASK) 5708 /*! @} */ 5709 5710 /*! @name TCD12_DOFF - TCD Signed Destination Address Offset */ 5711 /*! @{ */ 5712 5713 #define DMA_TCD_TCD12_DOFF_DOFF_MASK (0xFFFFU) 5714 #define DMA_TCD_TCD12_DOFF_DOFF_SHIFT (0U) 5715 #define DMA_TCD_TCD12_DOFF_DOFF_WIDTH (16U) 5716 #define DMA_TCD_TCD12_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD12_DOFF_DOFF_MASK) 5717 /*! @} */ 5718 5719 /*! @name TCD12_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 5720 /*! @{ */ 5721 5722 #define DMA_TCD_TCD12_CITER_ELINKNO_CITER_MASK (0x7FFFU) 5723 #define DMA_TCD_TCD12_CITER_ELINKNO_CITER_SHIFT (0U) 5724 #define DMA_TCD_TCD12_CITER_ELINKNO_CITER_WIDTH (15U) 5725 #define DMA_TCD_TCD12_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD12_CITER_ELINKNO_CITER_MASK) 5726 5727 #define DMA_TCD_TCD12_CITER_ELINKNO_ELINK_MASK (0x8000U) 5728 #define DMA_TCD_TCD12_CITER_ELINKNO_ELINK_SHIFT (15U) 5729 #define DMA_TCD_TCD12_CITER_ELINKNO_ELINK_WIDTH (1U) 5730 #define DMA_TCD_TCD12_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD12_CITER_ELINKNO_ELINK_MASK) 5731 /*! @} */ 5732 5733 /*! @name TCD12_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 5734 /*! @{ */ 5735 5736 #define DMA_TCD_TCD12_CITER_ELINKYES_CITER_MASK (0x1FFU) 5737 #define DMA_TCD_TCD12_CITER_ELINKYES_CITER_SHIFT (0U) 5738 #define DMA_TCD_TCD12_CITER_ELINKYES_CITER_WIDTH (9U) 5739 #define DMA_TCD_TCD12_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD12_CITER_ELINKYES_CITER_MASK) 5740 5741 #define DMA_TCD_TCD12_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 5742 #define DMA_TCD_TCD12_CITER_ELINKYES_LINKCH_SHIFT (9U) 5743 #define DMA_TCD_TCD12_CITER_ELINKYES_LINKCH_WIDTH (5U) 5744 #define DMA_TCD_TCD12_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD12_CITER_ELINKYES_LINKCH_MASK) 5745 5746 #define DMA_TCD_TCD12_CITER_ELINKYES_ELINK_MASK (0x8000U) 5747 #define DMA_TCD_TCD12_CITER_ELINKYES_ELINK_SHIFT (15U) 5748 #define DMA_TCD_TCD12_CITER_ELINKYES_ELINK_WIDTH (1U) 5749 #define DMA_TCD_TCD12_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD12_CITER_ELINKYES_ELINK_MASK) 5750 /*! @} */ 5751 5752 /*! @name TCD12_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 5753 /*! @{ */ 5754 5755 #define DMA_TCD_TCD12_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 5756 #define DMA_TCD_TCD12_DLAST_SGA_DLAST_SGA_SHIFT (0U) 5757 #define DMA_TCD_TCD12_DLAST_SGA_DLAST_SGA_WIDTH (32U) 5758 #define DMA_TCD_TCD12_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD12_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD12_DLAST_SGA_DLAST_SGA_MASK) 5759 /*! @} */ 5760 5761 /*! @name TCD12_CSR - TCD Control and Status */ 5762 /*! @{ */ 5763 5764 #define DMA_TCD_TCD12_CSR_START_MASK (0x1U) 5765 #define DMA_TCD_TCD12_CSR_START_SHIFT (0U) 5766 #define DMA_TCD_TCD12_CSR_START_WIDTH (1U) 5767 #define DMA_TCD_TCD12_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CSR_START_SHIFT)) & DMA_TCD_TCD12_CSR_START_MASK) 5768 5769 #define DMA_TCD_TCD12_CSR_INTMAJOR_MASK (0x2U) 5770 #define DMA_TCD_TCD12_CSR_INTMAJOR_SHIFT (1U) 5771 #define DMA_TCD_TCD12_CSR_INTMAJOR_WIDTH (1U) 5772 #define DMA_TCD_TCD12_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD12_CSR_INTMAJOR_MASK) 5773 5774 #define DMA_TCD_TCD12_CSR_INTHALF_MASK (0x4U) 5775 #define DMA_TCD_TCD12_CSR_INTHALF_SHIFT (2U) 5776 #define DMA_TCD_TCD12_CSR_INTHALF_WIDTH (1U) 5777 #define DMA_TCD_TCD12_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD12_CSR_INTHALF_MASK) 5778 5779 #define DMA_TCD_TCD12_CSR_DREQ_MASK (0x8U) 5780 #define DMA_TCD_TCD12_CSR_DREQ_SHIFT (3U) 5781 #define DMA_TCD_TCD12_CSR_DREQ_WIDTH (1U) 5782 #define DMA_TCD_TCD12_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CSR_DREQ_SHIFT)) & DMA_TCD_TCD12_CSR_DREQ_MASK) 5783 5784 #define DMA_TCD_TCD12_CSR_ESG_MASK (0x10U) 5785 #define DMA_TCD_TCD12_CSR_ESG_SHIFT (4U) 5786 #define DMA_TCD_TCD12_CSR_ESG_WIDTH (1U) 5787 #define DMA_TCD_TCD12_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CSR_ESG_SHIFT)) & DMA_TCD_TCD12_CSR_ESG_MASK) 5788 5789 #define DMA_TCD_TCD12_CSR_MAJORELINK_MASK (0x20U) 5790 #define DMA_TCD_TCD12_CSR_MAJORELINK_SHIFT (5U) 5791 #define DMA_TCD_TCD12_CSR_MAJORELINK_WIDTH (1U) 5792 #define DMA_TCD_TCD12_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD12_CSR_MAJORELINK_MASK) 5793 5794 #define DMA_TCD_TCD12_CSR_EEOP_MASK (0x40U) 5795 #define DMA_TCD_TCD12_CSR_EEOP_SHIFT (6U) 5796 #define DMA_TCD_TCD12_CSR_EEOP_WIDTH (1U) 5797 #define DMA_TCD_TCD12_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CSR_EEOP_SHIFT)) & DMA_TCD_TCD12_CSR_EEOP_MASK) 5798 5799 #define DMA_TCD_TCD12_CSR_ESDA_MASK (0x80U) 5800 #define DMA_TCD_TCD12_CSR_ESDA_SHIFT (7U) 5801 #define DMA_TCD_TCD12_CSR_ESDA_WIDTH (1U) 5802 #define DMA_TCD_TCD12_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CSR_ESDA_SHIFT)) & DMA_TCD_TCD12_CSR_ESDA_MASK) 5803 5804 #define DMA_TCD_TCD12_CSR_MAJORLINKCH_MASK (0x1F00U) 5805 #define DMA_TCD_TCD12_CSR_MAJORLINKCH_SHIFT (8U) 5806 #define DMA_TCD_TCD12_CSR_MAJORLINKCH_WIDTH (5U) 5807 #define DMA_TCD_TCD12_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD12_CSR_MAJORLINKCH_MASK) 5808 5809 #define DMA_TCD_TCD12_CSR_BWC_MASK (0xC000U) 5810 #define DMA_TCD_TCD12_CSR_BWC_SHIFT (14U) 5811 #define DMA_TCD_TCD12_CSR_BWC_WIDTH (2U) 5812 #define DMA_TCD_TCD12_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_CSR_BWC_SHIFT)) & DMA_TCD_TCD12_CSR_BWC_MASK) 5813 /*! @} */ 5814 5815 /*! @name TCD12_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 5816 /*! @{ */ 5817 5818 #define DMA_TCD_TCD12_BITER_ELINKNO_BITER_MASK (0x7FFFU) 5819 #define DMA_TCD_TCD12_BITER_ELINKNO_BITER_SHIFT (0U) 5820 #define DMA_TCD_TCD12_BITER_ELINKNO_BITER_WIDTH (15U) 5821 #define DMA_TCD_TCD12_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD12_BITER_ELINKNO_BITER_MASK) 5822 5823 #define DMA_TCD_TCD12_BITER_ELINKNO_ELINK_MASK (0x8000U) 5824 #define DMA_TCD_TCD12_BITER_ELINKNO_ELINK_SHIFT (15U) 5825 #define DMA_TCD_TCD12_BITER_ELINKNO_ELINK_WIDTH (1U) 5826 #define DMA_TCD_TCD12_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD12_BITER_ELINKNO_ELINK_MASK) 5827 /*! @} */ 5828 5829 /*! @name TCD12_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 5830 /*! @{ */ 5831 5832 #define DMA_TCD_TCD12_BITER_ELINKYES_BITER_MASK (0x1FFU) 5833 #define DMA_TCD_TCD12_BITER_ELINKYES_BITER_SHIFT (0U) 5834 #define DMA_TCD_TCD12_BITER_ELINKYES_BITER_WIDTH (9U) 5835 #define DMA_TCD_TCD12_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD12_BITER_ELINKYES_BITER_MASK) 5836 5837 #define DMA_TCD_TCD12_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 5838 #define DMA_TCD_TCD12_BITER_ELINKYES_LINKCH_SHIFT (9U) 5839 #define DMA_TCD_TCD12_BITER_ELINKYES_LINKCH_WIDTH (5U) 5840 #define DMA_TCD_TCD12_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD12_BITER_ELINKYES_LINKCH_MASK) 5841 5842 #define DMA_TCD_TCD12_BITER_ELINKYES_ELINK_MASK (0x8000U) 5843 #define DMA_TCD_TCD12_BITER_ELINKYES_ELINK_SHIFT (15U) 5844 #define DMA_TCD_TCD12_BITER_ELINKYES_ELINK_WIDTH (1U) 5845 #define DMA_TCD_TCD12_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD12_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD12_BITER_ELINKYES_ELINK_MASK) 5846 /*! @} */ 5847 5848 /*! @name CH13_CSR - Channel Control and Status */ 5849 /*! @{ */ 5850 5851 #define DMA_TCD_CH13_CSR_ERQ_MASK (0x1U) 5852 #define DMA_TCD_CH13_CSR_ERQ_SHIFT (0U) 5853 #define DMA_TCD_CH13_CSR_ERQ_WIDTH (1U) 5854 #define DMA_TCD_CH13_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_CSR_ERQ_SHIFT)) & DMA_TCD_CH13_CSR_ERQ_MASK) 5855 5856 #define DMA_TCD_CH13_CSR_EARQ_MASK (0x2U) 5857 #define DMA_TCD_CH13_CSR_EARQ_SHIFT (1U) 5858 #define DMA_TCD_CH13_CSR_EARQ_WIDTH (1U) 5859 #define DMA_TCD_CH13_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_CSR_EARQ_SHIFT)) & DMA_TCD_CH13_CSR_EARQ_MASK) 5860 5861 #define DMA_TCD_CH13_CSR_EEI_MASK (0x4U) 5862 #define DMA_TCD_CH13_CSR_EEI_SHIFT (2U) 5863 #define DMA_TCD_CH13_CSR_EEI_WIDTH (1U) 5864 #define DMA_TCD_CH13_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_CSR_EEI_SHIFT)) & DMA_TCD_CH13_CSR_EEI_MASK) 5865 5866 #define DMA_TCD_CH13_CSR_EBW_MASK (0x8U) 5867 #define DMA_TCD_CH13_CSR_EBW_SHIFT (3U) 5868 #define DMA_TCD_CH13_CSR_EBW_WIDTH (1U) 5869 #define DMA_TCD_CH13_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_CSR_EBW_SHIFT)) & DMA_TCD_CH13_CSR_EBW_MASK) 5870 5871 #define DMA_TCD_CH13_CSR_DONE_MASK (0x40000000U) 5872 #define DMA_TCD_CH13_CSR_DONE_SHIFT (30U) 5873 #define DMA_TCD_CH13_CSR_DONE_WIDTH (1U) 5874 #define DMA_TCD_CH13_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_CSR_DONE_SHIFT)) & DMA_TCD_CH13_CSR_DONE_MASK) 5875 5876 #define DMA_TCD_CH13_CSR_ACTIVE_MASK (0x80000000U) 5877 #define DMA_TCD_CH13_CSR_ACTIVE_SHIFT (31U) 5878 #define DMA_TCD_CH13_CSR_ACTIVE_WIDTH (1U) 5879 #define DMA_TCD_CH13_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH13_CSR_ACTIVE_MASK) 5880 /*! @} */ 5881 5882 /*! @name CH13_ES - Channel Error Status */ 5883 /*! @{ */ 5884 5885 #define DMA_TCD_CH13_ES_DBE_MASK (0x1U) 5886 #define DMA_TCD_CH13_ES_DBE_SHIFT (0U) 5887 #define DMA_TCD_CH13_ES_DBE_WIDTH (1U) 5888 #define DMA_TCD_CH13_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_ES_DBE_SHIFT)) & DMA_TCD_CH13_ES_DBE_MASK) 5889 5890 #define DMA_TCD_CH13_ES_SBE_MASK (0x2U) 5891 #define DMA_TCD_CH13_ES_SBE_SHIFT (1U) 5892 #define DMA_TCD_CH13_ES_SBE_WIDTH (1U) 5893 #define DMA_TCD_CH13_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_ES_SBE_SHIFT)) & DMA_TCD_CH13_ES_SBE_MASK) 5894 5895 #define DMA_TCD_CH13_ES_SGE_MASK (0x4U) 5896 #define DMA_TCD_CH13_ES_SGE_SHIFT (2U) 5897 #define DMA_TCD_CH13_ES_SGE_WIDTH (1U) 5898 #define DMA_TCD_CH13_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_ES_SGE_SHIFT)) & DMA_TCD_CH13_ES_SGE_MASK) 5899 5900 #define DMA_TCD_CH13_ES_NCE_MASK (0x8U) 5901 #define DMA_TCD_CH13_ES_NCE_SHIFT (3U) 5902 #define DMA_TCD_CH13_ES_NCE_WIDTH (1U) 5903 #define DMA_TCD_CH13_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_ES_NCE_SHIFT)) & DMA_TCD_CH13_ES_NCE_MASK) 5904 5905 #define DMA_TCD_CH13_ES_DOE_MASK (0x10U) 5906 #define DMA_TCD_CH13_ES_DOE_SHIFT (4U) 5907 #define DMA_TCD_CH13_ES_DOE_WIDTH (1U) 5908 #define DMA_TCD_CH13_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_ES_DOE_SHIFT)) & DMA_TCD_CH13_ES_DOE_MASK) 5909 5910 #define DMA_TCD_CH13_ES_DAE_MASK (0x20U) 5911 #define DMA_TCD_CH13_ES_DAE_SHIFT (5U) 5912 #define DMA_TCD_CH13_ES_DAE_WIDTH (1U) 5913 #define DMA_TCD_CH13_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_ES_DAE_SHIFT)) & DMA_TCD_CH13_ES_DAE_MASK) 5914 5915 #define DMA_TCD_CH13_ES_SOE_MASK (0x40U) 5916 #define DMA_TCD_CH13_ES_SOE_SHIFT (6U) 5917 #define DMA_TCD_CH13_ES_SOE_WIDTH (1U) 5918 #define DMA_TCD_CH13_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_ES_SOE_SHIFT)) & DMA_TCD_CH13_ES_SOE_MASK) 5919 5920 #define DMA_TCD_CH13_ES_SAE_MASK (0x80U) 5921 #define DMA_TCD_CH13_ES_SAE_SHIFT (7U) 5922 #define DMA_TCD_CH13_ES_SAE_WIDTH (1U) 5923 #define DMA_TCD_CH13_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_ES_SAE_SHIFT)) & DMA_TCD_CH13_ES_SAE_MASK) 5924 5925 #define DMA_TCD_CH13_ES_ERR_MASK (0x80000000U) 5926 #define DMA_TCD_CH13_ES_ERR_SHIFT (31U) 5927 #define DMA_TCD_CH13_ES_ERR_WIDTH (1U) 5928 #define DMA_TCD_CH13_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_ES_ERR_SHIFT)) & DMA_TCD_CH13_ES_ERR_MASK) 5929 /*! @} */ 5930 5931 /*! @name CH13_INT - Channel Interrupt Status */ 5932 /*! @{ */ 5933 5934 #define DMA_TCD_CH13_INT_INT_MASK (0x1U) 5935 #define DMA_TCD_CH13_INT_INT_SHIFT (0U) 5936 #define DMA_TCD_CH13_INT_INT_WIDTH (1U) 5937 #define DMA_TCD_CH13_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_INT_INT_SHIFT)) & DMA_TCD_CH13_INT_INT_MASK) 5938 /*! @} */ 5939 5940 /*! @name CH13_SBR - Channel System Bus */ 5941 /*! @{ */ 5942 5943 #define DMA_TCD_CH13_SBR_MID_MASK (0xFU) 5944 #define DMA_TCD_CH13_SBR_MID_SHIFT (0U) 5945 #define DMA_TCD_CH13_SBR_MID_WIDTH (4U) 5946 #define DMA_TCD_CH13_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_SBR_MID_SHIFT)) & DMA_TCD_CH13_SBR_MID_MASK) 5947 5948 #define DMA_TCD_CH13_SBR_PAL_MASK (0x8000U) 5949 #define DMA_TCD_CH13_SBR_PAL_SHIFT (15U) 5950 #define DMA_TCD_CH13_SBR_PAL_WIDTH (1U) 5951 #define DMA_TCD_CH13_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_SBR_PAL_SHIFT)) & DMA_TCD_CH13_SBR_PAL_MASK) 5952 5953 #define DMA_TCD_CH13_SBR_EMI_MASK (0x10000U) 5954 #define DMA_TCD_CH13_SBR_EMI_SHIFT (16U) 5955 #define DMA_TCD_CH13_SBR_EMI_WIDTH (1U) 5956 #define DMA_TCD_CH13_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_SBR_EMI_SHIFT)) & DMA_TCD_CH13_SBR_EMI_MASK) 5957 5958 #define DMA_TCD_CH13_SBR_ATTR_MASK (0xE0000U) 5959 #define DMA_TCD_CH13_SBR_ATTR_SHIFT (17U) 5960 #define DMA_TCD_CH13_SBR_ATTR_WIDTH (3U) 5961 #define DMA_TCD_CH13_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_SBR_ATTR_SHIFT)) & DMA_TCD_CH13_SBR_ATTR_MASK) 5962 /*! @} */ 5963 5964 /*! @name CH13_PRI - Channel Priority */ 5965 /*! @{ */ 5966 5967 #define DMA_TCD_CH13_PRI_APL_MASK (0x7U) 5968 #define DMA_TCD_CH13_PRI_APL_SHIFT (0U) 5969 #define DMA_TCD_CH13_PRI_APL_WIDTH (3U) 5970 #define DMA_TCD_CH13_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_PRI_APL_SHIFT)) & DMA_TCD_CH13_PRI_APL_MASK) 5971 5972 #define DMA_TCD_CH13_PRI_DPA_MASK (0x40000000U) 5973 #define DMA_TCD_CH13_PRI_DPA_SHIFT (30U) 5974 #define DMA_TCD_CH13_PRI_DPA_WIDTH (1U) 5975 #define DMA_TCD_CH13_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_PRI_DPA_SHIFT)) & DMA_TCD_CH13_PRI_DPA_MASK) 5976 5977 #define DMA_TCD_CH13_PRI_ECP_MASK (0x80000000U) 5978 #define DMA_TCD_CH13_PRI_ECP_SHIFT (31U) 5979 #define DMA_TCD_CH13_PRI_ECP_WIDTH (1U) 5980 #define DMA_TCD_CH13_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH13_PRI_ECP_SHIFT)) & DMA_TCD_CH13_PRI_ECP_MASK) 5981 /*! @} */ 5982 5983 /*! @name TCD13_SADDR - TCD Source Address */ 5984 /*! @{ */ 5985 5986 #define DMA_TCD_TCD13_SADDR_SADDR_MASK (0xFFFFFFFFU) 5987 #define DMA_TCD_TCD13_SADDR_SADDR_SHIFT (0U) 5988 #define DMA_TCD_TCD13_SADDR_SADDR_WIDTH (32U) 5989 #define DMA_TCD_TCD13_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD13_SADDR_SADDR_MASK) 5990 /*! @} */ 5991 5992 /*! @name TCD13_SOFF - TCD Signed Source Address Offset */ 5993 /*! @{ */ 5994 5995 #define DMA_TCD_TCD13_SOFF_SOFF_MASK (0xFFFFU) 5996 #define DMA_TCD_TCD13_SOFF_SOFF_SHIFT (0U) 5997 #define DMA_TCD_TCD13_SOFF_SOFF_WIDTH (16U) 5998 #define DMA_TCD_TCD13_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD13_SOFF_SOFF_MASK) 5999 /*! @} */ 6000 6001 /*! @name TCD13_ATTR - TCD Transfer Attributes */ 6002 /*! @{ */ 6003 6004 #define DMA_TCD_TCD13_ATTR_DSIZE_MASK (0x7U) 6005 #define DMA_TCD_TCD13_ATTR_DSIZE_SHIFT (0U) 6006 #define DMA_TCD_TCD13_ATTR_DSIZE_WIDTH (3U) 6007 #define DMA_TCD_TCD13_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD13_ATTR_DSIZE_MASK) 6008 6009 #define DMA_TCD_TCD13_ATTR_DMOD_MASK (0xF8U) 6010 #define DMA_TCD_TCD13_ATTR_DMOD_SHIFT (3U) 6011 #define DMA_TCD_TCD13_ATTR_DMOD_WIDTH (5U) 6012 #define DMA_TCD_TCD13_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD13_ATTR_DMOD_MASK) 6013 6014 #define DMA_TCD_TCD13_ATTR_SSIZE_MASK (0x700U) 6015 #define DMA_TCD_TCD13_ATTR_SSIZE_SHIFT (8U) 6016 #define DMA_TCD_TCD13_ATTR_SSIZE_WIDTH (3U) 6017 #define DMA_TCD_TCD13_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD13_ATTR_SSIZE_MASK) 6018 6019 #define DMA_TCD_TCD13_ATTR_SMOD_MASK (0xF800U) 6020 #define DMA_TCD_TCD13_ATTR_SMOD_SHIFT (11U) 6021 #define DMA_TCD_TCD13_ATTR_SMOD_WIDTH (5U) 6022 #define DMA_TCD_TCD13_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD13_ATTR_SMOD_MASK) 6023 /*! @} */ 6024 6025 /*! @name TCD13_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 6026 /*! @{ */ 6027 6028 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 6029 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 6030 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 6031 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD13_NBYTES_MLOFFNO_NBYTES_MASK) 6032 6033 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 6034 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 6035 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 6036 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD13_NBYTES_MLOFFNO_DMLOE_MASK) 6037 6038 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 6039 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 6040 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 6041 #define DMA_TCD_TCD13_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD13_NBYTES_MLOFFNO_SMLOE_MASK) 6042 /*! @} */ 6043 6044 /*! @name TCD13_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 6045 /*! @{ */ 6046 6047 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 6048 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 6049 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 6050 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD13_NBYTES_MLOFFYES_NBYTES_MASK) 6051 6052 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 6053 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 6054 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 6055 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD13_NBYTES_MLOFFYES_MLOFF_MASK) 6056 6057 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 6058 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 6059 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 6060 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD13_NBYTES_MLOFFYES_DMLOE_MASK) 6061 6062 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 6063 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 6064 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 6065 #define DMA_TCD_TCD13_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD13_NBYTES_MLOFFYES_SMLOE_MASK) 6066 /*! @} */ 6067 6068 /*! @name TCD13_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 6069 /*! @{ */ 6070 6071 #define DMA_TCD_TCD13_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 6072 #define DMA_TCD_TCD13_SLAST_SDA_SLAST_SDA_SHIFT (0U) 6073 #define DMA_TCD_TCD13_SLAST_SDA_SLAST_SDA_WIDTH (32U) 6074 #define DMA_TCD_TCD13_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD13_SLAST_SDA_SLAST_SDA_MASK) 6075 /*! @} */ 6076 6077 /*! @name TCD13_DADDR - TCD Destination Address */ 6078 /*! @{ */ 6079 6080 #define DMA_TCD_TCD13_DADDR_DADDR_MASK (0xFFFFFFFFU) 6081 #define DMA_TCD_TCD13_DADDR_DADDR_SHIFT (0U) 6082 #define DMA_TCD_TCD13_DADDR_DADDR_WIDTH (32U) 6083 #define DMA_TCD_TCD13_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD13_DADDR_DADDR_MASK) 6084 /*! @} */ 6085 6086 /*! @name TCD13_DOFF - TCD Signed Destination Address Offset */ 6087 /*! @{ */ 6088 6089 #define DMA_TCD_TCD13_DOFF_DOFF_MASK (0xFFFFU) 6090 #define DMA_TCD_TCD13_DOFF_DOFF_SHIFT (0U) 6091 #define DMA_TCD_TCD13_DOFF_DOFF_WIDTH (16U) 6092 #define DMA_TCD_TCD13_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD13_DOFF_DOFF_MASK) 6093 /*! @} */ 6094 6095 /*! @name TCD13_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 6096 /*! @{ */ 6097 6098 #define DMA_TCD_TCD13_CITER_ELINKNO_CITER_MASK (0x7FFFU) 6099 #define DMA_TCD_TCD13_CITER_ELINKNO_CITER_SHIFT (0U) 6100 #define DMA_TCD_TCD13_CITER_ELINKNO_CITER_WIDTH (15U) 6101 #define DMA_TCD_TCD13_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD13_CITER_ELINKNO_CITER_MASK) 6102 6103 #define DMA_TCD_TCD13_CITER_ELINKNO_ELINK_MASK (0x8000U) 6104 #define DMA_TCD_TCD13_CITER_ELINKNO_ELINK_SHIFT (15U) 6105 #define DMA_TCD_TCD13_CITER_ELINKNO_ELINK_WIDTH (1U) 6106 #define DMA_TCD_TCD13_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD13_CITER_ELINKNO_ELINK_MASK) 6107 /*! @} */ 6108 6109 /*! @name TCD13_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 6110 /*! @{ */ 6111 6112 #define DMA_TCD_TCD13_CITER_ELINKYES_CITER_MASK (0x1FFU) 6113 #define DMA_TCD_TCD13_CITER_ELINKYES_CITER_SHIFT (0U) 6114 #define DMA_TCD_TCD13_CITER_ELINKYES_CITER_WIDTH (9U) 6115 #define DMA_TCD_TCD13_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD13_CITER_ELINKYES_CITER_MASK) 6116 6117 #define DMA_TCD_TCD13_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 6118 #define DMA_TCD_TCD13_CITER_ELINKYES_LINKCH_SHIFT (9U) 6119 #define DMA_TCD_TCD13_CITER_ELINKYES_LINKCH_WIDTH (5U) 6120 #define DMA_TCD_TCD13_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD13_CITER_ELINKYES_LINKCH_MASK) 6121 6122 #define DMA_TCD_TCD13_CITER_ELINKYES_ELINK_MASK (0x8000U) 6123 #define DMA_TCD_TCD13_CITER_ELINKYES_ELINK_SHIFT (15U) 6124 #define DMA_TCD_TCD13_CITER_ELINKYES_ELINK_WIDTH (1U) 6125 #define DMA_TCD_TCD13_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD13_CITER_ELINKYES_ELINK_MASK) 6126 /*! @} */ 6127 6128 /*! @name TCD13_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 6129 /*! @{ */ 6130 6131 #define DMA_TCD_TCD13_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 6132 #define DMA_TCD_TCD13_DLAST_SGA_DLAST_SGA_SHIFT (0U) 6133 #define DMA_TCD_TCD13_DLAST_SGA_DLAST_SGA_WIDTH (32U) 6134 #define DMA_TCD_TCD13_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD13_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD13_DLAST_SGA_DLAST_SGA_MASK) 6135 /*! @} */ 6136 6137 /*! @name TCD13_CSR - TCD Control and Status */ 6138 /*! @{ */ 6139 6140 #define DMA_TCD_TCD13_CSR_START_MASK (0x1U) 6141 #define DMA_TCD_TCD13_CSR_START_SHIFT (0U) 6142 #define DMA_TCD_TCD13_CSR_START_WIDTH (1U) 6143 #define DMA_TCD_TCD13_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CSR_START_SHIFT)) & DMA_TCD_TCD13_CSR_START_MASK) 6144 6145 #define DMA_TCD_TCD13_CSR_INTMAJOR_MASK (0x2U) 6146 #define DMA_TCD_TCD13_CSR_INTMAJOR_SHIFT (1U) 6147 #define DMA_TCD_TCD13_CSR_INTMAJOR_WIDTH (1U) 6148 #define DMA_TCD_TCD13_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD13_CSR_INTMAJOR_MASK) 6149 6150 #define DMA_TCD_TCD13_CSR_INTHALF_MASK (0x4U) 6151 #define DMA_TCD_TCD13_CSR_INTHALF_SHIFT (2U) 6152 #define DMA_TCD_TCD13_CSR_INTHALF_WIDTH (1U) 6153 #define DMA_TCD_TCD13_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD13_CSR_INTHALF_MASK) 6154 6155 #define DMA_TCD_TCD13_CSR_DREQ_MASK (0x8U) 6156 #define DMA_TCD_TCD13_CSR_DREQ_SHIFT (3U) 6157 #define DMA_TCD_TCD13_CSR_DREQ_WIDTH (1U) 6158 #define DMA_TCD_TCD13_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CSR_DREQ_SHIFT)) & DMA_TCD_TCD13_CSR_DREQ_MASK) 6159 6160 #define DMA_TCD_TCD13_CSR_ESG_MASK (0x10U) 6161 #define DMA_TCD_TCD13_CSR_ESG_SHIFT (4U) 6162 #define DMA_TCD_TCD13_CSR_ESG_WIDTH (1U) 6163 #define DMA_TCD_TCD13_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CSR_ESG_SHIFT)) & DMA_TCD_TCD13_CSR_ESG_MASK) 6164 6165 #define DMA_TCD_TCD13_CSR_MAJORELINK_MASK (0x20U) 6166 #define DMA_TCD_TCD13_CSR_MAJORELINK_SHIFT (5U) 6167 #define DMA_TCD_TCD13_CSR_MAJORELINK_WIDTH (1U) 6168 #define DMA_TCD_TCD13_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD13_CSR_MAJORELINK_MASK) 6169 6170 #define DMA_TCD_TCD13_CSR_EEOP_MASK (0x40U) 6171 #define DMA_TCD_TCD13_CSR_EEOP_SHIFT (6U) 6172 #define DMA_TCD_TCD13_CSR_EEOP_WIDTH (1U) 6173 #define DMA_TCD_TCD13_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CSR_EEOP_SHIFT)) & DMA_TCD_TCD13_CSR_EEOP_MASK) 6174 6175 #define DMA_TCD_TCD13_CSR_ESDA_MASK (0x80U) 6176 #define DMA_TCD_TCD13_CSR_ESDA_SHIFT (7U) 6177 #define DMA_TCD_TCD13_CSR_ESDA_WIDTH (1U) 6178 #define DMA_TCD_TCD13_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CSR_ESDA_SHIFT)) & DMA_TCD_TCD13_CSR_ESDA_MASK) 6179 6180 #define DMA_TCD_TCD13_CSR_MAJORLINKCH_MASK (0x1F00U) 6181 #define DMA_TCD_TCD13_CSR_MAJORLINKCH_SHIFT (8U) 6182 #define DMA_TCD_TCD13_CSR_MAJORLINKCH_WIDTH (5U) 6183 #define DMA_TCD_TCD13_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD13_CSR_MAJORLINKCH_MASK) 6184 6185 #define DMA_TCD_TCD13_CSR_BWC_MASK (0xC000U) 6186 #define DMA_TCD_TCD13_CSR_BWC_SHIFT (14U) 6187 #define DMA_TCD_TCD13_CSR_BWC_WIDTH (2U) 6188 #define DMA_TCD_TCD13_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_CSR_BWC_SHIFT)) & DMA_TCD_TCD13_CSR_BWC_MASK) 6189 /*! @} */ 6190 6191 /*! @name TCD13_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 6192 /*! @{ */ 6193 6194 #define DMA_TCD_TCD13_BITER_ELINKNO_BITER_MASK (0x7FFFU) 6195 #define DMA_TCD_TCD13_BITER_ELINKNO_BITER_SHIFT (0U) 6196 #define DMA_TCD_TCD13_BITER_ELINKNO_BITER_WIDTH (15U) 6197 #define DMA_TCD_TCD13_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD13_BITER_ELINKNO_BITER_MASK) 6198 6199 #define DMA_TCD_TCD13_BITER_ELINKNO_ELINK_MASK (0x8000U) 6200 #define DMA_TCD_TCD13_BITER_ELINKNO_ELINK_SHIFT (15U) 6201 #define DMA_TCD_TCD13_BITER_ELINKNO_ELINK_WIDTH (1U) 6202 #define DMA_TCD_TCD13_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD13_BITER_ELINKNO_ELINK_MASK) 6203 /*! @} */ 6204 6205 /*! @name TCD13_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 6206 /*! @{ */ 6207 6208 #define DMA_TCD_TCD13_BITER_ELINKYES_BITER_MASK (0x1FFU) 6209 #define DMA_TCD_TCD13_BITER_ELINKYES_BITER_SHIFT (0U) 6210 #define DMA_TCD_TCD13_BITER_ELINKYES_BITER_WIDTH (9U) 6211 #define DMA_TCD_TCD13_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD13_BITER_ELINKYES_BITER_MASK) 6212 6213 #define DMA_TCD_TCD13_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 6214 #define DMA_TCD_TCD13_BITER_ELINKYES_LINKCH_SHIFT (9U) 6215 #define DMA_TCD_TCD13_BITER_ELINKYES_LINKCH_WIDTH (5U) 6216 #define DMA_TCD_TCD13_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD13_BITER_ELINKYES_LINKCH_MASK) 6217 6218 #define DMA_TCD_TCD13_BITER_ELINKYES_ELINK_MASK (0x8000U) 6219 #define DMA_TCD_TCD13_BITER_ELINKYES_ELINK_SHIFT (15U) 6220 #define DMA_TCD_TCD13_BITER_ELINKYES_ELINK_WIDTH (1U) 6221 #define DMA_TCD_TCD13_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD13_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD13_BITER_ELINKYES_ELINK_MASK) 6222 /*! @} */ 6223 6224 /*! @name CH14_CSR - Channel Control and Status */ 6225 /*! @{ */ 6226 6227 #define DMA_TCD_CH14_CSR_ERQ_MASK (0x1U) 6228 #define DMA_TCD_CH14_CSR_ERQ_SHIFT (0U) 6229 #define DMA_TCD_CH14_CSR_ERQ_WIDTH (1U) 6230 #define DMA_TCD_CH14_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_CSR_ERQ_SHIFT)) & DMA_TCD_CH14_CSR_ERQ_MASK) 6231 6232 #define DMA_TCD_CH14_CSR_EARQ_MASK (0x2U) 6233 #define DMA_TCD_CH14_CSR_EARQ_SHIFT (1U) 6234 #define DMA_TCD_CH14_CSR_EARQ_WIDTH (1U) 6235 #define DMA_TCD_CH14_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_CSR_EARQ_SHIFT)) & DMA_TCD_CH14_CSR_EARQ_MASK) 6236 6237 #define DMA_TCD_CH14_CSR_EEI_MASK (0x4U) 6238 #define DMA_TCD_CH14_CSR_EEI_SHIFT (2U) 6239 #define DMA_TCD_CH14_CSR_EEI_WIDTH (1U) 6240 #define DMA_TCD_CH14_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_CSR_EEI_SHIFT)) & DMA_TCD_CH14_CSR_EEI_MASK) 6241 6242 #define DMA_TCD_CH14_CSR_EBW_MASK (0x8U) 6243 #define DMA_TCD_CH14_CSR_EBW_SHIFT (3U) 6244 #define DMA_TCD_CH14_CSR_EBW_WIDTH (1U) 6245 #define DMA_TCD_CH14_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_CSR_EBW_SHIFT)) & DMA_TCD_CH14_CSR_EBW_MASK) 6246 6247 #define DMA_TCD_CH14_CSR_DONE_MASK (0x40000000U) 6248 #define DMA_TCD_CH14_CSR_DONE_SHIFT (30U) 6249 #define DMA_TCD_CH14_CSR_DONE_WIDTH (1U) 6250 #define DMA_TCD_CH14_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_CSR_DONE_SHIFT)) & DMA_TCD_CH14_CSR_DONE_MASK) 6251 6252 #define DMA_TCD_CH14_CSR_ACTIVE_MASK (0x80000000U) 6253 #define DMA_TCD_CH14_CSR_ACTIVE_SHIFT (31U) 6254 #define DMA_TCD_CH14_CSR_ACTIVE_WIDTH (1U) 6255 #define DMA_TCD_CH14_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH14_CSR_ACTIVE_MASK) 6256 /*! @} */ 6257 6258 /*! @name CH14_ES - Channel Error Status */ 6259 /*! @{ */ 6260 6261 #define DMA_TCD_CH14_ES_DBE_MASK (0x1U) 6262 #define DMA_TCD_CH14_ES_DBE_SHIFT (0U) 6263 #define DMA_TCD_CH14_ES_DBE_WIDTH (1U) 6264 #define DMA_TCD_CH14_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_ES_DBE_SHIFT)) & DMA_TCD_CH14_ES_DBE_MASK) 6265 6266 #define DMA_TCD_CH14_ES_SBE_MASK (0x2U) 6267 #define DMA_TCD_CH14_ES_SBE_SHIFT (1U) 6268 #define DMA_TCD_CH14_ES_SBE_WIDTH (1U) 6269 #define DMA_TCD_CH14_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_ES_SBE_SHIFT)) & DMA_TCD_CH14_ES_SBE_MASK) 6270 6271 #define DMA_TCD_CH14_ES_SGE_MASK (0x4U) 6272 #define DMA_TCD_CH14_ES_SGE_SHIFT (2U) 6273 #define DMA_TCD_CH14_ES_SGE_WIDTH (1U) 6274 #define DMA_TCD_CH14_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_ES_SGE_SHIFT)) & DMA_TCD_CH14_ES_SGE_MASK) 6275 6276 #define DMA_TCD_CH14_ES_NCE_MASK (0x8U) 6277 #define DMA_TCD_CH14_ES_NCE_SHIFT (3U) 6278 #define DMA_TCD_CH14_ES_NCE_WIDTH (1U) 6279 #define DMA_TCD_CH14_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_ES_NCE_SHIFT)) & DMA_TCD_CH14_ES_NCE_MASK) 6280 6281 #define DMA_TCD_CH14_ES_DOE_MASK (0x10U) 6282 #define DMA_TCD_CH14_ES_DOE_SHIFT (4U) 6283 #define DMA_TCD_CH14_ES_DOE_WIDTH (1U) 6284 #define DMA_TCD_CH14_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_ES_DOE_SHIFT)) & DMA_TCD_CH14_ES_DOE_MASK) 6285 6286 #define DMA_TCD_CH14_ES_DAE_MASK (0x20U) 6287 #define DMA_TCD_CH14_ES_DAE_SHIFT (5U) 6288 #define DMA_TCD_CH14_ES_DAE_WIDTH (1U) 6289 #define DMA_TCD_CH14_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_ES_DAE_SHIFT)) & DMA_TCD_CH14_ES_DAE_MASK) 6290 6291 #define DMA_TCD_CH14_ES_SOE_MASK (0x40U) 6292 #define DMA_TCD_CH14_ES_SOE_SHIFT (6U) 6293 #define DMA_TCD_CH14_ES_SOE_WIDTH (1U) 6294 #define DMA_TCD_CH14_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_ES_SOE_SHIFT)) & DMA_TCD_CH14_ES_SOE_MASK) 6295 6296 #define DMA_TCD_CH14_ES_SAE_MASK (0x80U) 6297 #define DMA_TCD_CH14_ES_SAE_SHIFT (7U) 6298 #define DMA_TCD_CH14_ES_SAE_WIDTH (1U) 6299 #define DMA_TCD_CH14_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_ES_SAE_SHIFT)) & DMA_TCD_CH14_ES_SAE_MASK) 6300 6301 #define DMA_TCD_CH14_ES_ERR_MASK (0x80000000U) 6302 #define DMA_TCD_CH14_ES_ERR_SHIFT (31U) 6303 #define DMA_TCD_CH14_ES_ERR_WIDTH (1U) 6304 #define DMA_TCD_CH14_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_ES_ERR_SHIFT)) & DMA_TCD_CH14_ES_ERR_MASK) 6305 /*! @} */ 6306 6307 /*! @name CH14_INT - Channel Interrupt Status */ 6308 /*! @{ */ 6309 6310 #define DMA_TCD_CH14_INT_INT_MASK (0x1U) 6311 #define DMA_TCD_CH14_INT_INT_SHIFT (0U) 6312 #define DMA_TCD_CH14_INT_INT_WIDTH (1U) 6313 #define DMA_TCD_CH14_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_INT_INT_SHIFT)) & DMA_TCD_CH14_INT_INT_MASK) 6314 /*! @} */ 6315 6316 /*! @name CH14_SBR - Channel System Bus */ 6317 /*! @{ */ 6318 6319 #define DMA_TCD_CH14_SBR_MID_MASK (0xFU) 6320 #define DMA_TCD_CH14_SBR_MID_SHIFT (0U) 6321 #define DMA_TCD_CH14_SBR_MID_WIDTH (4U) 6322 #define DMA_TCD_CH14_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_SBR_MID_SHIFT)) & DMA_TCD_CH14_SBR_MID_MASK) 6323 6324 #define DMA_TCD_CH14_SBR_PAL_MASK (0x8000U) 6325 #define DMA_TCD_CH14_SBR_PAL_SHIFT (15U) 6326 #define DMA_TCD_CH14_SBR_PAL_WIDTH (1U) 6327 #define DMA_TCD_CH14_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_SBR_PAL_SHIFT)) & DMA_TCD_CH14_SBR_PAL_MASK) 6328 6329 #define DMA_TCD_CH14_SBR_EMI_MASK (0x10000U) 6330 #define DMA_TCD_CH14_SBR_EMI_SHIFT (16U) 6331 #define DMA_TCD_CH14_SBR_EMI_WIDTH (1U) 6332 #define DMA_TCD_CH14_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_SBR_EMI_SHIFT)) & DMA_TCD_CH14_SBR_EMI_MASK) 6333 6334 #define DMA_TCD_CH14_SBR_ATTR_MASK (0xE0000U) 6335 #define DMA_TCD_CH14_SBR_ATTR_SHIFT (17U) 6336 #define DMA_TCD_CH14_SBR_ATTR_WIDTH (3U) 6337 #define DMA_TCD_CH14_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_SBR_ATTR_SHIFT)) & DMA_TCD_CH14_SBR_ATTR_MASK) 6338 /*! @} */ 6339 6340 /*! @name CH14_PRI - Channel Priority */ 6341 /*! @{ */ 6342 6343 #define DMA_TCD_CH14_PRI_APL_MASK (0x7U) 6344 #define DMA_TCD_CH14_PRI_APL_SHIFT (0U) 6345 #define DMA_TCD_CH14_PRI_APL_WIDTH (3U) 6346 #define DMA_TCD_CH14_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_PRI_APL_SHIFT)) & DMA_TCD_CH14_PRI_APL_MASK) 6347 6348 #define DMA_TCD_CH14_PRI_DPA_MASK (0x40000000U) 6349 #define DMA_TCD_CH14_PRI_DPA_SHIFT (30U) 6350 #define DMA_TCD_CH14_PRI_DPA_WIDTH (1U) 6351 #define DMA_TCD_CH14_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_PRI_DPA_SHIFT)) & DMA_TCD_CH14_PRI_DPA_MASK) 6352 6353 #define DMA_TCD_CH14_PRI_ECP_MASK (0x80000000U) 6354 #define DMA_TCD_CH14_PRI_ECP_SHIFT (31U) 6355 #define DMA_TCD_CH14_PRI_ECP_WIDTH (1U) 6356 #define DMA_TCD_CH14_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH14_PRI_ECP_SHIFT)) & DMA_TCD_CH14_PRI_ECP_MASK) 6357 /*! @} */ 6358 6359 /*! @name TCD14_SADDR - TCD Source Address */ 6360 /*! @{ */ 6361 6362 #define DMA_TCD_TCD14_SADDR_SADDR_MASK (0xFFFFFFFFU) 6363 #define DMA_TCD_TCD14_SADDR_SADDR_SHIFT (0U) 6364 #define DMA_TCD_TCD14_SADDR_SADDR_WIDTH (32U) 6365 #define DMA_TCD_TCD14_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD14_SADDR_SADDR_MASK) 6366 /*! @} */ 6367 6368 /*! @name TCD14_SOFF - TCD Signed Source Address Offset */ 6369 /*! @{ */ 6370 6371 #define DMA_TCD_TCD14_SOFF_SOFF_MASK (0xFFFFU) 6372 #define DMA_TCD_TCD14_SOFF_SOFF_SHIFT (0U) 6373 #define DMA_TCD_TCD14_SOFF_SOFF_WIDTH (16U) 6374 #define DMA_TCD_TCD14_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD14_SOFF_SOFF_MASK) 6375 /*! @} */ 6376 6377 /*! @name TCD14_ATTR - TCD Transfer Attributes */ 6378 /*! @{ */ 6379 6380 #define DMA_TCD_TCD14_ATTR_DSIZE_MASK (0x7U) 6381 #define DMA_TCD_TCD14_ATTR_DSIZE_SHIFT (0U) 6382 #define DMA_TCD_TCD14_ATTR_DSIZE_WIDTH (3U) 6383 #define DMA_TCD_TCD14_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD14_ATTR_DSIZE_MASK) 6384 6385 #define DMA_TCD_TCD14_ATTR_DMOD_MASK (0xF8U) 6386 #define DMA_TCD_TCD14_ATTR_DMOD_SHIFT (3U) 6387 #define DMA_TCD_TCD14_ATTR_DMOD_WIDTH (5U) 6388 #define DMA_TCD_TCD14_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD14_ATTR_DMOD_MASK) 6389 6390 #define DMA_TCD_TCD14_ATTR_SSIZE_MASK (0x700U) 6391 #define DMA_TCD_TCD14_ATTR_SSIZE_SHIFT (8U) 6392 #define DMA_TCD_TCD14_ATTR_SSIZE_WIDTH (3U) 6393 #define DMA_TCD_TCD14_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD14_ATTR_SSIZE_MASK) 6394 6395 #define DMA_TCD_TCD14_ATTR_SMOD_MASK (0xF800U) 6396 #define DMA_TCD_TCD14_ATTR_SMOD_SHIFT (11U) 6397 #define DMA_TCD_TCD14_ATTR_SMOD_WIDTH (5U) 6398 #define DMA_TCD_TCD14_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD14_ATTR_SMOD_MASK) 6399 /*! @} */ 6400 6401 /*! @name TCD14_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 6402 /*! @{ */ 6403 6404 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 6405 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 6406 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 6407 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD14_NBYTES_MLOFFNO_NBYTES_MASK) 6408 6409 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 6410 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 6411 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 6412 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD14_NBYTES_MLOFFNO_DMLOE_MASK) 6413 6414 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 6415 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 6416 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 6417 #define DMA_TCD_TCD14_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD14_NBYTES_MLOFFNO_SMLOE_MASK) 6418 /*! @} */ 6419 6420 /*! @name TCD14_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 6421 /*! @{ */ 6422 6423 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 6424 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 6425 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 6426 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD14_NBYTES_MLOFFYES_NBYTES_MASK) 6427 6428 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 6429 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 6430 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 6431 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD14_NBYTES_MLOFFYES_MLOFF_MASK) 6432 6433 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 6434 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 6435 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 6436 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD14_NBYTES_MLOFFYES_DMLOE_MASK) 6437 6438 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 6439 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 6440 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 6441 #define DMA_TCD_TCD14_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD14_NBYTES_MLOFFYES_SMLOE_MASK) 6442 /*! @} */ 6443 6444 /*! @name TCD14_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 6445 /*! @{ */ 6446 6447 #define DMA_TCD_TCD14_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 6448 #define DMA_TCD_TCD14_SLAST_SDA_SLAST_SDA_SHIFT (0U) 6449 #define DMA_TCD_TCD14_SLAST_SDA_SLAST_SDA_WIDTH (32U) 6450 #define DMA_TCD_TCD14_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD14_SLAST_SDA_SLAST_SDA_MASK) 6451 /*! @} */ 6452 6453 /*! @name TCD14_DADDR - TCD Destination Address */ 6454 /*! @{ */ 6455 6456 #define DMA_TCD_TCD14_DADDR_DADDR_MASK (0xFFFFFFFFU) 6457 #define DMA_TCD_TCD14_DADDR_DADDR_SHIFT (0U) 6458 #define DMA_TCD_TCD14_DADDR_DADDR_WIDTH (32U) 6459 #define DMA_TCD_TCD14_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD14_DADDR_DADDR_MASK) 6460 /*! @} */ 6461 6462 /*! @name TCD14_DOFF - TCD Signed Destination Address Offset */ 6463 /*! @{ */ 6464 6465 #define DMA_TCD_TCD14_DOFF_DOFF_MASK (0xFFFFU) 6466 #define DMA_TCD_TCD14_DOFF_DOFF_SHIFT (0U) 6467 #define DMA_TCD_TCD14_DOFF_DOFF_WIDTH (16U) 6468 #define DMA_TCD_TCD14_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD14_DOFF_DOFF_MASK) 6469 /*! @} */ 6470 6471 /*! @name TCD14_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 6472 /*! @{ */ 6473 6474 #define DMA_TCD_TCD14_CITER_ELINKNO_CITER_MASK (0x7FFFU) 6475 #define DMA_TCD_TCD14_CITER_ELINKNO_CITER_SHIFT (0U) 6476 #define DMA_TCD_TCD14_CITER_ELINKNO_CITER_WIDTH (15U) 6477 #define DMA_TCD_TCD14_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD14_CITER_ELINKNO_CITER_MASK) 6478 6479 #define DMA_TCD_TCD14_CITER_ELINKNO_ELINK_MASK (0x8000U) 6480 #define DMA_TCD_TCD14_CITER_ELINKNO_ELINK_SHIFT (15U) 6481 #define DMA_TCD_TCD14_CITER_ELINKNO_ELINK_WIDTH (1U) 6482 #define DMA_TCD_TCD14_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD14_CITER_ELINKNO_ELINK_MASK) 6483 /*! @} */ 6484 6485 /*! @name TCD14_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 6486 /*! @{ */ 6487 6488 #define DMA_TCD_TCD14_CITER_ELINKYES_CITER_MASK (0x1FFU) 6489 #define DMA_TCD_TCD14_CITER_ELINKYES_CITER_SHIFT (0U) 6490 #define DMA_TCD_TCD14_CITER_ELINKYES_CITER_WIDTH (9U) 6491 #define DMA_TCD_TCD14_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD14_CITER_ELINKYES_CITER_MASK) 6492 6493 #define DMA_TCD_TCD14_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 6494 #define DMA_TCD_TCD14_CITER_ELINKYES_LINKCH_SHIFT (9U) 6495 #define DMA_TCD_TCD14_CITER_ELINKYES_LINKCH_WIDTH (5U) 6496 #define DMA_TCD_TCD14_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD14_CITER_ELINKYES_LINKCH_MASK) 6497 6498 #define DMA_TCD_TCD14_CITER_ELINKYES_ELINK_MASK (0x8000U) 6499 #define DMA_TCD_TCD14_CITER_ELINKYES_ELINK_SHIFT (15U) 6500 #define DMA_TCD_TCD14_CITER_ELINKYES_ELINK_WIDTH (1U) 6501 #define DMA_TCD_TCD14_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD14_CITER_ELINKYES_ELINK_MASK) 6502 /*! @} */ 6503 6504 /*! @name TCD14_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 6505 /*! @{ */ 6506 6507 #define DMA_TCD_TCD14_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 6508 #define DMA_TCD_TCD14_DLAST_SGA_DLAST_SGA_SHIFT (0U) 6509 #define DMA_TCD_TCD14_DLAST_SGA_DLAST_SGA_WIDTH (32U) 6510 #define DMA_TCD_TCD14_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD14_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD14_DLAST_SGA_DLAST_SGA_MASK) 6511 /*! @} */ 6512 6513 /*! @name TCD14_CSR - TCD Control and Status */ 6514 /*! @{ */ 6515 6516 #define DMA_TCD_TCD14_CSR_START_MASK (0x1U) 6517 #define DMA_TCD_TCD14_CSR_START_SHIFT (0U) 6518 #define DMA_TCD_TCD14_CSR_START_WIDTH (1U) 6519 #define DMA_TCD_TCD14_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CSR_START_SHIFT)) & DMA_TCD_TCD14_CSR_START_MASK) 6520 6521 #define DMA_TCD_TCD14_CSR_INTMAJOR_MASK (0x2U) 6522 #define DMA_TCD_TCD14_CSR_INTMAJOR_SHIFT (1U) 6523 #define DMA_TCD_TCD14_CSR_INTMAJOR_WIDTH (1U) 6524 #define DMA_TCD_TCD14_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD14_CSR_INTMAJOR_MASK) 6525 6526 #define DMA_TCD_TCD14_CSR_INTHALF_MASK (0x4U) 6527 #define DMA_TCD_TCD14_CSR_INTHALF_SHIFT (2U) 6528 #define DMA_TCD_TCD14_CSR_INTHALF_WIDTH (1U) 6529 #define DMA_TCD_TCD14_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD14_CSR_INTHALF_MASK) 6530 6531 #define DMA_TCD_TCD14_CSR_DREQ_MASK (0x8U) 6532 #define DMA_TCD_TCD14_CSR_DREQ_SHIFT (3U) 6533 #define DMA_TCD_TCD14_CSR_DREQ_WIDTH (1U) 6534 #define DMA_TCD_TCD14_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CSR_DREQ_SHIFT)) & DMA_TCD_TCD14_CSR_DREQ_MASK) 6535 6536 #define DMA_TCD_TCD14_CSR_ESG_MASK (0x10U) 6537 #define DMA_TCD_TCD14_CSR_ESG_SHIFT (4U) 6538 #define DMA_TCD_TCD14_CSR_ESG_WIDTH (1U) 6539 #define DMA_TCD_TCD14_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CSR_ESG_SHIFT)) & DMA_TCD_TCD14_CSR_ESG_MASK) 6540 6541 #define DMA_TCD_TCD14_CSR_MAJORELINK_MASK (0x20U) 6542 #define DMA_TCD_TCD14_CSR_MAJORELINK_SHIFT (5U) 6543 #define DMA_TCD_TCD14_CSR_MAJORELINK_WIDTH (1U) 6544 #define DMA_TCD_TCD14_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD14_CSR_MAJORELINK_MASK) 6545 6546 #define DMA_TCD_TCD14_CSR_EEOP_MASK (0x40U) 6547 #define DMA_TCD_TCD14_CSR_EEOP_SHIFT (6U) 6548 #define DMA_TCD_TCD14_CSR_EEOP_WIDTH (1U) 6549 #define DMA_TCD_TCD14_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CSR_EEOP_SHIFT)) & DMA_TCD_TCD14_CSR_EEOP_MASK) 6550 6551 #define DMA_TCD_TCD14_CSR_ESDA_MASK (0x80U) 6552 #define DMA_TCD_TCD14_CSR_ESDA_SHIFT (7U) 6553 #define DMA_TCD_TCD14_CSR_ESDA_WIDTH (1U) 6554 #define DMA_TCD_TCD14_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CSR_ESDA_SHIFT)) & DMA_TCD_TCD14_CSR_ESDA_MASK) 6555 6556 #define DMA_TCD_TCD14_CSR_MAJORLINKCH_MASK (0x1F00U) 6557 #define DMA_TCD_TCD14_CSR_MAJORLINKCH_SHIFT (8U) 6558 #define DMA_TCD_TCD14_CSR_MAJORLINKCH_WIDTH (5U) 6559 #define DMA_TCD_TCD14_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD14_CSR_MAJORLINKCH_MASK) 6560 6561 #define DMA_TCD_TCD14_CSR_BWC_MASK (0xC000U) 6562 #define DMA_TCD_TCD14_CSR_BWC_SHIFT (14U) 6563 #define DMA_TCD_TCD14_CSR_BWC_WIDTH (2U) 6564 #define DMA_TCD_TCD14_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_CSR_BWC_SHIFT)) & DMA_TCD_TCD14_CSR_BWC_MASK) 6565 /*! @} */ 6566 6567 /*! @name TCD14_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 6568 /*! @{ */ 6569 6570 #define DMA_TCD_TCD14_BITER_ELINKNO_BITER_MASK (0x7FFFU) 6571 #define DMA_TCD_TCD14_BITER_ELINKNO_BITER_SHIFT (0U) 6572 #define DMA_TCD_TCD14_BITER_ELINKNO_BITER_WIDTH (15U) 6573 #define DMA_TCD_TCD14_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD14_BITER_ELINKNO_BITER_MASK) 6574 6575 #define DMA_TCD_TCD14_BITER_ELINKNO_ELINK_MASK (0x8000U) 6576 #define DMA_TCD_TCD14_BITER_ELINKNO_ELINK_SHIFT (15U) 6577 #define DMA_TCD_TCD14_BITER_ELINKNO_ELINK_WIDTH (1U) 6578 #define DMA_TCD_TCD14_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD14_BITER_ELINKNO_ELINK_MASK) 6579 /*! @} */ 6580 6581 /*! @name TCD14_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 6582 /*! @{ */ 6583 6584 #define DMA_TCD_TCD14_BITER_ELINKYES_BITER_MASK (0x1FFU) 6585 #define DMA_TCD_TCD14_BITER_ELINKYES_BITER_SHIFT (0U) 6586 #define DMA_TCD_TCD14_BITER_ELINKYES_BITER_WIDTH (9U) 6587 #define DMA_TCD_TCD14_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD14_BITER_ELINKYES_BITER_MASK) 6588 6589 #define DMA_TCD_TCD14_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 6590 #define DMA_TCD_TCD14_BITER_ELINKYES_LINKCH_SHIFT (9U) 6591 #define DMA_TCD_TCD14_BITER_ELINKYES_LINKCH_WIDTH (5U) 6592 #define DMA_TCD_TCD14_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD14_BITER_ELINKYES_LINKCH_MASK) 6593 6594 #define DMA_TCD_TCD14_BITER_ELINKYES_ELINK_MASK (0x8000U) 6595 #define DMA_TCD_TCD14_BITER_ELINKYES_ELINK_SHIFT (15U) 6596 #define DMA_TCD_TCD14_BITER_ELINKYES_ELINK_WIDTH (1U) 6597 #define DMA_TCD_TCD14_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD14_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD14_BITER_ELINKYES_ELINK_MASK) 6598 /*! @} */ 6599 6600 /*! @name CH15_CSR - Channel Control and Status */ 6601 /*! @{ */ 6602 6603 #define DMA_TCD_CH15_CSR_ERQ_MASK (0x1U) 6604 #define DMA_TCD_CH15_CSR_ERQ_SHIFT (0U) 6605 #define DMA_TCD_CH15_CSR_ERQ_WIDTH (1U) 6606 #define DMA_TCD_CH15_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_CSR_ERQ_SHIFT)) & DMA_TCD_CH15_CSR_ERQ_MASK) 6607 6608 #define DMA_TCD_CH15_CSR_EARQ_MASK (0x2U) 6609 #define DMA_TCD_CH15_CSR_EARQ_SHIFT (1U) 6610 #define DMA_TCD_CH15_CSR_EARQ_WIDTH (1U) 6611 #define DMA_TCD_CH15_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_CSR_EARQ_SHIFT)) & DMA_TCD_CH15_CSR_EARQ_MASK) 6612 6613 #define DMA_TCD_CH15_CSR_EEI_MASK (0x4U) 6614 #define DMA_TCD_CH15_CSR_EEI_SHIFT (2U) 6615 #define DMA_TCD_CH15_CSR_EEI_WIDTH (1U) 6616 #define DMA_TCD_CH15_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_CSR_EEI_SHIFT)) & DMA_TCD_CH15_CSR_EEI_MASK) 6617 6618 #define DMA_TCD_CH15_CSR_EBW_MASK (0x8U) 6619 #define DMA_TCD_CH15_CSR_EBW_SHIFT (3U) 6620 #define DMA_TCD_CH15_CSR_EBW_WIDTH (1U) 6621 #define DMA_TCD_CH15_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_CSR_EBW_SHIFT)) & DMA_TCD_CH15_CSR_EBW_MASK) 6622 6623 #define DMA_TCD_CH15_CSR_DONE_MASK (0x40000000U) 6624 #define DMA_TCD_CH15_CSR_DONE_SHIFT (30U) 6625 #define DMA_TCD_CH15_CSR_DONE_WIDTH (1U) 6626 #define DMA_TCD_CH15_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_CSR_DONE_SHIFT)) & DMA_TCD_CH15_CSR_DONE_MASK) 6627 6628 #define DMA_TCD_CH15_CSR_ACTIVE_MASK (0x80000000U) 6629 #define DMA_TCD_CH15_CSR_ACTIVE_SHIFT (31U) 6630 #define DMA_TCD_CH15_CSR_ACTIVE_WIDTH (1U) 6631 #define DMA_TCD_CH15_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH15_CSR_ACTIVE_MASK) 6632 /*! @} */ 6633 6634 /*! @name CH15_ES - Channel Error Status */ 6635 /*! @{ */ 6636 6637 #define DMA_TCD_CH15_ES_DBE_MASK (0x1U) 6638 #define DMA_TCD_CH15_ES_DBE_SHIFT (0U) 6639 #define DMA_TCD_CH15_ES_DBE_WIDTH (1U) 6640 #define DMA_TCD_CH15_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_ES_DBE_SHIFT)) & DMA_TCD_CH15_ES_DBE_MASK) 6641 6642 #define DMA_TCD_CH15_ES_SBE_MASK (0x2U) 6643 #define DMA_TCD_CH15_ES_SBE_SHIFT (1U) 6644 #define DMA_TCD_CH15_ES_SBE_WIDTH (1U) 6645 #define DMA_TCD_CH15_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_ES_SBE_SHIFT)) & DMA_TCD_CH15_ES_SBE_MASK) 6646 6647 #define DMA_TCD_CH15_ES_SGE_MASK (0x4U) 6648 #define DMA_TCD_CH15_ES_SGE_SHIFT (2U) 6649 #define DMA_TCD_CH15_ES_SGE_WIDTH (1U) 6650 #define DMA_TCD_CH15_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_ES_SGE_SHIFT)) & DMA_TCD_CH15_ES_SGE_MASK) 6651 6652 #define DMA_TCD_CH15_ES_NCE_MASK (0x8U) 6653 #define DMA_TCD_CH15_ES_NCE_SHIFT (3U) 6654 #define DMA_TCD_CH15_ES_NCE_WIDTH (1U) 6655 #define DMA_TCD_CH15_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_ES_NCE_SHIFT)) & DMA_TCD_CH15_ES_NCE_MASK) 6656 6657 #define DMA_TCD_CH15_ES_DOE_MASK (0x10U) 6658 #define DMA_TCD_CH15_ES_DOE_SHIFT (4U) 6659 #define DMA_TCD_CH15_ES_DOE_WIDTH (1U) 6660 #define DMA_TCD_CH15_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_ES_DOE_SHIFT)) & DMA_TCD_CH15_ES_DOE_MASK) 6661 6662 #define DMA_TCD_CH15_ES_DAE_MASK (0x20U) 6663 #define DMA_TCD_CH15_ES_DAE_SHIFT (5U) 6664 #define DMA_TCD_CH15_ES_DAE_WIDTH (1U) 6665 #define DMA_TCD_CH15_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_ES_DAE_SHIFT)) & DMA_TCD_CH15_ES_DAE_MASK) 6666 6667 #define DMA_TCD_CH15_ES_SOE_MASK (0x40U) 6668 #define DMA_TCD_CH15_ES_SOE_SHIFT (6U) 6669 #define DMA_TCD_CH15_ES_SOE_WIDTH (1U) 6670 #define DMA_TCD_CH15_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_ES_SOE_SHIFT)) & DMA_TCD_CH15_ES_SOE_MASK) 6671 6672 #define DMA_TCD_CH15_ES_SAE_MASK (0x80U) 6673 #define DMA_TCD_CH15_ES_SAE_SHIFT (7U) 6674 #define DMA_TCD_CH15_ES_SAE_WIDTH (1U) 6675 #define DMA_TCD_CH15_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_ES_SAE_SHIFT)) & DMA_TCD_CH15_ES_SAE_MASK) 6676 6677 #define DMA_TCD_CH15_ES_ERR_MASK (0x80000000U) 6678 #define DMA_TCD_CH15_ES_ERR_SHIFT (31U) 6679 #define DMA_TCD_CH15_ES_ERR_WIDTH (1U) 6680 #define DMA_TCD_CH15_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_ES_ERR_SHIFT)) & DMA_TCD_CH15_ES_ERR_MASK) 6681 /*! @} */ 6682 6683 /*! @name CH15_INT - Channel Interrupt Status */ 6684 /*! @{ */ 6685 6686 #define DMA_TCD_CH15_INT_INT_MASK (0x1U) 6687 #define DMA_TCD_CH15_INT_INT_SHIFT (0U) 6688 #define DMA_TCD_CH15_INT_INT_WIDTH (1U) 6689 #define DMA_TCD_CH15_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_INT_INT_SHIFT)) & DMA_TCD_CH15_INT_INT_MASK) 6690 /*! @} */ 6691 6692 /*! @name CH15_SBR - Channel System Bus */ 6693 /*! @{ */ 6694 6695 #define DMA_TCD_CH15_SBR_MID_MASK (0xFU) 6696 #define DMA_TCD_CH15_SBR_MID_SHIFT (0U) 6697 #define DMA_TCD_CH15_SBR_MID_WIDTH (4U) 6698 #define DMA_TCD_CH15_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_SBR_MID_SHIFT)) & DMA_TCD_CH15_SBR_MID_MASK) 6699 6700 #define DMA_TCD_CH15_SBR_PAL_MASK (0x8000U) 6701 #define DMA_TCD_CH15_SBR_PAL_SHIFT (15U) 6702 #define DMA_TCD_CH15_SBR_PAL_WIDTH (1U) 6703 #define DMA_TCD_CH15_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_SBR_PAL_SHIFT)) & DMA_TCD_CH15_SBR_PAL_MASK) 6704 6705 #define DMA_TCD_CH15_SBR_EMI_MASK (0x10000U) 6706 #define DMA_TCD_CH15_SBR_EMI_SHIFT (16U) 6707 #define DMA_TCD_CH15_SBR_EMI_WIDTH (1U) 6708 #define DMA_TCD_CH15_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_SBR_EMI_SHIFT)) & DMA_TCD_CH15_SBR_EMI_MASK) 6709 6710 #define DMA_TCD_CH15_SBR_ATTR_MASK (0xE0000U) 6711 #define DMA_TCD_CH15_SBR_ATTR_SHIFT (17U) 6712 #define DMA_TCD_CH15_SBR_ATTR_WIDTH (3U) 6713 #define DMA_TCD_CH15_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_SBR_ATTR_SHIFT)) & DMA_TCD_CH15_SBR_ATTR_MASK) 6714 /*! @} */ 6715 6716 /*! @name CH15_PRI - Channel Priority */ 6717 /*! @{ */ 6718 6719 #define DMA_TCD_CH15_PRI_APL_MASK (0x7U) 6720 #define DMA_TCD_CH15_PRI_APL_SHIFT (0U) 6721 #define DMA_TCD_CH15_PRI_APL_WIDTH (3U) 6722 #define DMA_TCD_CH15_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_PRI_APL_SHIFT)) & DMA_TCD_CH15_PRI_APL_MASK) 6723 6724 #define DMA_TCD_CH15_PRI_DPA_MASK (0x40000000U) 6725 #define DMA_TCD_CH15_PRI_DPA_SHIFT (30U) 6726 #define DMA_TCD_CH15_PRI_DPA_WIDTH (1U) 6727 #define DMA_TCD_CH15_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_PRI_DPA_SHIFT)) & DMA_TCD_CH15_PRI_DPA_MASK) 6728 6729 #define DMA_TCD_CH15_PRI_ECP_MASK (0x80000000U) 6730 #define DMA_TCD_CH15_PRI_ECP_SHIFT (31U) 6731 #define DMA_TCD_CH15_PRI_ECP_WIDTH (1U) 6732 #define DMA_TCD_CH15_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH15_PRI_ECP_SHIFT)) & DMA_TCD_CH15_PRI_ECP_MASK) 6733 /*! @} */ 6734 6735 /*! @name TCD15_SADDR - TCD Source Address */ 6736 /*! @{ */ 6737 6738 #define DMA_TCD_TCD15_SADDR_SADDR_MASK (0xFFFFFFFFU) 6739 #define DMA_TCD_TCD15_SADDR_SADDR_SHIFT (0U) 6740 #define DMA_TCD_TCD15_SADDR_SADDR_WIDTH (32U) 6741 #define DMA_TCD_TCD15_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD15_SADDR_SADDR_MASK) 6742 /*! @} */ 6743 6744 /*! @name TCD15_SOFF - TCD Signed Source Address Offset */ 6745 /*! @{ */ 6746 6747 #define DMA_TCD_TCD15_SOFF_SOFF_MASK (0xFFFFU) 6748 #define DMA_TCD_TCD15_SOFF_SOFF_SHIFT (0U) 6749 #define DMA_TCD_TCD15_SOFF_SOFF_WIDTH (16U) 6750 #define DMA_TCD_TCD15_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD15_SOFF_SOFF_MASK) 6751 /*! @} */ 6752 6753 /*! @name TCD15_ATTR - TCD Transfer Attributes */ 6754 /*! @{ */ 6755 6756 #define DMA_TCD_TCD15_ATTR_DSIZE_MASK (0x7U) 6757 #define DMA_TCD_TCD15_ATTR_DSIZE_SHIFT (0U) 6758 #define DMA_TCD_TCD15_ATTR_DSIZE_WIDTH (3U) 6759 #define DMA_TCD_TCD15_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD15_ATTR_DSIZE_MASK) 6760 6761 #define DMA_TCD_TCD15_ATTR_DMOD_MASK (0xF8U) 6762 #define DMA_TCD_TCD15_ATTR_DMOD_SHIFT (3U) 6763 #define DMA_TCD_TCD15_ATTR_DMOD_WIDTH (5U) 6764 #define DMA_TCD_TCD15_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD15_ATTR_DMOD_MASK) 6765 6766 #define DMA_TCD_TCD15_ATTR_SSIZE_MASK (0x700U) 6767 #define DMA_TCD_TCD15_ATTR_SSIZE_SHIFT (8U) 6768 #define DMA_TCD_TCD15_ATTR_SSIZE_WIDTH (3U) 6769 #define DMA_TCD_TCD15_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD15_ATTR_SSIZE_MASK) 6770 6771 #define DMA_TCD_TCD15_ATTR_SMOD_MASK (0xF800U) 6772 #define DMA_TCD_TCD15_ATTR_SMOD_SHIFT (11U) 6773 #define DMA_TCD_TCD15_ATTR_SMOD_WIDTH (5U) 6774 #define DMA_TCD_TCD15_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD15_ATTR_SMOD_MASK) 6775 /*! @} */ 6776 6777 /*! @name TCD15_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 6778 /*! @{ */ 6779 6780 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 6781 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 6782 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 6783 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD15_NBYTES_MLOFFNO_NBYTES_MASK) 6784 6785 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 6786 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 6787 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 6788 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD15_NBYTES_MLOFFNO_DMLOE_MASK) 6789 6790 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 6791 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 6792 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 6793 #define DMA_TCD_TCD15_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD15_NBYTES_MLOFFNO_SMLOE_MASK) 6794 /*! @} */ 6795 6796 /*! @name TCD15_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 6797 /*! @{ */ 6798 6799 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 6800 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 6801 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 6802 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD15_NBYTES_MLOFFYES_NBYTES_MASK) 6803 6804 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 6805 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 6806 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 6807 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD15_NBYTES_MLOFFYES_MLOFF_MASK) 6808 6809 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 6810 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 6811 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 6812 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD15_NBYTES_MLOFFYES_DMLOE_MASK) 6813 6814 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 6815 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 6816 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 6817 #define DMA_TCD_TCD15_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD15_NBYTES_MLOFFYES_SMLOE_MASK) 6818 /*! @} */ 6819 6820 /*! @name TCD15_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 6821 /*! @{ */ 6822 6823 #define DMA_TCD_TCD15_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 6824 #define DMA_TCD_TCD15_SLAST_SDA_SLAST_SDA_SHIFT (0U) 6825 #define DMA_TCD_TCD15_SLAST_SDA_SLAST_SDA_WIDTH (32U) 6826 #define DMA_TCD_TCD15_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD15_SLAST_SDA_SLAST_SDA_MASK) 6827 /*! @} */ 6828 6829 /*! @name TCD15_DADDR - TCD Destination Address */ 6830 /*! @{ */ 6831 6832 #define DMA_TCD_TCD15_DADDR_DADDR_MASK (0xFFFFFFFFU) 6833 #define DMA_TCD_TCD15_DADDR_DADDR_SHIFT (0U) 6834 #define DMA_TCD_TCD15_DADDR_DADDR_WIDTH (32U) 6835 #define DMA_TCD_TCD15_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD15_DADDR_DADDR_MASK) 6836 /*! @} */ 6837 6838 /*! @name TCD15_DOFF - TCD Signed Destination Address Offset */ 6839 /*! @{ */ 6840 6841 #define DMA_TCD_TCD15_DOFF_DOFF_MASK (0xFFFFU) 6842 #define DMA_TCD_TCD15_DOFF_DOFF_SHIFT (0U) 6843 #define DMA_TCD_TCD15_DOFF_DOFF_WIDTH (16U) 6844 #define DMA_TCD_TCD15_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD15_DOFF_DOFF_MASK) 6845 /*! @} */ 6846 6847 /*! @name TCD15_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 6848 /*! @{ */ 6849 6850 #define DMA_TCD_TCD15_CITER_ELINKNO_CITER_MASK (0x7FFFU) 6851 #define DMA_TCD_TCD15_CITER_ELINKNO_CITER_SHIFT (0U) 6852 #define DMA_TCD_TCD15_CITER_ELINKNO_CITER_WIDTH (15U) 6853 #define DMA_TCD_TCD15_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD15_CITER_ELINKNO_CITER_MASK) 6854 6855 #define DMA_TCD_TCD15_CITER_ELINKNO_ELINK_MASK (0x8000U) 6856 #define DMA_TCD_TCD15_CITER_ELINKNO_ELINK_SHIFT (15U) 6857 #define DMA_TCD_TCD15_CITER_ELINKNO_ELINK_WIDTH (1U) 6858 #define DMA_TCD_TCD15_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD15_CITER_ELINKNO_ELINK_MASK) 6859 /*! @} */ 6860 6861 /*! @name TCD15_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 6862 /*! @{ */ 6863 6864 #define DMA_TCD_TCD15_CITER_ELINKYES_CITER_MASK (0x1FFU) 6865 #define DMA_TCD_TCD15_CITER_ELINKYES_CITER_SHIFT (0U) 6866 #define DMA_TCD_TCD15_CITER_ELINKYES_CITER_WIDTH (9U) 6867 #define DMA_TCD_TCD15_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD15_CITER_ELINKYES_CITER_MASK) 6868 6869 #define DMA_TCD_TCD15_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 6870 #define DMA_TCD_TCD15_CITER_ELINKYES_LINKCH_SHIFT (9U) 6871 #define DMA_TCD_TCD15_CITER_ELINKYES_LINKCH_WIDTH (5U) 6872 #define DMA_TCD_TCD15_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD15_CITER_ELINKYES_LINKCH_MASK) 6873 6874 #define DMA_TCD_TCD15_CITER_ELINKYES_ELINK_MASK (0x8000U) 6875 #define DMA_TCD_TCD15_CITER_ELINKYES_ELINK_SHIFT (15U) 6876 #define DMA_TCD_TCD15_CITER_ELINKYES_ELINK_WIDTH (1U) 6877 #define DMA_TCD_TCD15_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD15_CITER_ELINKYES_ELINK_MASK) 6878 /*! @} */ 6879 6880 /*! @name TCD15_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 6881 /*! @{ */ 6882 6883 #define DMA_TCD_TCD15_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 6884 #define DMA_TCD_TCD15_DLAST_SGA_DLAST_SGA_SHIFT (0U) 6885 #define DMA_TCD_TCD15_DLAST_SGA_DLAST_SGA_WIDTH (32U) 6886 #define DMA_TCD_TCD15_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD15_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD15_DLAST_SGA_DLAST_SGA_MASK) 6887 /*! @} */ 6888 6889 /*! @name TCD15_CSR - TCD Control and Status */ 6890 /*! @{ */ 6891 6892 #define DMA_TCD_TCD15_CSR_START_MASK (0x1U) 6893 #define DMA_TCD_TCD15_CSR_START_SHIFT (0U) 6894 #define DMA_TCD_TCD15_CSR_START_WIDTH (1U) 6895 #define DMA_TCD_TCD15_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CSR_START_SHIFT)) & DMA_TCD_TCD15_CSR_START_MASK) 6896 6897 #define DMA_TCD_TCD15_CSR_INTMAJOR_MASK (0x2U) 6898 #define DMA_TCD_TCD15_CSR_INTMAJOR_SHIFT (1U) 6899 #define DMA_TCD_TCD15_CSR_INTMAJOR_WIDTH (1U) 6900 #define DMA_TCD_TCD15_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD15_CSR_INTMAJOR_MASK) 6901 6902 #define DMA_TCD_TCD15_CSR_INTHALF_MASK (0x4U) 6903 #define DMA_TCD_TCD15_CSR_INTHALF_SHIFT (2U) 6904 #define DMA_TCD_TCD15_CSR_INTHALF_WIDTH (1U) 6905 #define DMA_TCD_TCD15_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD15_CSR_INTHALF_MASK) 6906 6907 #define DMA_TCD_TCD15_CSR_DREQ_MASK (0x8U) 6908 #define DMA_TCD_TCD15_CSR_DREQ_SHIFT (3U) 6909 #define DMA_TCD_TCD15_CSR_DREQ_WIDTH (1U) 6910 #define DMA_TCD_TCD15_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CSR_DREQ_SHIFT)) & DMA_TCD_TCD15_CSR_DREQ_MASK) 6911 6912 #define DMA_TCD_TCD15_CSR_ESG_MASK (0x10U) 6913 #define DMA_TCD_TCD15_CSR_ESG_SHIFT (4U) 6914 #define DMA_TCD_TCD15_CSR_ESG_WIDTH (1U) 6915 #define DMA_TCD_TCD15_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CSR_ESG_SHIFT)) & DMA_TCD_TCD15_CSR_ESG_MASK) 6916 6917 #define DMA_TCD_TCD15_CSR_MAJORELINK_MASK (0x20U) 6918 #define DMA_TCD_TCD15_CSR_MAJORELINK_SHIFT (5U) 6919 #define DMA_TCD_TCD15_CSR_MAJORELINK_WIDTH (1U) 6920 #define DMA_TCD_TCD15_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD15_CSR_MAJORELINK_MASK) 6921 6922 #define DMA_TCD_TCD15_CSR_EEOP_MASK (0x40U) 6923 #define DMA_TCD_TCD15_CSR_EEOP_SHIFT (6U) 6924 #define DMA_TCD_TCD15_CSR_EEOP_WIDTH (1U) 6925 #define DMA_TCD_TCD15_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CSR_EEOP_SHIFT)) & DMA_TCD_TCD15_CSR_EEOP_MASK) 6926 6927 #define DMA_TCD_TCD15_CSR_ESDA_MASK (0x80U) 6928 #define DMA_TCD_TCD15_CSR_ESDA_SHIFT (7U) 6929 #define DMA_TCD_TCD15_CSR_ESDA_WIDTH (1U) 6930 #define DMA_TCD_TCD15_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CSR_ESDA_SHIFT)) & DMA_TCD_TCD15_CSR_ESDA_MASK) 6931 6932 #define DMA_TCD_TCD15_CSR_MAJORLINKCH_MASK (0x1F00U) 6933 #define DMA_TCD_TCD15_CSR_MAJORLINKCH_SHIFT (8U) 6934 #define DMA_TCD_TCD15_CSR_MAJORLINKCH_WIDTH (5U) 6935 #define DMA_TCD_TCD15_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD15_CSR_MAJORLINKCH_MASK) 6936 6937 #define DMA_TCD_TCD15_CSR_BWC_MASK (0xC000U) 6938 #define DMA_TCD_TCD15_CSR_BWC_SHIFT (14U) 6939 #define DMA_TCD_TCD15_CSR_BWC_WIDTH (2U) 6940 #define DMA_TCD_TCD15_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_CSR_BWC_SHIFT)) & DMA_TCD_TCD15_CSR_BWC_MASK) 6941 /*! @} */ 6942 6943 /*! @name TCD15_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 6944 /*! @{ */ 6945 6946 #define DMA_TCD_TCD15_BITER_ELINKNO_BITER_MASK (0x7FFFU) 6947 #define DMA_TCD_TCD15_BITER_ELINKNO_BITER_SHIFT (0U) 6948 #define DMA_TCD_TCD15_BITER_ELINKNO_BITER_WIDTH (15U) 6949 #define DMA_TCD_TCD15_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD15_BITER_ELINKNO_BITER_MASK) 6950 6951 #define DMA_TCD_TCD15_BITER_ELINKNO_ELINK_MASK (0x8000U) 6952 #define DMA_TCD_TCD15_BITER_ELINKNO_ELINK_SHIFT (15U) 6953 #define DMA_TCD_TCD15_BITER_ELINKNO_ELINK_WIDTH (1U) 6954 #define DMA_TCD_TCD15_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD15_BITER_ELINKNO_ELINK_MASK) 6955 /*! @} */ 6956 6957 /*! @name TCD15_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 6958 /*! @{ */ 6959 6960 #define DMA_TCD_TCD15_BITER_ELINKYES_BITER_MASK (0x1FFU) 6961 #define DMA_TCD_TCD15_BITER_ELINKYES_BITER_SHIFT (0U) 6962 #define DMA_TCD_TCD15_BITER_ELINKYES_BITER_WIDTH (9U) 6963 #define DMA_TCD_TCD15_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD15_BITER_ELINKYES_BITER_MASK) 6964 6965 #define DMA_TCD_TCD15_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 6966 #define DMA_TCD_TCD15_BITER_ELINKYES_LINKCH_SHIFT (9U) 6967 #define DMA_TCD_TCD15_BITER_ELINKYES_LINKCH_WIDTH (5U) 6968 #define DMA_TCD_TCD15_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD15_BITER_ELINKYES_LINKCH_MASK) 6969 6970 #define DMA_TCD_TCD15_BITER_ELINKYES_ELINK_MASK (0x8000U) 6971 #define DMA_TCD_TCD15_BITER_ELINKYES_ELINK_SHIFT (15U) 6972 #define DMA_TCD_TCD15_BITER_ELINKYES_ELINK_WIDTH (1U) 6973 #define DMA_TCD_TCD15_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD15_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD15_BITER_ELINKYES_ELINK_MASK) 6974 /*! @} */ 6975 6976 /*! @name CH16_CSR - Channel Control and Status */ 6977 /*! @{ */ 6978 6979 #define DMA_TCD_CH16_CSR_ERQ_MASK (0x1U) 6980 #define DMA_TCD_CH16_CSR_ERQ_SHIFT (0U) 6981 #define DMA_TCD_CH16_CSR_ERQ_WIDTH (1U) 6982 #define DMA_TCD_CH16_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_CSR_ERQ_SHIFT)) & DMA_TCD_CH16_CSR_ERQ_MASK) 6983 6984 #define DMA_TCD_CH16_CSR_EARQ_MASK (0x2U) 6985 #define DMA_TCD_CH16_CSR_EARQ_SHIFT (1U) 6986 #define DMA_TCD_CH16_CSR_EARQ_WIDTH (1U) 6987 #define DMA_TCD_CH16_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_CSR_EARQ_SHIFT)) & DMA_TCD_CH16_CSR_EARQ_MASK) 6988 6989 #define DMA_TCD_CH16_CSR_EEI_MASK (0x4U) 6990 #define DMA_TCD_CH16_CSR_EEI_SHIFT (2U) 6991 #define DMA_TCD_CH16_CSR_EEI_WIDTH (1U) 6992 #define DMA_TCD_CH16_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_CSR_EEI_SHIFT)) & DMA_TCD_CH16_CSR_EEI_MASK) 6993 6994 #define DMA_TCD_CH16_CSR_EBW_MASK (0x8U) 6995 #define DMA_TCD_CH16_CSR_EBW_SHIFT (3U) 6996 #define DMA_TCD_CH16_CSR_EBW_WIDTH (1U) 6997 #define DMA_TCD_CH16_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_CSR_EBW_SHIFT)) & DMA_TCD_CH16_CSR_EBW_MASK) 6998 6999 #define DMA_TCD_CH16_CSR_DONE_MASK (0x40000000U) 7000 #define DMA_TCD_CH16_CSR_DONE_SHIFT (30U) 7001 #define DMA_TCD_CH16_CSR_DONE_WIDTH (1U) 7002 #define DMA_TCD_CH16_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_CSR_DONE_SHIFT)) & DMA_TCD_CH16_CSR_DONE_MASK) 7003 7004 #define DMA_TCD_CH16_CSR_ACTIVE_MASK (0x80000000U) 7005 #define DMA_TCD_CH16_CSR_ACTIVE_SHIFT (31U) 7006 #define DMA_TCD_CH16_CSR_ACTIVE_WIDTH (1U) 7007 #define DMA_TCD_CH16_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH16_CSR_ACTIVE_MASK) 7008 /*! @} */ 7009 7010 /*! @name CH16_ES - Channel Error Status */ 7011 /*! @{ */ 7012 7013 #define DMA_TCD_CH16_ES_DBE_MASK (0x1U) 7014 #define DMA_TCD_CH16_ES_DBE_SHIFT (0U) 7015 #define DMA_TCD_CH16_ES_DBE_WIDTH (1U) 7016 #define DMA_TCD_CH16_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_ES_DBE_SHIFT)) & DMA_TCD_CH16_ES_DBE_MASK) 7017 7018 #define DMA_TCD_CH16_ES_SBE_MASK (0x2U) 7019 #define DMA_TCD_CH16_ES_SBE_SHIFT (1U) 7020 #define DMA_TCD_CH16_ES_SBE_WIDTH (1U) 7021 #define DMA_TCD_CH16_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_ES_SBE_SHIFT)) & DMA_TCD_CH16_ES_SBE_MASK) 7022 7023 #define DMA_TCD_CH16_ES_SGE_MASK (0x4U) 7024 #define DMA_TCD_CH16_ES_SGE_SHIFT (2U) 7025 #define DMA_TCD_CH16_ES_SGE_WIDTH (1U) 7026 #define DMA_TCD_CH16_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_ES_SGE_SHIFT)) & DMA_TCD_CH16_ES_SGE_MASK) 7027 7028 #define DMA_TCD_CH16_ES_NCE_MASK (0x8U) 7029 #define DMA_TCD_CH16_ES_NCE_SHIFT (3U) 7030 #define DMA_TCD_CH16_ES_NCE_WIDTH (1U) 7031 #define DMA_TCD_CH16_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_ES_NCE_SHIFT)) & DMA_TCD_CH16_ES_NCE_MASK) 7032 7033 #define DMA_TCD_CH16_ES_DOE_MASK (0x10U) 7034 #define DMA_TCD_CH16_ES_DOE_SHIFT (4U) 7035 #define DMA_TCD_CH16_ES_DOE_WIDTH (1U) 7036 #define DMA_TCD_CH16_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_ES_DOE_SHIFT)) & DMA_TCD_CH16_ES_DOE_MASK) 7037 7038 #define DMA_TCD_CH16_ES_DAE_MASK (0x20U) 7039 #define DMA_TCD_CH16_ES_DAE_SHIFT (5U) 7040 #define DMA_TCD_CH16_ES_DAE_WIDTH (1U) 7041 #define DMA_TCD_CH16_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_ES_DAE_SHIFT)) & DMA_TCD_CH16_ES_DAE_MASK) 7042 7043 #define DMA_TCD_CH16_ES_SOE_MASK (0x40U) 7044 #define DMA_TCD_CH16_ES_SOE_SHIFT (6U) 7045 #define DMA_TCD_CH16_ES_SOE_WIDTH (1U) 7046 #define DMA_TCD_CH16_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_ES_SOE_SHIFT)) & DMA_TCD_CH16_ES_SOE_MASK) 7047 7048 #define DMA_TCD_CH16_ES_SAE_MASK (0x80U) 7049 #define DMA_TCD_CH16_ES_SAE_SHIFT (7U) 7050 #define DMA_TCD_CH16_ES_SAE_WIDTH (1U) 7051 #define DMA_TCD_CH16_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_ES_SAE_SHIFT)) & DMA_TCD_CH16_ES_SAE_MASK) 7052 7053 #define DMA_TCD_CH16_ES_ERR_MASK (0x80000000U) 7054 #define DMA_TCD_CH16_ES_ERR_SHIFT (31U) 7055 #define DMA_TCD_CH16_ES_ERR_WIDTH (1U) 7056 #define DMA_TCD_CH16_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_ES_ERR_SHIFT)) & DMA_TCD_CH16_ES_ERR_MASK) 7057 /*! @} */ 7058 7059 /*! @name CH16_INT - Channel Interrupt Status */ 7060 /*! @{ */ 7061 7062 #define DMA_TCD_CH16_INT_INT_MASK (0x1U) 7063 #define DMA_TCD_CH16_INT_INT_SHIFT (0U) 7064 #define DMA_TCD_CH16_INT_INT_WIDTH (1U) 7065 #define DMA_TCD_CH16_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_INT_INT_SHIFT)) & DMA_TCD_CH16_INT_INT_MASK) 7066 /*! @} */ 7067 7068 /*! @name CH16_SBR - Channel System Bus */ 7069 /*! @{ */ 7070 7071 #define DMA_TCD_CH16_SBR_MID_MASK (0xFU) 7072 #define DMA_TCD_CH16_SBR_MID_SHIFT (0U) 7073 #define DMA_TCD_CH16_SBR_MID_WIDTH (4U) 7074 #define DMA_TCD_CH16_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_SBR_MID_SHIFT)) & DMA_TCD_CH16_SBR_MID_MASK) 7075 7076 #define DMA_TCD_CH16_SBR_PAL_MASK (0x8000U) 7077 #define DMA_TCD_CH16_SBR_PAL_SHIFT (15U) 7078 #define DMA_TCD_CH16_SBR_PAL_WIDTH (1U) 7079 #define DMA_TCD_CH16_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_SBR_PAL_SHIFT)) & DMA_TCD_CH16_SBR_PAL_MASK) 7080 7081 #define DMA_TCD_CH16_SBR_EMI_MASK (0x10000U) 7082 #define DMA_TCD_CH16_SBR_EMI_SHIFT (16U) 7083 #define DMA_TCD_CH16_SBR_EMI_WIDTH (1U) 7084 #define DMA_TCD_CH16_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_SBR_EMI_SHIFT)) & DMA_TCD_CH16_SBR_EMI_MASK) 7085 7086 #define DMA_TCD_CH16_SBR_ATTR_MASK (0xE0000U) 7087 #define DMA_TCD_CH16_SBR_ATTR_SHIFT (17U) 7088 #define DMA_TCD_CH16_SBR_ATTR_WIDTH (3U) 7089 #define DMA_TCD_CH16_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_SBR_ATTR_SHIFT)) & DMA_TCD_CH16_SBR_ATTR_MASK) 7090 /*! @} */ 7091 7092 /*! @name CH16_PRI - Channel Priority */ 7093 /*! @{ */ 7094 7095 #define DMA_TCD_CH16_PRI_APL_MASK (0x7U) 7096 #define DMA_TCD_CH16_PRI_APL_SHIFT (0U) 7097 #define DMA_TCD_CH16_PRI_APL_WIDTH (3U) 7098 #define DMA_TCD_CH16_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_PRI_APL_SHIFT)) & DMA_TCD_CH16_PRI_APL_MASK) 7099 7100 #define DMA_TCD_CH16_PRI_DPA_MASK (0x40000000U) 7101 #define DMA_TCD_CH16_PRI_DPA_SHIFT (30U) 7102 #define DMA_TCD_CH16_PRI_DPA_WIDTH (1U) 7103 #define DMA_TCD_CH16_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_PRI_DPA_SHIFT)) & DMA_TCD_CH16_PRI_DPA_MASK) 7104 7105 #define DMA_TCD_CH16_PRI_ECP_MASK (0x80000000U) 7106 #define DMA_TCD_CH16_PRI_ECP_SHIFT (31U) 7107 #define DMA_TCD_CH16_PRI_ECP_WIDTH (1U) 7108 #define DMA_TCD_CH16_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH16_PRI_ECP_SHIFT)) & DMA_TCD_CH16_PRI_ECP_MASK) 7109 /*! @} */ 7110 7111 /*! @name TCD16_SADDR - TCD Source Address */ 7112 /*! @{ */ 7113 7114 #define DMA_TCD_TCD16_SADDR_SADDR_MASK (0xFFFFFFFFU) 7115 #define DMA_TCD_TCD16_SADDR_SADDR_SHIFT (0U) 7116 #define DMA_TCD_TCD16_SADDR_SADDR_WIDTH (32U) 7117 #define DMA_TCD_TCD16_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD16_SADDR_SADDR_MASK) 7118 /*! @} */ 7119 7120 /*! @name TCD16_SOFF - TCD Signed Source Address Offset */ 7121 /*! @{ */ 7122 7123 #define DMA_TCD_TCD16_SOFF_SOFF_MASK (0xFFFFU) 7124 #define DMA_TCD_TCD16_SOFF_SOFF_SHIFT (0U) 7125 #define DMA_TCD_TCD16_SOFF_SOFF_WIDTH (16U) 7126 #define DMA_TCD_TCD16_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD16_SOFF_SOFF_MASK) 7127 /*! @} */ 7128 7129 /*! @name TCD16_ATTR - TCD Transfer Attributes */ 7130 /*! @{ */ 7131 7132 #define DMA_TCD_TCD16_ATTR_DSIZE_MASK (0x7U) 7133 #define DMA_TCD_TCD16_ATTR_DSIZE_SHIFT (0U) 7134 #define DMA_TCD_TCD16_ATTR_DSIZE_WIDTH (3U) 7135 #define DMA_TCD_TCD16_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD16_ATTR_DSIZE_MASK) 7136 7137 #define DMA_TCD_TCD16_ATTR_DMOD_MASK (0xF8U) 7138 #define DMA_TCD_TCD16_ATTR_DMOD_SHIFT (3U) 7139 #define DMA_TCD_TCD16_ATTR_DMOD_WIDTH (5U) 7140 #define DMA_TCD_TCD16_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD16_ATTR_DMOD_MASK) 7141 7142 #define DMA_TCD_TCD16_ATTR_SSIZE_MASK (0x700U) 7143 #define DMA_TCD_TCD16_ATTR_SSIZE_SHIFT (8U) 7144 #define DMA_TCD_TCD16_ATTR_SSIZE_WIDTH (3U) 7145 #define DMA_TCD_TCD16_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD16_ATTR_SSIZE_MASK) 7146 7147 #define DMA_TCD_TCD16_ATTR_SMOD_MASK (0xF800U) 7148 #define DMA_TCD_TCD16_ATTR_SMOD_SHIFT (11U) 7149 #define DMA_TCD_TCD16_ATTR_SMOD_WIDTH (5U) 7150 #define DMA_TCD_TCD16_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD16_ATTR_SMOD_MASK) 7151 /*! @} */ 7152 7153 /*! @name TCD16_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 7154 /*! @{ */ 7155 7156 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 7157 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 7158 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 7159 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD16_NBYTES_MLOFFNO_NBYTES_MASK) 7160 7161 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 7162 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 7163 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 7164 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD16_NBYTES_MLOFFNO_DMLOE_MASK) 7165 7166 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 7167 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 7168 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 7169 #define DMA_TCD_TCD16_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD16_NBYTES_MLOFFNO_SMLOE_MASK) 7170 /*! @} */ 7171 7172 /*! @name TCD16_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 7173 /*! @{ */ 7174 7175 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 7176 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 7177 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 7178 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD16_NBYTES_MLOFFYES_NBYTES_MASK) 7179 7180 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 7181 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 7182 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 7183 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD16_NBYTES_MLOFFYES_MLOFF_MASK) 7184 7185 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 7186 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 7187 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 7188 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD16_NBYTES_MLOFFYES_DMLOE_MASK) 7189 7190 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 7191 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 7192 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 7193 #define DMA_TCD_TCD16_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD16_NBYTES_MLOFFYES_SMLOE_MASK) 7194 /*! @} */ 7195 7196 /*! @name TCD16_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 7197 /*! @{ */ 7198 7199 #define DMA_TCD_TCD16_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 7200 #define DMA_TCD_TCD16_SLAST_SDA_SLAST_SDA_SHIFT (0U) 7201 #define DMA_TCD_TCD16_SLAST_SDA_SLAST_SDA_WIDTH (32U) 7202 #define DMA_TCD_TCD16_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD16_SLAST_SDA_SLAST_SDA_MASK) 7203 /*! @} */ 7204 7205 /*! @name TCD16_DADDR - TCD Destination Address */ 7206 /*! @{ */ 7207 7208 #define DMA_TCD_TCD16_DADDR_DADDR_MASK (0xFFFFFFFFU) 7209 #define DMA_TCD_TCD16_DADDR_DADDR_SHIFT (0U) 7210 #define DMA_TCD_TCD16_DADDR_DADDR_WIDTH (32U) 7211 #define DMA_TCD_TCD16_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD16_DADDR_DADDR_MASK) 7212 /*! @} */ 7213 7214 /*! @name TCD16_DOFF - TCD Signed Destination Address Offset */ 7215 /*! @{ */ 7216 7217 #define DMA_TCD_TCD16_DOFF_DOFF_MASK (0xFFFFU) 7218 #define DMA_TCD_TCD16_DOFF_DOFF_SHIFT (0U) 7219 #define DMA_TCD_TCD16_DOFF_DOFF_WIDTH (16U) 7220 #define DMA_TCD_TCD16_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD16_DOFF_DOFF_MASK) 7221 /*! @} */ 7222 7223 /*! @name TCD16_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 7224 /*! @{ */ 7225 7226 #define DMA_TCD_TCD16_CITER_ELINKNO_CITER_MASK (0x7FFFU) 7227 #define DMA_TCD_TCD16_CITER_ELINKNO_CITER_SHIFT (0U) 7228 #define DMA_TCD_TCD16_CITER_ELINKNO_CITER_WIDTH (15U) 7229 #define DMA_TCD_TCD16_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD16_CITER_ELINKNO_CITER_MASK) 7230 7231 #define DMA_TCD_TCD16_CITER_ELINKNO_ELINK_MASK (0x8000U) 7232 #define DMA_TCD_TCD16_CITER_ELINKNO_ELINK_SHIFT (15U) 7233 #define DMA_TCD_TCD16_CITER_ELINKNO_ELINK_WIDTH (1U) 7234 #define DMA_TCD_TCD16_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD16_CITER_ELINKNO_ELINK_MASK) 7235 /*! @} */ 7236 7237 /*! @name TCD16_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 7238 /*! @{ */ 7239 7240 #define DMA_TCD_TCD16_CITER_ELINKYES_CITER_MASK (0x1FFU) 7241 #define DMA_TCD_TCD16_CITER_ELINKYES_CITER_SHIFT (0U) 7242 #define DMA_TCD_TCD16_CITER_ELINKYES_CITER_WIDTH (9U) 7243 #define DMA_TCD_TCD16_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD16_CITER_ELINKYES_CITER_MASK) 7244 7245 #define DMA_TCD_TCD16_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 7246 #define DMA_TCD_TCD16_CITER_ELINKYES_LINKCH_SHIFT (9U) 7247 #define DMA_TCD_TCD16_CITER_ELINKYES_LINKCH_WIDTH (5U) 7248 #define DMA_TCD_TCD16_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD16_CITER_ELINKYES_LINKCH_MASK) 7249 7250 #define DMA_TCD_TCD16_CITER_ELINKYES_ELINK_MASK (0x8000U) 7251 #define DMA_TCD_TCD16_CITER_ELINKYES_ELINK_SHIFT (15U) 7252 #define DMA_TCD_TCD16_CITER_ELINKYES_ELINK_WIDTH (1U) 7253 #define DMA_TCD_TCD16_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD16_CITER_ELINKYES_ELINK_MASK) 7254 /*! @} */ 7255 7256 /*! @name TCD16_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 7257 /*! @{ */ 7258 7259 #define DMA_TCD_TCD16_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 7260 #define DMA_TCD_TCD16_DLAST_SGA_DLAST_SGA_SHIFT (0U) 7261 #define DMA_TCD_TCD16_DLAST_SGA_DLAST_SGA_WIDTH (32U) 7262 #define DMA_TCD_TCD16_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD16_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD16_DLAST_SGA_DLAST_SGA_MASK) 7263 /*! @} */ 7264 7265 /*! @name TCD16_CSR - TCD Control and Status */ 7266 /*! @{ */ 7267 7268 #define DMA_TCD_TCD16_CSR_START_MASK (0x1U) 7269 #define DMA_TCD_TCD16_CSR_START_SHIFT (0U) 7270 #define DMA_TCD_TCD16_CSR_START_WIDTH (1U) 7271 #define DMA_TCD_TCD16_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CSR_START_SHIFT)) & DMA_TCD_TCD16_CSR_START_MASK) 7272 7273 #define DMA_TCD_TCD16_CSR_INTMAJOR_MASK (0x2U) 7274 #define DMA_TCD_TCD16_CSR_INTMAJOR_SHIFT (1U) 7275 #define DMA_TCD_TCD16_CSR_INTMAJOR_WIDTH (1U) 7276 #define DMA_TCD_TCD16_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD16_CSR_INTMAJOR_MASK) 7277 7278 #define DMA_TCD_TCD16_CSR_INTHALF_MASK (0x4U) 7279 #define DMA_TCD_TCD16_CSR_INTHALF_SHIFT (2U) 7280 #define DMA_TCD_TCD16_CSR_INTHALF_WIDTH (1U) 7281 #define DMA_TCD_TCD16_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD16_CSR_INTHALF_MASK) 7282 7283 #define DMA_TCD_TCD16_CSR_DREQ_MASK (0x8U) 7284 #define DMA_TCD_TCD16_CSR_DREQ_SHIFT (3U) 7285 #define DMA_TCD_TCD16_CSR_DREQ_WIDTH (1U) 7286 #define DMA_TCD_TCD16_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CSR_DREQ_SHIFT)) & DMA_TCD_TCD16_CSR_DREQ_MASK) 7287 7288 #define DMA_TCD_TCD16_CSR_ESG_MASK (0x10U) 7289 #define DMA_TCD_TCD16_CSR_ESG_SHIFT (4U) 7290 #define DMA_TCD_TCD16_CSR_ESG_WIDTH (1U) 7291 #define DMA_TCD_TCD16_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CSR_ESG_SHIFT)) & DMA_TCD_TCD16_CSR_ESG_MASK) 7292 7293 #define DMA_TCD_TCD16_CSR_MAJORELINK_MASK (0x20U) 7294 #define DMA_TCD_TCD16_CSR_MAJORELINK_SHIFT (5U) 7295 #define DMA_TCD_TCD16_CSR_MAJORELINK_WIDTH (1U) 7296 #define DMA_TCD_TCD16_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD16_CSR_MAJORELINK_MASK) 7297 7298 #define DMA_TCD_TCD16_CSR_EEOP_MASK (0x40U) 7299 #define DMA_TCD_TCD16_CSR_EEOP_SHIFT (6U) 7300 #define DMA_TCD_TCD16_CSR_EEOP_WIDTH (1U) 7301 #define DMA_TCD_TCD16_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CSR_EEOP_SHIFT)) & DMA_TCD_TCD16_CSR_EEOP_MASK) 7302 7303 #define DMA_TCD_TCD16_CSR_ESDA_MASK (0x80U) 7304 #define DMA_TCD_TCD16_CSR_ESDA_SHIFT (7U) 7305 #define DMA_TCD_TCD16_CSR_ESDA_WIDTH (1U) 7306 #define DMA_TCD_TCD16_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CSR_ESDA_SHIFT)) & DMA_TCD_TCD16_CSR_ESDA_MASK) 7307 7308 #define DMA_TCD_TCD16_CSR_MAJORLINKCH_MASK (0x1F00U) 7309 #define DMA_TCD_TCD16_CSR_MAJORLINKCH_SHIFT (8U) 7310 #define DMA_TCD_TCD16_CSR_MAJORLINKCH_WIDTH (5U) 7311 #define DMA_TCD_TCD16_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD16_CSR_MAJORLINKCH_MASK) 7312 7313 #define DMA_TCD_TCD16_CSR_BWC_MASK (0xC000U) 7314 #define DMA_TCD_TCD16_CSR_BWC_SHIFT (14U) 7315 #define DMA_TCD_TCD16_CSR_BWC_WIDTH (2U) 7316 #define DMA_TCD_TCD16_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_CSR_BWC_SHIFT)) & DMA_TCD_TCD16_CSR_BWC_MASK) 7317 /*! @} */ 7318 7319 /*! @name TCD16_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 7320 /*! @{ */ 7321 7322 #define DMA_TCD_TCD16_BITER_ELINKNO_BITER_MASK (0x7FFFU) 7323 #define DMA_TCD_TCD16_BITER_ELINKNO_BITER_SHIFT (0U) 7324 #define DMA_TCD_TCD16_BITER_ELINKNO_BITER_WIDTH (15U) 7325 #define DMA_TCD_TCD16_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD16_BITER_ELINKNO_BITER_MASK) 7326 7327 #define DMA_TCD_TCD16_BITER_ELINKNO_ELINK_MASK (0x8000U) 7328 #define DMA_TCD_TCD16_BITER_ELINKNO_ELINK_SHIFT (15U) 7329 #define DMA_TCD_TCD16_BITER_ELINKNO_ELINK_WIDTH (1U) 7330 #define DMA_TCD_TCD16_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD16_BITER_ELINKNO_ELINK_MASK) 7331 /*! @} */ 7332 7333 /*! @name TCD16_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 7334 /*! @{ */ 7335 7336 #define DMA_TCD_TCD16_BITER_ELINKYES_BITER_MASK (0x1FFU) 7337 #define DMA_TCD_TCD16_BITER_ELINKYES_BITER_SHIFT (0U) 7338 #define DMA_TCD_TCD16_BITER_ELINKYES_BITER_WIDTH (9U) 7339 #define DMA_TCD_TCD16_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD16_BITER_ELINKYES_BITER_MASK) 7340 7341 #define DMA_TCD_TCD16_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 7342 #define DMA_TCD_TCD16_BITER_ELINKYES_LINKCH_SHIFT (9U) 7343 #define DMA_TCD_TCD16_BITER_ELINKYES_LINKCH_WIDTH (5U) 7344 #define DMA_TCD_TCD16_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD16_BITER_ELINKYES_LINKCH_MASK) 7345 7346 #define DMA_TCD_TCD16_BITER_ELINKYES_ELINK_MASK (0x8000U) 7347 #define DMA_TCD_TCD16_BITER_ELINKYES_ELINK_SHIFT (15U) 7348 #define DMA_TCD_TCD16_BITER_ELINKYES_ELINK_WIDTH (1U) 7349 #define DMA_TCD_TCD16_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD16_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD16_BITER_ELINKYES_ELINK_MASK) 7350 /*! @} */ 7351 7352 /*! @name CH17_CSR - Channel Control and Status */ 7353 /*! @{ */ 7354 7355 #define DMA_TCD_CH17_CSR_ERQ_MASK (0x1U) 7356 #define DMA_TCD_CH17_CSR_ERQ_SHIFT (0U) 7357 #define DMA_TCD_CH17_CSR_ERQ_WIDTH (1U) 7358 #define DMA_TCD_CH17_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_CSR_ERQ_SHIFT)) & DMA_TCD_CH17_CSR_ERQ_MASK) 7359 7360 #define DMA_TCD_CH17_CSR_EARQ_MASK (0x2U) 7361 #define DMA_TCD_CH17_CSR_EARQ_SHIFT (1U) 7362 #define DMA_TCD_CH17_CSR_EARQ_WIDTH (1U) 7363 #define DMA_TCD_CH17_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_CSR_EARQ_SHIFT)) & DMA_TCD_CH17_CSR_EARQ_MASK) 7364 7365 #define DMA_TCD_CH17_CSR_EEI_MASK (0x4U) 7366 #define DMA_TCD_CH17_CSR_EEI_SHIFT (2U) 7367 #define DMA_TCD_CH17_CSR_EEI_WIDTH (1U) 7368 #define DMA_TCD_CH17_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_CSR_EEI_SHIFT)) & DMA_TCD_CH17_CSR_EEI_MASK) 7369 7370 #define DMA_TCD_CH17_CSR_EBW_MASK (0x8U) 7371 #define DMA_TCD_CH17_CSR_EBW_SHIFT (3U) 7372 #define DMA_TCD_CH17_CSR_EBW_WIDTH (1U) 7373 #define DMA_TCD_CH17_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_CSR_EBW_SHIFT)) & DMA_TCD_CH17_CSR_EBW_MASK) 7374 7375 #define DMA_TCD_CH17_CSR_DONE_MASK (0x40000000U) 7376 #define DMA_TCD_CH17_CSR_DONE_SHIFT (30U) 7377 #define DMA_TCD_CH17_CSR_DONE_WIDTH (1U) 7378 #define DMA_TCD_CH17_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_CSR_DONE_SHIFT)) & DMA_TCD_CH17_CSR_DONE_MASK) 7379 7380 #define DMA_TCD_CH17_CSR_ACTIVE_MASK (0x80000000U) 7381 #define DMA_TCD_CH17_CSR_ACTIVE_SHIFT (31U) 7382 #define DMA_TCD_CH17_CSR_ACTIVE_WIDTH (1U) 7383 #define DMA_TCD_CH17_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH17_CSR_ACTIVE_MASK) 7384 /*! @} */ 7385 7386 /*! @name CH17_ES - Channel Error Status */ 7387 /*! @{ */ 7388 7389 #define DMA_TCD_CH17_ES_DBE_MASK (0x1U) 7390 #define DMA_TCD_CH17_ES_DBE_SHIFT (0U) 7391 #define DMA_TCD_CH17_ES_DBE_WIDTH (1U) 7392 #define DMA_TCD_CH17_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_ES_DBE_SHIFT)) & DMA_TCD_CH17_ES_DBE_MASK) 7393 7394 #define DMA_TCD_CH17_ES_SBE_MASK (0x2U) 7395 #define DMA_TCD_CH17_ES_SBE_SHIFT (1U) 7396 #define DMA_TCD_CH17_ES_SBE_WIDTH (1U) 7397 #define DMA_TCD_CH17_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_ES_SBE_SHIFT)) & DMA_TCD_CH17_ES_SBE_MASK) 7398 7399 #define DMA_TCD_CH17_ES_SGE_MASK (0x4U) 7400 #define DMA_TCD_CH17_ES_SGE_SHIFT (2U) 7401 #define DMA_TCD_CH17_ES_SGE_WIDTH (1U) 7402 #define DMA_TCD_CH17_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_ES_SGE_SHIFT)) & DMA_TCD_CH17_ES_SGE_MASK) 7403 7404 #define DMA_TCD_CH17_ES_NCE_MASK (0x8U) 7405 #define DMA_TCD_CH17_ES_NCE_SHIFT (3U) 7406 #define DMA_TCD_CH17_ES_NCE_WIDTH (1U) 7407 #define DMA_TCD_CH17_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_ES_NCE_SHIFT)) & DMA_TCD_CH17_ES_NCE_MASK) 7408 7409 #define DMA_TCD_CH17_ES_DOE_MASK (0x10U) 7410 #define DMA_TCD_CH17_ES_DOE_SHIFT (4U) 7411 #define DMA_TCD_CH17_ES_DOE_WIDTH (1U) 7412 #define DMA_TCD_CH17_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_ES_DOE_SHIFT)) & DMA_TCD_CH17_ES_DOE_MASK) 7413 7414 #define DMA_TCD_CH17_ES_DAE_MASK (0x20U) 7415 #define DMA_TCD_CH17_ES_DAE_SHIFT (5U) 7416 #define DMA_TCD_CH17_ES_DAE_WIDTH (1U) 7417 #define DMA_TCD_CH17_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_ES_DAE_SHIFT)) & DMA_TCD_CH17_ES_DAE_MASK) 7418 7419 #define DMA_TCD_CH17_ES_SOE_MASK (0x40U) 7420 #define DMA_TCD_CH17_ES_SOE_SHIFT (6U) 7421 #define DMA_TCD_CH17_ES_SOE_WIDTH (1U) 7422 #define DMA_TCD_CH17_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_ES_SOE_SHIFT)) & DMA_TCD_CH17_ES_SOE_MASK) 7423 7424 #define DMA_TCD_CH17_ES_SAE_MASK (0x80U) 7425 #define DMA_TCD_CH17_ES_SAE_SHIFT (7U) 7426 #define DMA_TCD_CH17_ES_SAE_WIDTH (1U) 7427 #define DMA_TCD_CH17_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_ES_SAE_SHIFT)) & DMA_TCD_CH17_ES_SAE_MASK) 7428 7429 #define DMA_TCD_CH17_ES_ERR_MASK (0x80000000U) 7430 #define DMA_TCD_CH17_ES_ERR_SHIFT (31U) 7431 #define DMA_TCD_CH17_ES_ERR_WIDTH (1U) 7432 #define DMA_TCD_CH17_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_ES_ERR_SHIFT)) & DMA_TCD_CH17_ES_ERR_MASK) 7433 /*! @} */ 7434 7435 /*! @name CH17_INT - Channel Interrupt Status */ 7436 /*! @{ */ 7437 7438 #define DMA_TCD_CH17_INT_INT_MASK (0x1U) 7439 #define DMA_TCD_CH17_INT_INT_SHIFT (0U) 7440 #define DMA_TCD_CH17_INT_INT_WIDTH (1U) 7441 #define DMA_TCD_CH17_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_INT_INT_SHIFT)) & DMA_TCD_CH17_INT_INT_MASK) 7442 /*! @} */ 7443 7444 /*! @name CH17_SBR - Channel System Bus */ 7445 /*! @{ */ 7446 7447 #define DMA_TCD_CH17_SBR_MID_MASK (0xFU) 7448 #define DMA_TCD_CH17_SBR_MID_SHIFT (0U) 7449 #define DMA_TCD_CH17_SBR_MID_WIDTH (4U) 7450 #define DMA_TCD_CH17_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_SBR_MID_SHIFT)) & DMA_TCD_CH17_SBR_MID_MASK) 7451 7452 #define DMA_TCD_CH17_SBR_PAL_MASK (0x8000U) 7453 #define DMA_TCD_CH17_SBR_PAL_SHIFT (15U) 7454 #define DMA_TCD_CH17_SBR_PAL_WIDTH (1U) 7455 #define DMA_TCD_CH17_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_SBR_PAL_SHIFT)) & DMA_TCD_CH17_SBR_PAL_MASK) 7456 7457 #define DMA_TCD_CH17_SBR_EMI_MASK (0x10000U) 7458 #define DMA_TCD_CH17_SBR_EMI_SHIFT (16U) 7459 #define DMA_TCD_CH17_SBR_EMI_WIDTH (1U) 7460 #define DMA_TCD_CH17_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_SBR_EMI_SHIFT)) & DMA_TCD_CH17_SBR_EMI_MASK) 7461 7462 #define DMA_TCD_CH17_SBR_ATTR_MASK (0xE0000U) 7463 #define DMA_TCD_CH17_SBR_ATTR_SHIFT (17U) 7464 #define DMA_TCD_CH17_SBR_ATTR_WIDTH (3U) 7465 #define DMA_TCD_CH17_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_SBR_ATTR_SHIFT)) & DMA_TCD_CH17_SBR_ATTR_MASK) 7466 /*! @} */ 7467 7468 /*! @name CH17_PRI - Channel Priority */ 7469 /*! @{ */ 7470 7471 #define DMA_TCD_CH17_PRI_APL_MASK (0x7U) 7472 #define DMA_TCD_CH17_PRI_APL_SHIFT (0U) 7473 #define DMA_TCD_CH17_PRI_APL_WIDTH (3U) 7474 #define DMA_TCD_CH17_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_PRI_APL_SHIFT)) & DMA_TCD_CH17_PRI_APL_MASK) 7475 7476 #define DMA_TCD_CH17_PRI_DPA_MASK (0x40000000U) 7477 #define DMA_TCD_CH17_PRI_DPA_SHIFT (30U) 7478 #define DMA_TCD_CH17_PRI_DPA_WIDTH (1U) 7479 #define DMA_TCD_CH17_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_PRI_DPA_SHIFT)) & DMA_TCD_CH17_PRI_DPA_MASK) 7480 7481 #define DMA_TCD_CH17_PRI_ECP_MASK (0x80000000U) 7482 #define DMA_TCD_CH17_PRI_ECP_SHIFT (31U) 7483 #define DMA_TCD_CH17_PRI_ECP_WIDTH (1U) 7484 #define DMA_TCD_CH17_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH17_PRI_ECP_SHIFT)) & DMA_TCD_CH17_PRI_ECP_MASK) 7485 /*! @} */ 7486 7487 /*! @name TCD17_SADDR - TCD Source Address */ 7488 /*! @{ */ 7489 7490 #define DMA_TCD_TCD17_SADDR_SADDR_MASK (0xFFFFFFFFU) 7491 #define DMA_TCD_TCD17_SADDR_SADDR_SHIFT (0U) 7492 #define DMA_TCD_TCD17_SADDR_SADDR_WIDTH (32U) 7493 #define DMA_TCD_TCD17_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD17_SADDR_SADDR_MASK) 7494 /*! @} */ 7495 7496 /*! @name TCD17_SOFF - TCD Signed Source Address Offset */ 7497 /*! @{ */ 7498 7499 #define DMA_TCD_TCD17_SOFF_SOFF_MASK (0xFFFFU) 7500 #define DMA_TCD_TCD17_SOFF_SOFF_SHIFT (0U) 7501 #define DMA_TCD_TCD17_SOFF_SOFF_WIDTH (16U) 7502 #define DMA_TCD_TCD17_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD17_SOFF_SOFF_MASK) 7503 /*! @} */ 7504 7505 /*! @name TCD17_ATTR - TCD Transfer Attributes */ 7506 /*! @{ */ 7507 7508 #define DMA_TCD_TCD17_ATTR_DSIZE_MASK (0x7U) 7509 #define DMA_TCD_TCD17_ATTR_DSIZE_SHIFT (0U) 7510 #define DMA_TCD_TCD17_ATTR_DSIZE_WIDTH (3U) 7511 #define DMA_TCD_TCD17_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD17_ATTR_DSIZE_MASK) 7512 7513 #define DMA_TCD_TCD17_ATTR_DMOD_MASK (0xF8U) 7514 #define DMA_TCD_TCD17_ATTR_DMOD_SHIFT (3U) 7515 #define DMA_TCD_TCD17_ATTR_DMOD_WIDTH (5U) 7516 #define DMA_TCD_TCD17_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD17_ATTR_DMOD_MASK) 7517 7518 #define DMA_TCD_TCD17_ATTR_SSIZE_MASK (0x700U) 7519 #define DMA_TCD_TCD17_ATTR_SSIZE_SHIFT (8U) 7520 #define DMA_TCD_TCD17_ATTR_SSIZE_WIDTH (3U) 7521 #define DMA_TCD_TCD17_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD17_ATTR_SSIZE_MASK) 7522 7523 #define DMA_TCD_TCD17_ATTR_SMOD_MASK (0xF800U) 7524 #define DMA_TCD_TCD17_ATTR_SMOD_SHIFT (11U) 7525 #define DMA_TCD_TCD17_ATTR_SMOD_WIDTH (5U) 7526 #define DMA_TCD_TCD17_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD17_ATTR_SMOD_MASK) 7527 /*! @} */ 7528 7529 /*! @name TCD17_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 7530 /*! @{ */ 7531 7532 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 7533 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 7534 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 7535 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD17_NBYTES_MLOFFNO_NBYTES_MASK) 7536 7537 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 7538 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 7539 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 7540 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD17_NBYTES_MLOFFNO_DMLOE_MASK) 7541 7542 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 7543 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 7544 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 7545 #define DMA_TCD_TCD17_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD17_NBYTES_MLOFFNO_SMLOE_MASK) 7546 /*! @} */ 7547 7548 /*! @name TCD17_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 7549 /*! @{ */ 7550 7551 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 7552 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 7553 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 7554 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD17_NBYTES_MLOFFYES_NBYTES_MASK) 7555 7556 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 7557 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 7558 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 7559 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD17_NBYTES_MLOFFYES_MLOFF_MASK) 7560 7561 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 7562 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 7563 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 7564 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD17_NBYTES_MLOFFYES_DMLOE_MASK) 7565 7566 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 7567 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 7568 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 7569 #define DMA_TCD_TCD17_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD17_NBYTES_MLOFFYES_SMLOE_MASK) 7570 /*! @} */ 7571 7572 /*! @name TCD17_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 7573 /*! @{ */ 7574 7575 #define DMA_TCD_TCD17_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 7576 #define DMA_TCD_TCD17_SLAST_SDA_SLAST_SDA_SHIFT (0U) 7577 #define DMA_TCD_TCD17_SLAST_SDA_SLAST_SDA_WIDTH (32U) 7578 #define DMA_TCD_TCD17_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD17_SLAST_SDA_SLAST_SDA_MASK) 7579 /*! @} */ 7580 7581 /*! @name TCD17_DADDR - TCD Destination Address */ 7582 /*! @{ */ 7583 7584 #define DMA_TCD_TCD17_DADDR_DADDR_MASK (0xFFFFFFFFU) 7585 #define DMA_TCD_TCD17_DADDR_DADDR_SHIFT (0U) 7586 #define DMA_TCD_TCD17_DADDR_DADDR_WIDTH (32U) 7587 #define DMA_TCD_TCD17_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD17_DADDR_DADDR_MASK) 7588 /*! @} */ 7589 7590 /*! @name TCD17_DOFF - TCD Signed Destination Address Offset */ 7591 /*! @{ */ 7592 7593 #define DMA_TCD_TCD17_DOFF_DOFF_MASK (0xFFFFU) 7594 #define DMA_TCD_TCD17_DOFF_DOFF_SHIFT (0U) 7595 #define DMA_TCD_TCD17_DOFF_DOFF_WIDTH (16U) 7596 #define DMA_TCD_TCD17_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD17_DOFF_DOFF_MASK) 7597 /*! @} */ 7598 7599 /*! @name TCD17_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 7600 /*! @{ */ 7601 7602 #define DMA_TCD_TCD17_CITER_ELINKNO_CITER_MASK (0x7FFFU) 7603 #define DMA_TCD_TCD17_CITER_ELINKNO_CITER_SHIFT (0U) 7604 #define DMA_TCD_TCD17_CITER_ELINKNO_CITER_WIDTH (15U) 7605 #define DMA_TCD_TCD17_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD17_CITER_ELINKNO_CITER_MASK) 7606 7607 #define DMA_TCD_TCD17_CITER_ELINKNO_ELINK_MASK (0x8000U) 7608 #define DMA_TCD_TCD17_CITER_ELINKNO_ELINK_SHIFT (15U) 7609 #define DMA_TCD_TCD17_CITER_ELINKNO_ELINK_WIDTH (1U) 7610 #define DMA_TCD_TCD17_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD17_CITER_ELINKNO_ELINK_MASK) 7611 /*! @} */ 7612 7613 /*! @name TCD17_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 7614 /*! @{ */ 7615 7616 #define DMA_TCD_TCD17_CITER_ELINKYES_CITER_MASK (0x1FFU) 7617 #define DMA_TCD_TCD17_CITER_ELINKYES_CITER_SHIFT (0U) 7618 #define DMA_TCD_TCD17_CITER_ELINKYES_CITER_WIDTH (9U) 7619 #define DMA_TCD_TCD17_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD17_CITER_ELINKYES_CITER_MASK) 7620 7621 #define DMA_TCD_TCD17_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 7622 #define DMA_TCD_TCD17_CITER_ELINKYES_LINKCH_SHIFT (9U) 7623 #define DMA_TCD_TCD17_CITER_ELINKYES_LINKCH_WIDTH (5U) 7624 #define DMA_TCD_TCD17_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD17_CITER_ELINKYES_LINKCH_MASK) 7625 7626 #define DMA_TCD_TCD17_CITER_ELINKYES_ELINK_MASK (0x8000U) 7627 #define DMA_TCD_TCD17_CITER_ELINKYES_ELINK_SHIFT (15U) 7628 #define DMA_TCD_TCD17_CITER_ELINKYES_ELINK_WIDTH (1U) 7629 #define DMA_TCD_TCD17_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD17_CITER_ELINKYES_ELINK_MASK) 7630 /*! @} */ 7631 7632 /*! @name TCD17_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 7633 /*! @{ */ 7634 7635 #define DMA_TCD_TCD17_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 7636 #define DMA_TCD_TCD17_DLAST_SGA_DLAST_SGA_SHIFT (0U) 7637 #define DMA_TCD_TCD17_DLAST_SGA_DLAST_SGA_WIDTH (32U) 7638 #define DMA_TCD_TCD17_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD17_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD17_DLAST_SGA_DLAST_SGA_MASK) 7639 /*! @} */ 7640 7641 /*! @name TCD17_CSR - TCD Control and Status */ 7642 /*! @{ */ 7643 7644 #define DMA_TCD_TCD17_CSR_START_MASK (0x1U) 7645 #define DMA_TCD_TCD17_CSR_START_SHIFT (0U) 7646 #define DMA_TCD_TCD17_CSR_START_WIDTH (1U) 7647 #define DMA_TCD_TCD17_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CSR_START_SHIFT)) & DMA_TCD_TCD17_CSR_START_MASK) 7648 7649 #define DMA_TCD_TCD17_CSR_INTMAJOR_MASK (0x2U) 7650 #define DMA_TCD_TCD17_CSR_INTMAJOR_SHIFT (1U) 7651 #define DMA_TCD_TCD17_CSR_INTMAJOR_WIDTH (1U) 7652 #define DMA_TCD_TCD17_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD17_CSR_INTMAJOR_MASK) 7653 7654 #define DMA_TCD_TCD17_CSR_INTHALF_MASK (0x4U) 7655 #define DMA_TCD_TCD17_CSR_INTHALF_SHIFT (2U) 7656 #define DMA_TCD_TCD17_CSR_INTHALF_WIDTH (1U) 7657 #define DMA_TCD_TCD17_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD17_CSR_INTHALF_MASK) 7658 7659 #define DMA_TCD_TCD17_CSR_DREQ_MASK (0x8U) 7660 #define DMA_TCD_TCD17_CSR_DREQ_SHIFT (3U) 7661 #define DMA_TCD_TCD17_CSR_DREQ_WIDTH (1U) 7662 #define DMA_TCD_TCD17_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CSR_DREQ_SHIFT)) & DMA_TCD_TCD17_CSR_DREQ_MASK) 7663 7664 #define DMA_TCD_TCD17_CSR_ESG_MASK (0x10U) 7665 #define DMA_TCD_TCD17_CSR_ESG_SHIFT (4U) 7666 #define DMA_TCD_TCD17_CSR_ESG_WIDTH (1U) 7667 #define DMA_TCD_TCD17_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CSR_ESG_SHIFT)) & DMA_TCD_TCD17_CSR_ESG_MASK) 7668 7669 #define DMA_TCD_TCD17_CSR_MAJORELINK_MASK (0x20U) 7670 #define DMA_TCD_TCD17_CSR_MAJORELINK_SHIFT (5U) 7671 #define DMA_TCD_TCD17_CSR_MAJORELINK_WIDTH (1U) 7672 #define DMA_TCD_TCD17_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD17_CSR_MAJORELINK_MASK) 7673 7674 #define DMA_TCD_TCD17_CSR_EEOP_MASK (0x40U) 7675 #define DMA_TCD_TCD17_CSR_EEOP_SHIFT (6U) 7676 #define DMA_TCD_TCD17_CSR_EEOP_WIDTH (1U) 7677 #define DMA_TCD_TCD17_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CSR_EEOP_SHIFT)) & DMA_TCD_TCD17_CSR_EEOP_MASK) 7678 7679 #define DMA_TCD_TCD17_CSR_ESDA_MASK (0x80U) 7680 #define DMA_TCD_TCD17_CSR_ESDA_SHIFT (7U) 7681 #define DMA_TCD_TCD17_CSR_ESDA_WIDTH (1U) 7682 #define DMA_TCD_TCD17_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CSR_ESDA_SHIFT)) & DMA_TCD_TCD17_CSR_ESDA_MASK) 7683 7684 #define DMA_TCD_TCD17_CSR_MAJORLINKCH_MASK (0x1F00U) 7685 #define DMA_TCD_TCD17_CSR_MAJORLINKCH_SHIFT (8U) 7686 #define DMA_TCD_TCD17_CSR_MAJORLINKCH_WIDTH (5U) 7687 #define DMA_TCD_TCD17_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD17_CSR_MAJORLINKCH_MASK) 7688 7689 #define DMA_TCD_TCD17_CSR_BWC_MASK (0xC000U) 7690 #define DMA_TCD_TCD17_CSR_BWC_SHIFT (14U) 7691 #define DMA_TCD_TCD17_CSR_BWC_WIDTH (2U) 7692 #define DMA_TCD_TCD17_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_CSR_BWC_SHIFT)) & DMA_TCD_TCD17_CSR_BWC_MASK) 7693 /*! @} */ 7694 7695 /*! @name TCD17_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 7696 /*! @{ */ 7697 7698 #define DMA_TCD_TCD17_BITER_ELINKNO_BITER_MASK (0x7FFFU) 7699 #define DMA_TCD_TCD17_BITER_ELINKNO_BITER_SHIFT (0U) 7700 #define DMA_TCD_TCD17_BITER_ELINKNO_BITER_WIDTH (15U) 7701 #define DMA_TCD_TCD17_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD17_BITER_ELINKNO_BITER_MASK) 7702 7703 #define DMA_TCD_TCD17_BITER_ELINKNO_ELINK_MASK (0x8000U) 7704 #define DMA_TCD_TCD17_BITER_ELINKNO_ELINK_SHIFT (15U) 7705 #define DMA_TCD_TCD17_BITER_ELINKNO_ELINK_WIDTH (1U) 7706 #define DMA_TCD_TCD17_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD17_BITER_ELINKNO_ELINK_MASK) 7707 /*! @} */ 7708 7709 /*! @name TCD17_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 7710 /*! @{ */ 7711 7712 #define DMA_TCD_TCD17_BITER_ELINKYES_BITER_MASK (0x1FFU) 7713 #define DMA_TCD_TCD17_BITER_ELINKYES_BITER_SHIFT (0U) 7714 #define DMA_TCD_TCD17_BITER_ELINKYES_BITER_WIDTH (9U) 7715 #define DMA_TCD_TCD17_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD17_BITER_ELINKYES_BITER_MASK) 7716 7717 #define DMA_TCD_TCD17_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 7718 #define DMA_TCD_TCD17_BITER_ELINKYES_LINKCH_SHIFT (9U) 7719 #define DMA_TCD_TCD17_BITER_ELINKYES_LINKCH_WIDTH (5U) 7720 #define DMA_TCD_TCD17_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD17_BITER_ELINKYES_LINKCH_MASK) 7721 7722 #define DMA_TCD_TCD17_BITER_ELINKYES_ELINK_MASK (0x8000U) 7723 #define DMA_TCD_TCD17_BITER_ELINKYES_ELINK_SHIFT (15U) 7724 #define DMA_TCD_TCD17_BITER_ELINKYES_ELINK_WIDTH (1U) 7725 #define DMA_TCD_TCD17_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD17_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD17_BITER_ELINKYES_ELINK_MASK) 7726 /*! @} */ 7727 7728 /*! @name CH18_CSR - Channel Control and Status */ 7729 /*! @{ */ 7730 7731 #define DMA_TCD_CH18_CSR_ERQ_MASK (0x1U) 7732 #define DMA_TCD_CH18_CSR_ERQ_SHIFT (0U) 7733 #define DMA_TCD_CH18_CSR_ERQ_WIDTH (1U) 7734 #define DMA_TCD_CH18_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_CSR_ERQ_SHIFT)) & DMA_TCD_CH18_CSR_ERQ_MASK) 7735 7736 #define DMA_TCD_CH18_CSR_EARQ_MASK (0x2U) 7737 #define DMA_TCD_CH18_CSR_EARQ_SHIFT (1U) 7738 #define DMA_TCD_CH18_CSR_EARQ_WIDTH (1U) 7739 #define DMA_TCD_CH18_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_CSR_EARQ_SHIFT)) & DMA_TCD_CH18_CSR_EARQ_MASK) 7740 7741 #define DMA_TCD_CH18_CSR_EEI_MASK (0x4U) 7742 #define DMA_TCD_CH18_CSR_EEI_SHIFT (2U) 7743 #define DMA_TCD_CH18_CSR_EEI_WIDTH (1U) 7744 #define DMA_TCD_CH18_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_CSR_EEI_SHIFT)) & DMA_TCD_CH18_CSR_EEI_MASK) 7745 7746 #define DMA_TCD_CH18_CSR_EBW_MASK (0x8U) 7747 #define DMA_TCD_CH18_CSR_EBW_SHIFT (3U) 7748 #define DMA_TCD_CH18_CSR_EBW_WIDTH (1U) 7749 #define DMA_TCD_CH18_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_CSR_EBW_SHIFT)) & DMA_TCD_CH18_CSR_EBW_MASK) 7750 7751 #define DMA_TCD_CH18_CSR_DONE_MASK (0x40000000U) 7752 #define DMA_TCD_CH18_CSR_DONE_SHIFT (30U) 7753 #define DMA_TCD_CH18_CSR_DONE_WIDTH (1U) 7754 #define DMA_TCD_CH18_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_CSR_DONE_SHIFT)) & DMA_TCD_CH18_CSR_DONE_MASK) 7755 7756 #define DMA_TCD_CH18_CSR_ACTIVE_MASK (0x80000000U) 7757 #define DMA_TCD_CH18_CSR_ACTIVE_SHIFT (31U) 7758 #define DMA_TCD_CH18_CSR_ACTIVE_WIDTH (1U) 7759 #define DMA_TCD_CH18_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH18_CSR_ACTIVE_MASK) 7760 /*! @} */ 7761 7762 /*! @name CH18_ES - Channel Error Status */ 7763 /*! @{ */ 7764 7765 #define DMA_TCD_CH18_ES_DBE_MASK (0x1U) 7766 #define DMA_TCD_CH18_ES_DBE_SHIFT (0U) 7767 #define DMA_TCD_CH18_ES_DBE_WIDTH (1U) 7768 #define DMA_TCD_CH18_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_ES_DBE_SHIFT)) & DMA_TCD_CH18_ES_DBE_MASK) 7769 7770 #define DMA_TCD_CH18_ES_SBE_MASK (0x2U) 7771 #define DMA_TCD_CH18_ES_SBE_SHIFT (1U) 7772 #define DMA_TCD_CH18_ES_SBE_WIDTH (1U) 7773 #define DMA_TCD_CH18_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_ES_SBE_SHIFT)) & DMA_TCD_CH18_ES_SBE_MASK) 7774 7775 #define DMA_TCD_CH18_ES_SGE_MASK (0x4U) 7776 #define DMA_TCD_CH18_ES_SGE_SHIFT (2U) 7777 #define DMA_TCD_CH18_ES_SGE_WIDTH (1U) 7778 #define DMA_TCD_CH18_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_ES_SGE_SHIFT)) & DMA_TCD_CH18_ES_SGE_MASK) 7779 7780 #define DMA_TCD_CH18_ES_NCE_MASK (0x8U) 7781 #define DMA_TCD_CH18_ES_NCE_SHIFT (3U) 7782 #define DMA_TCD_CH18_ES_NCE_WIDTH (1U) 7783 #define DMA_TCD_CH18_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_ES_NCE_SHIFT)) & DMA_TCD_CH18_ES_NCE_MASK) 7784 7785 #define DMA_TCD_CH18_ES_DOE_MASK (0x10U) 7786 #define DMA_TCD_CH18_ES_DOE_SHIFT (4U) 7787 #define DMA_TCD_CH18_ES_DOE_WIDTH (1U) 7788 #define DMA_TCD_CH18_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_ES_DOE_SHIFT)) & DMA_TCD_CH18_ES_DOE_MASK) 7789 7790 #define DMA_TCD_CH18_ES_DAE_MASK (0x20U) 7791 #define DMA_TCD_CH18_ES_DAE_SHIFT (5U) 7792 #define DMA_TCD_CH18_ES_DAE_WIDTH (1U) 7793 #define DMA_TCD_CH18_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_ES_DAE_SHIFT)) & DMA_TCD_CH18_ES_DAE_MASK) 7794 7795 #define DMA_TCD_CH18_ES_SOE_MASK (0x40U) 7796 #define DMA_TCD_CH18_ES_SOE_SHIFT (6U) 7797 #define DMA_TCD_CH18_ES_SOE_WIDTH (1U) 7798 #define DMA_TCD_CH18_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_ES_SOE_SHIFT)) & DMA_TCD_CH18_ES_SOE_MASK) 7799 7800 #define DMA_TCD_CH18_ES_SAE_MASK (0x80U) 7801 #define DMA_TCD_CH18_ES_SAE_SHIFT (7U) 7802 #define DMA_TCD_CH18_ES_SAE_WIDTH (1U) 7803 #define DMA_TCD_CH18_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_ES_SAE_SHIFT)) & DMA_TCD_CH18_ES_SAE_MASK) 7804 7805 #define DMA_TCD_CH18_ES_ERR_MASK (0x80000000U) 7806 #define DMA_TCD_CH18_ES_ERR_SHIFT (31U) 7807 #define DMA_TCD_CH18_ES_ERR_WIDTH (1U) 7808 #define DMA_TCD_CH18_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_ES_ERR_SHIFT)) & DMA_TCD_CH18_ES_ERR_MASK) 7809 /*! @} */ 7810 7811 /*! @name CH18_INT - Channel Interrupt Status */ 7812 /*! @{ */ 7813 7814 #define DMA_TCD_CH18_INT_INT_MASK (0x1U) 7815 #define DMA_TCD_CH18_INT_INT_SHIFT (0U) 7816 #define DMA_TCD_CH18_INT_INT_WIDTH (1U) 7817 #define DMA_TCD_CH18_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_INT_INT_SHIFT)) & DMA_TCD_CH18_INT_INT_MASK) 7818 /*! @} */ 7819 7820 /*! @name CH18_SBR - Channel System Bus */ 7821 /*! @{ */ 7822 7823 #define DMA_TCD_CH18_SBR_MID_MASK (0xFU) 7824 #define DMA_TCD_CH18_SBR_MID_SHIFT (0U) 7825 #define DMA_TCD_CH18_SBR_MID_WIDTH (4U) 7826 #define DMA_TCD_CH18_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_SBR_MID_SHIFT)) & DMA_TCD_CH18_SBR_MID_MASK) 7827 7828 #define DMA_TCD_CH18_SBR_PAL_MASK (0x8000U) 7829 #define DMA_TCD_CH18_SBR_PAL_SHIFT (15U) 7830 #define DMA_TCD_CH18_SBR_PAL_WIDTH (1U) 7831 #define DMA_TCD_CH18_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_SBR_PAL_SHIFT)) & DMA_TCD_CH18_SBR_PAL_MASK) 7832 7833 #define DMA_TCD_CH18_SBR_EMI_MASK (0x10000U) 7834 #define DMA_TCD_CH18_SBR_EMI_SHIFT (16U) 7835 #define DMA_TCD_CH18_SBR_EMI_WIDTH (1U) 7836 #define DMA_TCD_CH18_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_SBR_EMI_SHIFT)) & DMA_TCD_CH18_SBR_EMI_MASK) 7837 7838 #define DMA_TCD_CH18_SBR_ATTR_MASK (0xE0000U) 7839 #define DMA_TCD_CH18_SBR_ATTR_SHIFT (17U) 7840 #define DMA_TCD_CH18_SBR_ATTR_WIDTH (3U) 7841 #define DMA_TCD_CH18_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_SBR_ATTR_SHIFT)) & DMA_TCD_CH18_SBR_ATTR_MASK) 7842 /*! @} */ 7843 7844 /*! @name CH18_PRI - Channel Priority */ 7845 /*! @{ */ 7846 7847 #define DMA_TCD_CH18_PRI_APL_MASK (0x7U) 7848 #define DMA_TCD_CH18_PRI_APL_SHIFT (0U) 7849 #define DMA_TCD_CH18_PRI_APL_WIDTH (3U) 7850 #define DMA_TCD_CH18_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_PRI_APL_SHIFT)) & DMA_TCD_CH18_PRI_APL_MASK) 7851 7852 #define DMA_TCD_CH18_PRI_DPA_MASK (0x40000000U) 7853 #define DMA_TCD_CH18_PRI_DPA_SHIFT (30U) 7854 #define DMA_TCD_CH18_PRI_DPA_WIDTH (1U) 7855 #define DMA_TCD_CH18_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_PRI_DPA_SHIFT)) & DMA_TCD_CH18_PRI_DPA_MASK) 7856 7857 #define DMA_TCD_CH18_PRI_ECP_MASK (0x80000000U) 7858 #define DMA_TCD_CH18_PRI_ECP_SHIFT (31U) 7859 #define DMA_TCD_CH18_PRI_ECP_WIDTH (1U) 7860 #define DMA_TCD_CH18_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH18_PRI_ECP_SHIFT)) & DMA_TCD_CH18_PRI_ECP_MASK) 7861 /*! @} */ 7862 7863 /*! @name TCD18_SADDR - TCD Source Address */ 7864 /*! @{ */ 7865 7866 #define DMA_TCD_TCD18_SADDR_SADDR_MASK (0xFFFFFFFFU) 7867 #define DMA_TCD_TCD18_SADDR_SADDR_SHIFT (0U) 7868 #define DMA_TCD_TCD18_SADDR_SADDR_WIDTH (32U) 7869 #define DMA_TCD_TCD18_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD18_SADDR_SADDR_MASK) 7870 /*! @} */ 7871 7872 /*! @name TCD18_SOFF - TCD Signed Source Address Offset */ 7873 /*! @{ */ 7874 7875 #define DMA_TCD_TCD18_SOFF_SOFF_MASK (0xFFFFU) 7876 #define DMA_TCD_TCD18_SOFF_SOFF_SHIFT (0U) 7877 #define DMA_TCD_TCD18_SOFF_SOFF_WIDTH (16U) 7878 #define DMA_TCD_TCD18_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD18_SOFF_SOFF_MASK) 7879 /*! @} */ 7880 7881 /*! @name TCD18_ATTR - TCD Transfer Attributes */ 7882 /*! @{ */ 7883 7884 #define DMA_TCD_TCD18_ATTR_DSIZE_MASK (0x7U) 7885 #define DMA_TCD_TCD18_ATTR_DSIZE_SHIFT (0U) 7886 #define DMA_TCD_TCD18_ATTR_DSIZE_WIDTH (3U) 7887 #define DMA_TCD_TCD18_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD18_ATTR_DSIZE_MASK) 7888 7889 #define DMA_TCD_TCD18_ATTR_DMOD_MASK (0xF8U) 7890 #define DMA_TCD_TCD18_ATTR_DMOD_SHIFT (3U) 7891 #define DMA_TCD_TCD18_ATTR_DMOD_WIDTH (5U) 7892 #define DMA_TCD_TCD18_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD18_ATTR_DMOD_MASK) 7893 7894 #define DMA_TCD_TCD18_ATTR_SSIZE_MASK (0x700U) 7895 #define DMA_TCD_TCD18_ATTR_SSIZE_SHIFT (8U) 7896 #define DMA_TCD_TCD18_ATTR_SSIZE_WIDTH (3U) 7897 #define DMA_TCD_TCD18_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD18_ATTR_SSIZE_MASK) 7898 7899 #define DMA_TCD_TCD18_ATTR_SMOD_MASK (0xF800U) 7900 #define DMA_TCD_TCD18_ATTR_SMOD_SHIFT (11U) 7901 #define DMA_TCD_TCD18_ATTR_SMOD_WIDTH (5U) 7902 #define DMA_TCD_TCD18_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD18_ATTR_SMOD_MASK) 7903 /*! @} */ 7904 7905 /*! @name TCD18_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 7906 /*! @{ */ 7907 7908 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 7909 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 7910 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 7911 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD18_NBYTES_MLOFFNO_NBYTES_MASK) 7912 7913 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 7914 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 7915 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 7916 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD18_NBYTES_MLOFFNO_DMLOE_MASK) 7917 7918 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 7919 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 7920 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 7921 #define DMA_TCD_TCD18_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD18_NBYTES_MLOFFNO_SMLOE_MASK) 7922 /*! @} */ 7923 7924 /*! @name TCD18_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 7925 /*! @{ */ 7926 7927 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 7928 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 7929 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 7930 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD18_NBYTES_MLOFFYES_NBYTES_MASK) 7931 7932 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 7933 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 7934 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 7935 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD18_NBYTES_MLOFFYES_MLOFF_MASK) 7936 7937 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 7938 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 7939 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 7940 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD18_NBYTES_MLOFFYES_DMLOE_MASK) 7941 7942 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 7943 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 7944 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 7945 #define DMA_TCD_TCD18_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD18_NBYTES_MLOFFYES_SMLOE_MASK) 7946 /*! @} */ 7947 7948 /*! @name TCD18_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 7949 /*! @{ */ 7950 7951 #define DMA_TCD_TCD18_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 7952 #define DMA_TCD_TCD18_SLAST_SDA_SLAST_SDA_SHIFT (0U) 7953 #define DMA_TCD_TCD18_SLAST_SDA_SLAST_SDA_WIDTH (32U) 7954 #define DMA_TCD_TCD18_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD18_SLAST_SDA_SLAST_SDA_MASK) 7955 /*! @} */ 7956 7957 /*! @name TCD18_DADDR - TCD Destination Address */ 7958 /*! @{ */ 7959 7960 #define DMA_TCD_TCD18_DADDR_DADDR_MASK (0xFFFFFFFFU) 7961 #define DMA_TCD_TCD18_DADDR_DADDR_SHIFT (0U) 7962 #define DMA_TCD_TCD18_DADDR_DADDR_WIDTH (32U) 7963 #define DMA_TCD_TCD18_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD18_DADDR_DADDR_MASK) 7964 /*! @} */ 7965 7966 /*! @name TCD18_DOFF - TCD Signed Destination Address Offset */ 7967 /*! @{ */ 7968 7969 #define DMA_TCD_TCD18_DOFF_DOFF_MASK (0xFFFFU) 7970 #define DMA_TCD_TCD18_DOFF_DOFF_SHIFT (0U) 7971 #define DMA_TCD_TCD18_DOFF_DOFF_WIDTH (16U) 7972 #define DMA_TCD_TCD18_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD18_DOFF_DOFF_MASK) 7973 /*! @} */ 7974 7975 /*! @name TCD18_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 7976 /*! @{ */ 7977 7978 #define DMA_TCD_TCD18_CITER_ELINKNO_CITER_MASK (0x7FFFU) 7979 #define DMA_TCD_TCD18_CITER_ELINKNO_CITER_SHIFT (0U) 7980 #define DMA_TCD_TCD18_CITER_ELINKNO_CITER_WIDTH (15U) 7981 #define DMA_TCD_TCD18_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD18_CITER_ELINKNO_CITER_MASK) 7982 7983 #define DMA_TCD_TCD18_CITER_ELINKNO_ELINK_MASK (0x8000U) 7984 #define DMA_TCD_TCD18_CITER_ELINKNO_ELINK_SHIFT (15U) 7985 #define DMA_TCD_TCD18_CITER_ELINKNO_ELINK_WIDTH (1U) 7986 #define DMA_TCD_TCD18_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD18_CITER_ELINKNO_ELINK_MASK) 7987 /*! @} */ 7988 7989 /*! @name TCD18_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 7990 /*! @{ */ 7991 7992 #define DMA_TCD_TCD18_CITER_ELINKYES_CITER_MASK (0x1FFU) 7993 #define DMA_TCD_TCD18_CITER_ELINKYES_CITER_SHIFT (0U) 7994 #define DMA_TCD_TCD18_CITER_ELINKYES_CITER_WIDTH (9U) 7995 #define DMA_TCD_TCD18_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD18_CITER_ELINKYES_CITER_MASK) 7996 7997 #define DMA_TCD_TCD18_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 7998 #define DMA_TCD_TCD18_CITER_ELINKYES_LINKCH_SHIFT (9U) 7999 #define DMA_TCD_TCD18_CITER_ELINKYES_LINKCH_WIDTH (5U) 8000 #define DMA_TCD_TCD18_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD18_CITER_ELINKYES_LINKCH_MASK) 8001 8002 #define DMA_TCD_TCD18_CITER_ELINKYES_ELINK_MASK (0x8000U) 8003 #define DMA_TCD_TCD18_CITER_ELINKYES_ELINK_SHIFT (15U) 8004 #define DMA_TCD_TCD18_CITER_ELINKYES_ELINK_WIDTH (1U) 8005 #define DMA_TCD_TCD18_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD18_CITER_ELINKYES_ELINK_MASK) 8006 /*! @} */ 8007 8008 /*! @name TCD18_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 8009 /*! @{ */ 8010 8011 #define DMA_TCD_TCD18_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 8012 #define DMA_TCD_TCD18_DLAST_SGA_DLAST_SGA_SHIFT (0U) 8013 #define DMA_TCD_TCD18_DLAST_SGA_DLAST_SGA_WIDTH (32U) 8014 #define DMA_TCD_TCD18_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD18_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD18_DLAST_SGA_DLAST_SGA_MASK) 8015 /*! @} */ 8016 8017 /*! @name TCD18_CSR - TCD Control and Status */ 8018 /*! @{ */ 8019 8020 #define DMA_TCD_TCD18_CSR_START_MASK (0x1U) 8021 #define DMA_TCD_TCD18_CSR_START_SHIFT (0U) 8022 #define DMA_TCD_TCD18_CSR_START_WIDTH (1U) 8023 #define DMA_TCD_TCD18_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CSR_START_SHIFT)) & DMA_TCD_TCD18_CSR_START_MASK) 8024 8025 #define DMA_TCD_TCD18_CSR_INTMAJOR_MASK (0x2U) 8026 #define DMA_TCD_TCD18_CSR_INTMAJOR_SHIFT (1U) 8027 #define DMA_TCD_TCD18_CSR_INTMAJOR_WIDTH (1U) 8028 #define DMA_TCD_TCD18_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD18_CSR_INTMAJOR_MASK) 8029 8030 #define DMA_TCD_TCD18_CSR_INTHALF_MASK (0x4U) 8031 #define DMA_TCD_TCD18_CSR_INTHALF_SHIFT (2U) 8032 #define DMA_TCD_TCD18_CSR_INTHALF_WIDTH (1U) 8033 #define DMA_TCD_TCD18_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD18_CSR_INTHALF_MASK) 8034 8035 #define DMA_TCD_TCD18_CSR_DREQ_MASK (0x8U) 8036 #define DMA_TCD_TCD18_CSR_DREQ_SHIFT (3U) 8037 #define DMA_TCD_TCD18_CSR_DREQ_WIDTH (1U) 8038 #define DMA_TCD_TCD18_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CSR_DREQ_SHIFT)) & DMA_TCD_TCD18_CSR_DREQ_MASK) 8039 8040 #define DMA_TCD_TCD18_CSR_ESG_MASK (0x10U) 8041 #define DMA_TCD_TCD18_CSR_ESG_SHIFT (4U) 8042 #define DMA_TCD_TCD18_CSR_ESG_WIDTH (1U) 8043 #define DMA_TCD_TCD18_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CSR_ESG_SHIFT)) & DMA_TCD_TCD18_CSR_ESG_MASK) 8044 8045 #define DMA_TCD_TCD18_CSR_MAJORELINK_MASK (0x20U) 8046 #define DMA_TCD_TCD18_CSR_MAJORELINK_SHIFT (5U) 8047 #define DMA_TCD_TCD18_CSR_MAJORELINK_WIDTH (1U) 8048 #define DMA_TCD_TCD18_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD18_CSR_MAJORELINK_MASK) 8049 8050 #define DMA_TCD_TCD18_CSR_EEOP_MASK (0x40U) 8051 #define DMA_TCD_TCD18_CSR_EEOP_SHIFT (6U) 8052 #define DMA_TCD_TCD18_CSR_EEOP_WIDTH (1U) 8053 #define DMA_TCD_TCD18_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CSR_EEOP_SHIFT)) & DMA_TCD_TCD18_CSR_EEOP_MASK) 8054 8055 #define DMA_TCD_TCD18_CSR_ESDA_MASK (0x80U) 8056 #define DMA_TCD_TCD18_CSR_ESDA_SHIFT (7U) 8057 #define DMA_TCD_TCD18_CSR_ESDA_WIDTH (1U) 8058 #define DMA_TCD_TCD18_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CSR_ESDA_SHIFT)) & DMA_TCD_TCD18_CSR_ESDA_MASK) 8059 8060 #define DMA_TCD_TCD18_CSR_MAJORLINKCH_MASK (0x1F00U) 8061 #define DMA_TCD_TCD18_CSR_MAJORLINKCH_SHIFT (8U) 8062 #define DMA_TCD_TCD18_CSR_MAJORLINKCH_WIDTH (5U) 8063 #define DMA_TCD_TCD18_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD18_CSR_MAJORLINKCH_MASK) 8064 8065 #define DMA_TCD_TCD18_CSR_BWC_MASK (0xC000U) 8066 #define DMA_TCD_TCD18_CSR_BWC_SHIFT (14U) 8067 #define DMA_TCD_TCD18_CSR_BWC_WIDTH (2U) 8068 #define DMA_TCD_TCD18_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_CSR_BWC_SHIFT)) & DMA_TCD_TCD18_CSR_BWC_MASK) 8069 /*! @} */ 8070 8071 /*! @name TCD18_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 8072 /*! @{ */ 8073 8074 #define DMA_TCD_TCD18_BITER_ELINKNO_BITER_MASK (0x7FFFU) 8075 #define DMA_TCD_TCD18_BITER_ELINKNO_BITER_SHIFT (0U) 8076 #define DMA_TCD_TCD18_BITER_ELINKNO_BITER_WIDTH (15U) 8077 #define DMA_TCD_TCD18_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD18_BITER_ELINKNO_BITER_MASK) 8078 8079 #define DMA_TCD_TCD18_BITER_ELINKNO_ELINK_MASK (0x8000U) 8080 #define DMA_TCD_TCD18_BITER_ELINKNO_ELINK_SHIFT (15U) 8081 #define DMA_TCD_TCD18_BITER_ELINKNO_ELINK_WIDTH (1U) 8082 #define DMA_TCD_TCD18_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD18_BITER_ELINKNO_ELINK_MASK) 8083 /*! @} */ 8084 8085 /*! @name TCD18_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 8086 /*! @{ */ 8087 8088 #define DMA_TCD_TCD18_BITER_ELINKYES_BITER_MASK (0x1FFU) 8089 #define DMA_TCD_TCD18_BITER_ELINKYES_BITER_SHIFT (0U) 8090 #define DMA_TCD_TCD18_BITER_ELINKYES_BITER_WIDTH (9U) 8091 #define DMA_TCD_TCD18_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD18_BITER_ELINKYES_BITER_MASK) 8092 8093 #define DMA_TCD_TCD18_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 8094 #define DMA_TCD_TCD18_BITER_ELINKYES_LINKCH_SHIFT (9U) 8095 #define DMA_TCD_TCD18_BITER_ELINKYES_LINKCH_WIDTH (5U) 8096 #define DMA_TCD_TCD18_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD18_BITER_ELINKYES_LINKCH_MASK) 8097 8098 #define DMA_TCD_TCD18_BITER_ELINKYES_ELINK_MASK (0x8000U) 8099 #define DMA_TCD_TCD18_BITER_ELINKYES_ELINK_SHIFT (15U) 8100 #define DMA_TCD_TCD18_BITER_ELINKYES_ELINK_WIDTH (1U) 8101 #define DMA_TCD_TCD18_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD18_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD18_BITER_ELINKYES_ELINK_MASK) 8102 /*! @} */ 8103 8104 /*! @name CH19_CSR - Channel Control and Status */ 8105 /*! @{ */ 8106 8107 #define DMA_TCD_CH19_CSR_ERQ_MASK (0x1U) 8108 #define DMA_TCD_CH19_CSR_ERQ_SHIFT (0U) 8109 #define DMA_TCD_CH19_CSR_ERQ_WIDTH (1U) 8110 #define DMA_TCD_CH19_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_CSR_ERQ_SHIFT)) & DMA_TCD_CH19_CSR_ERQ_MASK) 8111 8112 #define DMA_TCD_CH19_CSR_EARQ_MASK (0x2U) 8113 #define DMA_TCD_CH19_CSR_EARQ_SHIFT (1U) 8114 #define DMA_TCD_CH19_CSR_EARQ_WIDTH (1U) 8115 #define DMA_TCD_CH19_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_CSR_EARQ_SHIFT)) & DMA_TCD_CH19_CSR_EARQ_MASK) 8116 8117 #define DMA_TCD_CH19_CSR_EEI_MASK (0x4U) 8118 #define DMA_TCD_CH19_CSR_EEI_SHIFT (2U) 8119 #define DMA_TCD_CH19_CSR_EEI_WIDTH (1U) 8120 #define DMA_TCD_CH19_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_CSR_EEI_SHIFT)) & DMA_TCD_CH19_CSR_EEI_MASK) 8121 8122 #define DMA_TCD_CH19_CSR_EBW_MASK (0x8U) 8123 #define DMA_TCD_CH19_CSR_EBW_SHIFT (3U) 8124 #define DMA_TCD_CH19_CSR_EBW_WIDTH (1U) 8125 #define DMA_TCD_CH19_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_CSR_EBW_SHIFT)) & DMA_TCD_CH19_CSR_EBW_MASK) 8126 8127 #define DMA_TCD_CH19_CSR_DONE_MASK (0x40000000U) 8128 #define DMA_TCD_CH19_CSR_DONE_SHIFT (30U) 8129 #define DMA_TCD_CH19_CSR_DONE_WIDTH (1U) 8130 #define DMA_TCD_CH19_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_CSR_DONE_SHIFT)) & DMA_TCD_CH19_CSR_DONE_MASK) 8131 8132 #define DMA_TCD_CH19_CSR_ACTIVE_MASK (0x80000000U) 8133 #define DMA_TCD_CH19_CSR_ACTIVE_SHIFT (31U) 8134 #define DMA_TCD_CH19_CSR_ACTIVE_WIDTH (1U) 8135 #define DMA_TCD_CH19_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH19_CSR_ACTIVE_MASK) 8136 /*! @} */ 8137 8138 /*! @name CH19_ES - Channel Error Status */ 8139 /*! @{ */ 8140 8141 #define DMA_TCD_CH19_ES_DBE_MASK (0x1U) 8142 #define DMA_TCD_CH19_ES_DBE_SHIFT (0U) 8143 #define DMA_TCD_CH19_ES_DBE_WIDTH (1U) 8144 #define DMA_TCD_CH19_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_ES_DBE_SHIFT)) & DMA_TCD_CH19_ES_DBE_MASK) 8145 8146 #define DMA_TCD_CH19_ES_SBE_MASK (0x2U) 8147 #define DMA_TCD_CH19_ES_SBE_SHIFT (1U) 8148 #define DMA_TCD_CH19_ES_SBE_WIDTH (1U) 8149 #define DMA_TCD_CH19_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_ES_SBE_SHIFT)) & DMA_TCD_CH19_ES_SBE_MASK) 8150 8151 #define DMA_TCD_CH19_ES_SGE_MASK (0x4U) 8152 #define DMA_TCD_CH19_ES_SGE_SHIFT (2U) 8153 #define DMA_TCD_CH19_ES_SGE_WIDTH (1U) 8154 #define DMA_TCD_CH19_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_ES_SGE_SHIFT)) & DMA_TCD_CH19_ES_SGE_MASK) 8155 8156 #define DMA_TCD_CH19_ES_NCE_MASK (0x8U) 8157 #define DMA_TCD_CH19_ES_NCE_SHIFT (3U) 8158 #define DMA_TCD_CH19_ES_NCE_WIDTH (1U) 8159 #define DMA_TCD_CH19_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_ES_NCE_SHIFT)) & DMA_TCD_CH19_ES_NCE_MASK) 8160 8161 #define DMA_TCD_CH19_ES_DOE_MASK (0x10U) 8162 #define DMA_TCD_CH19_ES_DOE_SHIFT (4U) 8163 #define DMA_TCD_CH19_ES_DOE_WIDTH (1U) 8164 #define DMA_TCD_CH19_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_ES_DOE_SHIFT)) & DMA_TCD_CH19_ES_DOE_MASK) 8165 8166 #define DMA_TCD_CH19_ES_DAE_MASK (0x20U) 8167 #define DMA_TCD_CH19_ES_DAE_SHIFT (5U) 8168 #define DMA_TCD_CH19_ES_DAE_WIDTH (1U) 8169 #define DMA_TCD_CH19_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_ES_DAE_SHIFT)) & DMA_TCD_CH19_ES_DAE_MASK) 8170 8171 #define DMA_TCD_CH19_ES_SOE_MASK (0x40U) 8172 #define DMA_TCD_CH19_ES_SOE_SHIFT (6U) 8173 #define DMA_TCD_CH19_ES_SOE_WIDTH (1U) 8174 #define DMA_TCD_CH19_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_ES_SOE_SHIFT)) & DMA_TCD_CH19_ES_SOE_MASK) 8175 8176 #define DMA_TCD_CH19_ES_SAE_MASK (0x80U) 8177 #define DMA_TCD_CH19_ES_SAE_SHIFT (7U) 8178 #define DMA_TCD_CH19_ES_SAE_WIDTH (1U) 8179 #define DMA_TCD_CH19_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_ES_SAE_SHIFT)) & DMA_TCD_CH19_ES_SAE_MASK) 8180 8181 #define DMA_TCD_CH19_ES_ERR_MASK (0x80000000U) 8182 #define DMA_TCD_CH19_ES_ERR_SHIFT (31U) 8183 #define DMA_TCD_CH19_ES_ERR_WIDTH (1U) 8184 #define DMA_TCD_CH19_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_ES_ERR_SHIFT)) & DMA_TCD_CH19_ES_ERR_MASK) 8185 /*! @} */ 8186 8187 /*! @name CH19_INT - Channel Interrupt Status */ 8188 /*! @{ */ 8189 8190 #define DMA_TCD_CH19_INT_INT_MASK (0x1U) 8191 #define DMA_TCD_CH19_INT_INT_SHIFT (0U) 8192 #define DMA_TCD_CH19_INT_INT_WIDTH (1U) 8193 #define DMA_TCD_CH19_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_INT_INT_SHIFT)) & DMA_TCD_CH19_INT_INT_MASK) 8194 /*! @} */ 8195 8196 /*! @name CH19_SBR - Channel System Bus */ 8197 /*! @{ */ 8198 8199 #define DMA_TCD_CH19_SBR_MID_MASK (0xFU) 8200 #define DMA_TCD_CH19_SBR_MID_SHIFT (0U) 8201 #define DMA_TCD_CH19_SBR_MID_WIDTH (4U) 8202 #define DMA_TCD_CH19_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_SBR_MID_SHIFT)) & DMA_TCD_CH19_SBR_MID_MASK) 8203 8204 #define DMA_TCD_CH19_SBR_PAL_MASK (0x8000U) 8205 #define DMA_TCD_CH19_SBR_PAL_SHIFT (15U) 8206 #define DMA_TCD_CH19_SBR_PAL_WIDTH (1U) 8207 #define DMA_TCD_CH19_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_SBR_PAL_SHIFT)) & DMA_TCD_CH19_SBR_PAL_MASK) 8208 8209 #define DMA_TCD_CH19_SBR_EMI_MASK (0x10000U) 8210 #define DMA_TCD_CH19_SBR_EMI_SHIFT (16U) 8211 #define DMA_TCD_CH19_SBR_EMI_WIDTH (1U) 8212 #define DMA_TCD_CH19_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_SBR_EMI_SHIFT)) & DMA_TCD_CH19_SBR_EMI_MASK) 8213 8214 #define DMA_TCD_CH19_SBR_ATTR_MASK (0xE0000U) 8215 #define DMA_TCD_CH19_SBR_ATTR_SHIFT (17U) 8216 #define DMA_TCD_CH19_SBR_ATTR_WIDTH (3U) 8217 #define DMA_TCD_CH19_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_SBR_ATTR_SHIFT)) & DMA_TCD_CH19_SBR_ATTR_MASK) 8218 /*! @} */ 8219 8220 /*! @name CH19_PRI - Channel Priority */ 8221 /*! @{ */ 8222 8223 #define DMA_TCD_CH19_PRI_APL_MASK (0x7U) 8224 #define DMA_TCD_CH19_PRI_APL_SHIFT (0U) 8225 #define DMA_TCD_CH19_PRI_APL_WIDTH (3U) 8226 #define DMA_TCD_CH19_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_PRI_APL_SHIFT)) & DMA_TCD_CH19_PRI_APL_MASK) 8227 8228 #define DMA_TCD_CH19_PRI_DPA_MASK (0x40000000U) 8229 #define DMA_TCD_CH19_PRI_DPA_SHIFT (30U) 8230 #define DMA_TCD_CH19_PRI_DPA_WIDTH (1U) 8231 #define DMA_TCD_CH19_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_PRI_DPA_SHIFT)) & DMA_TCD_CH19_PRI_DPA_MASK) 8232 8233 #define DMA_TCD_CH19_PRI_ECP_MASK (0x80000000U) 8234 #define DMA_TCD_CH19_PRI_ECP_SHIFT (31U) 8235 #define DMA_TCD_CH19_PRI_ECP_WIDTH (1U) 8236 #define DMA_TCD_CH19_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH19_PRI_ECP_SHIFT)) & DMA_TCD_CH19_PRI_ECP_MASK) 8237 /*! @} */ 8238 8239 /*! @name TCD19_SADDR - TCD Source Address */ 8240 /*! @{ */ 8241 8242 #define DMA_TCD_TCD19_SADDR_SADDR_MASK (0xFFFFFFFFU) 8243 #define DMA_TCD_TCD19_SADDR_SADDR_SHIFT (0U) 8244 #define DMA_TCD_TCD19_SADDR_SADDR_WIDTH (32U) 8245 #define DMA_TCD_TCD19_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD19_SADDR_SADDR_MASK) 8246 /*! @} */ 8247 8248 /*! @name TCD19_SOFF - TCD Signed Source Address Offset */ 8249 /*! @{ */ 8250 8251 #define DMA_TCD_TCD19_SOFF_SOFF_MASK (0xFFFFU) 8252 #define DMA_TCD_TCD19_SOFF_SOFF_SHIFT (0U) 8253 #define DMA_TCD_TCD19_SOFF_SOFF_WIDTH (16U) 8254 #define DMA_TCD_TCD19_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD19_SOFF_SOFF_MASK) 8255 /*! @} */ 8256 8257 /*! @name TCD19_ATTR - TCD Transfer Attributes */ 8258 /*! @{ */ 8259 8260 #define DMA_TCD_TCD19_ATTR_DSIZE_MASK (0x7U) 8261 #define DMA_TCD_TCD19_ATTR_DSIZE_SHIFT (0U) 8262 #define DMA_TCD_TCD19_ATTR_DSIZE_WIDTH (3U) 8263 #define DMA_TCD_TCD19_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD19_ATTR_DSIZE_MASK) 8264 8265 #define DMA_TCD_TCD19_ATTR_DMOD_MASK (0xF8U) 8266 #define DMA_TCD_TCD19_ATTR_DMOD_SHIFT (3U) 8267 #define DMA_TCD_TCD19_ATTR_DMOD_WIDTH (5U) 8268 #define DMA_TCD_TCD19_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD19_ATTR_DMOD_MASK) 8269 8270 #define DMA_TCD_TCD19_ATTR_SSIZE_MASK (0x700U) 8271 #define DMA_TCD_TCD19_ATTR_SSIZE_SHIFT (8U) 8272 #define DMA_TCD_TCD19_ATTR_SSIZE_WIDTH (3U) 8273 #define DMA_TCD_TCD19_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD19_ATTR_SSIZE_MASK) 8274 8275 #define DMA_TCD_TCD19_ATTR_SMOD_MASK (0xF800U) 8276 #define DMA_TCD_TCD19_ATTR_SMOD_SHIFT (11U) 8277 #define DMA_TCD_TCD19_ATTR_SMOD_WIDTH (5U) 8278 #define DMA_TCD_TCD19_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD19_ATTR_SMOD_MASK) 8279 /*! @} */ 8280 8281 /*! @name TCD19_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 8282 /*! @{ */ 8283 8284 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 8285 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 8286 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 8287 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD19_NBYTES_MLOFFNO_NBYTES_MASK) 8288 8289 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 8290 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 8291 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 8292 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD19_NBYTES_MLOFFNO_DMLOE_MASK) 8293 8294 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 8295 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 8296 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 8297 #define DMA_TCD_TCD19_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD19_NBYTES_MLOFFNO_SMLOE_MASK) 8298 /*! @} */ 8299 8300 /*! @name TCD19_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 8301 /*! @{ */ 8302 8303 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 8304 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 8305 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 8306 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD19_NBYTES_MLOFFYES_NBYTES_MASK) 8307 8308 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 8309 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 8310 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 8311 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD19_NBYTES_MLOFFYES_MLOFF_MASK) 8312 8313 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 8314 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 8315 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 8316 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD19_NBYTES_MLOFFYES_DMLOE_MASK) 8317 8318 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 8319 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 8320 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 8321 #define DMA_TCD_TCD19_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD19_NBYTES_MLOFFYES_SMLOE_MASK) 8322 /*! @} */ 8323 8324 /*! @name TCD19_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 8325 /*! @{ */ 8326 8327 #define DMA_TCD_TCD19_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 8328 #define DMA_TCD_TCD19_SLAST_SDA_SLAST_SDA_SHIFT (0U) 8329 #define DMA_TCD_TCD19_SLAST_SDA_SLAST_SDA_WIDTH (32U) 8330 #define DMA_TCD_TCD19_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD19_SLAST_SDA_SLAST_SDA_MASK) 8331 /*! @} */ 8332 8333 /*! @name TCD19_DADDR - TCD Destination Address */ 8334 /*! @{ */ 8335 8336 #define DMA_TCD_TCD19_DADDR_DADDR_MASK (0xFFFFFFFFU) 8337 #define DMA_TCD_TCD19_DADDR_DADDR_SHIFT (0U) 8338 #define DMA_TCD_TCD19_DADDR_DADDR_WIDTH (32U) 8339 #define DMA_TCD_TCD19_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD19_DADDR_DADDR_MASK) 8340 /*! @} */ 8341 8342 /*! @name TCD19_DOFF - TCD Signed Destination Address Offset */ 8343 /*! @{ */ 8344 8345 #define DMA_TCD_TCD19_DOFF_DOFF_MASK (0xFFFFU) 8346 #define DMA_TCD_TCD19_DOFF_DOFF_SHIFT (0U) 8347 #define DMA_TCD_TCD19_DOFF_DOFF_WIDTH (16U) 8348 #define DMA_TCD_TCD19_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD19_DOFF_DOFF_MASK) 8349 /*! @} */ 8350 8351 /*! @name TCD19_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 8352 /*! @{ */ 8353 8354 #define DMA_TCD_TCD19_CITER_ELINKNO_CITER_MASK (0x7FFFU) 8355 #define DMA_TCD_TCD19_CITER_ELINKNO_CITER_SHIFT (0U) 8356 #define DMA_TCD_TCD19_CITER_ELINKNO_CITER_WIDTH (15U) 8357 #define DMA_TCD_TCD19_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD19_CITER_ELINKNO_CITER_MASK) 8358 8359 #define DMA_TCD_TCD19_CITER_ELINKNO_ELINK_MASK (0x8000U) 8360 #define DMA_TCD_TCD19_CITER_ELINKNO_ELINK_SHIFT (15U) 8361 #define DMA_TCD_TCD19_CITER_ELINKNO_ELINK_WIDTH (1U) 8362 #define DMA_TCD_TCD19_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD19_CITER_ELINKNO_ELINK_MASK) 8363 /*! @} */ 8364 8365 /*! @name TCD19_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 8366 /*! @{ */ 8367 8368 #define DMA_TCD_TCD19_CITER_ELINKYES_CITER_MASK (0x1FFU) 8369 #define DMA_TCD_TCD19_CITER_ELINKYES_CITER_SHIFT (0U) 8370 #define DMA_TCD_TCD19_CITER_ELINKYES_CITER_WIDTH (9U) 8371 #define DMA_TCD_TCD19_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD19_CITER_ELINKYES_CITER_MASK) 8372 8373 #define DMA_TCD_TCD19_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 8374 #define DMA_TCD_TCD19_CITER_ELINKYES_LINKCH_SHIFT (9U) 8375 #define DMA_TCD_TCD19_CITER_ELINKYES_LINKCH_WIDTH (5U) 8376 #define DMA_TCD_TCD19_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD19_CITER_ELINKYES_LINKCH_MASK) 8377 8378 #define DMA_TCD_TCD19_CITER_ELINKYES_ELINK_MASK (0x8000U) 8379 #define DMA_TCD_TCD19_CITER_ELINKYES_ELINK_SHIFT (15U) 8380 #define DMA_TCD_TCD19_CITER_ELINKYES_ELINK_WIDTH (1U) 8381 #define DMA_TCD_TCD19_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD19_CITER_ELINKYES_ELINK_MASK) 8382 /*! @} */ 8383 8384 /*! @name TCD19_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 8385 /*! @{ */ 8386 8387 #define DMA_TCD_TCD19_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 8388 #define DMA_TCD_TCD19_DLAST_SGA_DLAST_SGA_SHIFT (0U) 8389 #define DMA_TCD_TCD19_DLAST_SGA_DLAST_SGA_WIDTH (32U) 8390 #define DMA_TCD_TCD19_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD19_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD19_DLAST_SGA_DLAST_SGA_MASK) 8391 /*! @} */ 8392 8393 /*! @name TCD19_CSR - TCD Control and Status */ 8394 /*! @{ */ 8395 8396 #define DMA_TCD_TCD19_CSR_START_MASK (0x1U) 8397 #define DMA_TCD_TCD19_CSR_START_SHIFT (0U) 8398 #define DMA_TCD_TCD19_CSR_START_WIDTH (1U) 8399 #define DMA_TCD_TCD19_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CSR_START_SHIFT)) & DMA_TCD_TCD19_CSR_START_MASK) 8400 8401 #define DMA_TCD_TCD19_CSR_INTMAJOR_MASK (0x2U) 8402 #define DMA_TCD_TCD19_CSR_INTMAJOR_SHIFT (1U) 8403 #define DMA_TCD_TCD19_CSR_INTMAJOR_WIDTH (1U) 8404 #define DMA_TCD_TCD19_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD19_CSR_INTMAJOR_MASK) 8405 8406 #define DMA_TCD_TCD19_CSR_INTHALF_MASK (0x4U) 8407 #define DMA_TCD_TCD19_CSR_INTHALF_SHIFT (2U) 8408 #define DMA_TCD_TCD19_CSR_INTHALF_WIDTH (1U) 8409 #define DMA_TCD_TCD19_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD19_CSR_INTHALF_MASK) 8410 8411 #define DMA_TCD_TCD19_CSR_DREQ_MASK (0x8U) 8412 #define DMA_TCD_TCD19_CSR_DREQ_SHIFT (3U) 8413 #define DMA_TCD_TCD19_CSR_DREQ_WIDTH (1U) 8414 #define DMA_TCD_TCD19_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CSR_DREQ_SHIFT)) & DMA_TCD_TCD19_CSR_DREQ_MASK) 8415 8416 #define DMA_TCD_TCD19_CSR_ESG_MASK (0x10U) 8417 #define DMA_TCD_TCD19_CSR_ESG_SHIFT (4U) 8418 #define DMA_TCD_TCD19_CSR_ESG_WIDTH (1U) 8419 #define DMA_TCD_TCD19_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CSR_ESG_SHIFT)) & DMA_TCD_TCD19_CSR_ESG_MASK) 8420 8421 #define DMA_TCD_TCD19_CSR_MAJORELINK_MASK (0x20U) 8422 #define DMA_TCD_TCD19_CSR_MAJORELINK_SHIFT (5U) 8423 #define DMA_TCD_TCD19_CSR_MAJORELINK_WIDTH (1U) 8424 #define DMA_TCD_TCD19_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD19_CSR_MAJORELINK_MASK) 8425 8426 #define DMA_TCD_TCD19_CSR_EEOP_MASK (0x40U) 8427 #define DMA_TCD_TCD19_CSR_EEOP_SHIFT (6U) 8428 #define DMA_TCD_TCD19_CSR_EEOP_WIDTH (1U) 8429 #define DMA_TCD_TCD19_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CSR_EEOP_SHIFT)) & DMA_TCD_TCD19_CSR_EEOP_MASK) 8430 8431 #define DMA_TCD_TCD19_CSR_ESDA_MASK (0x80U) 8432 #define DMA_TCD_TCD19_CSR_ESDA_SHIFT (7U) 8433 #define DMA_TCD_TCD19_CSR_ESDA_WIDTH (1U) 8434 #define DMA_TCD_TCD19_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CSR_ESDA_SHIFT)) & DMA_TCD_TCD19_CSR_ESDA_MASK) 8435 8436 #define DMA_TCD_TCD19_CSR_MAJORLINKCH_MASK (0x1F00U) 8437 #define DMA_TCD_TCD19_CSR_MAJORLINKCH_SHIFT (8U) 8438 #define DMA_TCD_TCD19_CSR_MAJORLINKCH_WIDTH (5U) 8439 #define DMA_TCD_TCD19_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD19_CSR_MAJORLINKCH_MASK) 8440 8441 #define DMA_TCD_TCD19_CSR_BWC_MASK (0xC000U) 8442 #define DMA_TCD_TCD19_CSR_BWC_SHIFT (14U) 8443 #define DMA_TCD_TCD19_CSR_BWC_WIDTH (2U) 8444 #define DMA_TCD_TCD19_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_CSR_BWC_SHIFT)) & DMA_TCD_TCD19_CSR_BWC_MASK) 8445 /*! @} */ 8446 8447 /*! @name TCD19_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 8448 /*! @{ */ 8449 8450 #define DMA_TCD_TCD19_BITER_ELINKNO_BITER_MASK (0x7FFFU) 8451 #define DMA_TCD_TCD19_BITER_ELINKNO_BITER_SHIFT (0U) 8452 #define DMA_TCD_TCD19_BITER_ELINKNO_BITER_WIDTH (15U) 8453 #define DMA_TCD_TCD19_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD19_BITER_ELINKNO_BITER_MASK) 8454 8455 #define DMA_TCD_TCD19_BITER_ELINKNO_ELINK_MASK (0x8000U) 8456 #define DMA_TCD_TCD19_BITER_ELINKNO_ELINK_SHIFT (15U) 8457 #define DMA_TCD_TCD19_BITER_ELINKNO_ELINK_WIDTH (1U) 8458 #define DMA_TCD_TCD19_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD19_BITER_ELINKNO_ELINK_MASK) 8459 /*! @} */ 8460 8461 /*! @name TCD19_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 8462 /*! @{ */ 8463 8464 #define DMA_TCD_TCD19_BITER_ELINKYES_BITER_MASK (0x1FFU) 8465 #define DMA_TCD_TCD19_BITER_ELINKYES_BITER_SHIFT (0U) 8466 #define DMA_TCD_TCD19_BITER_ELINKYES_BITER_WIDTH (9U) 8467 #define DMA_TCD_TCD19_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD19_BITER_ELINKYES_BITER_MASK) 8468 8469 #define DMA_TCD_TCD19_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 8470 #define DMA_TCD_TCD19_BITER_ELINKYES_LINKCH_SHIFT (9U) 8471 #define DMA_TCD_TCD19_BITER_ELINKYES_LINKCH_WIDTH (5U) 8472 #define DMA_TCD_TCD19_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD19_BITER_ELINKYES_LINKCH_MASK) 8473 8474 #define DMA_TCD_TCD19_BITER_ELINKYES_ELINK_MASK (0x8000U) 8475 #define DMA_TCD_TCD19_BITER_ELINKYES_ELINK_SHIFT (15U) 8476 #define DMA_TCD_TCD19_BITER_ELINKYES_ELINK_WIDTH (1U) 8477 #define DMA_TCD_TCD19_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD19_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD19_BITER_ELINKYES_ELINK_MASK) 8478 /*! @} */ 8479 8480 /*! @name CH20_CSR - Channel Control and Status */ 8481 /*! @{ */ 8482 8483 #define DMA_TCD_CH20_CSR_ERQ_MASK (0x1U) 8484 #define DMA_TCD_CH20_CSR_ERQ_SHIFT (0U) 8485 #define DMA_TCD_CH20_CSR_ERQ_WIDTH (1U) 8486 #define DMA_TCD_CH20_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_CSR_ERQ_SHIFT)) & DMA_TCD_CH20_CSR_ERQ_MASK) 8487 8488 #define DMA_TCD_CH20_CSR_EARQ_MASK (0x2U) 8489 #define DMA_TCD_CH20_CSR_EARQ_SHIFT (1U) 8490 #define DMA_TCD_CH20_CSR_EARQ_WIDTH (1U) 8491 #define DMA_TCD_CH20_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_CSR_EARQ_SHIFT)) & DMA_TCD_CH20_CSR_EARQ_MASK) 8492 8493 #define DMA_TCD_CH20_CSR_EEI_MASK (0x4U) 8494 #define DMA_TCD_CH20_CSR_EEI_SHIFT (2U) 8495 #define DMA_TCD_CH20_CSR_EEI_WIDTH (1U) 8496 #define DMA_TCD_CH20_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_CSR_EEI_SHIFT)) & DMA_TCD_CH20_CSR_EEI_MASK) 8497 8498 #define DMA_TCD_CH20_CSR_EBW_MASK (0x8U) 8499 #define DMA_TCD_CH20_CSR_EBW_SHIFT (3U) 8500 #define DMA_TCD_CH20_CSR_EBW_WIDTH (1U) 8501 #define DMA_TCD_CH20_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_CSR_EBW_SHIFT)) & DMA_TCD_CH20_CSR_EBW_MASK) 8502 8503 #define DMA_TCD_CH20_CSR_DONE_MASK (0x40000000U) 8504 #define DMA_TCD_CH20_CSR_DONE_SHIFT (30U) 8505 #define DMA_TCD_CH20_CSR_DONE_WIDTH (1U) 8506 #define DMA_TCD_CH20_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_CSR_DONE_SHIFT)) & DMA_TCD_CH20_CSR_DONE_MASK) 8507 8508 #define DMA_TCD_CH20_CSR_ACTIVE_MASK (0x80000000U) 8509 #define DMA_TCD_CH20_CSR_ACTIVE_SHIFT (31U) 8510 #define DMA_TCD_CH20_CSR_ACTIVE_WIDTH (1U) 8511 #define DMA_TCD_CH20_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH20_CSR_ACTIVE_MASK) 8512 /*! @} */ 8513 8514 /*! @name CH20_ES - Channel Error Status */ 8515 /*! @{ */ 8516 8517 #define DMA_TCD_CH20_ES_DBE_MASK (0x1U) 8518 #define DMA_TCD_CH20_ES_DBE_SHIFT (0U) 8519 #define DMA_TCD_CH20_ES_DBE_WIDTH (1U) 8520 #define DMA_TCD_CH20_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_ES_DBE_SHIFT)) & DMA_TCD_CH20_ES_DBE_MASK) 8521 8522 #define DMA_TCD_CH20_ES_SBE_MASK (0x2U) 8523 #define DMA_TCD_CH20_ES_SBE_SHIFT (1U) 8524 #define DMA_TCD_CH20_ES_SBE_WIDTH (1U) 8525 #define DMA_TCD_CH20_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_ES_SBE_SHIFT)) & DMA_TCD_CH20_ES_SBE_MASK) 8526 8527 #define DMA_TCD_CH20_ES_SGE_MASK (0x4U) 8528 #define DMA_TCD_CH20_ES_SGE_SHIFT (2U) 8529 #define DMA_TCD_CH20_ES_SGE_WIDTH (1U) 8530 #define DMA_TCD_CH20_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_ES_SGE_SHIFT)) & DMA_TCD_CH20_ES_SGE_MASK) 8531 8532 #define DMA_TCD_CH20_ES_NCE_MASK (0x8U) 8533 #define DMA_TCD_CH20_ES_NCE_SHIFT (3U) 8534 #define DMA_TCD_CH20_ES_NCE_WIDTH (1U) 8535 #define DMA_TCD_CH20_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_ES_NCE_SHIFT)) & DMA_TCD_CH20_ES_NCE_MASK) 8536 8537 #define DMA_TCD_CH20_ES_DOE_MASK (0x10U) 8538 #define DMA_TCD_CH20_ES_DOE_SHIFT (4U) 8539 #define DMA_TCD_CH20_ES_DOE_WIDTH (1U) 8540 #define DMA_TCD_CH20_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_ES_DOE_SHIFT)) & DMA_TCD_CH20_ES_DOE_MASK) 8541 8542 #define DMA_TCD_CH20_ES_DAE_MASK (0x20U) 8543 #define DMA_TCD_CH20_ES_DAE_SHIFT (5U) 8544 #define DMA_TCD_CH20_ES_DAE_WIDTH (1U) 8545 #define DMA_TCD_CH20_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_ES_DAE_SHIFT)) & DMA_TCD_CH20_ES_DAE_MASK) 8546 8547 #define DMA_TCD_CH20_ES_SOE_MASK (0x40U) 8548 #define DMA_TCD_CH20_ES_SOE_SHIFT (6U) 8549 #define DMA_TCD_CH20_ES_SOE_WIDTH (1U) 8550 #define DMA_TCD_CH20_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_ES_SOE_SHIFT)) & DMA_TCD_CH20_ES_SOE_MASK) 8551 8552 #define DMA_TCD_CH20_ES_SAE_MASK (0x80U) 8553 #define DMA_TCD_CH20_ES_SAE_SHIFT (7U) 8554 #define DMA_TCD_CH20_ES_SAE_WIDTH (1U) 8555 #define DMA_TCD_CH20_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_ES_SAE_SHIFT)) & DMA_TCD_CH20_ES_SAE_MASK) 8556 8557 #define DMA_TCD_CH20_ES_ERR_MASK (0x80000000U) 8558 #define DMA_TCD_CH20_ES_ERR_SHIFT (31U) 8559 #define DMA_TCD_CH20_ES_ERR_WIDTH (1U) 8560 #define DMA_TCD_CH20_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_ES_ERR_SHIFT)) & DMA_TCD_CH20_ES_ERR_MASK) 8561 /*! @} */ 8562 8563 /*! @name CH20_INT - Channel Interrupt Status */ 8564 /*! @{ */ 8565 8566 #define DMA_TCD_CH20_INT_INT_MASK (0x1U) 8567 #define DMA_TCD_CH20_INT_INT_SHIFT (0U) 8568 #define DMA_TCD_CH20_INT_INT_WIDTH (1U) 8569 #define DMA_TCD_CH20_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_INT_INT_SHIFT)) & DMA_TCD_CH20_INT_INT_MASK) 8570 /*! @} */ 8571 8572 /*! @name CH20_SBR - Channel System Bus */ 8573 /*! @{ */ 8574 8575 #define DMA_TCD_CH20_SBR_MID_MASK (0xFU) 8576 #define DMA_TCD_CH20_SBR_MID_SHIFT (0U) 8577 #define DMA_TCD_CH20_SBR_MID_WIDTH (4U) 8578 #define DMA_TCD_CH20_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_SBR_MID_SHIFT)) & DMA_TCD_CH20_SBR_MID_MASK) 8579 8580 #define DMA_TCD_CH20_SBR_PAL_MASK (0x8000U) 8581 #define DMA_TCD_CH20_SBR_PAL_SHIFT (15U) 8582 #define DMA_TCD_CH20_SBR_PAL_WIDTH (1U) 8583 #define DMA_TCD_CH20_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_SBR_PAL_SHIFT)) & DMA_TCD_CH20_SBR_PAL_MASK) 8584 8585 #define DMA_TCD_CH20_SBR_EMI_MASK (0x10000U) 8586 #define DMA_TCD_CH20_SBR_EMI_SHIFT (16U) 8587 #define DMA_TCD_CH20_SBR_EMI_WIDTH (1U) 8588 #define DMA_TCD_CH20_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_SBR_EMI_SHIFT)) & DMA_TCD_CH20_SBR_EMI_MASK) 8589 8590 #define DMA_TCD_CH20_SBR_ATTR_MASK (0xE0000U) 8591 #define DMA_TCD_CH20_SBR_ATTR_SHIFT (17U) 8592 #define DMA_TCD_CH20_SBR_ATTR_WIDTH (3U) 8593 #define DMA_TCD_CH20_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_SBR_ATTR_SHIFT)) & DMA_TCD_CH20_SBR_ATTR_MASK) 8594 /*! @} */ 8595 8596 /*! @name CH20_PRI - Channel Priority */ 8597 /*! @{ */ 8598 8599 #define DMA_TCD_CH20_PRI_APL_MASK (0x7U) 8600 #define DMA_TCD_CH20_PRI_APL_SHIFT (0U) 8601 #define DMA_TCD_CH20_PRI_APL_WIDTH (3U) 8602 #define DMA_TCD_CH20_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_PRI_APL_SHIFT)) & DMA_TCD_CH20_PRI_APL_MASK) 8603 8604 #define DMA_TCD_CH20_PRI_DPA_MASK (0x40000000U) 8605 #define DMA_TCD_CH20_PRI_DPA_SHIFT (30U) 8606 #define DMA_TCD_CH20_PRI_DPA_WIDTH (1U) 8607 #define DMA_TCD_CH20_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_PRI_DPA_SHIFT)) & DMA_TCD_CH20_PRI_DPA_MASK) 8608 8609 #define DMA_TCD_CH20_PRI_ECP_MASK (0x80000000U) 8610 #define DMA_TCD_CH20_PRI_ECP_SHIFT (31U) 8611 #define DMA_TCD_CH20_PRI_ECP_WIDTH (1U) 8612 #define DMA_TCD_CH20_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH20_PRI_ECP_SHIFT)) & DMA_TCD_CH20_PRI_ECP_MASK) 8613 /*! @} */ 8614 8615 /*! @name TCD20_SADDR - TCD Source Address */ 8616 /*! @{ */ 8617 8618 #define DMA_TCD_TCD20_SADDR_SADDR_MASK (0xFFFFFFFFU) 8619 #define DMA_TCD_TCD20_SADDR_SADDR_SHIFT (0U) 8620 #define DMA_TCD_TCD20_SADDR_SADDR_WIDTH (32U) 8621 #define DMA_TCD_TCD20_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD20_SADDR_SADDR_MASK) 8622 /*! @} */ 8623 8624 /*! @name TCD20_SOFF - TCD Signed Source Address Offset */ 8625 /*! @{ */ 8626 8627 #define DMA_TCD_TCD20_SOFF_SOFF_MASK (0xFFFFU) 8628 #define DMA_TCD_TCD20_SOFF_SOFF_SHIFT (0U) 8629 #define DMA_TCD_TCD20_SOFF_SOFF_WIDTH (16U) 8630 #define DMA_TCD_TCD20_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD20_SOFF_SOFF_MASK) 8631 /*! @} */ 8632 8633 /*! @name TCD20_ATTR - TCD Transfer Attributes */ 8634 /*! @{ */ 8635 8636 #define DMA_TCD_TCD20_ATTR_DSIZE_MASK (0x7U) 8637 #define DMA_TCD_TCD20_ATTR_DSIZE_SHIFT (0U) 8638 #define DMA_TCD_TCD20_ATTR_DSIZE_WIDTH (3U) 8639 #define DMA_TCD_TCD20_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD20_ATTR_DSIZE_MASK) 8640 8641 #define DMA_TCD_TCD20_ATTR_DMOD_MASK (0xF8U) 8642 #define DMA_TCD_TCD20_ATTR_DMOD_SHIFT (3U) 8643 #define DMA_TCD_TCD20_ATTR_DMOD_WIDTH (5U) 8644 #define DMA_TCD_TCD20_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD20_ATTR_DMOD_MASK) 8645 8646 #define DMA_TCD_TCD20_ATTR_SSIZE_MASK (0x700U) 8647 #define DMA_TCD_TCD20_ATTR_SSIZE_SHIFT (8U) 8648 #define DMA_TCD_TCD20_ATTR_SSIZE_WIDTH (3U) 8649 #define DMA_TCD_TCD20_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD20_ATTR_SSIZE_MASK) 8650 8651 #define DMA_TCD_TCD20_ATTR_SMOD_MASK (0xF800U) 8652 #define DMA_TCD_TCD20_ATTR_SMOD_SHIFT (11U) 8653 #define DMA_TCD_TCD20_ATTR_SMOD_WIDTH (5U) 8654 #define DMA_TCD_TCD20_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD20_ATTR_SMOD_MASK) 8655 /*! @} */ 8656 8657 /*! @name TCD20_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 8658 /*! @{ */ 8659 8660 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 8661 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 8662 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 8663 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD20_NBYTES_MLOFFNO_NBYTES_MASK) 8664 8665 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 8666 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 8667 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 8668 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD20_NBYTES_MLOFFNO_DMLOE_MASK) 8669 8670 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 8671 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 8672 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 8673 #define DMA_TCD_TCD20_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD20_NBYTES_MLOFFNO_SMLOE_MASK) 8674 /*! @} */ 8675 8676 /*! @name TCD20_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 8677 /*! @{ */ 8678 8679 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 8680 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 8681 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 8682 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD20_NBYTES_MLOFFYES_NBYTES_MASK) 8683 8684 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 8685 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 8686 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 8687 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD20_NBYTES_MLOFFYES_MLOFF_MASK) 8688 8689 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 8690 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 8691 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 8692 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD20_NBYTES_MLOFFYES_DMLOE_MASK) 8693 8694 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 8695 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 8696 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 8697 #define DMA_TCD_TCD20_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD20_NBYTES_MLOFFYES_SMLOE_MASK) 8698 /*! @} */ 8699 8700 /*! @name TCD20_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 8701 /*! @{ */ 8702 8703 #define DMA_TCD_TCD20_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 8704 #define DMA_TCD_TCD20_SLAST_SDA_SLAST_SDA_SHIFT (0U) 8705 #define DMA_TCD_TCD20_SLAST_SDA_SLAST_SDA_WIDTH (32U) 8706 #define DMA_TCD_TCD20_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD20_SLAST_SDA_SLAST_SDA_MASK) 8707 /*! @} */ 8708 8709 /*! @name TCD20_DADDR - TCD Destination Address */ 8710 /*! @{ */ 8711 8712 #define DMA_TCD_TCD20_DADDR_DADDR_MASK (0xFFFFFFFFU) 8713 #define DMA_TCD_TCD20_DADDR_DADDR_SHIFT (0U) 8714 #define DMA_TCD_TCD20_DADDR_DADDR_WIDTH (32U) 8715 #define DMA_TCD_TCD20_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD20_DADDR_DADDR_MASK) 8716 /*! @} */ 8717 8718 /*! @name TCD20_DOFF - TCD Signed Destination Address Offset */ 8719 /*! @{ */ 8720 8721 #define DMA_TCD_TCD20_DOFF_DOFF_MASK (0xFFFFU) 8722 #define DMA_TCD_TCD20_DOFF_DOFF_SHIFT (0U) 8723 #define DMA_TCD_TCD20_DOFF_DOFF_WIDTH (16U) 8724 #define DMA_TCD_TCD20_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD20_DOFF_DOFF_MASK) 8725 /*! @} */ 8726 8727 /*! @name TCD20_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 8728 /*! @{ */ 8729 8730 #define DMA_TCD_TCD20_CITER_ELINKNO_CITER_MASK (0x7FFFU) 8731 #define DMA_TCD_TCD20_CITER_ELINKNO_CITER_SHIFT (0U) 8732 #define DMA_TCD_TCD20_CITER_ELINKNO_CITER_WIDTH (15U) 8733 #define DMA_TCD_TCD20_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD20_CITER_ELINKNO_CITER_MASK) 8734 8735 #define DMA_TCD_TCD20_CITER_ELINKNO_ELINK_MASK (0x8000U) 8736 #define DMA_TCD_TCD20_CITER_ELINKNO_ELINK_SHIFT (15U) 8737 #define DMA_TCD_TCD20_CITER_ELINKNO_ELINK_WIDTH (1U) 8738 #define DMA_TCD_TCD20_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD20_CITER_ELINKNO_ELINK_MASK) 8739 /*! @} */ 8740 8741 /*! @name TCD20_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 8742 /*! @{ */ 8743 8744 #define DMA_TCD_TCD20_CITER_ELINKYES_CITER_MASK (0x1FFU) 8745 #define DMA_TCD_TCD20_CITER_ELINKYES_CITER_SHIFT (0U) 8746 #define DMA_TCD_TCD20_CITER_ELINKYES_CITER_WIDTH (9U) 8747 #define DMA_TCD_TCD20_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD20_CITER_ELINKYES_CITER_MASK) 8748 8749 #define DMA_TCD_TCD20_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 8750 #define DMA_TCD_TCD20_CITER_ELINKYES_LINKCH_SHIFT (9U) 8751 #define DMA_TCD_TCD20_CITER_ELINKYES_LINKCH_WIDTH (5U) 8752 #define DMA_TCD_TCD20_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD20_CITER_ELINKYES_LINKCH_MASK) 8753 8754 #define DMA_TCD_TCD20_CITER_ELINKYES_ELINK_MASK (0x8000U) 8755 #define DMA_TCD_TCD20_CITER_ELINKYES_ELINK_SHIFT (15U) 8756 #define DMA_TCD_TCD20_CITER_ELINKYES_ELINK_WIDTH (1U) 8757 #define DMA_TCD_TCD20_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD20_CITER_ELINKYES_ELINK_MASK) 8758 /*! @} */ 8759 8760 /*! @name TCD20_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 8761 /*! @{ */ 8762 8763 #define DMA_TCD_TCD20_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 8764 #define DMA_TCD_TCD20_DLAST_SGA_DLAST_SGA_SHIFT (0U) 8765 #define DMA_TCD_TCD20_DLAST_SGA_DLAST_SGA_WIDTH (32U) 8766 #define DMA_TCD_TCD20_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD20_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD20_DLAST_SGA_DLAST_SGA_MASK) 8767 /*! @} */ 8768 8769 /*! @name TCD20_CSR - TCD Control and Status */ 8770 /*! @{ */ 8771 8772 #define DMA_TCD_TCD20_CSR_START_MASK (0x1U) 8773 #define DMA_TCD_TCD20_CSR_START_SHIFT (0U) 8774 #define DMA_TCD_TCD20_CSR_START_WIDTH (1U) 8775 #define DMA_TCD_TCD20_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CSR_START_SHIFT)) & DMA_TCD_TCD20_CSR_START_MASK) 8776 8777 #define DMA_TCD_TCD20_CSR_INTMAJOR_MASK (0x2U) 8778 #define DMA_TCD_TCD20_CSR_INTMAJOR_SHIFT (1U) 8779 #define DMA_TCD_TCD20_CSR_INTMAJOR_WIDTH (1U) 8780 #define DMA_TCD_TCD20_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD20_CSR_INTMAJOR_MASK) 8781 8782 #define DMA_TCD_TCD20_CSR_INTHALF_MASK (0x4U) 8783 #define DMA_TCD_TCD20_CSR_INTHALF_SHIFT (2U) 8784 #define DMA_TCD_TCD20_CSR_INTHALF_WIDTH (1U) 8785 #define DMA_TCD_TCD20_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD20_CSR_INTHALF_MASK) 8786 8787 #define DMA_TCD_TCD20_CSR_DREQ_MASK (0x8U) 8788 #define DMA_TCD_TCD20_CSR_DREQ_SHIFT (3U) 8789 #define DMA_TCD_TCD20_CSR_DREQ_WIDTH (1U) 8790 #define DMA_TCD_TCD20_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CSR_DREQ_SHIFT)) & DMA_TCD_TCD20_CSR_DREQ_MASK) 8791 8792 #define DMA_TCD_TCD20_CSR_ESG_MASK (0x10U) 8793 #define DMA_TCD_TCD20_CSR_ESG_SHIFT (4U) 8794 #define DMA_TCD_TCD20_CSR_ESG_WIDTH (1U) 8795 #define DMA_TCD_TCD20_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CSR_ESG_SHIFT)) & DMA_TCD_TCD20_CSR_ESG_MASK) 8796 8797 #define DMA_TCD_TCD20_CSR_MAJORELINK_MASK (0x20U) 8798 #define DMA_TCD_TCD20_CSR_MAJORELINK_SHIFT (5U) 8799 #define DMA_TCD_TCD20_CSR_MAJORELINK_WIDTH (1U) 8800 #define DMA_TCD_TCD20_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD20_CSR_MAJORELINK_MASK) 8801 8802 #define DMA_TCD_TCD20_CSR_EEOP_MASK (0x40U) 8803 #define DMA_TCD_TCD20_CSR_EEOP_SHIFT (6U) 8804 #define DMA_TCD_TCD20_CSR_EEOP_WIDTH (1U) 8805 #define DMA_TCD_TCD20_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CSR_EEOP_SHIFT)) & DMA_TCD_TCD20_CSR_EEOP_MASK) 8806 8807 #define DMA_TCD_TCD20_CSR_ESDA_MASK (0x80U) 8808 #define DMA_TCD_TCD20_CSR_ESDA_SHIFT (7U) 8809 #define DMA_TCD_TCD20_CSR_ESDA_WIDTH (1U) 8810 #define DMA_TCD_TCD20_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CSR_ESDA_SHIFT)) & DMA_TCD_TCD20_CSR_ESDA_MASK) 8811 8812 #define DMA_TCD_TCD20_CSR_MAJORLINKCH_MASK (0x1F00U) 8813 #define DMA_TCD_TCD20_CSR_MAJORLINKCH_SHIFT (8U) 8814 #define DMA_TCD_TCD20_CSR_MAJORLINKCH_WIDTH (5U) 8815 #define DMA_TCD_TCD20_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD20_CSR_MAJORLINKCH_MASK) 8816 8817 #define DMA_TCD_TCD20_CSR_BWC_MASK (0xC000U) 8818 #define DMA_TCD_TCD20_CSR_BWC_SHIFT (14U) 8819 #define DMA_TCD_TCD20_CSR_BWC_WIDTH (2U) 8820 #define DMA_TCD_TCD20_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_CSR_BWC_SHIFT)) & DMA_TCD_TCD20_CSR_BWC_MASK) 8821 /*! @} */ 8822 8823 /*! @name TCD20_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 8824 /*! @{ */ 8825 8826 #define DMA_TCD_TCD20_BITER_ELINKNO_BITER_MASK (0x7FFFU) 8827 #define DMA_TCD_TCD20_BITER_ELINKNO_BITER_SHIFT (0U) 8828 #define DMA_TCD_TCD20_BITER_ELINKNO_BITER_WIDTH (15U) 8829 #define DMA_TCD_TCD20_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD20_BITER_ELINKNO_BITER_MASK) 8830 8831 #define DMA_TCD_TCD20_BITER_ELINKNO_ELINK_MASK (0x8000U) 8832 #define DMA_TCD_TCD20_BITER_ELINKNO_ELINK_SHIFT (15U) 8833 #define DMA_TCD_TCD20_BITER_ELINKNO_ELINK_WIDTH (1U) 8834 #define DMA_TCD_TCD20_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD20_BITER_ELINKNO_ELINK_MASK) 8835 /*! @} */ 8836 8837 /*! @name TCD20_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 8838 /*! @{ */ 8839 8840 #define DMA_TCD_TCD20_BITER_ELINKYES_BITER_MASK (0x1FFU) 8841 #define DMA_TCD_TCD20_BITER_ELINKYES_BITER_SHIFT (0U) 8842 #define DMA_TCD_TCD20_BITER_ELINKYES_BITER_WIDTH (9U) 8843 #define DMA_TCD_TCD20_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD20_BITER_ELINKYES_BITER_MASK) 8844 8845 #define DMA_TCD_TCD20_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 8846 #define DMA_TCD_TCD20_BITER_ELINKYES_LINKCH_SHIFT (9U) 8847 #define DMA_TCD_TCD20_BITER_ELINKYES_LINKCH_WIDTH (5U) 8848 #define DMA_TCD_TCD20_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD20_BITER_ELINKYES_LINKCH_MASK) 8849 8850 #define DMA_TCD_TCD20_BITER_ELINKYES_ELINK_MASK (0x8000U) 8851 #define DMA_TCD_TCD20_BITER_ELINKYES_ELINK_SHIFT (15U) 8852 #define DMA_TCD_TCD20_BITER_ELINKYES_ELINK_WIDTH (1U) 8853 #define DMA_TCD_TCD20_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD20_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD20_BITER_ELINKYES_ELINK_MASK) 8854 /*! @} */ 8855 8856 /*! @name CH21_CSR - Channel Control and Status */ 8857 /*! @{ */ 8858 8859 #define DMA_TCD_CH21_CSR_ERQ_MASK (0x1U) 8860 #define DMA_TCD_CH21_CSR_ERQ_SHIFT (0U) 8861 #define DMA_TCD_CH21_CSR_ERQ_WIDTH (1U) 8862 #define DMA_TCD_CH21_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_CSR_ERQ_SHIFT)) & DMA_TCD_CH21_CSR_ERQ_MASK) 8863 8864 #define DMA_TCD_CH21_CSR_EARQ_MASK (0x2U) 8865 #define DMA_TCD_CH21_CSR_EARQ_SHIFT (1U) 8866 #define DMA_TCD_CH21_CSR_EARQ_WIDTH (1U) 8867 #define DMA_TCD_CH21_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_CSR_EARQ_SHIFT)) & DMA_TCD_CH21_CSR_EARQ_MASK) 8868 8869 #define DMA_TCD_CH21_CSR_EEI_MASK (0x4U) 8870 #define DMA_TCD_CH21_CSR_EEI_SHIFT (2U) 8871 #define DMA_TCD_CH21_CSR_EEI_WIDTH (1U) 8872 #define DMA_TCD_CH21_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_CSR_EEI_SHIFT)) & DMA_TCD_CH21_CSR_EEI_MASK) 8873 8874 #define DMA_TCD_CH21_CSR_EBW_MASK (0x8U) 8875 #define DMA_TCD_CH21_CSR_EBW_SHIFT (3U) 8876 #define DMA_TCD_CH21_CSR_EBW_WIDTH (1U) 8877 #define DMA_TCD_CH21_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_CSR_EBW_SHIFT)) & DMA_TCD_CH21_CSR_EBW_MASK) 8878 8879 #define DMA_TCD_CH21_CSR_DONE_MASK (0x40000000U) 8880 #define DMA_TCD_CH21_CSR_DONE_SHIFT (30U) 8881 #define DMA_TCD_CH21_CSR_DONE_WIDTH (1U) 8882 #define DMA_TCD_CH21_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_CSR_DONE_SHIFT)) & DMA_TCD_CH21_CSR_DONE_MASK) 8883 8884 #define DMA_TCD_CH21_CSR_ACTIVE_MASK (0x80000000U) 8885 #define DMA_TCD_CH21_CSR_ACTIVE_SHIFT (31U) 8886 #define DMA_TCD_CH21_CSR_ACTIVE_WIDTH (1U) 8887 #define DMA_TCD_CH21_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH21_CSR_ACTIVE_MASK) 8888 /*! @} */ 8889 8890 /*! @name CH21_ES - Channel Error Status */ 8891 /*! @{ */ 8892 8893 #define DMA_TCD_CH21_ES_DBE_MASK (0x1U) 8894 #define DMA_TCD_CH21_ES_DBE_SHIFT (0U) 8895 #define DMA_TCD_CH21_ES_DBE_WIDTH (1U) 8896 #define DMA_TCD_CH21_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_ES_DBE_SHIFT)) & DMA_TCD_CH21_ES_DBE_MASK) 8897 8898 #define DMA_TCD_CH21_ES_SBE_MASK (0x2U) 8899 #define DMA_TCD_CH21_ES_SBE_SHIFT (1U) 8900 #define DMA_TCD_CH21_ES_SBE_WIDTH (1U) 8901 #define DMA_TCD_CH21_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_ES_SBE_SHIFT)) & DMA_TCD_CH21_ES_SBE_MASK) 8902 8903 #define DMA_TCD_CH21_ES_SGE_MASK (0x4U) 8904 #define DMA_TCD_CH21_ES_SGE_SHIFT (2U) 8905 #define DMA_TCD_CH21_ES_SGE_WIDTH (1U) 8906 #define DMA_TCD_CH21_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_ES_SGE_SHIFT)) & DMA_TCD_CH21_ES_SGE_MASK) 8907 8908 #define DMA_TCD_CH21_ES_NCE_MASK (0x8U) 8909 #define DMA_TCD_CH21_ES_NCE_SHIFT (3U) 8910 #define DMA_TCD_CH21_ES_NCE_WIDTH (1U) 8911 #define DMA_TCD_CH21_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_ES_NCE_SHIFT)) & DMA_TCD_CH21_ES_NCE_MASK) 8912 8913 #define DMA_TCD_CH21_ES_DOE_MASK (0x10U) 8914 #define DMA_TCD_CH21_ES_DOE_SHIFT (4U) 8915 #define DMA_TCD_CH21_ES_DOE_WIDTH (1U) 8916 #define DMA_TCD_CH21_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_ES_DOE_SHIFT)) & DMA_TCD_CH21_ES_DOE_MASK) 8917 8918 #define DMA_TCD_CH21_ES_DAE_MASK (0x20U) 8919 #define DMA_TCD_CH21_ES_DAE_SHIFT (5U) 8920 #define DMA_TCD_CH21_ES_DAE_WIDTH (1U) 8921 #define DMA_TCD_CH21_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_ES_DAE_SHIFT)) & DMA_TCD_CH21_ES_DAE_MASK) 8922 8923 #define DMA_TCD_CH21_ES_SOE_MASK (0x40U) 8924 #define DMA_TCD_CH21_ES_SOE_SHIFT (6U) 8925 #define DMA_TCD_CH21_ES_SOE_WIDTH (1U) 8926 #define DMA_TCD_CH21_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_ES_SOE_SHIFT)) & DMA_TCD_CH21_ES_SOE_MASK) 8927 8928 #define DMA_TCD_CH21_ES_SAE_MASK (0x80U) 8929 #define DMA_TCD_CH21_ES_SAE_SHIFT (7U) 8930 #define DMA_TCD_CH21_ES_SAE_WIDTH (1U) 8931 #define DMA_TCD_CH21_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_ES_SAE_SHIFT)) & DMA_TCD_CH21_ES_SAE_MASK) 8932 8933 #define DMA_TCD_CH21_ES_ERR_MASK (0x80000000U) 8934 #define DMA_TCD_CH21_ES_ERR_SHIFT (31U) 8935 #define DMA_TCD_CH21_ES_ERR_WIDTH (1U) 8936 #define DMA_TCD_CH21_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_ES_ERR_SHIFT)) & DMA_TCD_CH21_ES_ERR_MASK) 8937 /*! @} */ 8938 8939 /*! @name CH21_INT - Channel Interrupt Status */ 8940 /*! @{ */ 8941 8942 #define DMA_TCD_CH21_INT_INT_MASK (0x1U) 8943 #define DMA_TCD_CH21_INT_INT_SHIFT (0U) 8944 #define DMA_TCD_CH21_INT_INT_WIDTH (1U) 8945 #define DMA_TCD_CH21_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_INT_INT_SHIFT)) & DMA_TCD_CH21_INT_INT_MASK) 8946 /*! @} */ 8947 8948 /*! @name CH21_SBR - Channel System Bus */ 8949 /*! @{ */ 8950 8951 #define DMA_TCD_CH21_SBR_MID_MASK (0xFU) 8952 #define DMA_TCD_CH21_SBR_MID_SHIFT (0U) 8953 #define DMA_TCD_CH21_SBR_MID_WIDTH (4U) 8954 #define DMA_TCD_CH21_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_SBR_MID_SHIFT)) & DMA_TCD_CH21_SBR_MID_MASK) 8955 8956 #define DMA_TCD_CH21_SBR_PAL_MASK (0x8000U) 8957 #define DMA_TCD_CH21_SBR_PAL_SHIFT (15U) 8958 #define DMA_TCD_CH21_SBR_PAL_WIDTH (1U) 8959 #define DMA_TCD_CH21_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_SBR_PAL_SHIFT)) & DMA_TCD_CH21_SBR_PAL_MASK) 8960 8961 #define DMA_TCD_CH21_SBR_EMI_MASK (0x10000U) 8962 #define DMA_TCD_CH21_SBR_EMI_SHIFT (16U) 8963 #define DMA_TCD_CH21_SBR_EMI_WIDTH (1U) 8964 #define DMA_TCD_CH21_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_SBR_EMI_SHIFT)) & DMA_TCD_CH21_SBR_EMI_MASK) 8965 8966 #define DMA_TCD_CH21_SBR_ATTR_MASK (0xE0000U) 8967 #define DMA_TCD_CH21_SBR_ATTR_SHIFT (17U) 8968 #define DMA_TCD_CH21_SBR_ATTR_WIDTH (3U) 8969 #define DMA_TCD_CH21_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_SBR_ATTR_SHIFT)) & DMA_TCD_CH21_SBR_ATTR_MASK) 8970 /*! @} */ 8971 8972 /*! @name CH21_PRI - Channel Priority */ 8973 /*! @{ */ 8974 8975 #define DMA_TCD_CH21_PRI_APL_MASK (0x7U) 8976 #define DMA_TCD_CH21_PRI_APL_SHIFT (0U) 8977 #define DMA_TCD_CH21_PRI_APL_WIDTH (3U) 8978 #define DMA_TCD_CH21_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_PRI_APL_SHIFT)) & DMA_TCD_CH21_PRI_APL_MASK) 8979 8980 #define DMA_TCD_CH21_PRI_DPA_MASK (0x40000000U) 8981 #define DMA_TCD_CH21_PRI_DPA_SHIFT (30U) 8982 #define DMA_TCD_CH21_PRI_DPA_WIDTH (1U) 8983 #define DMA_TCD_CH21_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_PRI_DPA_SHIFT)) & DMA_TCD_CH21_PRI_DPA_MASK) 8984 8985 #define DMA_TCD_CH21_PRI_ECP_MASK (0x80000000U) 8986 #define DMA_TCD_CH21_PRI_ECP_SHIFT (31U) 8987 #define DMA_TCD_CH21_PRI_ECP_WIDTH (1U) 8988 #define DMA_TCD_CH21_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH21_PRI_ECP_SHIFT)) & DMA_TCD_CH21_PRI_ECP_MASK) 8989 /*! @} */ 8990 8991 /*! @name TCD21_SADDR - TCD Source Address */ 8992 /*! @{ */ 8993 8994 #define DMA_TCD_TCD21_SADDR_SADDR_MASK (0xFFFFFFFFU) 8995 #define DMA_TCD_TCD21_SADDR_SADDR_SHIFT (0U) 8996 #define DMA_TCD_TCD21_SADDR_SADDR_WIDTH (32U) 8997 #define DMA_TCD_TCD21_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD21_SADDR_SADDR_MASK) 8998 /*! @} */ 8999 9000 /*! @name TCD21_SOFF - TCD Signed Source Address Offset */ 9001 /*! @{ */ 9002 9003 #define DMA_TCD_TCD21_SOFF_SOFF_MASK (0xFFFFU) 9004 #define DMA_TCD_TCD21_SOFF_SOFF_SHIFT (0U) 9005 #define DMA_TCD_TCD21_SOFF_SOFF_WIDTH (16U) 9006 #define DMA_TCD_TCD21_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD21_SOFF_SOFF_MASK) 9007 /*! @} */ 9008 9009 /*! @name TCD21_ATTR - TCD Transfer Attributes */ 9010 /*! @{ */ 9011 9012 #define DMA_TCD_TCD21_ATTR_DSIZE_MASK (0x7U) 9013 #define DMA_TCD_TCD21_ATTR_DSIZE_SHIFT (0U) 9014 #define DMA_TCD_TCD21_ATTR_DSIZE_WIDTH (3U) 9015 #define DMA_TCD_TCD21_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD21_ATTR_DSIZE_MASK) 9016 9017 #define DMA_TCD_TCD21_ATTR_DMOD_MASK (0xF8U) 9018 #define DMA_TCD_TCD21_ATTR_DMOD_SHIFT (3U) 9019 #define DMA_TCD_TCD21_ATTR_DMOD_WIDTH (5U) 9020 #define DMA_TCD_TCD21_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD21_ATTR_DMOD_MASK) 9021 9022 #define DMA_TCD_TCD21_ATTR_SSIZE_MASK (0x700U) 9023 #define DMA_TCD_TCD21_ATTR_SSIZE_SHIFT (8U) 9024 #define DMA_TCD_TCD21_ATTR_SSIZE_WIDTH (3U) 9025 #define DMA_TCD_TCD21_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD21_ATTR_SSIZE_MASK) 9026 9027 #define DMA_TCD_TCD21_ATTR_SMOD_MASK (0xF800U) 9028 #define DMA_TCD_TCD21_ATTR_SMOD_SHIFT (11U) 9029 #define DMA_TCD_TCD21_ATTR_SMOD_WIDTH (5U) 9030 #define DMA_TCD_TCD21_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD21_ATTR_SMOD_MASK) 9031 /*! @} */ 9032 9033 /*! @name TCD21_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 9034 /*! @{ */ 9035 9036 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 9037 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 9038 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 9039 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD21_NBYTES_MLOFFNO_NBYTES_MASK) 9040 9041 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 9042 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 9043 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 9044 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD21_NBYTES_MLOFFNO_DMLOE_MASK) 9045 9046 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 9047 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 9048 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 9049 #define DMA_TCD_TCD21_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD21_NBYTES_MLOFFNO_SMLOE_MASK) 9050 /*! @} */ 9051 9052 /*! @name TCD21_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 9053 /*! @{ */ 9054 9055 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 9056 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 9057 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 9058 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD21_NBYTES_MLOFFYES_NBYTES_MASK) 9059 9060 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 9061 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 9062 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 9063 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD21_NBYTES_MLOFFYES_MLOFF_MASK) 9064 9065 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 9066 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 9067 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 9068 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD21_NBYTES_MLOFFYES_DMLOE_MASK) 9069 9070 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 9071 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 9072 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 9073 #define DMA_TCD_TCD21_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD21_NBYTES_MLOFFYES_SMLOE_MASK) 9074 /*! @} */ 9075 9076 /*! @name TCD21_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 9077 /*! @{ */ 9078 9079 #define DMA_TCD_TCD21_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 9080 #define DMA_TCD_TCD21_SLAST_SDA_SLAST_SDA_SHIFT (0U) 9081 #define DMA_TCD_TCD21_SLAST_SDA_SLAST_SDA_WIDTH (32U) 9082 #define DMA_TCD_TCD21_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD21_SLAST_SDA_SLAST_SDA_MASK) 9083 /*! @} */ 9084 9085 /*! @name TCD21_DADDR - TCD Destination Address */ 9086 /*! @{ */ 9087 9088 #define DMA_TCD_TCD21_DADDR_DADDR_MASK (0xFFFFFFFFU) 9089 #define DMA_TCD_TCD21_DADDR_DADDR_SHIFT (0U) 9090 #define DMA_TCD_TCD21_DADDR_DADDR_WIDTH (32U) 9091 #define DMA_TCD_TCD21_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD21_DADDR_DADDR_MASK) 9092 /*! @} */ 9093 9094 /*! @name TCD21_DOFF - TCD Signed Destination Address Offset */ 9095 /*! @{ */ 9096 9097 #define DMA_TCD_TCD21_DOFF_DOFF_MASK (0xFFFFU) 9098 #define DMA_TCD_TCD21_DOFF_DOFF_SHIFT (0U) 9099 #define DMA_TCD_TCD21_DOFF_DOFF_WIDTH (16U) 9100 #define DMA_TCD_TCD21_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD21_DOFF_DOFF_MASK) 9101 /*! @} */ 9102 9103 /*! @name TCD21_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 9104 /*! @{ */ 9105 9106 #define DMA_TCD_TCD21_CITER_ELINKNO_CITER_MASK (0x7FFFU) 9107 #define DMA_TCD_TCD21_CITER_ELINKNO_CITER_SHIFT (0U) 9108 #define DMA_TCD_TCD21_CITER_ELINKNO_CITER_WIDTH (15U) 9109 #define DMA_TCD_TCD21_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD21_CITER_ELINKNO_CITER_MASK) 9110 9111 #define DMA_TCD_TCD21_CITER_ELINKNO_ELINK_MASK (0x8000U) 9112 #define DMA_TCD_TCD21_CITER_ELINKNO_ELINK_SHIFT (15U) 9113 #define DMA_TCD_TCD21_CITER_ELINKNO_ELINK_WIDTH (1U) 9114 #define DMA_TCD_TCD21_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD21_CITER_ELINKNO_ELINK_MASK) 9115 /*! @} */ 9116 9117 /*! @name TCD21_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 9118 /*! @{ */ 9119 9120 #define DMA_TCD_TCD21_CITER_ELINKYES_CITER_MASK (0x1FFU) 9121 #define DMA_TCD_TCD21_CITER_ELINKYES_CITER_SHIFT (0U) 9122 #define DMA_TCD_TCD21_CITER_ELINKYES_CITER_WIDTH (9U) 9123 #define DMA_TCD_TCD21_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD21_CITER_ELINKYES_CITER_MASK) 9124 9125 #define DMA_TCD_TCD21_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 9126 #define DMA_TCD_TCD21_CITER_ELINKYES_LINKCH_SHIFT (9U) 9127 #define DMA_TCD_TCD21_CITER_ELINKYES_LINKCH_WIDTH (5U) 9128 #define DMA_TCD_TCD21_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD21_CITER_ELINKYES_LINKCH_MASK) 9129 9130 #define DMA_TCD_TCD21_CITER_ELINKYES_ELINK_MASK (0x8000U) 9131 #define DMA_TCD_TCD21_CITER_ELINKYES_ELINK_SHIFT (15U) 9132 #define DMA_TCD_TCD21_CITER_ELINKYES_ELINK_WIDTH (1U) 9133 #define DMA_TCD_TCD21_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD21_CITER_ELINKYES_ELINK_MASK) 9134 /*! @} */ 9135 9136 /*! @name TCD21_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 9137 /*! @{ */ 9138 9139 #define DMA_TCD_TCD21_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 9140 #define DMA_TCD_TCD21_DLAST_SGA_DLAST_SGA_SHIFT (0U) 9141 #define DMA_TCD_TCD21_DLAST_SGA_DLAST_SGA_WIDTH (32U) 9142 #define DMA_TCD_TCD21_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD21_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD21_DLAST_SGA_DLAST_SGA_MASK) 9143 /*! @} */ 9144 9145 /*! @name TCD21_CSR - TCD Control and Status */ 9146 /*! @{ */ 9147 9148 #define DMA_TCD_TCD21_CSR_START_MASK (0x1U) 9149 #define DMA_TCD_TCD21_CSR_START_SHIFT (0U) 9150 #define DMA_TCD_TCD21_CSR_START_WIDTH (1U) 9151 #define DMA_TCD_TCD21_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CSR_START_SHIFT)) & DMA_TCD_TCD21_CSR_START_MASK) 9152 9153 #define DMA_TCD_TCD21_CSR_INTMAJOR_MASK (0x2U) 9154 #define DMA_TCD_TCD21_CSR_INTMAJOR_SHIFT (1U) 9155 #define DMA_TCD_TCD21_CSR_INTMAJOR_WIDTH (1U) 9156 #define DMA_TCD_TCD21_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD21_CSR_INTMAJOR_MASK) 9157 9158 #define DMA_TCD_TCD21_CSR_INTHALF_MASK (0x4U) 9159 #define DMA_TCD_TCD21_CSR_INTHALF_SHIFT (2U) 9160 #define DMA_TCD_TCD21_CSR_INTHALF_WIDTH (1U) 9161 #define DMA_TCD_TCD21_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD21_CSR_INTHALF_MASK) 9162 9163 #define DMA_TCD_TCD21_CSR_DREQ_MASK (0x8U) 9164 #define DMA_TCD_TCD21_CSR_DREQ_SHIFT (3U) 9165 #define DMA_TCD_TCD21_CSR_DREQ_WIDTH (1U) 9166 #define DMA_TCD_TCD21_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CSR_DREQ_SHIFT)) & DMA_TCD_TCD21_CSR_DREQ_MASK) 9167 9168 #define DMA_TCD_TCD21_CSR_ESG_MASK (0x10U) 9169 #define DMA_TCD_TCD21_CSR_ESG_SHIFT (4U) 9170 #define DMA_TCD_TCD21_CSR_ESG_WIDTH (1U) 9171 #define DMA_TCD_TCD21_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CSR_ESG_SHIFT)) & DMA_TCD_TCD21_CSR_ESG_MASK) 9172 9173 #define DMA_TCD_TCD21_CSR_MAJORELINK_MASK (0x20U) 9174 #define DMA_TCD_TCD21_CSR_MAJORELINK_SHIFT (5U) 9175 #define DMA_TCD_TCD21_CSR_MAJORELINK_WIDTH (1U) 9176 #define DMA_TCD_TCD21_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD21_CSR_MAJORELINK_MASK) 9177 9178 #define DMA_TCD_TCD21_CSR_EEOP_MASK (0x40U) 9179 #define DMA_TCD_TCD21_CSR_EEOP_SHIFT (6U) 9180 #define DMA_TCD_TCD21_CSR_EEOP_WIDTH (1U) 9181 #define DMA_TCD_TCD21_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CSR_EEOP_SHIFT)) & DMA_TCD_TCD21_CSR_EEOP_MASK) 9182 9183 #define DMA_TCD_TCD21_CSR_ESDA_MASK (0x80U) 9184 #define DMA_TCD_TCD21_CSR_ESDA_SHIFT (7U) 9185 #define DMA_TCD_TCD21_CSR_ESDA_WIDTH (1U) 9186 #define DMA_TCD_TCD21_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CSR_ESDA_SHIFT)) & DMA_TCD_TCD21_CSR_ESDA_MASK) 9187 9188 #define DMA_TCD_TCD21_CSR_MAJORLINKCH_MASK (0x1F00U) 9189 #define DMA_TCD_TCD21_CSR_MAJORLINKCH_SHIFT (8U) 9190 #define DMA_TCD_TCD21_CSR_MAJORLINKCH_WIDTH (5U) 9191 #define DMA_TCD_TCD21_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD21_CSR_MAJORLINKCH_MASK) 9192 9193 #define DMA_TCD_TCD21_CSR_BWC_MASK (0xC000U) 9194 #define DMA_TCD_TCD21_CSR_BWC_SHIFT (14U) 9195 #define DMA_TCD_TCD21_CSR_BWC_WIDTH (2U) 9196 #define DMA_TCD_TCD21_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_CSR_BWC_SHIFT)) & DMA_TCD_TCD21_CSR_BWC_MASK) 9197 /*! @} */ 9198 9199 /*! @name TCD21_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 9200 /*! @{ */ 9201 9202 #define DMA_TCD_TCD21_BITER_ELINKNO_BITER_MASK (0x7FFFU) 9203 #define DMA_TCD_TCD21_BITER_ELINKNO_BITER_SHIFT (0U) 9204 #define DMA_TCD_TCD21_BITER_ELINKNO_BITER_WIDTH (15U) 9205 #define DMA_TCD_TCD21_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD21_BITER_ELINKNO_BITER_MASK) 9206 9207 #define DMA_TCD_TCD21_BITER_ELINKNO_ELINK_MASK (0x8000U) 9208 #define DMA_TCD_TCD21_BITER_ELINKNO_ELINK_SHIFT (15U) 9209 #define DMA_TCD_TCD21_BITER_ELINKNO_ELINK_WIDTH (1U) 9210 #define DMA_TCD_TCD21_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD21_BITER_ELINKNO_ELINK_MASK) 9211 /*! @} */ 9212 9213 /*! @name TCD21_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 9214 /*! @{ */ 9215 9216 #define DMA_TCD_TCD21_BITER_ELINKYES_BITER_MASK (0x1FFU) 9217 #define DMA_TCD_TCD21_BITER_ELINKYES_BITER_SHIFT (0U) 9218 #define DMA_TCD_TCD21_BITER_ELINKYES_BITER_WIDTH (9U) 9219 #define DMA_TCD_TCD21_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD21_BITER_ELINKYES_BITER_MASK) 9220 9221 #define DMA_TCD_TCD21_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 9222 #define DMA_TCD_TCD21_BITER_ELINKYES_LINKCH_SHIFT (9U) 9223 #define DMA_TCD_TCD21_BITER_ELINKYES_LINKCH_WIDTH (5U) 9224 #define DMA_TCD_TCD21_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD21_BITER_ELINKYES_LINKCH_MASK) 9225 9226 #define DMA_TCD_TCD21_BITER_ELINKYES_ELINK_MASK (0x8000U) 9227 #define DMA_TCD_TCD21_BITER_ELINKYES_ELINK_SHIFT (15U) 9228 #define DMA_TCD_TCD21_BITER_ELINKYES_ELINK_WIDTH (1U) 9229 #define DMA_TCD_TCD21_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD21_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD21_BITER_ELINKYES_ELINK_MASK) 9230 /*! @} */ 9231 9232 /*! @name CH22_CSR - Channel Control and Status */ 9233 /*! @{ */ 9234 9235 #define DMA_TCD_CH22_CSR_ERQ_MASK (0x1U) 9236 #define DMA_TCD_CH22_CSR_ERQ_SHIFT (0U) 9237 #define DMA_TCD_CH22_CSR_ERQ_WIDTH (1U) 9238 #define DMA_TCD_CH22_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_CSR_ERQ_SHIFT)) & DMA_TCD_CH22_CSR_ERQ_MASK) 9239 9240 #define DMA_TCD_CH22_CSR_EARQ_MASK (0x2U) 9241 #define DMA_TCD_CH22_CSR_EARQ_SHIFT (1U) 9242 #define DMA_TCD_CH22_CSR_EARQ_WIDTH (1U) 9243 #define DMA_TCD_CH22_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_CSR_EARQ_SHIFT)) & DMA_TCD_CH22_CSR_EARQ_MASK) 9244 9245 #define DMA_TCD_CH22_CSR_EEI_MASK (0x4U) 9246 #define DMA_TCD_CH22_CSR_EEI_SHIFT (2U) 9247 #define DMA_TCD_CH22_CSR_EEI_WIDTH (1U) 9248 #define DMA_TCD_CH22_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_CSR_EEI_SHIFT)) & DMA_TCD_CH22_CSR_EEI_MASK) 9249 9250 #define DMA_TCD_CH22_CSR_EBW_MASK (0x8U) 9251 #define DMA_TCD_CH22_CSR_EBW_SHIFT (3U) 9252 #define DMA_TCD_CH22_CSR_EBW_WIDTH (1U) 9253 #define DMA_TCD_CH22_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_CSR_EBW_SHIFT)) & DMA_TCD_CH22_CSR_EBW_MASK) 9254 9255 #define DMA_TCD_CH22_CSR_DONE_MASK (0x40000000U) 9256 #define DMA_TCD_CH22_CSR_DONE_SHIFT (30U) 9257 #define DMA_TCD_CH22_CSR_DONE_WIDTH (1U) 9258 #define DMA_TCD_CH22_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_CSR_DONE_SHIFT)) & DMA_TCD_CH22_CSR_DONE_MASK) 9259 9260 #define DMA_TCD_CH22_CSR_ACTIVE_MASK (0x80000000U) 9261 #define DMA_TCD_CH22_CSR_ACTIVE_SHIFT (31U) 9262 #define DMA_TCD_CH22_CSR_ACTIVE_WIDTH (1U) 9263 #define DMA_TCD_CH22_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH22_CSR_ACTIVE_MASK) 9264 /*! @} */ 9265 9266 /*! @name CH22_ES - Channel Error Status */ 9267 /*! @{ */ 9268 9269 #define DMA_TCD_CH22_ES_DBE_MASK (0x1U) 9270 #define DMA_TCD_CH22_ES_DBE_SHIFT (0U) 9271 #define DMA_TCD_CH22_ES_DBE_WIDTH (1U) 9272 #define DMA_TCD_CH22_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_ES_DBE_SHIFT)) & DMA_TCD_CH22_ES_DBE_MASK) 9273 9274 #define DMA_TCD_CH22_ES_SBE_MASK (0x2U) 9275 #define DMA_TCD_CH22_ES_SBE_SHIFT (1U) 9276 #define DMA_TCD_CH22_ES_SBE_WIDTH (1U) 9277 #define DMA_TCD_CH22_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_ES_SBE_SHIFT)) & DMA_TCD_CH22_ES_SBE_MASK) 9278 9279 #define DMA_TCD_CH22_ES_SGE_MASK (0x4U) 9280 #define DMA_TCD_CH22_ES_SGE_SHIFT (2U) 9281 #define DMA_TCD_CH22_ES_SGE_WIDTH (1U) 9282 #define DMA_TCD_CH22_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_ES_SGE_SHIFT)) & DMA_TCD_CH22_ES_SGE_MASK) 9283 9284 #define DMA_TCD_CH22_ES_NCE_MASK (0x8U) 9285 #define DMA_TCD_CH22_ES_NCE_SHIFT (3U) 9286 #define DMA_TCD_CH22_ES_NCE_WIDTH (1U) 9287 #define DMA_TCD_CH22_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_ES_NCE_SHIFT)) & DMA_TCD_CH22_ES_NCE_MASK) 9288 9289 #define DMA_TCD_CH22_ES_DOE_MASK (0x10U) 9290 #define DMA_TCD_CH22_ES_DOE_SHIFT (4U) 9291 #define DMA_TCD_CH22_ES_DOE_WIDTH (1U) 9292 #define DMA_TCD_CH22_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_ES_DOE_SHIFT)) & DMA_TCD_CH22_ES_DOE_MASK) 9293 9294 #define DMA_TCD_CH22_ES_DAE_MASK (0x20U) 9295 #define DMA_TCD_CH22_ES_DAE_SHIFT (5U) 9296 #define DMA_TCD_CH22_ES_DAE_WIDTH (1U) 9297 #define DMA_TCD_CH22_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_ES_DAE_SHIFT)) & DMA_TCD_CH22_ES_DAE_MASK) 9298 9299 #define DMA_TCD_CH22_ES_SOE_MASK (0x40U) 9300 #define DMA_TCD_CH22_ES_SOE_SHIFT (6U) 9301 #define DMA_TCD_CH22_ES_SOE_WIDTH (1U) 9302 #define DMA_TCD_CH22_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_ES_SOE_SHIFT)) & DMA_TCD_CH22_ES_SOE_MASK) 9303 9304 #define DMA_TCD_CH22_ES_SAE_MASK (0x80U) 9305 #define DMA_TCD_CH22_ES_SAE_SHIFT (7U) 9306 #define DMA_TCD_CH22_ES_SAE_WIDTH (1U) 9307 #define DMA_TCD_CH22_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_ES_SAE_SHIFT)) & DMA_TCD_CH22_ES_SAE_MASK) 9308 9309 #define DMA_TCD_CH22_ES_ERR_MASK (0x80000000U) 9310 #define DMA_TCD_CH22_ES_ERR_SHIFT (31U) 9311 #define DMA_TCD_CH22_ES_ERR_WIDTH (1U) 9312 #define DMA_TCD_CH22_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_ES_ERR_SHIFT)) & DMA_TCD_CH22_ES_ERR_MASK) 9313 /*! @} */ 9314 9315 /*! @name CH22_INT - Channel Interrupt Status */ 9316 /*! @{ */ 9317 9318 #define DMA_TCD_CH22_INT_INT_MASK (0x1U) 9319 #define DMA_TCD_CH22_INT_INT_SHIFT (0U) 9320 #define DMA_TCD_CH22_INT_INT_WIDTH (1U) 9321 #define DMA_TCD_CH22_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_INT_INT_SHIFT)) & DMA_TCD_CH22_INT_INT_MASK) 9322 /*! @} */ 9323 9324 /*! @name CH22_SBR - Channel System Bus */ 9325 /*! @{ */ 9326 9327 #define DMA_TCD_CH22_SBR_MID_MASK (0xFU) 9328 #define DMA_TCD_CH22_SBR_MID_SHIFT (0U) 9329 #define DMA_TCD_CH22_SBR_MID_WIDTH (4U) 9330 #define DMA_TCD_CH22_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_SBR_MID_SHIFT)) & DMA_TCD_CH22_SBR_MID_MASK) 9331 9332 #define DMA_TCD_CH22_SBR_PAL_MASK (0x8000U) 9333 #define DMA_TCD_CH22_SBR_PAL_SHIFT (15U) 9334 #define DMA_TCD_CH22_SBR_PAL_WIDTH (1U) 9335 #define DMA_TCD_CH22_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_SBR_PAL_SHIFT)) & DMA_TCD_CH22_SBR_PAL_MASK) 9336 9337 #define DMA_TCD_CH22_SBR_EMI_MASK (0x10000U) 9338 #define DMA_TCD_CH22_SBR_EMI_SHIFT (16U) 9339 #define DMA_TCD_CH22_SBR_EMI_WIDTH (1U) 9340 #define DMA_TCD_CH22_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_SBR_EMI_SHIFT)) & DMA_TCD_CH22_SBR_EMI_MASK) 9341 9342 #define DMA_TCD_CH22_SBR_ATTR_MASK (0xE0000U) 9343 #define DMA_TCD_CH22_SBR_ATTR_SHIFT (17U) 9344 #define DMA_TCD_CH22_SBR_ATTR_WIDTH (3U) 9345 #define DMA_TCD_CH22_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_SBR_ATTR_SHIFT)) & DMA_TCD_CH22_SBR_ATTR_MASK) 9346 /*! @} */ 9347 9348 /*! @name CH22_PRI - Channel Priority */ 9349 /*! @{ */ 9350 9351 #define DMA_TCD_CH22_PRI_APL_MASK (0x7U) 9352 #define DMA_TCD_CH22_PRI_APL_SHIFT (0U) 9353 #define DMA_TCD_CH22_PRI_APL_WIDTH (3U) 9354 #define DMA_TCD_CH22_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_PRI_APL_SHIFT)) & DMA_TCD_CH22_PRI_APL_MASK) 9355 9356 #define DMA_TCD_CH22_PRI_DPA_MASK (0x40000000U) 9357 #define DMA_TCD_CH22_PRI_DPA_SHIFT (30U) 9358 #define DMA_TCD_CH22_PRI_DPA_WIDTH (1U) 9359 #define DMA_TCD_CH22_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_PRI_DPA_SHIFT)) & DMA_TCD_CH22_PRI_DPA_MASK) 9360 9361 #define DMA_TCD_CH22_PRI_ECP_MASK (0x80000000U) 9362 #define DMA_TCD_CH22_PRI_ECP_SHIFT (31U) 9363 #define DMA_TCD_CH22_PRI_ECP_WIDTH (1U) 9364 #define DMA_TCD_CH22_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH22_PRI_ECP_SHIFT)) & DMA_TCD_CH22_PRI_ECP_MASK) 9365 /*! @} */ 9366 9367 /*! @name TCD22_SADDR - TCD Source Address */ 9368 /*! @{ */ 9369 9370 #define DMA_TCD_TCD22_SADDR_SADDR_MASK (0xFFFFFFFFU) 9371 #define DMA_TCD_TCD22_SADDR_SADDR_SHIFT (0U) 9372 #define DMA_TCD_TCD22_SADDR_SADDR_WIDTH (32U) 9373 #define DMA_TCD_TCD22_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD22_SADDR_SADDR_MASK) 9374 /*! @} */ 9375 9376 /*! @name TCD22_SOFF - TCD Signed Source Address Offset */ 9377 /*! @{ */ 9378 9379 #define DMA_TCD_TCD22_SOFF_SOFF_MASK (0xFFFFU) 9380 #define DMA_TCD_TCD22_SOFF_SOFF_SHIFT (0U) 9381 #define DMA_TCD_TCD22_SOFF_SOFF_WIDTH (16U) 9382 #define DMA_TCD_TCD22_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD22_SOFF_SOFF_MASK) 9383 /*! @} */ 9384 9385 /*! @name TCD22_ATTR - TCD Transfer Attributes */ 9386 /*! @{ */ 9387 9388 #define DMA_TCD_TCD22_ATTR_DSIZE_MASK (0x7U) 9389 #define DMA_TCD_TCD22_ATTR_DSIZE_SHIFT (0U) 9390 #define DMA_TCD_TCD22_ATTR_DSIZE_WIDTH (3U) 9391 #define DMA_TCD_TCD22_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD22_ATTR_DSIZE_MASK) 9392 9393 #define DMA_TCD_TCD22_ATTR_DMOD_MASK (0xF8U) 9394 #define DMA_TCD_TCD22_ATTR_DMOD_SHIFT (3U) 9395 #define DMA_TCD_TCD22_ATTR_DMOD_WIDTH (5U) 9396 #define DMA_TCD_TCD22_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD22_ATTR_DMOD_MASK) 9397 9398 #define DMA_TCD_TCD22_ATTR_SSIZE_MASK (0x700U) 9399 #define DMA_TCD_TCD22_ATTR_SSIZE_SHIFT (8U) 9400 #define DMA_TCD_TCD22_ATTR_SSIZE_WIDTH (3U) 9401 #define DMA_TCD_TCD22_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD22_ATTR_SSIZE_MASK) 9402 9403 #define DMA_TCD_TCD22_ATTR_SMOD_MASK (0xF800U) 9404 #define DMA_TCD_TCD22_ATTR_SMOD_SHIFT (11U) 9405 #define DMA_TCD_TCD22_ATTR_SMOD_WIDTH (5U) 9406 #define DMA_TCD_TCD22_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD22_ATTR_SMOD_MASK) 9407 /*! @} */ 9408 9409 /*! @name TCD22_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 9410 /*! @{ */ 9411 9412 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 9413 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 9414 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 9415 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD22_NBYTES_MLOFFNO_NBYTES_MASK) 9416 9417 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 9418 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 9419 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 9420 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD22_NBYTES_MLOFFNO_DMLOE_MASK) 9421 9422 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 9423 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 9424 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 9425 #define DMA_TCD_TCD22_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD22_NBYTES_MLOFFNO_SMLOE_MASK) 9426 /*! @} */ 9427 9428 /*! @name TCD22_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 9429 /*! @{ */ 9430 9431 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 9432 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 9433 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 9434 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD22_NBYTES_MLOFFYES_NBYTES_MASK) 9435 9436 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 9437 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 9438 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 9439 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD22_NBYTES_MLOFFYES_MLOFF_MASK) 9440 9441 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 9442 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 9443 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 9444 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD22_NBYTES_MLOFFYES_DMLOE_MASK) 9445 9446 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 9447 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 9448 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 9449 #define DMA_TCD_TCD22_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD22_NBYTES_MLOFFYES_SMLOE_MASK) 9450 /*! @} */ 9451 9452 /*! @name TCD22_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 9453 /*! @{ */ 9454 9455 #define DMA_TCD_TCD22_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 9456 #define DMA_TCD_TCD22_SLAST_SDA_SLAST_SDA_SHIFT (0U) 9457 #define DMA_TCD_TCD22_SLAST_SDA_SLAST_SDA_WIDTH (32U) 9458 #define DMA_TCD_TCD22_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD22_SLAST_SDA_SLAST_SDA_MASK) 9459 /*! @} */ 9460 9461 /*! @name TCD22_DADDR - TCD Destination Address */ 9462 /*! @{ */ 9463 9464 #define DMA_TCD_TCD22_DADDR_DADDR_MASK (0xFFFFFFFFU) 9465 #define DMA_TCD_TCD22_DADDR_DADDR_SHIFT (0U) 9466 #define DMA_TCD_TCD22_DADDR_DADDR_WIDTH (32U) 9467 #define DMA_TCD_TCD22_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD22_DADDR_DADDR_MASK) 9468 /*! @} */ 9469 9470 /*! @name TCD22_DOFF - TCD Signed Destination Address Offset */ 9471 /*! @{ */ 9472 9473 #define DMA_TCD_TCD22_DOFF_DOFF_MASK (0xFFFFU) 9474 #define DMA_TCD_TCD22_DOFF_DOFF_SHIFT (0U) 9475 #define DMA_TCD_TCD22_DOFF_DOFF_WIDTH (16U) 9476 #define DMA_TCD_TCD22_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD22_DOFF_DOFF_MASK) 9477 /*! @} */ 9478 9479 /*! @name TCD22_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 9480 /*! @{ */ 9481 9482 #define DMA_TCD_TCD22_CITER_ELINKNO_CITER_MASK (0x7FFFU) 9483 #define DMA_TCD_TCD22_CITER_ELINKNO_CITER_SHIFT (0U) 9484 #define DMA_TCD_TCD22_CITER_ELINKNO_CITER_WIDTH (15U) 9485 #define DMA_TCD_TCD22_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD22_CITER_ELINKNO_CITER_MASK) 9486 9487 #define DMA_TCD_TCD22_CITER_ELINKNO_ELINK_MASK (0x8000U) 9488 #define DMA_TCD_TCD22_CITER_ELINKNO_ELINK_SHIFT (15U) 9489 #define DMA_TCD_TCD22_CITER_ELINKNO_ELINK_WIDTH (1U) 9490 #define DMA_TCD_TCD22_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD22_CITER_ELINKNO_ELINK_MASK) 9491 /*! @} */ 9492 9493 /*! @name TCD22_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 9494 /*! @{ */ 9495 9496 #define DMA_TCD_TCD22_CITER_ELINKYES_CITER_MASK (0x1FFU) 9497 #define DMA_TCD_TCD22_CITER_ELINKYES_CITER_SHIFT (0U) 9498 #define DMA_TCD_TCD22_CITER_ELINKYES_CITER_WIDTH (9U) 9499 #define DMA_TCD_TCD22_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD22_CITER_ELINKYES_CITER_MASK) 9500 9501 #define DMA_TCD_TCD22_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 9502 #define DMA_TCD_TCD22_CITER_ELINKYES_LINKCH_SHIFT (9U) 9503 #define DMA_TCD_TCD22_CITER_ELINKYES_LINKCH_WIDTH (5U) 9504 #define DMA_TCD_TCD22_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD22_CITER_ELINKYES_LINKCH_MASK) 9505 9506 #define DMA_TCD_TCD22_CITER_ELINKYES_ELINK_MASK (0x8000U) 9507 #define DMA_TCD_TCD22_CITER_ELINKYES_ELINK_SHIFT (15U) 9508 #define DMA_TCD_TCD22_CITER_ELINKYES_ELINK_WIDTH (1U) 9509 #define DMA_TCD_TCD22_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD22_CITER_ELINKYES_ELINK_MASK) 9510 /*! @} */ 9511 9512 /*! @name TCD22_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 9513 /*! @{ */ 9514 9515 #define DMA_TCD_TCD22_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 9516 #define DMA_TCD_TCD22_DLAST_SGA_DLAST_SGA_SHIFT (0U) 9517 #define DMA_TCD_TCD22_DLAST_SGA_DLAST_SGA_WIDTH (32U) 9518 #define DMA_TCD_TCD22_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD22_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD22_DLAST_SGA_DLAST_SGA_MASK) 9519 /*! @} */ 9520 9521 /*! @name TCD22_CSR - TCD Control and Status */ 9522 /*! @{ */ 9523 9524 #define DMA_TCD_TCD22_CSR_START_MASK (0x1U) 9525 #define DMA_TCD_TCD22_CSR_START_SHIFT (0U) 9526 #define DMA_TCD_TCD22_CSR_START_WIDTH (1U) 9527 #define DMA_TCD_TCD22_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CSR_START_SHIFT)) & DMA_TCD_TCD22_CSR_START_MASK) 9528 9529 #define DMA_TCD_TCD22_CSR_INTMAJOR_MASK (0x2U) 9530 #define DMA_TCD_TCD22_CSR_INTMAJOR_SHIFT (1U) 9531 #define DMA_TCD_TCD22_CSR_INTMAJOR_WIDTH (1U) 9532 #define DMA_TCD_TCD22_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD22_CSR_INTMAJOR_MASK) 9533 9534 #define DMA_TCD_TCD22_CSR_INTHALF_MASK (0x4U) 9535 #define DMA_TCD_TCD22_CSR_INTHALF_SHIFT (2U) 9536 #define DMA_TCD_TCD22_CSR_INTHALF_WIDTH (1U) 9537 #define DMA_TCD_TCD22_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD22_CSR_INTHALF_MASK) 9538 9539 #define DMA_TCD_TCD22_CSR_DREQ_MASK (0x8U) 9540 #define DMA_TCD_TCD22_CSR_DREQ_SHIFT (3U) 9541 #define DMA_TCD_TCD22_CSR_DREQ_WIDTH (1U) 9542 #define DMA_TCD_TCD22_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CSR_DREQ_SHIFT)) & DMA_TCD_TCD22_CSR_DREQ_MASK) 9543 9544 #define DMA_TCD_TCD22_CSR_ESG_MASK (0x10U) 9545 #define DMA_TCD_TCD22_CSR_ESG_SHIFT (4U) 9546 #define DMA_TCD_TCD22_CSR_ESG_WIDTH (1U) 9547 #define DMA_TCD_TCD22_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CSR_ESG_SHIFT)) & DMA_TCD_TCD22_CSR_ESG_MASK) 9548 9549 #define DMA_TCD_TCD22_CSR_MAJORELINK_MASK (0x20U) 9550 #define DMA_TCD_TCD22_CSR_MAJORELINK_SHIFT (5U) 9551 #define DMA_TCD_TCD22_CSR_MAJORELINK_WIDTH (1U) 9552 #define DMA_TCD_TCD22_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD22_CSR_MAJORELINK_MASK) 9553 9554 #define DMA_TCD_TCD22_CSR_EEOP_MASK (0x40U) 9555 #define DMA_TCD_TCD22_CSR_EEOP_SHIFT (6U) 9556 #define DMA_TCD_TCD22_CSR_EEOP_WIDTH (1U) 9557 #define DMA_TCD_TCD22_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CSR_EEOP_SHIFT)) & DMA_TCD_TCD22_CSR_EEOP_MASK) 9558 9559 #define DMA_TCD_TCD22_CSR_ESDA_MASK (0x80U) 9560 #define DMA_TCD_TCD22_CSR_ESDA_SHIFT (7U) 9561 #define DMA_TCD_TCD22_CSR_ESDA_WIDTH (1U) 9562 #define DMA_TCD_TCD22_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CSR_ESDA_SHIFT)) & DMA_TCD_TCD22_CSR_ESDA_MASK) 9563 9564 #define DMA_TCD_TCD22_CSR_MAJORLINKCH_MASK (0x1F00U) 9565 #define DMA_TCD_TCD22_CSR_MAJORLINKCH_SHIFT (8U) 9566 #define DMA_TCD_TCD22_CSR_MAJORLINKCH_WIDTH (5U) 9567 #define DMA_TCD_TCD22_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD22_CSR_MAJORLINKCH_MASK) 9568 9569 #define DMA_TCD_TCD22_CSR_BWC_MASK (0xC000U) 9570 #define DMA_TCD_TCD22_CSR_BWC_SHIFT (14U) 9571 #define DMA_TCD_TCD22_CSR_BWC_WIDTH (2U) 9572 #define DMA_TCD_TCD22_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_CSR_BWC_SHIFT)) & DMA_TCD_TCD22_CSR_BWC_MASK) 9573 /*! @} */ 9574 9575 /*! @name TCD22_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 9576 /*! @{ */ 9577 9578 #define DMA_TCD_TCD22_BITER_ELINKNO_BITER_MASK (0x7FFFU) 9579 #define DMA_TCD_TCD22_BITER_ELINKNO_BITER_SHIFT (0U) 9580 #define DMA_TCD_TCD22_BITER_ELINKNO_BITER_WIDTH (15U) 9581 #define DMA_TCD_TCD22_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD22_BITER_ELINKNO_BITER_MASK) 9582 9583 #define DMA_TCD_TCD22_BITER_ELINKNO_ELINK_MASK (0x8000U) 9584 #define DMA_TCD_TCD22_BITER_ELINKNO_ELINK_SHIFT (15U) 9585 #define DMA_TCD_TCD22_BITER_ELINKNO_ELINK_WIDTH (1U) 9586 #define DMA_TCD_TCD22_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD22_BITER_ELINKNO_ELINK_MASK) 9587 /*! @} */ 9588 9589 /*! @name TCD22_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 9590 /*! @{ */ 9591 9592 #define DMA_TCD_TCD22_BITER_ELINKYES_BITER_MASK (0x1FFU) 9593 #define DMA_TCD_TCD22_BITER_ELINKYES_BITER_SHIFT (0U) 9594 #define DMA_TCD_TCD22_BITER_ELINKYES_BITER_WIDTH (9U) 9595 #define DMA_TCD_TCD22_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD22_BITER_ELINKYES_BITER_MASK) 9596 9597 #define DMA_TCD_TCD22_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 9598 #define DMA_TCD_TCD22_BITER_ELINKYES_LINKCH_SHIFT (9U) 9599 #define DMA_TCD_TCD22_BITER_ELINKYES_LINKCH_WIDTH (5U) 9600 #define DMA_TCD_TCD22_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD22_BITER_ELINKYES_LINKCH_MASK) 9601 9602 #define DMA_TCD_TCD22_BITER_ELINKYES_ELINK_MASK (0x8000U) 9603 #define DMA_TCD_TCD22_BITER_ELINKYES_ELINK_SHIFT (15U) 9604 #define DMA_TCD_TCD22_BITER_ELINKYES_ELINK_WIDTH (1U) 9605 #define DMA_TCD_TCD22_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD22_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD22_BITER_ELINKYES_ELINK_MASK) 9606 /*! @} */ 9607 9608 /*! @name CH23_CSR - Channel Control and Status */ 9609 /*! @{ */ 9610 9611 #define DMA_TCD_CH23_CSR_ERQ_MASK (0x1U) 9612 #define DMA_TCD_CH23_CSR_ERQ_SHIFT (0U) 9613 #define DMA_TCD_CH23_CSR_ERQ_WIDTH (1U) 9614 #define DMA_TCD_CH23_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_CSR_ERQ_SHIFT)) & DMA_TCD_CH23_CSR_ERQ_MASK) 9615 9616 #define DMA_TCD_CH23_CSR_EARQ_MASK (0x2U) 9617 #define DMA_TCD_CH23_CSR_EARQ_SHIFT (1U) 9618 #define DMA_TCD_CH23_CSR_EARQ_WIDTH (1U) 9619 #define DMA_TCD_CH23_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_CSR_EARQ_SHIFT)) & DMA_TCD_CH23_CSR_EARQ_MASK) 9620 9621 #define DMA_TCD_CH23_CSR_EEI_MASK (0x4U) 9622 #define DMA_TCD_CH23_CSR_EEI_SHIFT (2U) 9623 #define DMA_TCD_CH23_CSR_EEI_WIDTH (1U) 9624 #define DMA_TCD_CH23_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_CSR_EEI_SHIFT)) & DMA_TCD_CH23_CSR_EEI_MASK) 9625 9626 #define DMA_TCD_CH23_CSR_EBW_MASK (0x8U) 9627 #define DMA_TCD_CH23_CSR_EBW_SHIFT (3U) 9628 #define DMA_TCD_CH23_CSR_EBW_WIDTH (1U) 9629 #define DMA_TCD_CH23_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_CSR_EBW_SHIFT)) & DMA_TCD_CH23_CSR_EBW_MASK) 9630 9631 #define DMA_TCD_CH23_CSR_DONE_MASK (0x40000000U) 9632 #define DMA_TCD_CH23_CSR_DONE_SHIFT (30U) 9633 #define DMA_TCD_CH23_CSR_DONE_WIDTH (1U) 9634 #define DMA_TCD_CH23_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_CSR_DONE_SHIFT)) & DMA_TCD_CH23_CSR_DONE_MASK) 9635 9636 #define DMA_TCD_CH23_CSR_ACTIVE_MASK (0x80000000U) 9637 #define DMA_TCD_CH23_CSR_ACTIVE_SHIFT (31U) 9638 #define DMA_TCD_CH23_CSR_ACTIVE_WIDTH (1U) 9639 #define DMA_TCD_CH23_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH23_CSR_ACTIVE_MASK) 9640 /*! @} */ 9641 9642 /*! @name CH23_ES - Channel Error Status */ 9643 /*! @{ */ 9644 9645 #define DMA_TCD_CH23_ES_DBE_MASK (0x1U) 9646 #define DMA_TCD_CH23_ES_DBE_SHIFT (0U) 9647 #define DMA_TCD_CH23_ES_DBE_WIDTH (1U) 9648 #define DMA_TCD_CH23_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_ES_DBE_SHIFT)) & DMA_TCD_CH23_ES_DBE_MASK) 9649 9650 #define DMA_TCD_CH23_ES_SBE_MASK (0x2U) 9651 #define DMA_TCD_CH23_ES_SBE_SHIFT (1U) 9652 #define DMA_TCD_CH23_ES_SBE_WIDTH (1U) 9653 #define DMA_TCD_CH23_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_ES_SBE_SHIFT)) & DMA_TCD_CH23_ES_SBE_MASK) 9654 9655 #define DMA_TCD_CH23_ES_SGE_MASK (0x4U) 9656 #define DMA_TCD_CH23_ES_SGE_SHIFT (2U) 9657 #define DMA_TCD_CH23_ES_SGE_WIDTH (1U) 9658 #define DMA_TCD_CH23_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_ES_SGE_SHIFT)) & DMA_TCD_CH23_ES_SGE_MASK) 9659 9660 #define DMA_TCD_CH23_ES_NCE_MASK (0x8U) 9661 #define DMA_TCD_CH23_ES_NCE_SHIFT (3U) 9662 #define DMA_TCD_CH23_ES_NCE_WIDTH (1U) 9663 #define DMA_TCD_CH23_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_ES_NCE_SHIFT)) & DMA_TCD_CH23_ES_NCE_MASK) 9664 9665 #define DMA_TCD_CH23_ES_DOE_MASK (0x10U) 9666 #define DMA_TCD_CH23_ES_DOE_SHIFT (4U) 9667 #define DMA_TCD_CH23_ES_DOE_WIDTH (1U) 9668 #define DMA_TCD_CH23_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_ES_DOE_SHIFT)) & DMA_TCD_CH23_ES_DOE_MASK) 9669 9670 #define DMA_TCD_CH23_ES_DAE_MASK (0x20U) 9671 #define DMA_TCD_CH23_ES_DAE_SHIFT (5U) 9672 #define DMA_TCD_CH23_ES_DAE_WIDTH (1U) 9673 #define DMA_TCD_CH23_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_ES_DAE_SHIFT)) & DMA_TCD_CH23_ES_DAE_MASK) 9674 9675 #define DMA_TCD_CH23_ES_SOE_MASK (0x40U) 9676 #define DMA_TCD_CH23_ES_SOE_SHIFT (6U) 9677 #define DMA_TCD_CH23_ES_SOE_WIDTH (1U) 9678 #define DMA_TCD_CH23_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_ES_SOE_SHIFT)) & DMA_TCD_CH23_ES_SOE_MASK) 9679 9680 #define DMA_TCD_CH23_ES_SAE_MASK (0x80U) 9681 #define DMA_TCD_CH23_ES_SAE_SHIFT (7U) 9682 #define DMA_TCD_CH23_ES_SAE_WIDTH (1U) 9683 #define DMA_TCD_CH23_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_ES_SAE_SHIFT)) & DMA_TCD_CH23_ES_SAE_MASK) 9684 9685 #define DMA_TCD_CH23_ES_ERR_MASK (0x80000000U) 9686 #define DMA_TCD_CH23_ES_ERR_SHIFT (31U) 9687 #define DMA_TCD_CH23_ES_ERR_WIDTH (1U) 9688 #define DMA_TCD_CH23_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_ES_ERR_SHIFT)) & DMA_TCD_CH23_ES_ERR_MASK) 9689 /*! @} */ 9690 9691 /*! @name CH23_INT - Channel Interrupt Status */ 9692 /*! @{ */ 9693 9694 #define DMA_TCD_CH23_INT_INT_MASK (0x1U) 9695 #define DMA_TCD_CH23_INT_INT_SHIFT (0U) 9696 #define DMA_TCD_CH23_INT_INT_WIDTH (1U) 9697 #define DMA_TCD_CH23_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_INT_INT_SHIFT)) & DMA_TCD_CH23_INT_INT_MASK) 9698 /*! @} */ 9699 9700 /*! @name CH23_SBR - Channel System Bus */ 9701 /*! @{ */ 9702 9703 #define DMA_TCD_CH23_SBR_MID_MASK (0xFU) 9704 #define DMA_TCD_CH23_SBR_MID_SHIFT (0U) 9705 #define DMA_TCD_CH23_SBR_MID_WIDTH (4U) 9706 #define DMA_TCD_CH23_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_SBR_MID_SHIFT)) & DMA_TCD_CH23_SBR_MID_MASK) 9707 9708 #define DMA_TCD_CH23_SBR_PAL_MASK (0x8000U) 9709 #define DMA_TCD_CH23_SBR_PAL_SHIFT (15U) 9710 #define DMA_TCD_CH23_SBR_PAL_WIDTH (1U) 9711 #define DMA_TCD_CH23_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_SBR_PAL_SHIFT)) & DMA_TCD_CH23_SBR_PAL_MASK) 9712 9713 #define DMA_TCD_CH23_SBR_EMI_MASK (0x10000U) 9714 #define DMA_TCD_CH23_SBR_EMI_SHIFT (16U) 9715 #define DMA_TCD_CH23_SBR_EMI_WIDTH (1U) 9716 #define DMA_TCD_CH23_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_SBR_EMI_SHIFT)) & DMA_TCD_CH23_SBR_EMI_MASK) 9717 9718 #define DMA_TCD_CH23_SBR_ATTR_MASK (0xE0000U) 9719 #define DMA_TCD_CH23_SBR_ATTR_SHIFT (17U) 9720 #define DMA_TCD_CH23_SBR_ATTR_WIDTH (3U) 9721 #define DMA_TCD_CH23_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_SBR_ATTR_SHIFT)) & DMA_TCD_CH23_SBR_ATTR_MASK) 9722 /*! @} */ 9723 9724 /*! @name CH23_PRI - Channel Priority */ 9725 /*! @{ */ 9726 9727 #define DMA_TCD_CH23_PRI_APL_MASK (0x7U) 9728 #define DMA_TCD_CH23_PRI_APL_SHIFT (0U) 9729 #define DMA_TCD_CH23_PRI_APL_WIDTH (3U) 9730 #define DMA_TCD_CH23_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_PRI_APL_SHIFT)) & DMA_TCD_CH23_PRI_APL_MASK) 9731 9732 #define DMA_TCD_CH23_PRI_DPA_MASK (0x40000000U) 9733 #define DMA_TCD_CH23_PRI_DPA_SHIFT (30U) 9734 #define DMA_TCD_CH23_PRI_DPA_WIDTH (1U) 9735 #define DMA_TCD_CH23_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_PRI_DPA_SHIFT)) & DMA_TCD_CH23_PRI_DPA_MASK) 9736 9737 #define DMA_TCD_CH23_PRI_ECP_MASK (0x80000000U) 9738 #define DMA_TCD_CH23_PRI_ECP_SHIFT (31U) 9739 #define DMA_TCD_CH23_PRI_ECP_WIDTH (1U) 9740 #define DMA_TCD_CH23_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH23_PRI_ECP_SHIFT)) & DMA_TCD_CH23_PRI_ECP_MASK) 9741 /*! @} */ 9742 9743 /*! @name TCD23_SADDR - TCD Source Address */ 9744 /*! @{ */ 9745 9746 #define DMA_TCD_TCD23_SADDR_SADDR_MASK (0xFFFFFFFFU) 9747 #define DMA_TCD_TCD23_SADDR_SADDR_SHIFT (0U) 9748 #define DMA_TCD_TCD23_SADDR_SADDR_WIDTH (32U) 9749 #define DMA_TCD_TCD23_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD23_SADDR_SADDR_MASK) 9750 /*! @} */ 9751 9752 /*! @name TCD23_SOFF - TCD Signed Source Address Offset */ 9753 /*! @{ */ 9754 9755 #define DMA_TCD_TCD23_SOFF_SOFF_MASK (0xFFFFU) 9756 #define DMA_TCD_TCD23_SOFF_SOFF_SHIFT (0U) 9757 #define DMA_TCD_TCD23_SOFF_SOFF_WIDTH (16U) 9758 #define DMA_TCD_TCD23_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD23_SOFF_SOFF_MASK) 9759 /*! @} */ 9760 9761 /*! @name TCD23_ATTR - TCD Transfer Attributes */ 9762 /*! @{ */ 9763 9764 #define DMA_TCD_TCD23_ATTR_DSIZE_MASK (0x7U) 9765 #define DMA_TCD_TCD23_ATTR_DSIZE_SHIFT (0U) 9766 #define DMA_TCD_TCD23_ATTR_DSIZE_WIDTH (3U) 9767 #define DMA_TCD_TCD23_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD23_ATTR_DSIZE_MASK) 9768 9769 #define DMA_TCD_TCD23_ATTR_DMOD_MASK (0xF8U) 9770 #define DMA_TCD_TCD23_ATTR_DMOD_SHIFT (3U) 9771 #define DMA_TCD_TCD23_ATTR_DMOD_WIDTH (5U) 9772 #define DMA_TCD_TCD23_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD23_ATTR_DMOD_MASK) 9773 9774 #define DMA_TCD_TCD23_ATTR_SSIZE_MASK (0x700U) 9775 #define DMA_TCD_TCD23_ATTR_SSIZE_SHIFT (8U) 9776 #define DMA_TCD_TCD23_ATTR_SSIZE_WIDTH (3U) 9777 #define DMA_TCD_TCD23_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD23_ATTR_SSIZE_MASK) 9778 9779 #define DMA_TCD_TCD23_ATTR_SMOD_MASK (0xF800U) 9780 #define DMA_TCD_TCD23_ATTR_SMOD_SHIFT (11U) 9781 #define DMA_TCD_TCD23_ATTR_SMOD_WIDTH (5U) 9782 #define DMA_TCD_TCD23_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD23_ATTR_SMOD_MASK) 9783 /*! @} */ 9784 9785 /*! @name TCD23_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 9786 /*! @{ */ 9787 9788 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 9789 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 9790 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 9791 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD23_NBYTES_MLOFFNO_NBYTES_MASK) 9792 9793 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 9794 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 9795 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 9796 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD23_NBYTES_MLOFFNO_DMLOE_MASK) 9797 9798 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 9799 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 9800 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 9801 #define DMA_TCD_TCD23_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD23_NBYTES_MLOFFNO_SMLOE_MASK) 9802 /*! @} */ 9803 9804 /*! @name TCD23_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 9805 /*! @{ */ 9806 9807 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 9808 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 9809 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 9810 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD23_NBYTES_MLOFFYES_NBYTES_MASK) 9811 9812 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 9813 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 9814 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 9815 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD23_NBYTES_MLOFFYES_MLOFF_MASK) 9816 9817 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 9818 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 9819 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 9820 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD23_NBYTES_MLOFFYES_DMLOE_MASK) 9821 9822 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 9823 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 9824 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 9825 #define DMA_TCD_TCD23_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD23_NBYTES_MLOFFYES_SMLOE_MASK) 9826 /*! @} */ 9827 9828 /*! @name TCD23_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 9829 /*! @{ */ 9830 9831 #define DMA_TCD_TCD23_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 9832 #define DMA_TCD_TCD23_SLAST_SDA_SLAST_SDA_SHIFT (0U) 9833 #define DMA_TCD_TCD23_SLAST_SDA_SLAST_SDA_WIDTH (32U) 9834 #define DMA_TCD_TCD23_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD23_SLAST_SDA_SLAST_SDA_MASK) 9835 /*! @} */ 9836 9837 /*! @name TCD23_DADDR - TCD Destination Address */ 9838 /*! @{ */ 9839 9840 #define DMA_TCD_TCD23_DADDR_DADDR_MASK (0xFFFFFFFFU) 9841 #define DMA_TCD_TCD23_DADDR_DADDR_SHIFT (0U) 9842 #define DMA_TCD_TCD23_DADDR_DADDR_WIDTH (32U) 9843 #define DMA_TCD_TCD23_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD23_DADDR_DADDR_MASK) 9844 /*! @} */ 9845 9846 /*! @name TCD23_DOFF - TCD Signed Destination Address Offset */ 9847 /*! @{ */ 9848 9849 #define DMA_TCD_TCD23_DOFF_DOFF_MASK (0xFFFFU) 9850 #define DMA_TCD_TCD23_DOFF_DOFF_SHIFT (0U) 9851 #define DMA_TCD_TCD23_DOFF_DOFF_WIDTH (16U) 9852 #define DMA_TCD_TCD23_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD23_DOFF_DOFF_MASK) 9853 /*! @} */ 9854 9855 /*! @name TCD23_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 9856 /*! @{ */ 9857 9858 #define DMA_TCD_TCD23_CITER_ELINKNO_CITER_MASK (0x7FFFU) 9859 #define DMA_TCD_TCD23_CITER_ELINKNO_CITER_SHIFT (0U) 9860 #define DMA_TCD_TCD23_CITER_ELINKNO_CITER_WIDTH (15U) 9861 #define DMA_TCD_TCD23_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD23_CITER_ELINKNO_CITER_MASK) 9862 9863 #define DMA_TCD_TCD23_CITER_ELINKNO_ELINK_MASK (0x8000U) 9864 #define DMA_TCD_TCD23_CITER_ELINKNO_ELINK_SHIFT (15U) 9865 #define DMA_TCD_TCD23_CITER_ELINKNO_ELINK_WIDTH (1U) 9866 #define DMA_TCD_TCD23_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD23_CITER_ELINKNO_ELINK_MASK) 9867 /*! @} */ 9868 9869 /*! @name TCD23_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 9870 /*! @{ */ 9871 9872 #define DMA_TCD_TCD23_CITER_ELINKYES_CITER_MASK (0x1FFU) 9873 #define DMA_TCD_TCD23_CITER_ELINKYES_CITER_SHIFT (0U) 9874 #define DMA_TCD_TCD23_CITER_ELINKYES_CITER_WIDTH (9U) 9875 #define DMA_TCD_TCD23_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD23_CITER_ELINKYES_CITER_MASK) 9876 9877 #define DMA_TCD_TCD23_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 9878 #define DMA_TCD_TCD23_CITER_ELINKYES_LINKCH_SHIFT (9U) 9879 #define DMA_TCD_TCD23_CITER_ELINKYES_LINKCH_WIDTH (5U) 9880 #define DMA_TCD_TCD23_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD23_CITER_ELINKYES_LINKCH_MASK) 9881 9882 #define DMA_TCD_TCD23_CITER_ELINKYES_ELINK_MASK (0x8000U) 9883 #define DMA_TCD_TCD23_CITER_ELINKYES_ELINK_SHIFT (15U) 9884 #define DMA_TCD_TCD23_CITER_ELINKYES_ELINK_WIDTH (1U) 9885 #define DMA_TCD_TCD23_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD23_CITER_ELINKYES_ELINK_MASK) 9886 /*! @} */ 9887 9888 /*! @name TCD23_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 9889 /*! @{ */ 9890 9891 #define DMA_TCD_TCD23_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 9892 #define DMA_TCD_TCD23_DLAST_SGA_DLAST_SGA_SHIFT (0U) 9893 #define DMA_TCD_TCD23_DLAST_SGA_DLAST_SGA_WIDTH (32U) 9894 #define DMA_TCD_TCD23_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD23_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD23_DLAST_SGA_DLAST_SGA_MASK) 9895 /*! @} */ 9896 9897 /*! @name TCD23_CSR - TCD Control and Status */ 9898 /*! @{ */ 9899 9900 #define DMA_TCD_TCD23_CSR_START_MASK (0x1U) 9901 #define DMA_TCD_TCD23_CSR_START_SHIFT (0U) 9902 #define DMA_TCD_TCD23_CSR_START_WIDTH (1U) 9903 #define DMA_TCD_TCD23_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CSR_START_SHIFT)) & DMA_TCD_TCD23_CSR_START_MASK) 9904 9905 #define DMA_TCD_TCD23_CSR_INTMAJOR_MASK (0x2U) 9906 #define DMA_TCD_TCD23_CSR_INTMAJOR_SHIFT (1U) 9907 #define DMA_TCD_TCD23_CSR_INTMAJOR_WIDTH (1U) 9908 #define DMA_TCD_TCD23_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD23_CSR_INTMAJOR_MASK) 9909 9910 #define DMA_TCD_TCD23_CSR_INTHALF_MASK (0x4U) 9911 #define DMA_TCD_TCD23_CSR_INTHALF_SHIFT (2U) 9912 #define DMA_TCD_TCD23_CSR_INTHALF_WIDTH (1U) 9913 #define DMA_TCD_TCD23_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD23_CSR_INTHALF_MASK) 9914 9915 #define DMA_TCD_TCD23_CSR_DREQ_MASK (0x8U) 9916 #define DMA_TCD_TCD23_CSR_DREQ_SHIFT (3U) 9917 #define DMA_TCD_TCD23_CSR_DREQ_WIDTH (1U) 9918 #define DMA_TCD_TCD23_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CSR_DREQ_SHIFT)) & DMA_TCD_TCD23_CSR_DREQ_MASK) 9919 9920 #define DMA_TCD_TCD23_CSR_ESG_MASK (0x10U) 9921 #define DMA_TCD_TCD23_CSR_ESG_SHIFT (4U) 9922 #define DMA_TCD_TCD23_CSR_ESG_WIDTH (1U) 9923 #define DMA_TCD_TCD23_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CSR_ESG_SHIFT)) & DMA_TCD_TCD23_CSR_ESG_MASK) 9924 9925 #define DMA_TCD_TCD23_CSR_MAJORELINK_MASK (0x20U) 9926 #define DMA_TCD_TCD23_CSR_MAJORELINK_SHIFT (5U) 9927 #define DMA_TCD_TCD23_CSR_MAJORELINK_WIDTH (1U) 9928 #define DMA_TCD_TCD23_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD23_CSR_MAJORELINK_MASK) 9929 9930 #define DMA_TCD_TCD23_CSR_EEOP_MASK (0x40U) 9931 #define DMA_TCD_TCD23_CSR_EEOP_SHIFT (6U) 9932 #define DMA_TCD_TCD23_CSR_EEOP_WIDTH (1U) 9933 #define DMA_TCD_TCD23_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CSR_EEOP_SHIFT)) & DMA_TCD_TCD23_CSR_EEOP_MASK) 9934 9935 #define DMA_TCD_TCD23_CSR_ESDA_MASK (0x80U) 9936 #define DMA_TCD_TCD23_CSR_ESDA_SHIFT (7U) 9937 #define DMA_TCD_TCD23_CSR_ESDA_WIDTH (1U) 9938 #define DMA_TCD_TCD23_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CSR_ESDA_SHIFT)) & DMA_TCD_TCD23_CSR_ESDA_MASK) 9939 9940 #define DMA_TCD_TCD23_CSR_MAJORLINKCH_MASK (0x1F00U) 9941 #define DMA_TCD_TCD23_CSR_MAJORLINKCH_SHIFT (8U) 9942 #define DMA_TCD_TCD23_CSR_MAJORLINKCH_WIDTH (5U) 9943 #define DMA_TCD_TCD23_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD23_CSR_MAJORLINKCH_MASK) 9944 9945 #define DMA_TCD_TCD23_CSR_BWC_MASK (0xC000U) 9946 #define DMA_TCD_TCD23_CSR_BWC_SHIFT (14U) 9947 #define DMA_TCD_TCD23_CSR_BWC_WIDTH (2U) 9948 #define DMA_TCD_TCD23_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_CSR_BWC_SHIFT)) & DMA_TCD_TCD23_CSR_BWC_MASK) 9949 /*! @} */ 9950 9951 /*! @name TCD23_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 9952 /*! @{ */ 9953 9954 #define DMA_TCD_TCD23_BITER_ELINKNO_BITER_MASK (0x7FFFU) 9955 #define DMA_TCD_TCD23_BITER_ELINKNO_BITER_SHIFT (0U) 9956 #define DMA_TCD_TCD23_BITER_ELINKNO_BITER_WIDTH (15U) 9957 #define DMA_TCD_TCD23_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD23_BITER_ELINKNO_BITER_MASK) 9958 9959 #define DMA_TCD_TCD23_BITER_ELINKNO_ELINK_MASK (0x8000U) 9960 #define DMA_TCD_TCD23_BITER_ELINKNO_ELINK_SHIFT (15U) 9961 #define DMA_TCD_TCD23_BITER_ELINKNO_ELINK_WIDTH (1U) 9962 #define DMA_TCD_TCD23_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD23_BITER_ELINKNO_ELINK_MASK) 9963 /*! @} */ 9964 9965 /*! @name TCD23_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 9966 /*! @{ */ 9967 9968 #define DMA_TCD_TCD23_BITER_ELINKYES_BITER_MASK (0x1FFU) 9969 #define DMA_TCD_TCD23_BITER_ELINKYES_BITER_SHIFT (0U) 9970 #define DMA_TCD_TCD23_BITER_ELINKYES_BITER_WIDTH (9U) 9971 #define DMA_TCD_TCD23_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD23_BITER_ELINKYES_BITER_MASK) 9972 9973 #define DMA_TCD_TCD23_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 9974 #define DMA_TCD_TCD23_BITER_ELINKYES_LINKCH_SHIFT (9U) 9975 #define DMA_TCD_TCD23_BITER_ELINKYES_LINKCH_WIDTH (5U) 9976 #define DMA_TCD_TCD23_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD23_BITER_ELINKYES_LINKCH_MASK) 9977 9978 #define DMA_TCD_TCD23_BITER_ELINKYES_ELINK_MASK (0x8000U) 9979 #define DMA_TCD_TCD23_BITER_ELINKYES_ELINK_SHIFT (15U) 9980 #define DMA_TCD_TCD23_BITER_ELINKYES_ELINK_WIDTH (1U) 9981 #define DMA_TCD_TCD23_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD23_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD23_BITER_ELINKYES_ELINK_MASK) 9982 /*! @} */ 9983 9984 /*! @name CH24_CSR - Channel Control and Status */ 9985 /*! @{ */ 9986 9987 #define DMA_TCD_CH24_CSR_ERQ_MASK (0x1U) 9988 #define DMA_TCD_CH24_CSR_ERQ_SHIFT (0U) 9989 #define DMA_TCD_CH24_CSR_ERQ_WIDTH (1U) 9990 #define DMA_TCD_CH24_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_CSR_ERQ_SHIFT)) & DMA_TCD_CH24_CSR_ERQ_MASK) 9991 9992 #define DMA_TCD_CH24_CSR_EARQ_MASK (0x2U) 9993 #define DMA_TCD_CH24_CSR_EARQ_SHIFT (1U) 9994 #define DMA_TCD_CH24_CSR_EARQ_WIDTH (1U) 9995 #define DMA_TCD_CH24_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_CSR_EARQ_SHIFT)) & DMA_TCD_CH24_CSR_EARQ_MASK) 9996 9997 #define DMA_TCD_CH24_CSR_EEI_MASK (0x4U) 9998 #define DMA_TCD_CH24_CSR_EEI_SHIFT (2U) 9999 #define DMA_TCD_CH24_CSR_EEI_WIDTH (1U) 10000 #define DMA_TCD_CH24_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_CSR_EEI_SHIFT)) & DMA_TCD_CH24_CSR_EEI_MASK) 10001 10002 #define DMA_TCD_CH24_CSR_EBW_MASK (0x8U) 10003 #define DMA_TCD_CH24_CSR_EBW_SHIFT (3U) 10004 #define DMA_TCD_CH24_CSR_EBW_WIDTH (1U) 10005 #define DMA_TCD_CH24_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_CSR_EBW_SHIFT)) & DMA_TCD_CH24_CSR_EBW_MASK) 10006 10007 #define DMA_TCD_CH24_CSR_DONE_MASK (0x40000000U) 10008 #define DMA_TCD_CH24_CSR_DONE_SHIFT (30U) 10009 #define DMA_TCD_CH24_CSR_DONE_WIDTH (1U) 10010 #define DMA_TCD_CH24_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_CSR_DONE_SHIFT)) & DMA_TCD_CH24_CSR_DONE_MASK) 10011 10012 #define DMA_TCD_CH24_CSR_ACTIVE_MASK (0x80000000U) 10013 #define DMA_TCD_CH24_CSR_ACTIVE_SHIFT (31U) 10014 #define DMA_TCD_CH24_CSR_ACTIVE_WIDTH (1U) 10015 #define DMA_TCD_CH24_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH24_CSR_ACTIVE_MASK) 10016 /*! @} */ 10017 10018 /*! @name CH24_ES - Channel Error Status */ 10019 /*! @{ */ 10020 10021 #define DMA_TCD_CH24_ES_DBE_MASK (0x1U) 10022 #define DMA_TCD_CH24_ES_DBE_SHIFT (0U) 10023 #define DMA_TCD_CH24_ES_DBE_WIDTH (1U) 10024 #define DMA_TCD_CH24_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_ES_DBE_SHIFT)) & DMA_TCD_CH24_ES_DBE_MASK) 10025 10026 #define DMA_TCD_CH24_ES_SBE_MASK (0x2U) 10027 #define DMA_TCD_CH24_ES_SBE_SHIFT (1U) 10028 #define DMA_TCD_CH24_ES_SBE_WIDTH (1U) 10029 #define DMA_TCD_CH24_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_ES_SBE_SHIFT)) & DMA_TCD_CH24_ES_SBE_MASK) 10030 10031 #define DMA_TCD_CH24_ES_SGE_MASK (0x4U) 10032 #define DMA_TCD_CH24_ES_SGE_SHIFT (2U) 10033 #define DMA_TCD_CH24_ES_SGE_WIDTH (1U) 10034 #define DMA_TCD_CH24_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_ES_SGE_SHIFT)) & DMA_TCD_CH24_ES_SGE_MASK) 10035 10036 #define DMA_TCD_CH24_ES_NCE_MASK (0x8U) 10037 #define DMA_TCD_CH24_ES_NCE_SHIFT (3U) 10038 #define DMA_TCD_CH24_ES_NCE_WIDTH (1U) 10039 #define DMA_TCD_CH24_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_ES_NCE_SHIFT)) & DMA_TCD_CH24_ES_NCE_MASK) 10040 10041 #define DMA_TCD_CH24_ES_DOE_MASK (0x10U) 10042 #define DMA_TCD_CH24_ES_DOE_SHIFT (4U) 10043 #define DMA_TCD_CH24_ES_DOE_WIDTH (1U) 10044 #define DMA_TCD_CH24_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_ES_DOE_SHIFT)) & DMA_TCD_CH24_ES_DOE_MASK) 10045 10046 #define DMA_TCD_CH24_ES_DAE_MASK (0x20U) 10047 #define DMA_TCD_CH24_ES_DAE_SHIFT (5U) 10048 #define DMA_TCD_CH24_ES_DAE_WIDTH (1U) 10049 #define DMA_TCD_CH24_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_ES_DAE_SHIFT)) & DMA_TCD_CH24_ES_DAE_MASK) 10050 10051 #define DMA_TCD_CH24_ES_SOE_MASK (0x40U) 10052 #define DMA_TCD_CH24_ES_SOE_SHIFT (6U) 10053 #define DMA_TCD_CH24_ES_SOE_WIDTH (1U) 10054 #define DMA_TCD_CH24_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_ES_SOE_SHIFT)) & DMA_TCD_CH24_ES_SOE_MASK) 10055 10056 #define DMA_TCD_CH24_ES_SAE_MASK (0x80U) 10057 #define DMA_TCD_CH24_ES_SAE_SHIFT (7U) 10058 #define DMA_TCD_CH24_ES_SAE_WIDTH (1U) 10059 #define DMA_TCD_CH24_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_ES_SAE_SHIFT)) & DMA_TCD_CH24_ES_SAE_MASK) 10060 10061 #define DMA_TCD_CH24_ES_ERR_MASK (0x80000000U) 10062 #define DMA_TCD_CH24_ES_ERR_SHIFT (31U) 10063 #define DMA_TCD_CH24_ES_ERR_WIDTH (1U) 10064 #define DMA_TCD_CH24_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_ES_ERR_SHIFT)) & DMA_TCD_CH24_ES_ERR_MASK) 10065 /*! @} */ 10066 10067 /*! @name CH24_INT - Channel Interrupt Status */ 10068 /*! @{ */ 10069 10070 #define DMA_TCD_CH24_INT_INT_MASK (0x1U) 10071 #define DMA_TCD_CH24_INT_INT_SHIFT (0U) 10072 #define DMA_TCD_CH24_INT_INT_WIDTH (1U) 10073 #define DMA_TCD_CH24_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_INT_INT_SHIFT)) & DMA_TCD_CH24_INT_INT_MASK) 10074 /*! @} */ 10075 10076 /*! @name CH24_SBR - Channel System Bus */ 10077 /*! @{ */ 10078 10079 #define DMA_TCD_CH24_SBR_MID_MASK (0xFU) 10080 #define DMA_TCD_CH24_SBR_MID_SHIFT (0U) 10081 #define DMA_TCD_CH24_SBR_MID_WIDTH (4U) 10082 #define DMA_TCD_CH24_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_SBR_MID_SHIFT)) & DMA_TCD_CH24_SBR_MID_MASK) 10083 10084 #define DMA_TCD_CH24_SBR_PAL_MASK (0x8000U) 10085 #define DMA_TCD_CH24_SBR_PAL_SHIFT (15U) 10086 #define DMA_TCD_CH24_SBR_PAL_WIDTH (1U) 10087 #define DMA_TCD_CH24_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_SBR_PAL_SHIFT)) & DMA_TCD_CH24_SBR_PAL_MASK) 10088 10089 #define DMA_TCD_CH24_SBR_EMI_MASK (0x10000U) 10090 #define DMA_TCD_CH24_SBR_EMI_SHIFT (16U) 10091 #define DMA_TCD_CH24_SBR_EMI_WIDTH (1U) 10092 #define DMA_TCD_CH24_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_SBR_EMI_SHIFT)) & DMA_TCD_CH24_SBR_EMI_MASK) 10093 10094 #define DMA_TCD_CH24_SBR_ATTR_MASK (0xE0000U) 10095 #define DMA_TCD_CH24_SBR_ATTR_SHIFT (17U) 10096 #define DMA_TCD_CH24_SBR_ATTR_WIDTH (3U) 10097 #define DMA_TCD_CH24_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_SBR_ATTR_SHIFT)) & DMA_TCD_CH24_SBR_ATTR_MASK) 10098 /*! @} */ 10099 10100 /*! @name CH24_PRI - Channel Priority */ 10101 /*! @{ */ 10102 10103 #define DMA_TCD_CH24_PRI_APL_MASK (0x7U) 10104 #define DMA_TCD_CH24_PRI_APL_SHIFT (0U) 10105 #define DMA_TCD_CH24_PRI_APL_WIDTH (3U) 10106 #define DMA_TCD_CH24_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_PRI_APL_SHIFT)) & DMA_TCD_CH24_PRI_APL_MASK) 10107 10108 #define DMA_TCD_CH24_PRI_DPA_MASK (0x40000000U) 10109 #define DMA_TCD_CH24_PRI_DPA_SHIFT (30U) 10110 #define DMA_TCD_CH24_PRI_DPA_WIDTH (1U) 10111 #define DMA_TCD_CH24_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_PRI_DPA_SHIFT)) & DMA_TCD_CH24_PRI_DPA_MASK) 10112 10113 #define DMA_TCD_CH24_PRI_ECP_MASK (0x80000000U) 10114 #define DMA_TCD_CH24_PRI_ECP_SHIFT (31U) 10115 #define DMA_TCD_CH24_PRI_ECP_WIDTH (1U) 10116 #define DMA_TCD_CH24_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH24_PRI_ECP_SHIFT)) & DMA_TCD_CH24_PRI_ECP_MASK) 10117 /*! @} */ 10118 10119 /*! @name TCD24_SADDR - TCD Source Address */ 10120 /*! @{ */ 10121 10122 #define DMA_TCD_TCD24_SADDR_SADDR_MASK (0xFFFFFFFFU) 10123 #define DMA_TCD_TCD24_SADDR_SADDR_SHIFT (0U) 10124 #define DMA_TCD_TCD24_SADDR_SADDR_WIDTH (32U) 10125 #define DMA_TCD_TCD24_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD24_SADDR_SADDR_MASK) 10126 /*! @} */ 10127 10128 /*! @name TCD24_SOFF - TCD Signed Source Address Offset */ 10129 /*! @{ */ 10130 10131 #define DMA_TCD_TCD24_SOFF_SOFF_MASK (0xFFFFU) 10132 #define DMA_TCD_TCD24_SOFF_SOFF_SHIFT (0U) 10133 #define DMA_TCD_TCD24_SOFF_SOFF_WIDTH (16U) 10134 #define DMA_TCD_TCD24_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD24_SOFF_SOFF_MASK) 10135 /*! @} */ 10136 10137 /*! @name TCD24_ATTR - TCD Transfer Attributes */ 10138 /*! @{ */ 10139 10140 #define DMA_TCD_TCD24_ATTR_DSIZE_MASK (0x7U) 10141 #define DMA_TCD_TCD24_ATTR_DSIZE_SHIFT (0U) 10142 #define DMA_TCD_TCD24_ATTR_DSIZE_WIDTH (3U) 10143 #define DMA_TCD_TCD24_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD24_ATTR_DSIZE_MASK) 10144 10145 #define DMA_TCD_TCD24_ATTR_DMOD_MASK (0xF8U) 10146 #define DMA_TCD_TCD24_ATTR_DMOD_SHIFT (3U) 10147 #define DMA_TCD_TCD24_ATTR_DMOD_WIDTH (5U) 10148 #define DMA_TCD_TCD24_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD24_ATTR_DMOD_MASK) 10149 10150 #define DMA_TCD_TCD24_ATTR_SSIZE_MASK (0x700U) 10151 #define DMA_TCD_TCD24_ATTR_SSIZE_SHIFT (8U) 10152 #define DMA_TCD_TCD24_ATTR_SSIZE_WIDTH (3U) 10153 #define DMA_TCD_TCD24_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD24_ATTR_SSIZE_MASK) 10154 10155 #define DMA_TCD_TCD24_ATTR_SMOD_MASK (0xF800U) 10156 #define DMA_TCD_TCD24_ATTR_SMOD_SHIFT (11U) 10157 #define DMA_TCD_TCD24_ATTR_SMOD_WIDTH (5U) 10158 #define DMA_TCD_TCD24_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD24_ATTR_SMOD_MASK) 10159 /*! @} */ 10160 10161 /*! @name TCD24_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 10162 /*! @{ */ 10163 10164 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 10165 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 10166 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 10167 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD24_NBYTES_MLOFFNO_NBYTES_MASK) 10168 10169 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 10170 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 10171 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 10172 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD24_NBYTES_MLOFFNO_DMLOE_MASK) 10173 10174 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 10175 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 10176 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 10177 #define DMA_TCD_TCD24_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD24_NBYTES_MLOFFNO_SMLOE_MASK) 10178 /*! @} */ 10179 10180 /*! @name TCD24_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 10181 /*! @{ */ 10182 10183 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 10184 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 10185 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 10186 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD24_NBYTES_MLOFFYES_NBYTES_MASK) 10187 10188 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 10189 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 10190 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 10191 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD24_NBYTES_MLOFFYES_MLOFF_MASK) 10192 10193 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 10194 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 10195 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 10196 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD24_NBYTES_MLOFFYES_DMLOE_MASK) 10197 10198 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 10199 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 10200 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 10201 #define DMA_TCD_TCD24_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD24_NBYTES_MLOFFYES_SMLOE_MASK) 10202 /*! @} */ 10203 10204 /*! @name TCD24_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 10205 /*! @{ */ 10206 10207 #define DMA_TCD_TCD24_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 10208 #define DMA_TCD_TCD24_SLAST_SDA_SLAST_SDA_SHIFT (0U) 10209 #define DMA_TCD_TCD24_SLAST_SDA_SLAST_SDA_WIDTH (32U) 10210 #define DMA_TCD_TCD24_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD24_SLAST_SDA_SLAST_SDA_MASK) 10211 /*! @} */ 10212 10213 /*! @name TCD24_DADDR - TCD Destination Address */ 10214 /*! @{ */ 10215 10216 #define DMA_TCD_TCD24_DADDR_DADDR_MASK (0xFFFFFFFFU) 10217 #define DMA_TCD_TCD24_DADDR_DADDR_SHIFT (0U) 10218 #define DMA_TCD_TCD24_DADDR_DADDR_WIDTH (32U) 10219 #define DMA_TCD_TCD24_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD24_DADDR_DADDR_MASK) 10220 /*! @} */ 10221 10222 /*! @name TCD24_DOFF - TCD Signed Destination Address Offset */ 10223 /*! @{ */ 10224 10225 #define DMA_TCD_TCD24_DOFF_DOFF_MASK (0xFFFFU) 10226 #define DMA_TCD_TCD24_DOFF_DOFF_SHIFT (0U) 10227 #define DMA_TCD_TCD24_DOFF_DOFF_WIDTH (16U) 10228 #define DMA_TCD_TCD24_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD24_DOFF_DOFF_MASK) 10229 /*! @} */ 10230 10231 /*! @name TCD24_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 10232 /*! @{ */ 10233 10234 #define DMA_TCD_TCD24_CITER_ELINKNO_CITER_MASK (0x7FFFU) 10235 #define DMA_TCD_TCD24_CITER_ELINKNO_CITER_SHIFT (0U) 10236 #define DMA_TCD_TCD24_CITER_ELINKNO_CITER_WIDTH (15U) 10237 #define DMA_TCD_TCD24_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD24_CITER_ELINKNO_CITER_MASK) 10238 10239 #define DMA_TCD_TCD24_CITER_ELINKNO_ELINK_MASK (0x8000U) 10240 #define DMA_TCD_TCD24_CITER_ELINKNO_ELINK_SHIFT (15U) 10241 #define DMA_TCD_TCD24_CITER_ELINKNO_ELINK_WIDTH (1U) 10242 #define DMA_TCD_TCD24_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD24_CITER_ELINKNO_ELINK_MASK) 10243 /*! @} */ 10244 10245 /*! @name TCD24_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 10246 /*! @{ */ 10247 10248 #define DMA_TCD_TCD24_CITER_ELINKYES_CITER_MASK (0x1FFU) 10249 #define DMA_TCD_TCD24_CITER_ELINKYES_CITER_SHIFT (0U) 10250 #define DMA_TCD_TCD24_CITER_ELINKYES_CITER_WIDTH (9U) 10251 #define DMA_TCD_TCD24_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD24_CITER_ELINKYES_CITER_MASK) 10252 10253 #define DMA_TCD_TCD24_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 10254 #define DMA_TCD_TCD24_CITER_ELINKYES_LINKCH_SHIFT (9U) 10255 #define DMA_TCD_TCD24_CITER_ELINKYES_LINKCH_WIDTH (5U) 10256 #define DMA_TCD_TCD24_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD24_CITER_ELINKYES_LINKCH_MASK) 10257 10258 #define DMA_TCD_TCD24_CITER_ELINKYES_ELINK_MASK (0x8000U) 10259 #define DMA_TCD_TCD24_CITER_ELINKYES_ELINK_SHIFT (15U) 10260 #define DMA_TCD_TCD24_CITER_ELINKYES_ELINK_WIDTH (1U) 10261 #define DMA_TCD_TCD24_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD24_CITER_ELINKYES_ELINK_MASK) 10262 /*! @} */ 10263 10264 /*! @name TCD24_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 10265 /*! @{ */ 10266 10267 #define DMA_TCD_TCD24_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 10268 #define DMA_TCD_TCD24_DLAST_SGA_DLAST_SGA_SHIFT (0U) 10269 #define DMA_TCD_TCD24_DLAST_SGA_DLAST_SGA_WIDTH (32U) 10270 #define DMA_TCD_TCD24_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD24_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD24_DLAST_SGA_DLAST_SGA_MASK) 10271 /*! @} */ 10272 10273 /*! @name TCD24_CSR - TCD Control and Status */ 10274 /*! @{ */ 10275 10276 #define DMA_TCD_TCD24_CSR_START_MASK (0x1U) 10277 #define DMA_TCD_TCD24_CSR_START_SHIFT (0U) 10278 #define DMA_TCD_TCD24_CSR_START_WIDTH (1U) 10279 #define DMA_TCD_TCD24_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CSR_START_SHIFT)) & DMA_TCD_TCD24_CSR_START_MASK) 10280 10281 #define DMA_TCD_TCD24_CSR_INTMAJOR_MASK (0x2U) 10282 #define DMA_TCD_TCD24_CSR_INTMAJOR_SHIFT (1U) 10283 #define DMA_TCD_TCD24_CSR_INTMAJOR_WIDTH (1U) 10284 #define DMA_TCD_TCD24_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD24_CSR_INTMAJOR_MASK) 10285 10286 #define DMA_TCD_TCD24_CSR_INTHALF_MASK (0x4U) 10287 #define DMA_TCD_TCD24_CSR_INTHALF_SHIFT (2U) 10288 #define DMA_TCD_TCD24_CSR_INTHALF_WIDTH (1U) 10289 #define DMA_TCD_TCD24_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD24_CSR_INTHALF_MASK) 10290 10291 #define DMA_TCD_TCD24_CSR_DREQ_MASK (0x8U) 10292 #define DMA_TCD_TCD24_CSR_DREQ_SHIFT (3U) 10293 #define DMA_TCD_TCD24_CSR_DREQ_WIDTH (1U) 10294 #define DMA_TCD_TCD24_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CSR_DREQ_SHIFT)) & DMA_TCD_TCD24_CSR_DREQ_MASK) 10295 10296 #define DMA_TCD_TCD24_CSR_ESG_MASK (0x10U) 10297 #define DMA_TCD_TCD24_CSR_ESG_SHIFT (4U) 10298 #define DMA_TCD_TCD24_CSR_ESG_WIDTH (1U) 10299 #define DMA_TCD_TCD24_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CSR_ESG_SHIFT)) & DMA_TCD_TCD24_CSR_ESG_MASK) 10300 10301 #define DMA_TCD_TCD24_CSR_MAJORELINK_MASK (0x20U) 10302 #define DMA_TCD_TCD24_CSR_MAJORELINK_SHIFT (5U) 10303 #define DMA_TCD_TCD24_CSR_MAJORELINK_WIDTH (1U) 10304 #define DMA_TCD_TCD24_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD24_CSR_MAJORELINK_MASK) 10305 10306 #define DMA_TCD_TCD24_CSR_EEOP_MASK (0x40U) 10307 #define DMA_TCD_TCD24_CSR_EEOP_SHIFT (6U) 10308 #define DMA_TCD_TCD24_CSR_EEOP_WIDTH (1U) 10309 #define DMA_TCD_TCD24_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CSR_EEOP_SHIFT)) & DMA_TCD_TCD24_CSR_EEOP_MASK) 10310 10311 #define DMA_TCD_TCD24_CSR_ESDA_MASK (0x80U) 10312 #define DMA_TCD_TCD24_CSR_ESDA_SHIFT (7U) 10313 #define DMA_TCD_TCD24_CSR_ESDA_WIDTH (1U) 10314 #define DMA_TCD_TCD24_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CSR_ESDA_SHIFT)) & DMA_TCD_TCD24_CSR_ESDA_MASK) 10315 10316 #define DMA_TCD_TCD24_CSR_MAJORLINKCH_MASK (0x1F00U) 10317 #define DMA_TCD_TCD24_CSR_MAJORLINKCH_SHIFT (8U) 10318 #define DMA_TCD_TCD24_CSR_MAJORLINKCH_WIDTH (5U) 10319 #define DMA_TCD_TCD24_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD24_CSR_MAJORLINKCH_MASK) 10320 10321 #define DMA_TCD_TCD24_CSR_BWC_MASK (0xC000U) 10322 #define DMA_TCD_TCD24_CSR_BWC_SHIFT (14U) 10323 #define DMA_TCD_TCD24_CSR_BWC_WIDTH (2U) 10324 #define DMA_TCD_TCD24_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_CSR_BWC_SHIFT)) & DMA_TCD_TCD24_CSR_BWC_MASK) 10325 /*! @} */ 10326 10327 /*! @name TCD24_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 10328 /*! @{ */ 10329 10330 #define DMA_TCD_TCD24_BITER_ELINKNO_BITER_MASK (0x7FFFU) 10331 #define DMA_TCD_TCD24_BITER_ELINKNO_BITER_SHIFT (0U) 10332 #define DMA_TCD_TCD24_BITER_ELINKNO_BITER_WIDTH (15U) 10333 #define DMA_TCD_TCD24_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD24_BITER_ELINKNO_BITER_MASK) 10334 10335 #define DMA_TCD_TCD24_BITER_ELINKNO_ELINK_MASK (0x8000U) 10336 #define DMA_TCD_TCD24_BITER_ELINKNO_ELINK_SHIFT (15U) 10337 #define DMA_TCD_TCD24_BITER_ELINKNO_ELINK_WIDTH (1U) 10338 #define DMA_TCD_TCD24_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD24_BITER_ELINKNO_ELINK_MASK) 10339 /*! @} */ 10340 10341 /*! @name TCD24_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 10342 /*! @{ */ 10343 10344 #define DMA_TCD_TCD24_BITER_ELINKYES_BITER_MASK (0x1FFU) 10345 #define DMA_TCD_TCD24_BITER_ELINKYES_BITER_SHIFT (0U) 10346 #define DMA_TCD_TCD24_BITER_ELINKYES_BITER_WIDTH (9U) 10347 #define DMA_TCD_TCD24_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD24_BITER_ELINKYES_BITER_MASK) 10348 10349 #define DMA_TCD_TCD24_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 10350 #define DMA_TCD_TCD24_BITER_ELINKYES_LINKCH_SHIFT (9U) 10351 #define DMA_TCD_TCD24_BITER_ELINKYES_LINKCH_WIDTH (5U) 10352 #define DMA_TCD_TCD24_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD24_BITER_ELINKYES_LINKCH_MASK) 10353 10354 #define DMA_TCD_TCD24_BITER_ELINKYES_ELINK_MASK (0x8000U) 10355 #define DMA_TCD_TCD24_BITER_ELINKYES_ELINK_SHIFT (15U) 10356 #define DMA_TCD_TCD24_BITER_ELINKYES_ELINK_WIDTH (1U) 10357 #define DMA_TCD_TCD24_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD24_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD24_BITER_ELINKYES_ELINK_MASK) 10358 /*! @} */ 10359 10360 /*! @name CH25_CSR - Channel Control and Status */ 10361 /*! @{ */ 10362 10363 #define DMA_TCD_CH25_CSR_ERQ_MASK (0x1U) 10364 #define DMA_TCD_CH25_CSR_ERQ_SHIFT (0U) 10365 #define DMA_TCD_CH25_CSR_ERQ_WIDTH (1U) 10366 #define DMA_TCD_CH25_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_CSR_ERQ_SHIFT)) & DMA_TCD_CH25_CSR_ERQ_MASK) 10367 10368 #define DMA_TCD_CH25_CSR_EARQ_MASK (0x2U) 10369 #define DMA_TCD_CH25_CSR_EARQ_SHIFT (1U) 10370 #define DMA_TCD_CH25_CSR_EARQ_WIDTH (1U) 10371 #define DMA_TCD_CH25_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_CSR_EARQ_SHIFT)) & DMA_TCD_CH25_CSR_EARQ_MASK) 10372 10373 #define DMA_TCD_CH25_CSR_EEI_MASK (0x4U) 10374 #define DMA_TCD_CH25_CSR_EEI_SHIFT (2U) 10375 #define DMA_TCD_CH25_CSR_EEI_WIDTH (1U) 10376 #define DMA_TCD_CH25_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_CSR_EEI_SHIFT)) & DMA_TCD_CH25_CSR_EEI_MASK) 10377 10378 #define DMA_TCD_CH25_CSR_EBW_MASK (0x8U) 10379 #define DMA_TCD_CH25_CSR_EBW_SHIFT (3U) 10380 #define DMA_TCD_CH25_CSR_EBW_WIDTH (1U) 10381 #define DMA_TCD_CH25_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_CSR_EBW_SHIFT)) & DMA_TCD_CH25_CSR_EBW_MASK) 10382 10383 #define DMA_TCD_CH25_CSR_DONE_MASK (0x40000000U) 10384 #define DMA_TCD_CH25_CSR_DONE_SHIFT (30U) 10385 #define DMA_TCD_CH25_CSR_DONE_WIDTH (1U) 10386 #define DMA_TCD_CH25_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_CSR_DONE_SHIFT)) & DMA_TCD_CH25_CSR_DONE_MASK) 10387 10388 #define DMA_TCD_CH25_CSR_ACTIVE_MASK (0x80000000U) 10389 #define DMA_TCD_CH25_CSR_ACTIVE_SHIFT (31U) 10390 #define DMA_TCD_CH25_CSR_ACTIVE_WIDTH (1U) 10391 #define DMA_TCD_CH25_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH25_CSR_ACTIVE_MASK) 10392 /*! @} */ 10393 10394 /*! @name CH25_ES - Channel Error Status */ 10395 /*! @{ */ 10396 10397 #define DMA_TCD_CH25_ES_DBE_MASK (0x1U) 10398 #define DMA_TCD_CH25_ES_DBE_SHIFT (0U) 10399 #define DMA_TCD_CH25_ES_DBE_WIDTH (1U) 10400 #define DMA_TCD_CH25_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_ES_DBE_SHIFT)) & DMA_TCD_CH25_ES_DBE_MASK) 10401 10402 #define DMA_TCD_CH25_ES_SBE_MASK (0x2U) 10403 #define DMA_TCD_CH25_ES_SBE_SHIFT (1U) 10404 #define DMA_TCD_CH25_ES_SBE_WIDTH (1U) 10405 #define DMA_TCD_CH25_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_ES_SBE_SHIFT)) & DMA_TCD_CH25_ES_SBE_MASK) 10406 10407 #define DMA_TCD_CH25_ES_SGE_MASK (0x4U) 10408 #define DMA_TCD_CH25_ES_SGE_SHIFT (2U) 10409 #define DMA_TCD_CH25_ES_SGE_WIDTH (1U) 10410 #define DMA_TCD_CH25_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_ES_SGE_SHIFT)) & DMA_TCD_CH25_ES_SGE_MASK) 10411 10412 #define DMA_TCD_CH25_ES_NCE_MASK (0x8U) 10413 #define DMA_TCD_CH25_ES_NCE_SHIFT (3U) 10414 #define DMA_TCD_CH25_ES_NCE_WIDTH (1U) 10415 #define DMA_TCD_CH25_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_ES_NCE_SHIFT)) & DMA_TCD_CH25_ES_NCE_MASK) 10416 10417 #define DMA_TCD_CH25_ES_DOE_MASK (0x10U) 10418 #define DMA_TCD_CH25_ES_DOE_SHIFT (4U) 10419 #define DMA_TCD_CH25_ES_DOE_WIDTH (1U) 10420 #define DMA_TCD_CH25_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_ES_DOE_SHIFT)) & DMA_TCD_CH25_ES_DOE_MASK) 10421 10422 #define DMA_TCD_CH25_ES_DAE_MASK (0x20U) 10423 #define DMA_TCD_CH25_ES_DAE_SHIFT (5U) 10424 #define DMA_TCD_CH25_ES_DAE_WIDTH (1U) 10425 #define DMA_TCD_CH25_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_ES_DAE_SHIFT)) & DMA_TCD_CH25_ES_DAE_MASK) 10426 10427 #define DMA_TCD_CH25_ES_SOE_MASK (0x40U) 10428 #define DMA_TCD_CH25_ES_SOE_SHIFT (6U) 10429 #define DMA_TCD_CH25_ES_SOE_WIDTH (1U) 10430 #define DMA_TCD_CH25_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_ES_SOE_SHIFT)) & DMA_TCD_CH25_ES_SOE_MASK) 10431 10432 #define DMA_TCD_CH25_ES_SAE_MASK (0x80U) 10433 #define DMA_TCD_CH25_ES_SAE_SHIFT (7U) 10434 #define DMA_TCD_CH25_ES_SAE_WIDTH (1U) 10435 #define DMA_TCD_CH25_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_ES_SAE_SHIFT)) & DMA_TCD_CH25_ES_SAE_MASK) 10436 10437 #define DMA_TCD_CH25_ES_ERR_MASK (0x80000000U) 10438 #define DMA_TCD_CH25_ES_ERR_SHIFT (31U) 10439 #define DMA_TCD_CH25_ES_ERR_WIDTH (1U) 10440 #define DMA_TCD_CH25_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_ES_ERR_SHIFT)) & DMA_TCD_CH25_ES_ERR_MASK) 10441 /*! @} */ 10442 10443 /*! @name CH25_INT - Channel Interrupt Status */ 10444 /*! @{ */ 10445 10446 #define DMA_TCD_CH25_INT_INT_MASK (0x1U) 10447 #define DMA_TCD_CH25_INT_INT_SHIFT (0U) 10448 #define DMA_TCD_CH25_INT_INT_WIDTH (1U) 10449 #define DMA_TCD_CH25_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_INT_INT_SHIFT)) & DMA_TCD_CH25_INT_INT_MASK) 10450 /*! @} */ 10451 10452 /*! @name CH25_SBR - Channel System Bus */ 10453 /*! @{ */ 10454 10455 #define DMA_TCD_CH25_SBR_MID_MASK (0xFU) 10456 #define DMA_TCD_CH25_SBR_MID_SHIFT (0U) 10457 #define DMA_TCD_CH25_SBR_MID_WIDTH (4U) 10458 #define DMA_TCD_CH25_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_SBR_MID_SHIFT)) & DMA_TCD_CH25_SBR_MID_MASK) 10459 10460 #define DMA_TCD_CH25_SBR_PAL_MASK (0x8000U) 10461 #define DMA_TCD_CH25_SBR_PAL_SHIFT (15U) 10462 #define DMA_TCD_CH25_SBR_PAL_WIDTH (1U) 10463 #define DMA_TCD_CH25_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_SBR_PAL_SHIFT)) & DMA_TCD_CH25_SBR_PAL_MASK) 10464 10465 #define DMA_TCD_CH25_SBR_EMI_MASK (0x10000U) 10466 #define DMA_TCD_CH25_SBR_EMI_SHIFT (16U) 10467 #define DMA_TCD_CH25_SBR_EMI_WIDTH (1U) 10468 #define DMA_TCD_CH25_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_SBR_EMI_SHIFT)) & DMA_TCD_CH25_SBR_EMI_MASK) 10469 10470 #define DMA_TCD_CH25_SBR_ATTR_MASK (0xE0000U) 10471 #define DMA_TCD_CH25_SBR_ATTR_SHIFT (17U) 10472 #define DMA_TCD_CH25_SBR_ATTR_WIDTH (3U) 10473 #define DMA_TCD_CH25_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_SBR_ATTR_SHIFT)) & DMA_TCD_CH25_SBR_ATTR_MASK) 10474 /*! @} */ 10475 10476 /*! @name CH25_PRI - Channel Priority */ 10477 /*! @{ */ 10478 10479 #define DMA_TCD_CH25_PRI_APL_MASK (0x7U) 10480 #define DMA_TCD_CH25_PRI_APL_SHIFT (0U) 10481 #define DMA_TCD_CH25_PRI_APL_WIDTH (3U) 10482 #define DMA_TCD_CH25_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_PRI_APL_SHIFT)) & DMA_TCD_CH25_PRI_APL_MASK) 10483 10484 #define DMA_TCD_CH25_PRI_DPA_MASK (0x40000000U) 10485 #define DMA_TCD_CH25_PRI_DPA_SHIFT (30U) 10486 #define DMA_TCD_CH25_PRI_DPA_WIDTH (1U) 10487 #define DMA_TCD_CH25_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_PRI_DPA_SHIFT)) & DMA_TCD_CH25_PRI_DPA_MASK) 10488 10489 #define DMA_TCD_CH25_PRI_ECP_MASK (0x80000000U) 10490 #define DMA_TCD_CH25_PRI_ECP_SHIFT (31U) 10491 #define DMA_TCD_CH25_PRI_ECP_WIDTH (1U) 10492 #define DMA_TCD_CH25_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH25_PRI_ECP_SHIFT)) & DMA_TCD_CH25_PRI_ECP_MASK) 10493 /*! @} */ 10494 10495 /*! @name TCD25_SADDR - TCD Source Address */ 10496 /*! @{ */ 10497 10498 #define DMA_TCD_TCD25_SADDR_SADDR_MASK (0xFFFFFFFFU) 10499 #define DMA_TCD_TCD25_SADDR_SADDR_SHIFT (0U) 10500 #define DMA_TCD_TCD25_SADDR_SADDR_WIDTH (32U) 10501 #define DMA_TCD_TCD25_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD25_SADDR_SADDR_MASK) 10502 /*! @} */ 10503 10504 /*! @name TCD25_SOFF - TCD Signed Source Address Offset */ 10505 /*! @{ */ 10506 10507 #define DMA_TCD_TCD25_SOFF_SOFF_MASK (0xFFFFU) 10508 #define DMA_TCD_TCD25_SOFF_SOFF_SHIFT (0U) 10509 #define DMA_TCD_TCD25_SOFF_SOFF_WIDTH (16U) 10510 #define DMA_TCD_TCD25_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD25_SOFF_SOFF_MASK) 10511 /*! @} */ 10512 10513 /*! @name TCD25_ATTR - TCD Transfer Attributes */ 10514 /*! @{ */ 10515 10516 #define DMA_TCD_TCD25_ATTR_DSIZE_MASK (0x7U) 10517 #define DMA_TCD_TCD25_ATTR_DSIZE_SHIFT (0U) 10518 #define DMA_TCD_TCD25_ATTR_DSIZE_WIDTH (3U) 10519 #define DMA_TCD_TCD25_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD25_ATTR_DSIZE_MASK) 10520 10521 #define DMA_TCD_TCD25_ATTR_DMOD_MASK (0xF8U) 10522 #define DMA_TCD_TCD25_ATTR_DMOD_SHIFT (3U) 10523 #define DMA_TCD_TCD25_ATTR_DMOD_WIDTH (5U) 10524 #define DMA_TCD_TCD25_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD25_ATTR_DMOD_MASK) 10525 10526 #define DMA_TCD_TCD25_ATTR_SSIZE_MASK (0x700U) 10527 #define DMA_TCD_TCD25_ATTR_SSIZE_SHIFT (8U) 10528 #define DMA_TCD_TCD25_ATTR_SSIZE_WIDTH (3U) 10529 #define DMA_TCD_TCD25_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD25_ATTR_SSIZE_MASK) 10530 10531 #define DMA_TCD_TCD25_ATTR_SMOD_MASK (0xF800U) 10532 #define DMA_TCD_TCD25_ATTR_SMOD_SHIFT (11U) 10533 #define DMA_TCD_TCD25_ATTR_SMOD_WIDTH (5U) 10534 #define DMA_TCD_TCD25_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD25_ATTR_SMOD_MASK) 10535 /*! @} */ 10536 10537 /*! @name TCD25_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 10538 /*! @{ */ 10539 10540 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 10541 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 10542 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 10543 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD25_NBYTES_MLOFFNO_NBYTES_MASK) 10544 10545 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 10546 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 10547 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 10548 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD25_NBYTES_MLOFFNO_DMLOE_MASK) 10549 10550 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 10551 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 10552 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 10553 #define DMA_TCD_TCD25_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD25_NBYTES_MLOFFNO_SMLOE_MASK) 10554 /*! @} */ 10555 10556 /*! @name TCD25_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 10557 /*! @{ */ 10558 10559 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 10560 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 10561 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 10562 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD25_NBYTES_MLOFFYES_NBYTES_MASK) 10563 10564 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 10565 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 10566 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 10567 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD25_NBYTES_MLOFFYES_MLOFF_MASK) 10568 10569 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 10570 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 10571 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 10572 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD25_NBYTES_MLOFFYES_DMLOE_MASK) 10573 10574 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 10575 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 10576 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 10577 #define DMA_TCD_TCD25_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD25_NBYTES_MLOFFYES_SMLOE_MASK) 10578 /*! @} */ 10579 10580 /*! @name TCD25_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 10581 /*! @{ */ 10582 10583 #define DMA_TCD_TCD25_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 10584 #define DMA_TCD_TCD25_SLAST_SDA_SLAST_SDA_SHIFT (0U) 10585 #define DMA_TCD_TCD25_SLAST_SDA_SLAST_SDA_WIDTH (32U) 10586 #define DMA_TCD_TCD25_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD25_SLAST_SDA_SLAST_SDA_MASK) 10587 /*! @} */ 10588 10589 /*! @name TCD25_DADDR - TCD Destination Address */ 10590 /*! @{ */ 10591 10592 #define DMA_TCD_TCD25_DADDR_DADDR_MASK (0xFFFFFFFFU) 10593 #define DMA_TCD_TCD25_DADDR_DADDR_SHIFT (0U) 10594 #define DMA_TCD_TCD25_DADDR_DADDR_WIDTH (32U) 10595 #define DMA_TCD_TCD25_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD25_DADDR_DADDR_MASK) 10596 /*! @} */ 10597 10598 /*! @name TCD25_DOFF - TCD Signed Destination Address Offset */ 10599 /*! @{ */ 10600 10601 #define DMA_TCD_TCD25_DOFF_DOFF_MASK (0xFFFFU) 10602 #define DMA_TCD_TCD25_DOFF_DOFF_SHIFT (0U) 10603 #define DMA_TCD_TCD25_DOFF_DOFF_WIDTH (16U) 10604 #define DMA_TCD_TCD25_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD25_DOFF_DOFF_MASK) 10605 /*! @} */ 10606 10607 /*! @name TCD25_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 10608 /*! @{ */ 10609 10610 #define DMA_TCD_TCD25_CITER_ELINKNO_CITER_MASK (0x7FFFU) 10611 #define DMA_TCD_TCD25_CITER_ELINKNO_CITER_SHIFT (0U) 10612 #define DMA_TCD_TCD25_CITER_ELINKNO_CITER_WIDTH (15U) 10613 #define DMA_TCD_TCD25_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD25_CITER_ELINKNO_CITER_MASK) 10614 10615 #define DMA_TCD_TCD25_CITER_ELINKNO_ELINK_MASK (0x8000U) 10616 #define DMA_TCD_TCD25_CITER_ELINKNO_ELINK_SHIFT (15U) 10617 #define DMA_TCD_TCD25_CITER_ELINKNO_ELINK_WIDTH (1U) 10618 #define DMA_TCD_TCD25_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD25_CITER_ELINKNO_ELINK_MASK) 10619 /*! @} */ 10620 10621 /*! @name TCD25_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 10622 /*! @{ */ 10623 10624 #define DMA_TCD_TCD25_CITER_ELINKYES_CITER_MASK (0x1FFU) 10625 #define DMA_TCD_TCD25_CITER_ELINKYES_CITER_SHIFT (0U) 10626 #define DMA_TCD_TCD25_CITER_ELINKYES_CITER_WIDTH (9U) 10627 #define DMA_TCD_TCD25_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD25_CITER_ELINKYES_CITER_MASK) 10628 10629 #define DMA_TCD_TCD25_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 10630 #define DMA_TCD_TCD25_CITER_ELINKYES_LINKCH_SHIFT (9U) 10631 #define DMA_TCD_TCD25_CITER_ELINKYES_LINKCH_WIDTH (5U) 10632 #define DMA_TCD_TCD25_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD25_CITER_ELINKYES_LINKCH_MASK) 10633 10634 #define DMA_TCD_TCD25_CITER_ELINKYES_ELINK_MASK (0x8000U) 10635 #define DMA_TCD_TCD25_CITER_ELINKYES_ELINK_SHIFT (15U) 10636 #define DMA_TCD_TCD25_CITER_ELINKYES_ELINK_WIDTH (1U) 10637 #define DMA_TCD_TCD25_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD25_CITER_ELINKYES_ELINK_MASK) 10638 /*! @} */ 10639 10640 /*! @name TCD25_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 10641 /*! @{ */ 10642 10643 #define DMA_TCD_TCD25_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 10644 #define DMA_TCD_TCD25_DLAST_SGA_DLAST_SGA_SHIFT (0U) 10645 #define DMA_TCD_TCD25_DLAST_SGA_DLAST_SGA_WIDTH (32U) 10646 #define DMA_TCD_TCD25_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD25_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD25_DLAST_SGA_DLAST_SGA_MASK) 10647 /*! @} */ 10648 10649 /*! @name TCD25_CSR - TCD Control and Status */ 10650 /*! @{ */ 10651 10652 #define DMA_TCD_TCD25_CSR_START_MASK (0x1U) 10653 #define DMA_TCD_TCD25_CSR_START_SHIFT (0U) 10654 #define DMA_TCD_TCD25_CSR_START_WIDTH (1U) 10655 #define DMA_TCD_TCD25_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CSR_START_SHIFT)) & DMA_TCD_TCD25_CSR_START_MASK) 10656 10657 #define DMA_TCD_TCD25_CSR_INTMAJOR_MASK (0x2U) 10658 #define DMA_TCD_TCD25_CSR_INTMAJOR_SHIFT (1U) 10659 #define DMA_TCD_TCD25_CSR_INTMAJOR_WIDTH (1U) 10660 #define DMA_TCD_TCD25_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD25_CSR_INTMAJOR_MASK) 10661 10662 #define DMA_TCD_TCD25_CSR_INTHALF_MASK (0x4U) 10663 #define DMA_TCD_TCD25_CSR_INTHALF_SHIFT (2U) 10664 #define DMA_TCD_TCD25_CSR_INTHALF_WIDTH (1U) 10665 #define DMA_TCD_TCD25_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD25_CSR_INTHALF_MASK) 10666 10667 #define DMA_TCD_TCD25_CSR_DREQ_MASK (0x8U) 10668 #define DMA_TCD_TCD25_CSR_DREQ_SHIFT (3U) 10669 #define DMA_TCD_TCD25_CSR_DREQ_WIDTH (1U) 10670 #define DMA_TCD_TCD25_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CSR_DREQ_SHIFT)) & DMA_TCD_TCD25_CSR_DREQ_MASK) 10671 10672 #define DMA_TCD_TCD25_CSR_ESG_MASK (0x10U) 10673 #define DMA_TCD_TCD25_CSR_ESG_SHIFT (4U) 10674 #define DMA_TCD_TCD25_CSR_ESG_WIDTH (1U) 10675 #define DMA_TCD_TCD25_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CSR_ESG_SHIFT)) & DMA_TCD_TCD25_CSR_ESG_MASK) 10676 10677 #define DMA_TCD_TCD25_CSR_MAJORELINK_MASK (0x20U) 10678 #define DMA_TCD_TCD25_CSR_MAJORELINK_SHIFT (5U) 10679 #define DMA_TCD_TCD25_CSR_MAJORELINK_WIDTH (1U) 10680 #define DMA_TCD_TCD25_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD25_CSR_MAJORELINK_MASK) 10681 10682 #define DMA_TCD_TCD25_CSR_EEOP_MASK (0x40U) 10683 #define DMA_TCD_TCD25_CSR_EEOP_SHIFT (6U) 10684 #define DMA_TCD_TCD25_CSR_EEOP_WIDTH (1U) 10685 #define DMA_TCD_TCD25_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CSR_EEOP_SHIFT)) & DMA_TCD_TCD25_CSR_EEOP_MASK) 10686 10687 #define DMA_TCD_TCD25_CSR_ESDA_MASK (0x80U) 10688 #define DMA_TCD_TCD25_CSR_ESDA_SHIFT (7U) 10689 #define DMA_TCD_TCD25_CSR_ESDA_WIDTH (1U) 10690 #define DMA_TCD_TCD25_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CSR_ESDA_SHIFT)) & DMA_TCD_TCD25_CSR_ESDA_MASK) 10691 10692 #define DMA_TCD_TCD25_CSR_MAJORLINKCH_MASK (0x1F00U) 10693 #define DMA_TCD_TCD25_CSR_MAJORLINKCH_SHIFT (8U) 10694 #define DMA_TCD_TCD25_CSR_MAJORLINKCH_WIDTH (5U) 10695 #define DMA_TCD_TCD25_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD25_CSR_MAJORLINKCH_MASK) 10696 10697 #define DMA_TCD_TCD25_CSR_BWC_MASK (0xC000U) 10698 #define DMA_TCD_TCD25_CSR_BWC_SHIFT (14U) 10699 #define DMA_TCD_TCD25_CSR_BWC_WIDTH (2U) 10700 #define DMA_TCD_TCD25_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_CSR_BWC_SHIFT)) & DMA_TCD_TCD25_CSR_BWC_MASK) 10701 /*! @} */ 10702 10703 /*! @name TCD25_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 10704 /*! @{ */ 10705 10706 #define DMA_TCD_TCD25_BITER_ELINKNO_BITER_MASK (0x7FFFU) 10707 #define DMA_TCD_TCD25_BITER_ELINKNO_BITER_SHIFT (0U) 10708 #define DMA_TCD_TCD25_BITER_ELINKNO_BITER_WIDTH (15U) 10709 #define DMA_TCD_TCD25_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD25_BITER_ELINKNO_BITER_MASK) 10710 10711 #define DMA_TCD_TCD25_BITER_ELINKNO_ELINK_MASK (0x8000U) 10712 #define DMA_TCD_TCD25_BITER_ELINKNO_ELINK_SHIFT (15U) 10713 #define DMA_TCD_TCD25_BITER_ELINKNO_ELINK_WIDTH (1U) 10714 #define DMA_TCD_TCD25_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD25_BITER_ELINKNO_ELINK_MASK) 10715 /*! @} */ 10716 10717 /*! @name TCD25_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 10718 /*! @{ */ 10719 10720 #define DMA_TCD_TCD25_BITER_ELINKYES_BITER_MASK (0x1FFU) 10721 #define DMA_TCD_TCD25_BITER_ELINKYES_BITER_SHIFT (0U) 10722 #define DMA_TCD_TCD25_BITER_ELINKYES_BITER_WIDTH (9U) 10723 #define DMA_TCD_TCD25_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD25_BITER_ELINKYES_BITER_MASK) 10724 10725 #define DMA_TCD_TCD25_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 10726 #define DMA_TCD_TCD25_BITER_ELINKYES_LINKCH_SHIFT (9U) 10727 #define DMA_TCD_TCD25_BITER_ELINKYES_LINKCH_WIDTH (5U) 10728 #define DMA_TCD_TCD25_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD25_BITER_ELINKYES_LINKCH_MASK) 10729 10730 #define DMA_TCD_TCD25_BITER_ELINKYES_ELINK_MASK (0x8000U) 10731 #define DMA_TCD_TCD25_BITER_ELINKYES_ELINK_SHIFT (15U) 10732 #define DMA_TCD_TCD25_BITER_ELINKYES_ELINK_WIDTH (1U) 10733 #define DMA_TCD_TCD25_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD25_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD25_BITER_ELINKYES_ELINK_MASK) 10734 /*! @} */ 10735 10736 /*! @name CH26_CSR - Channel Control and Status */ 10737 /*! @{ */ 10738 10739 #define DMA_TCD_CH26_CSR_ERQ_MASK (0x1U) 10740 #define DMA_TCD_CH26_CSR_ERQ_SHIFT (0U) 10741 #define DMA_TCD_CH26_CSR_ERQ_WIDTH (1U) 10742 #define DMA_TCD_CH26_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_CSR_ERQ_SHIFT)) & DMA_TCD_CH26_CSR_ERQ_MASK) 10743 10744 #define DMA_TCD_CH26_CSR_EARQ_MASK (0x2U) 10745 #define DMA_TCD_CH26_CSR_EARQ_SHIFT (1U) 10746 #define DMA_TCD_CH26_CSR_EARQ_WIDTH (1U) 10747 #define DMA_TCD_CH26_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_CSR_EARQ_SHIFT)) & DMA_TCD_CH26_CSR_EARQ_MASK) 10748 10749 #define DMA_TCD_CH26_CSR_EEI_MASK (0x4U) 10750 #define DMA_TCD_CH26_CSR_EEI_SHIFT (2U) 10751 #define DMA_TCD_CH26_CSR_EEI_WIDTH (1U) 10752 #define DMA_TCD_CH26_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_CSR_EEI_SHIFT)) & DMA_TCD_CH26_CSR_EEI_MASK) 10753 10754 #define DMA_TCD_CH26_CSR_EBW_MASK (0x8U) 10755 #define DMA_TCD_CH26_CSR_EBW_SHIFT (3U) 10756 #define DMA_TCD_CH26_CSR_EBW_WIDTH (1U) 10757 #define DMA_TCD_CH26_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_CSR_EBW_SHIFT)) & DMA_TCD_CH26_CSR_EBW_MASK) 10758 10759 #define DMA_TCD_CH26_CSR_DONE_MASK (0x40000000U) 10760 #define DMA_TCD_CH26_CSR_DONE_SHIFT (30U) 10761 #define DMA_TCD_CH26_CSR_DONE_WIDTH (1U) 10762 #define DMA_TCD_CH26_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_CSR_DONE_SHIFT)) & DMA_TCD_CH26_CSR_DONE_MASK) 10763 10764 #define DMA_TCD_CH26_CSR_ACTIVE_MASK (0x80000000U) 10765 #define DMA_TCD_CH26_CSR_ACTIVE_SHIFT (31U) 10766 #define DMA_TCD_CH26_CSR_ACTIVE_WIDTH (1U) 10767 #define DMA_TCD_CH26_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH26_CSR_ACTIVE_MASK) 10768 /*! @} */ 10769 10770 /*! @name CH26_ES - Channel Error Status */ 10771 /*! @{ */ 10772 10773 #define DMA_TCD_CH26_ES_DBE_MASK (0x1U) 10774 #define DMA_TCD_CH26_ES_DBE_SHIFT (0U) 10775 #define DMA_TCD_CH26_ES_DBE_WIDTH (1U) 10776 #define DMA_TCD_CH26_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_ES_DBE_SHIFT)) & DMA_TCD_CH26_ES_DBE_MASK) 10777 10778 #define DMA_TCD_CH26_ES_SBE_MASK (0x2U) 10779 #define DMA_TCD_CH26_ES_SBE_SHIFT (1U) 10780 #define DMA_TCD_CH26_ES_SBE_WIDTH (1U) 10781 #define DMA_TCD_CH26_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_ES_SBE_SHIFT)) & DMA_TCD_CH26_ES_SBE_MASK) 10782 10783 #define DMA_TCD_CH26_ES_SGE_MASK (0x4U) 10784 #define DMA_TCD_CH26_ES_SGE_SHIFT (2U) 10785 #define DMA_TCD_CH26_ES_SGE_WIDTH (1U) 10786 #define DMA_TCD_CH26_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_ES_SGE_SHIFT)) & DMA_TCD_CH26_ES_SGE_MASK) 10787 10788 #define DMA_TCD_CH26_ES_NCE_MASK (0x8U) 10789 #define DMA_TCD_CH26_ES_NCE_SHIFT (3U) 10790 #define DMA_TCD_CH26_ES_NCE_WIDTH (1U) 10791 #define DMA_TCD_CH26_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_ES_NCE_SHIFT)) & DMA_TCD_CH26_ES_NCE_MASK) 10792 10793 #define DMA_TCD_CH26_ES_DOE_MASK (0x10U) 10794 #define DMA_TCD_CH26_ES_DOE_SHIFT (4U) 10795 #define DMA_TCD_CH26_ES_DOE_WIDTH (1U) 10796 #define DMA_TCD_CH26_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_ES_DOE_SHIFT)) & DMA_TCD_CH26_ES_DOE_MASK) 10797 10798 #define DMA_TCD_CH26_ES_DAE_MASK (0x20U) 10799 #define DMA_TCD_CH26_ES_DAE_SHIFT (5U) 10800 #define DMA_TCD_CH26_ES_DAE_WIDTH (1U) 10801 #define DMA_TCD_CH26_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_ES_DAE_SHIFT)) & DMA_TCD_CH26_ES_DAE_MASK) 10802 10803 #define DMA_TCD_CH26_ES_SOE_MASK (0x40U) 10804 #define DMA_TCD_CH26_ES_SOE_SHIFT (6U) 10805 #define DMA_TCD_CH26_ES_SOE_WIDTH (1U) 10806 #define DMA_TCD_CH26_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_ES_SOE_SHIFT)) & DMA_TCD_CH26_ES_SOE_MASK) 10807 10808 #define DMA_TCD_CH26_ES_SAE_MASK (0x80U) 10809 #define DMA_TCD_CH26_ES_SAE_SHIFT (7U) 10810 #define DMA_TCD_CH26_ES_SAE_WIDTH (1U) 10811 #define DMA_TCD_CH26_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_ES_SAE_SHIFT)) & DMA_TCD_CH26_ES_SAE_MASK) 10812 10813 #define DMA_TCD_CH26_ES_ERR_MASK (0x80000000U) 10814 #define DMA_TCD_CH26_ES_ERR_SHIFT (31U) 10815 #define DMA_TCD_CH26_ES_ERR_WIDTH (1U) 10816 #define DMA_TCD_CH26_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_ES_ERR_SHIFT)) & DMA_TCD_CH26_ES_ERR_MASK) 10817 /*! @} */ 10818 10819 /*! @name CH26_INT - Channel Interrupt Status */ 10820 /*! @{ */ 10821 10822 #define DMA_TCD_CH26_INT_INT_MASK (0x1U) 10823 #define DMA_TCD_CH26_INT_INT_SHIFT (0U) 10824 #define DMA_TCD_CH26_INT_INT_WIDTH (1U) 10825 #define DMA_TCD_CH26_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_INT_INT_SHIFT)) & DMA_TCD_CH26_INT_INT_MASK) 10826 /*! @} */ 10827 10828 /*! @name CH26_SBR - Channel System Bus */ 10829 /*! @{ */ 10830 10831 #define DMA_TCD_CH26_SBR_MID_MASK (0xFU) 10832 #define DMA_TCD_CH26_SBR_MID_SHIFT (0U) 10833 #define DMA_TCD_CH26_SBR_MID_WIDTH (4U) 10834 #define DMA_TCD_CH26_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_SBR_MID_SHIFT)) & DMA_TCD_CH26_SBR_MID_MASK) 10835 10836 #define DMA_TCD_CH26_SBR_PAL_MASK (0x8000U) 10837 #define DMA_TCD_CH26_SBR_PAL_SHIFT (15U) 10838 #define DMA_TCD_CH26_SBR_PAL_WIDTH (1U) 10839 #define DMA_TCD_CH26_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_SBR_PAL_SHIFT)) & DMA_TCD_CH26_SBR_PAL_MASK) 10840 10841 #define DMA_TCD_CH26_SBR_EMI_MASK (0x10000U) 10842 #define DMA_TCD_CH26_SBR_EMI_SHIFT (16U) 10843 #define DMA_TCD_CH26_SBR_EMI_WIDTH (1U) 10844 #define DMA_TCD_CH26_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_SBR_EMI_SHIFT)) & DMA_TCD_CH26_SBR_EMI_MASK) 10845 10846 #define DMA_TCD_CH26_SBR_ATTR_MASK (0xE0000U) 10847 #define DMA_TCD_CH26_SBR_ATTR_SHIFT (17U) 10848 #define DMA_TCD_CH26_SBR_ATTR_WIDTH (3U) 10849 #define DMA_TCD_CH26_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_SBR_ATTR_SHIFT)) & DMA_TCD_CH26_SBR_ATTR_MASK) 10850 /*! @} */ 10851 10852 /*! @name CH26_PRI - Channel Priority */ 10853 /*! @{ */ 10854 10855 #define DMA_TCD_CH26_PRI_APL_MASK (0x7U) 10856 #define DMA_TCD_CH26_PRI_APL_SHIFT (0U) 10857 #define DMA_TCD_CH26_PRI_APL_WIDTH (3U) 10858 #define DMA_TCD_CH26_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_PRI_APL_SHIFT)) & DMA_TCD_CH26_PRI_APL_MASK) 10859 10860 #define DMA_TCD_CH26_PRI_DPA_MASK (0x40000000U) 10861 #define DMA_TCD_CH26_PRI_DPA_SHIFT (30U) 10862 #define DMA_TCD_CH26_PRI_DPA_WIDTH (1U) 10863 #define DMA_TCD_CH26_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_PRI_DPA_SHIFT)) & DMA_TCD_CH26_PRI_DPA_MASK) 10864 10865 #define DMA_TCD_CH26_PRI_ECP_MASK (0x80000000U) 10866 #define DMA_TCD_CH26_PRI_ECP_SHIFT (31U) 10867 #define DMA_TCD_CH26_PRI_ECP_WIDTH (1U) 10868 #define DMA_TCD_CH26_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH26_PRI_ECP_SHIFT)) & DMA_TCD_CH26_PRI_ECP_MASK) 10869 /*! @} */ 10870 10871 /*! @name TCD26_SADDR - TCD Source Address */ 10872 /*! @{ */ 10873 10874 #define DMA_TCD_TCD26_SADDR_SADDR_MASK (0xFFFFFFFFU) 10875 #define DMA_TCD_TCD26_SADDR_SADDR_SHIFT (0U) 10876 #define DMA_TCD_TCD26_SADDR_SADDR_WIDTH (32U) 10877 #define DMA_TCD_TCD26_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD26_SADDR_SADDR_MASK) 10878 /*! @} */ 10879 10880 /*! @name TCD26_SOFF - TCD Signed Source Address Offset */ 10881 /*! @{ */ 10882 10883 #define DMA_TCD_TCD26_SOFF_SOFF_MASK (0xFFFFU) 10884 #define DMA_TCD_TCD26_SOFF_SOFF_SHIFT (0U) 10885 #define DMA_TCD_TCD26_SOFF_SOFF_WIDTH (16U) 10886 #define DMA_TCD_TCD26_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD26_SOFF_SOFF_MASK) 10887 /*! @} */ 10888 10889 /*! @name TCD26_ATTR - TCD Transfer Attributes */ 10890 /*! @{ */ 10891 10892 #define DMA_TCD_TCD26_ATTR_DSIZE_MASK (0x7U) 10893 #define DMA_TCD_TCD26_ATTR_DSIZE_SHIFT (0U) 10894 #define DMA_TCD_TCD26_ATTR_DSIZE_WIDTH (3U) 10895 #define DMA_TCD_TCD26_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD26_ATTR_DSIZE_MASK) 10896 10897 #define DMA_TCD_TCD26_ATTR_DMOD_MASK (0xF8U) 10898 #define DMA_TCD_TCD26_ATTR_DMOD_SHIFT (3U) 10899 #define DMA_TCD_TCD26_ATTR_DMOD_WIDTH (5U) 10900 #define DMA_TCD_TCD26_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD26_ATTR_DMOD_MASK) 10901 10902 #define DMA_TCD_TCD26_ATTR_SSIZE_MASK (0x700U) 10903 #define DMA_TCD_TCD26_ATTR_SSIZE_SHIFT (8U) 10904 #define DMA_TCD_TCD26_ATTR_SSIZE_WIDTH (3U) 10905 #define DMA_TCD_TCD26_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD26_ATTR_SSIZE_MASK) 10906 10907 #define DMA_TCD_TCD26_ATTR_SMOD_MASK (0xF800U) 10908 #define DMA_TCD_TCD26_ATTR_SMOD_SHIFT (11U) 10909 #define DMA_TCD_TCD26_ATTR_SMOD_WIDTH (5U) 10910 #define DMA_TCD_TCD26_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD26_ATTR_SMOD_MASK) 10911 /*! @} */ 10912 10913 /*! @name TCD26_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 10914 /*! @{ */ 10915 10916 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 10917 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 10918 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 10919 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD26_NBYTES_MLOFFNO_NBYTES_MASK) 10920 10921 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 10922 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 10923 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 10924 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD26_NBYTES_MLOFFNO_DMLOE_MASK) 10925 10926 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 10927 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 10928 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 10929 #define DMA_TCD_TCD26_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD26_NBYTES_MLOFFNO_SMLOE_MASK) 10930 /*! @} */ 10931 10932 /*! @name TCD26_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 10933 /*! @{ */ 10934 10935 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 10936 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 10937 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 10938 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD26_NBYTES_MLOFFYES_NBYTES_MASK) 10939 10940 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 10941 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 10942 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 10943 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD26_NBYTES_MLOFFYES_MLOFF_MASK) 10944 10945 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 10946 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 10947 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 10948 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD26_NBYTES_MLOFFYES_DMLOE_MASK) 10949 10950 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 10951 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 10952 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 10953 #define DMA_TCD_TCD26_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD26_NBYTES_MLOFFYES_SMLOE_MASK) 10954 /*! @} */ 10955 10956 /*! @name TCD26_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 10957 /*! @{ */ 10958 10959 #define DMA_TCD_TCD26_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 10960 #define DMA_TCD_TCD26_SLAST_SDA_SLAST_SDA_SHIFT (0U) 10961 #define DMA_TCD_TCD26_SLAST_SDA_SLAST_SDA_WIDTH (32U) 10962 #define DMA_TCD_TCD26_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD26_SLAST_SDA_SLAST_SDA_MASK) 10963 /*! @} */ 10964 10965 /*! @name TCD26_DADDR - TCD Destination Address */ 10966 /*! @{ */ 10967 10968 #define DMA_TCD_TCD26_DADDR_DADDR_MASK (0xFFFFFFFFU) 10969 #define DMA_TCD_TCD26_DADDR_DADDR_SHIFT (0U) 10970 #define DMA_TCD_TCD26_DADDR_DADDR_WIDTH (32U) 10971 #define DMA_TCD_TCD26_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD26_DADDR_DADDR_MASK) 10972 /*! @} */ 10973 10974 /*! @name TCD26_DOFF - TCD Signed Destination Address Offset */ 10975 /*! @{ */ 10976 10977 #define DMA_TCD_TCD26_DOFF_DOFF_MASK (0xFFFFU) 10978 #define DMA_TCD_TCD26_DOFF_DOFF_SHIFT (0U) 10979 #define DMA_TCD_TCD26_DOFF_DOFF_WIDTH (16U) 10980 #define DMA_TCD_TCD26_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD26_DOFF_DOFF_MASK) 10981 /*! @} */ 10982 10983 /*! @name TCD26_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 10984 /*! @{ */ 10985 10986 #define DMA_TCD_TCD26_CITER_ELINKNO_CITER_MASK (0x7FFFU) 10987 #define DMA_TCD_TCD26_CITER_ELINKNO_CITER_SHIFT (0U) 10988 #define DMA_TCD_TCD26_CITER_ELINKNO_CITER_WIDTH (15U) 10989 #define DMA_TCD_TCD26_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD26_CITER_ELINKNO_CITER_MASK) 10990 10991 #define DMA_TCD_TCD26_CITER_ELINKNO_ELINK_MASK (0x8000U) 10992 #define DMA_TCD_TCD26_CITER_ELINKNO_ELINK_SHIFT (15U) 10993 #define DMA_TCD_TCD26_CITER_ELINKNO_ELINK_WIDTH (1U) 10994 #define DMA_TCD_TCD26_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD26_CITER_ELINKNO_ELINK_MASK) 10995 /*! @} */ 10996 10997 /*! @name TCD26_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 10998 /*! @{ */ 10999 11000 #define DMA_TCD_TCD26_CITER_ELINKYES_CITER_MASK (0x1FFU) 11001 #define DMA_TCD_TCD26_CITER_ELINKYES_CITER_SHIFT (0U) 11002 #define DMA_TCD_TCD26_CITER_ELINKYES_CITER_WIDTH (9U) 11003 #define DMA_TCD_TCD26_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD26_CITER_ELINKYES_CITER_MASK) 11004 11005 #define DMA_TCD_TCD26_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 11006 #define DMA_TCD_TCD26_CITER_ELINKYES_LINKCH_SHIFT (9U) 11007 #define DMA_TCD_TCD26_CITER_ELINKYES_LINKCH_WIDTH (5U) 11008 #define DMA_TCD_TCD26_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD26_CITER_ELINKYES_LINKCH_MASK) 11009 11010 #define DMA_TCD_TCD26_CITER_ELINKYES_ELINK_MASK (0x8000U) 11011 #define DMA_TCD_TCD26_CITER_ELINKYES_ELINK_SHIFT (15U) 11012 #define DMA_TCD_TCD26_CITER_ELINKYES_ELINK_WIDTH (1U) 11013 #define DMA_TCD_TCD26_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD26_CITER_ELINKYES_ELINK_MASK) 11014 /*! @} */ 11015 11016 /*! @name TCD26_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 11017 /*! @{ */ 11018 11019 #define DMA_TCD_TCD26_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 11020 #define DMA_TCD_TCD26_DLAST_SGA_DLAST_SGA_SHIFT (0U) 11021 #define DMA_TCD_TCD26_DLAST_SGA_DLAST_SGA_WIDTH (32U) 11022 #define DMA_TCD_TCD26_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD26_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD26_DLAST_SGA_DLAST_SGA_MASK) 11023 /*! @} */ 11024 11025 /*! @name TCD26_CSR - TCD Control and Status */ 11026 /*! @{ */ 11027 11028 #define DMA_TCD_TCD26_CSR_START_MASK (0x1U) 11029 #define DMA_TCD_TCD26_CSR_START_SHIFT (0U) 11030 #define DMA_TCD_TCD26_CSR_START_WIDTH (1U) 11031 #define DMA_TCD_TCD26_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CSR_START_SHIFT)) & DMA_TCD_TCD26_CSR_START_MASK) 11032 11033 #define DMA_TCD_TCD26_CSR_INTMAJOR_MASK (0x2U) 11034 #define DMA_TCD_TCD26_CSR_INTMAJOR_SHIFT (1U) 11035 #define DMA_TCD_TCD26_CSR_INTMAJOR_WIDTH (1U) 11036 #define DMA_TCD_TCD26_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD26_CSR_INTMAJOR_MASK) 11037 11038 #define DMA_TCD_TCD26_CSR_INTHALF_MASK (0x4U) 11039 #define DMA_TCD_TCD26_CSR_INTHALF_SHIFT (2U) 11040 #define DMA_TCD_TCD26_CSR_INTHALF_WIDTH (1U) 11041 #define DMA_TCD_TCD26_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD26_CSR_INTHALF_MASK) 11042 11043 #define DMA_TCD_TCD26_CSR_DREQ_MASK (0x8U) 11044 #define DMA_TCD_TCD26_CSR_DREQ_SHIFT (3U) 11045 #define DMA_TCD_TCD26_CSR_DREQ_WIDTH (1U) 11046 #define DMA_TCD_TCD26_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CSR_DREQ_SHIFT)) & DMA_TCD_TCD26_CSR_DREQ_MASK) 11047 11048 #define DMA_TCD_TCD26_CSR_ESG_MASK (0x10U) 11049 #define DMA_TCD_TCD26_CSR_ESG_SHIFT (4U) 11050 #define DMA_TCD_TCD26_CSR_ESG_WIDTH (1U) 11051 #define DMA_TCD_TCD26_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CSR_ESG_SHIFT)) & DMA_TCD_TCD26_CSR_ESG_MASK) 11052 11053 #define DMA_TCD_TCD26_CSR_MAJORELINK_MASK (0x20U) 11054 #define DMA_TCD_TCD26_CSR_MAJORELINK_SHIFT (5U) 11055 #define DMA_TCD_TCD26_CSR_MAJORELINK_WIDTH (1U) 11056 #define DMA_TCD_TCD26_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD26_CSR_MAJORELINK_MASK) 11057 11058 #define DMA_TCD_TCD26_CSR_EEOP_MASK (0x40U) 11059 #define DMA_TCD_TCD26_CSR_EEOP_SHIFT (6U) 11060 #define DMA_TCD_TCD26_CSR_EEOP_WIDTH (1U) 11061 #define DMA_TCD_TCD26_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CSR_EEOP_SHIFT)) & DMA_TCD_TCD26_CSR_EEOP_MASK) 11062 11063 #define DMA_TCD_TCD26_CSR_ESDA_MASK (0x80U) 11064 #define DMA_TCD_TCD26_CSR_ESDA_SHIFT (7U) 11065 #define DMA_TCD_TCD26_CSR_ESDA_WIDTH (1U) 11066 #define DMA_TCD_TCD26_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CSR_ESDA_SHIFT)) & DMA_TCD_TCD26_CSR_ESDA_MASK) 11067 11068 #define DMA_TCD_TCD26_CSR_MAJORLINKCH_MASK (0x1F00U) 11069 #define DMA_TCD_TCD26_CSR_MAJORLINKCH_SHIFT (8U) 11070 #define DMA_TCD_TCD26_CSR_MAJORLINKCH_WIDTH (5U) 11071 #define DMA_TCD_TCD26_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD26_CSR_MAJORLINKCH_MASK) 11072 11073 #define DMA_TCD_TCD26_CSR_BWC_MASK (0xC000U) 11074 #define DMA_TCD_TCD26_CSR_BWC_SHIFT (14U) 11075 #define DMA_TCD_TCD26_CSR_BWC_WIDTH (2U) 11076 #define DMA_TCD_TCD26_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_CSR_BWC_SHIFT)) & DMA_TCD_TCD26_CSR_BWC_MASK) 11077 /*! @} */ 11078 11079 /*! @name TCD26_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 11080 /*! @{ */ 11081 11082 #define DMA_TCD_TCD26_BITER_ELINKNO_BITER_MASK (0x7FFFU) 11083 #define DMA_TCD_TCD26_BITER_ELINKNO_BITER_SHIFT (0U) 11084 #define DMA_TCD_TCD26_BITER_ELINKNO_BITER_WIDTH (15U) 11085 #define DMA_TCD_TCD26_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD26_BITER_ELINKNO_BITER_MASK) 11086 11087 #define DMA_TCD_TCD26_BITER_ELINKNO_ELINK_MASK (0x8000U) 11088 #define DMA_TCD_TCD26_BITER_ELINKNO_ELINK_SHIFT (15U) 11089 #define DMA_TCD_TCD26_BITER_ELINKNO_ELINK_WIDTH (1U) 11090 #define DMA_TCD_TCD26_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD26_BITER_ELINKNO_ELINK_MASK) 11091 /*! @} */ 11092 11093 /*! @name TCD26_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 11094 /*! @{ */ 11095 11096 #define DMA_TCD_TCD26_BITER_ELINKYES_BITER_MASK (0x1FFU) 11097 #define DMA_TCD_TCD26_BITER_ELINKYES_BITER_SHIFT (0U) 11098 #define DMA_TCD_TCD26_BITER_ELINKYES_BITER_WIDTH (9U) 11099 #define DMA_TCD_TCD26_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD26_BITER_ELINKYES_BITER_MASK) 11100 11101 #define DMA_TCD_TCD26_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 11102 #define DMA_TCD_TCD26_BITER_ELINKYES_LINKCH_SHIFT (9U) 11103 #define DMA_TCD_TCD26_BITER_ELINKYES_LINKCH_WIDTH (5U) 11104 #define DMA_TCD_TCD26_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD26_BITER_ELINKYES_LINKCH_MASK) 11105 11106 #define DMA_TCD_TCD26_BITER_ELINKYES_ELINK_MASK (0x8000U) 11107 #define DMA_TCD_TCD26_BITER_ELINKYES_ELINK_SHIFT (15U) 11108 #define DMA_TCD_TCD26_BITER_ELINKYES_ELINK_WIDTH (1U) 11109 #define DMA_TCD_TCD26_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD26_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD26_BITER_ELINKYES_ELINK_MASK) 11110 /*! @} */ 11111 11112 /*! @name CH27_CSR - Channel Control and Status */ 11113 /*! @{ */ 11114 11115 #define DMA_TCD_CH27_CSR_ERQ_MASK (0x1U) 11116 #define DMA_TCD_CH27_CSR_ERQ_SHIFT (0U) 11117 #define DMA_TCD_CH27_CSR_ERQ_WIDTH (1U) 11118 #define DMA_TCD_CH27_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_CSR_ERQ_SHIFT)) & DMA_TCD_CH27_CSR_ERQ_MASK) 11119 11120 #define DMA_TCD_CH27_CSR_EARQ_MASK (0x2U) 11121 #define DMA_TCD_CH27_CSR_EARQ_SHIFT (1U) 11122 #define DMA_TCD_CH27_CSR_EARQ_WIDTH (1U) 11123 #define DMA_TCD_CH27_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_CSR_EARQ_SHIFT)) & DMA_TCD_CH27_CSR_EARQ_MASK) 11124 11125 #define DMA_TCD_CH27_CSR_EEI_MASK (0x4U) 11126 #define DMA_TCD_CH27_CSR_EEI_SHIFT (2U) 11127 #define DMA_TCD_CH27_CSR_EEI_WIDTH (1U) 11128 #define DMA_TCD_CH27_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_CSR_EEI_SHIFT)) & DMA_TCD_CH27_CSR_EEI_MASK) 11129 11130 #define DMA_TCD_CH27_CSR_EBW_MASK (0x8U) 11131 #define DMA_TCD_CH27_CSR_EBW_SHIFT (3U) 11132 #define DMA_TCD_CH27_CSR_EBW_WIDTH (1U) 11133 #define DMA_TCD_CH27_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_CSR_EBW_SHIFT)) & DMA_TCD_CH27_CSR_EBW_MASK) 11134 11135 #define DMA_TCD_CH27_CSR_DONE_MASK (0x40000000U) 11136 #define DMA_TCD_CH27_CSR_DONE_SHIFT (30U) 11137 #define DMA_TCD_CH27_CSR_DONE_WIDTH (1U) 11138 #define DMA_TCD_CH27_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_CSR_DONE_SHIFT)) & DMA_TCD_CH27_CSR_DONE_MASK) 11139 11140 #define DMA_TCD_CH27_CSR_ACTIVE_MASK (0x80000000U) 11141 #define DMA_TCD_CH27_CSR_ACTIVE_SHIFT (31U) 11142 #define DMA_TCD_CH27_CSR_ACTIVE_WIDTH (1U) 11143 #define DMA_TCD_CH27_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH27_CSR_ACTIVE_MASK) 11144 /*! @} */ 11145 11146 /*! @name CH27_ES - Channel Error Status */ 11147 /*! @{ */ 11148 11149 #define DMA_TCD_CH27_ES_DBE_MASK (0x1U) 11150 #define DMA_TCD_CH27_ES_DBE_SHIFT (0U) 11151 #define DMA_TCD_CH27_ES_DBE_WIDTH (1U) 11152 #define DMA_TCD_CH27_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_ES_DBE_SHIFT)) & DMA_TCD_CH27_ES_DBE_MASK) 11153 11154 #define DMA_TCD_CH27_ES_SBE_MASK (0x2U) 11155 #define DMA_TCD_CH27_ES_SBE_SHIFT (1U) 11156 #define DMA_TCD_CH27_ES_SBE_WIDTH (1U) 11157 #define DMA_TCD_CH27_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_ES_SBE_SHIFT)) & DMA_TCD_CH27_ES_SBE_MASK) 11158 11159 #define DMA_TCD_CH27_ES_SGE_MASK (0x4U) 11160 #define DMA_TCD_CH27_ES_SGE_SHIFT (2U) 11161 #define DMA_TCD_CH27_ES_SGE_WIDTH (1U) 11162 #define DMA_TCD_CH27_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_ES_SGE_SHIFT)) & DMA_TCD_CH27_ES_SGE_MASK) 11163 11164 #define DMA_TCD_CH27_ES_NCE_MASK (0x8U) 11165 #define DMA_TCD_CH27_ES_NCE_SHIFT (3U) 11166 #define DMA_TCD_CH27_ES_NCE_WIDTH (1U) 11167 #define DMA_TCD_CH27_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_ES_NCE_SHIFT)) & DMA_TCD_CH27_ES_NCE_MASK) 11168 11169 #define DMA_TCD_CH27_ES_DOE_MASK (0x10U) 11170 #define DMA_TCD_CH27_ES_DOE_SHIFT (4U) 11171 #define DMA_TCD_CH27_ES_DOE_WIDTH (1U) 11172 #define DMA_TCD_CH27_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_ES_DOE_SHIFT)) & DMA_TCD_CH27_ES_DOE_MASK) 11173 11174 #define DMA_TCD_CH27_ES_DAE_MASK (0x20U) 11175 #define DMA_TCD_CH27_ES_DAE_SHIFT (5U) 11176 #define DMA_TCD_CH27_ES_DAE_WIDTH (1U) 11177 #define DMA_TCD_CH27_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_ES_DAE_SHIFT)) & DMA_TCD_CH27_ES_DAE_MASK) 11178 11179 #define DMA_TCD_CH27_ES_SOE_MASK (0x40U) 11180 #define DMA_TCD_CH27_ES_SOE_SHIFT (6U) 11181 #define DMA_TCD_CH27_ES_SOE_WIDTH (1U) 11182 #define DMA_TCD_CH27_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_ES_SOE_SHIFT)) & DMA_TCD_CH27_ES_SOE_MASK) 11183 11184 #define DMA_TCD_CH27_ES_SAE_MASK (0x80U) 11185 #define DMA_TCD_CH27_ES_SAE_SHIFT (7U) 11186 #define DMA_TCD_CH27_ES_SAE_WIDTH (1U) 11187 #define DMA_TCD_CH27_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_ES_SAE_SHIFT)) & DMA_TCD_CH27_ES_SAE_MASK) 11188 11189 #define DMA_TCD_CH27_ES_ERR_MASK (0x80000000U) 11190 #define DMA_TCD_CH27_ES_ERR_SHIFT (31U) 11191 #define DMA_TCD_CH27_ES_ERR_WIDTH (1U) 11192 #define DMA_TCD_CH27_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_ES_ERR_SHIFT)) & DMA_TCD_CH27_ES_ERR_MASK) 11193 /*! @} */ 11194 11195 /*! @name CH27_INT - Channel Interrupt Status */ 11196 /*! @{ */ 11197 11198 #define DMA_TCD_CH27_INT_INT_MASK (0x1U) 11199 #define DMA_TCD_CH27_INT_INT_SHIFT (0U) 11200 #define DMA_TCD_CH27_INT_INT_WIDTH (1U) 11201 #define DMA_TCD_CH27_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_INT_INT_SHIFT)) & DMA_TCD_CH27_INT_INT_MASK) 11202 /*! @} */ 11203 11204 /*! @name CH27_SBR - Channel System Bus */ 11205 /*! @{ */ 11206 11207 #define DMA_TCD_CH27_SBR_MID_MASK (0xFU) 11208 #define DMA_TCD_CH27_SBR_MID_SHIFT (0U) 11209 #define DMA_TCD_CH27_SBR_MID_WIDTH (4U) 11210 #define DMA_TCD_CH27_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_SBR_MID_SHIFT)) & DMA_TCD_CH27_SBR_MID_MASK) 11211 11212 #define DMA_TCD_CH27_SBR_PAL_MASK (0x8000U) 11213 #define DMA_TCD_CH27_SBR_PAL_SHIFT (15U) 11214 #define DMA_TCD_CH27_SBR_PAL_WIDTH (1U) 11215 #define DMA_TCD_CH27_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_SBR_PAL_SHIFT)) & DMA_TCD_CH27_SBR_PAL_MASK) 11216 11217 #define DMA_TCD_CH27_SBR_EMI_MASK (0x10000U) 11218 #define DMA_TCD_CH27_SBR_EMI_SHIFT (16U) 11219 #define DMA_TCD_CH27_SBR_EMI_WIDTH (1U) 11220 #define DMA_TCD_CH27_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_SBR_EMI_SHIFT)) & DMA_TCD_CH27_SBR_EMI_MASK) 11221 11222 #define DMA_TCD_CH27_SBR_ATTR_MASK (0xE0000U) 11223 #define DMA_TCD_CH27_SBR_ATTR_SHIFT (17U) 11224 #define DMA_TCD_CH27_SBR_ATTR_WIDTH (3U) 11225 #define DMA_TCD_CH27_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_SBR_ATTR_SHIFT)) & DMA_TCD_CH27_SBR_ATTR_MASK) 11226 /*! @} */ 11227 11228 /*! @name CH27_PRI - Channel Priority */ 11229 /*! @{ */ 11230 11231 #define DMA_TCD_CH27_PRI_APL_MASK (0x7U) 11232 #define DMA_TCD_CH27_PRI_APL_SHIFT (0U) 11233 #define DMA_TCD_CH27_PRI_APL_WIDTH (3U) 11234 #define DMA_TCD_CH27_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_PRI_APL_SHIFT)) & DMA_TCD_CH27_PRI_APL_MASK) 11235 11236 #define DMA_TCD_CH27_PRI_DPA_MASK (0x40000000U) 11237 #define DMA_TCD_CH27_PRI_DPA_SHIFT (30U) 11238 #define DMA_TCD_CH27_PRI_DPA_WIDTH (1U) 11239 #define DMA_TCD_CH27_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_PRI_DPA_SHIFT)) & DMA_TCD_CH27_PRI_DPA_MASK) 11240 11241 #define DMA_TCD_CH27_PRI_ECP_MASK (0x80000000U) 11242 #define DMA_TCD_CH27_PRI_ECP_SHIFT (31U) 11243 #define DMA_TCD_CH27_PRI_ECP_WIDTH (1U) 11244 #define DMA_TCD_CH27_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH27_PRI_ECP_SHIFT)) & DMA_TCD_CH27_PRI_ECP_MASK) 11245 /*! @} */ 11246 11247 /*! @name TCD27_SADDR - TCD Source Address */ 11248 /*! @{ */ 11249 11250 #define DMA_TCD_TCD27_SADDR_SADDR_MASK (0xFFFFFFFFU) 11251 #define DMA_TCD_TCD27_SADDR_SADDR_SHIFT (0U) 11252 #define DMA_TCD_TCD27_SADDR_SADDR_WIDTH (32U) 11253 #define DMA_TCD_TCD27_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD27_SADDR_SADDR_MASK) 11254 /*! @} */ 11255 11256 /*! @name TCD27_SOFF - TCD Signed Source Address Offset */ 11257 /*! @{ */ 11258 11259 #define DMA_TCD_TCD27_SOFF_SOFF_MASK (0xFFFFU) 11260 #define DMA_TCD_TCD27_SOFF_SOFF_SHIFT (0U) 11261 #define DMA_TCD_TCD27_SOFF_SOFF_WIDTH (16U) 11262 #define DMA_TCD_TCD27_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD27_SOFF_SOFF_MASK) 11263 /*! @} */ 11264 11265 /*! @name TCD27_ATTR - TCD Transfer Attributes */ 11266 /*! @{ */ 11267 11268 #define DMA_TCD_TCD27_ATTR_DSIZE_MASK (0x7U) 11269 #define DMA_TCD_TCD27_ATTR_DSIZE_SHIFT (0U) 11270 #define DMA_TCD_TCD27_ATTR_DSIZE_WIDTH (3U) 11271 #define DMA_TCD_TCD27_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD27_ATTR_DSIZE_MASK) 11272 11273 #define DMA_TCD_TCD27_ATTR_DMOD_MASK (0xF8U) 11274 #define DMA_TCD_TCD27_ATTR_DMOD_SHIFT (3U) 11275 #define DMA_TCD_TCD27_ATTR_DMOD_WIDTH (5U) 11276 #define DMA_TCD_TCD27_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD27_ATTR_DMOD_MASK) 11277 11278 #define DMA_TCD_TCD27_ATTR_SSIZE_MASK (0x700U) 11279 #define DMA_TCD_TCD27_ATTR_SSIZE_SHIFT (8U) 11280 #define DMA_TCD_TCD27_ATTR_SSIZE_WIDTH (3U) 11281 #define DMA_TCD_TCD27_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD27_ATTR_SSIZE_MASK) 11282 11283 #define DMA_TCD_TCD27_ATTR_SMOD_MASK (0xF800U) 11284 #define DMA_TCD_TCD27_ATTR_SMOD_SHIFT (11U) 11285 #define DMA_TCD_TCD27_ATTR_SMOD_WIDTH (5U) 11286 #define DMA_TCD_TCD27_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD27_ATTR_SMOD_MASK) 11287 /*! @} */ 11288 11289 /*! @name TCD27_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 11290 /*! @{ */ 11291 11292 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 11293 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 11294 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 11295 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD27_NBYTES_MLOFFNO_NBYTES_MASK) 11296 11297 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 11298 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 11299 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 11300 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD27_NBYTES_MLOFFNO_DMLOE_MASK) 11301 11302 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 11303 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 11304 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 11305 #define DMA_TCD_TCD27_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD27_NBYTES_MLOFFNO_SMLOE_MASK) 11306 /*! @} */ 11307 11308 /*! @name TCD27_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 11309 /*! @{ */ 11310 11311 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 11312 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 11313 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 11314 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD27_NBYTES_MLOFFYES_NBYTES_MASK) 11315 11316 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 11317 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 11318 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 11319 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD27_NBYTES_MLOFFYES_MLOFF_MASK) 11320 11321 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 11322 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 11323 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 11324 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD27_NBYTES_MLOFFYES_DMLOE_MASK) 11325 11326 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 11327 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 11328 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 11329 #define DMA_TCD_TCD27_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD27_NBYTES_MLOFFYES_SMLOE_MASK) 11330 /*! @} */ 11331 11332 /*! @name TCD27_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 11333 /*! @{ */ 11334 11335 #define DMA_TCD_TCD27_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 11336 #define DMA_TCD_TCD27_SLAST_SDA_SLAST_SDA_SHIFT (0U) 11337 #define DMA_TCD_TCD27_SLAST_SDA_SLAST_SDA_WIDTH (32U) 11338 #define DMA_TCD_TCD27_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD27_SLAST_SDA_SLAST_SDA_MASK) 11339 /*! @} */ 11340 11341 /*! @name TCD27_DADDR - TCD Destination Address */ 11342 /*! @{ */ 11343 11344 #define DMA_TCD_TCD27_DADDR_DADDR_MASK (0xFFFFFFFFU) 11345 #define DMA_TCD_TCD27_DADDR_DADDR_SHIFT (0U) 11346 #define DMA_TCD_TCD27_DADDR_DADDR_WIDTH (32U) 11347 #define DMA_TCD_TCD27_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD27_DADDR_DADDR_MASK) 11348 /*! @} */ 11349 11350 /*! @name TCD27_DOFF - TCD Signed Destination Address Offset */ 11351 /*! @{ */ 11352 11353 #define DMA_TCD_TCD27_DOFF_DOFF_MASK (0xFFFFU) 11354 #define DMA_TCD_TCD27_DOFF_DOFF_SHIFT (0U) 11355 #define DMA_TCD_TCD27_DOFF_DOFF_WIDTH (16U) 11356 #define DMA_TCD_TCD27_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD27_DOFF_DOFF_MASK) 11357 /*! @} */ 11358 11359 /*! @name TCD27_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 11360 /*! @{ */ 11361 11362 #define DMA_TCD_TCD27_CITER_ELINKNO_CITER_MASK (0x7FFFU) 11363 #define DMA_TCD_TCD27_CITER_ELINKNO_CITER_SHIFT (0U) 11364 #define DMA_TCD_TCD27_CITER_ELINKNO_CITER_WIDTH (15U) 11365 #define DMA_TCD_TCD27_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD27_CITER_ELINKNO_CITER_MASK) 11366 11367 #define DMA_TCD_TCD27_CITER_ELINKNO_ELINK_MASK (0x8000U) 11368 #define DMA_TCD_TCD27_CITER_ELINKNO_ELINK_SHIFT (15U) 11369 #define DMA_TCD_TCD27_CITER_ELINKNO_ELINK_WIDTH (1U) 11370 #define DMA_TCD_TCD27_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD27_CITER_ELINKNO_ELINK_MASK) 11371 /*! @} */ 11372 11373 /*! @name TCD27_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 11374 /*! @{ */ 11375 11376 #define DMA_TCD_TCD27_CITER_ELINKYES_CITER_MASK (0x1FFU) 11377 #define DMA_TCD_TCD27_CITER_ELINKYES_CITER_SHIFT (0U) 11378 #define DMA_TCD_TCD27_CITER_ELINKYES_CITER_WIDTH (9U) 11379 #define DMA_TCD_TCD27_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD27_CITER_ELINKYES_CITER_MASK) 11380 11381 #define DMA_TCD_TCD27_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 11382 #define DMA_TCD_TCD27_CITER_ELINKYES_LINKCH_SHIFT (9U) 11383 #define DMA_TCD_TCD27_CITER_ELINKYES_LINKCH_WIDTH (5U) 11384 #define DMA_TCD_TCD27_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD27_CITER_ELINKYES_LINKCH_MASK) 11385 11386 #define DMA_TCD_TCD27_CITER_ELINKYES_ELINK_MASK (0x8000U) 11387 #define DMA_TCD_TCD27_CITER_ELINKYES_ELINK_SHIFT (15U) 11388 #define DMA_TCD_TCD27_CITER_ELINKYES_ELINK_WIDTH (1U) 11389 #define DMA_TCD_TCD27_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD27_CITER_ELINKYES_ELINK_MASK) 11390 /*! @} */ 11391 11392 /*! @name TCD27_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 11393 /*! @{ */ 11394 11395 #define DMA_TCD_TCD27_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 11396 #define DMA_TCD_TCD27_DLAST_SGA_DLAST_SGA_SHIFT (0U) 11397 #define DMA_TCD_TCD27_DLAST_SGA_DLAST_SGA_WIDTH (32U) 11398 #define DMA_TCD_TCD27_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD27_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD27_DLAST_SGA_DLAST_SGA_MASK) 11399 /*! @} */ 11400 11401 /*! @name TCD27_CSR - TCD Control and Status */ 11402 /*! @{ */ 11403 11404 #define DMA_TCD_TCD27_CSR_START_MASK (0x1U) 11405 #define DMA_TCD_TCD27_CSR_START_SHIFT (0U) 11406 #define DMA_TCD_TCD27_CSR_START_WIDTH (1U) 11407 #define DMA_TCD_TCD27_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CSR_START_SHIFT)) & DMA_TCD_TCD27_CSR_START_MASK) 11408 11409 #define DMA_TCD_TCD27_CSR_INTMAJOR_MASK (0x2U) 11410 #define DMA_TCD_TCD27_CSR_INTMAJOR_SHIFT (1U) 11411 #define DMA_TCD_TCD27_CSR_INTMAJOR_WIDTH (1U) 11412 #define DMA_TCD_TCD27_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD27_CSR_INTMAJOR_MASK) 11413 11414 #define DMA_TCD_TCD27_CSR_INTHALF_MASK (0x4U) 11415 #define DMA_TCD_TCD27_CSR_INTHALF_SHIFT (2U) 11416 #define DMA_TCD_TCD27_CSR_INTHALF_WIDTH (1U) 11417 #define DMA_TCD_TCD27_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD27_CSR_INTHALF_MASK) 11418 11419 #define DMA_TCD_TCD27_CSR_DREQ_MASK (0x8U) 11420 #define DMA_TCD_TCD27_CSR_DREQ_SHIFT (3U) 11421 #define DMA_TCD_TCD27_CSR_DREQ_WIDTH (1U) 11422 #define DMA_TCD_TCD27_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CSR_DREQ_SHIFT)) & DMA_TCD_TCD27_CSR_DREQ_MASK) 11423 11424 #define DMA_TCD_TCD27_CSR_ESG_MASK (0x10U) 11425 #define DMA_TCD_TCD27_CSR_ESG_SHIFT (4U) 11426 #define DMA_TCD_TCD27_CSR_ESG_WIDTH (1U) 11427 #define DMA_TCD_TCD27_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CSR_ESG_SHIFT)) & DMA_TCD_TCD27_CSR_ESG_MASK) 11428 11429 #define DMA_TCD_TCD27_CSR_MAJORELINK_MASK (0x20U) 11430 #define DMA_TCD_TCD27_CSR_MAJORELINK_SHIFT (5U) 11431 #define DMA_TCD_TCD27_CSR_MAJORELINK_WIDTH (1U) 11432 #define DMA_TCD_TCD27_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD27_CSR_MAJORELINK_MASK) 11433 11434 #define DMA_TCD_TCD27_CSR_EEOP_MASK (0x40U) 11435 #define DMA_TCD_TCD27_CSR_EEOP_SHIFT (6U) 11436 #define DMA_TCD_TCD27_CSR_EEOP_WIDTH (1U) 11437 #define DMA_TCD_TCD27_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CSR_EEOP_SHIFT)) & DMA_TCD_TCD27_CSR_EEOP_MASK) 11438 11439 #define DMA_TCD_TCD27_CSR_ESDA_MASK (0x80U) 11440 #define DMA_TCD_TCD27_CSR_ESDA_SHIFT (7U) 11441 #define DMA_TCD_TCD27_CSR_ESDA_WIDTH (1U) 11442 #define DMA_TCD_TCD27_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CSR_ESDA_SHIFT)) & DMA_TCD_TCD27_CSR_ESDA_MASK) 11443 11444 #define DMA_TCD_TCD27_CSR_MAJORLINKCH_MASK (0x1F00U) 11445 #define DMA_TCD_TCD27_CSR_MAJORLINKCH_SHIFT (8U) 11446 #define DMA_TCD_TCD27_CSR_MAJORLINKCH_WIDTH (5U) 11447 #define DMA_TCD_TCD27_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD27_CSR_MAJORLINKCH_MASK) 11448 11449 #define DMA_TCD_TCD27_CSR_BWC_MASK (0xC000U) 11450 #define DMA_TCD_TCD27_CSR_BWC_SHIFT (14U) 11451 #define DMA_TCD_TCD27_CSR_BWC_WIDTH (2U) 11452 #define DMA_TCD_TCD27_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_CSR_BWC_SHIFT)) & DMA_TCD_TCD27_CSR_BWC_MASK) 11453 /*! @} */ 11454 11455 /*! @name TCD27_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 11456 /*! @{ */ 11457 11458 #define DMA_TCD_TCD27_BITER_ELINKNO_BITER_MASK (0x7FFFU) 11459 #define DMA_TCD_TCD27_BITER_ELINKNO_BITER_SHIFT (0U) 11460 #define DMA_TCD_TCD27_BITER_ELINKNO_BITER_WIDTH (15U) 11461 #define DMA_TCD_TCD27_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD27_BITER_ELINKNO_BITER_MASK) 11462 11463 #define DMA_TCD_TCD27_BITER_ELINKNO_ELINK_MASK (0x8000U) 11464 #define DMA_TCD_TCD27_BITER_ELINKNO_ELINK_SHIFT (15U) 11465 #define DMA_TCD_TCD27_BITER_ELINKNO_ELINK_WIDTH (1U) 11466 #define DMA_TCD_TCD27_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD27_BITER_ELINKNO_ELINK_MASK) 11467 /*! @} */ 11468 11469 /*! @name TCD27_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 11470 /*! @{ */ 11471 11472 #define DMA_TCD_TCD27_BITER_ELINKYES_BITER_MASK (0x1FFU) 11473 #define DMA_TCD_TCD27_BITER_ELINKYES_BITER_SHIFT (0U) 11474 #define DMA_TCD_TCD27_BITER_ELINKYES_BITER_WIDTH (9U) 11475 #define DMA_TCD_TCD27_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD27_BITER_ELINKYES_BITER_MASK) 11476 11477 #define DMA_TCD_TCD27_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 11478 #define DMA_TCD_TCD27_BITER_ELINKYES_LINKCH_SHIFT (9U) 11479 #define DMA_TCD_TCD27_BITER_ELINKYES_LINKCH_WIDTH (5U) 11480 #define DMA_TCD_TCD27_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD27_BITER_ELINKYES_LINKCH_MASK) 11481 11482 #define DMA_TCD_TCD27_BITER_ELINKYES_ELINK_MASK (0x8000U) 11483 #define DMA_TCD_TCD27_BITER_ELINKYES_ELINK_SHIFT (15U) 11484 #define DMA_TCD_TCD27_BITER_ELINKYES_ELINK_WIDTH (1U) 11485 #define DMA_TCD_TCD27_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD27_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD27_BITER_ELINKYES_ELINK_MASK) 11486 /*! @} */ 11487 11488 /*! @name CH28_CSR - Channel Control and Status */ 11489 /*! @{ */ 11490 11491 #define DMA_TCD_CH28_CSR_ERQ_MASK (0x1U) 11492 #define DMA_TCD_CH28_CSR_ERQ_SHIFT (0U) 11493 #define DMA_TCD_CH28_CSR_ERQ_WIDTH (1U) 11494 #define DMA_TCD_CH28_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_CSR_ERQ_SHIFT)) & DMA_TCD_CH28_CSR_ERQ_MASK) 11495 11496 #define DMA_TCD_CH28_CSR_EARQ_MASK (0x2U) 11497 #define DMA_TCD_CH28_CSR_EARQ_SHIFT (1U) 11498 #define DMA_TCD_CH28_CSR_EARQ_WIDTH (1U) 11499 #define DMA_TCD_CH28_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_CSR_EARQ_SHIFT)) & DMA_TCD_CH28_CSR_EARQ_MASK) 11500 11501 #define DMA_TCD_CH28_CSR_EEI_MASK (0x4U) 11502 #define DMA_TCD_CH28_CSR_EEI_SHIFT (2U) 11503 #define DMA_TCD_CH28_CSR_EEI_WIDTH (1U) 11504 #define DMA_TCD_CH28_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_CSR_EEI_SHIFT)) & DMA_TCD_CH28_CSR_EEI_MASK) 11505 11506 #define DMA_TCD_CH28_CSR_EBW_MASK (0x8U) 11507 #define DMA_TCD_CH28_CSR_EBW_SHIFT (3U) 11508 #define DMA_TCD_CH28_CSR_EBW_WIDTH (1U) 11509 #define DMA_TCD_CH28_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_CSR_EBW_SHIFT)) & DMA_TCD_CH28_CSR_EBW_MASK) 11510 11511 #define DMA_TCD_CH28_CSR_DONE_MASK (0x40000000U) 11512 #define DMA_TCD_CH28_CSR_DONE_SHIFT (30U) 11513 #define DMA_TCD_CH28_CSR_DONE_WIDTH (1U) 11514 #define DMA_TCD_CH28_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_CSR_DONE_SHIFT)) & DMA_TCD_CH28_CSR_DONE_MASK) 11515 11516 #define DMA_TCD_CH28_CSR_ACTIVE_MASK (0x80000000U) 11517 #define DMA_TCD_CH28_CSR_ACTIVE_SHIFT (31U) 11518 #define DMA_TCD_CH28_CSR_ACTIVE_WIDTH (1U) 11519 #define DMA_TCD_CH28_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH28_CSR_ACTIVE_MASK) 11520 /*! @} */ 11521 11522 /*! @name CH28_ES - Channel Error Status */ 11523 /*! @{ */ 11524 11525 #define DMA_TCD_CH28_ES_DBE_MASK (0x1U) 11526 #define DMA_TCD_CH28_ES_DBE_SHIFT (0U) 11527 #define DMA_TCD_CH28_ES_DBE_WIDTH (1U) 11528 #define DMA_TCD_CH28_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_ES_DBE_SHIFT)) & DMA_TCD_CH28_ES_DBE_MASK) 11529 11530 #define DMA_TCD_CH28_ES_SBE_MASK (0x2U) 11531 #define DMA_TCD_CH28_ES_SBE_SHIFT (1U) 11532 #define DMA_TCD_CH28_ES_SBE_WIDTH (1U) 11533 #define DMA_TCD_CH28_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_ES_SBE_SHIFT)) & DMA_TCD_CH28_ES_SBE_MASK) 11534 11535 #define DMA_TCD_CH28_ES_SGE_MASK (0x4U) 11536 #define DMA_TCD_CH28_ES_SGE_SHIFT (2U) 11537 #define DMA_TCD_CH28_ES_SGE_WIDTH (1U) 11538 #define DMA_TCD_CH28_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_ES_SGE_SHIFT)) & DMA_TCD_CH28_ES_SGE_MASK) 11539 11540 #define DMA_TCD_CH28_ES_NCE_MASK (0x8U) 11541 #define DMA_TCD_CH28_ES_NCE_SHIFT (3U) 11542 #define DMA_TCD_CH28_ES_NCE_WIDTH (1U) 11543 #define DMA_TCD_CH28_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_ES_NCE_SHIFT)) & DMA_TCD_CH28_ES_NCE_MASK) 11544 11545 #define DMA_TCD_CH28_ES_DOE_MASK (0x10U) 11546 #define DMA_TCD_CH28_ES_DOE_SHIFT (4U) 11547 #define DMA_TCD_CH28_ES_DOE_WIDTH (1U) 11548 #define DMA_TCD_CH28_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_ES_DOE_SHIFT)) & DMA_TCD_CH28_ES_DOE_MASK) 11549 11550 #define DMA_TCD_CH28_ES_DAE_MASK (0x20U) 11551 #define DMA_TCD_CH28_ES_DAE_SHIFT (5U) 11552 #define DMA_TCD_CH28_ES_DAE_WIDTH (1U) 11553 #define DMA_TCD_CH28_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_ES_DAE_SHIFT)) & DMA_TCD_CH28_ES_DAE_MASK) 11554 11555 #define DMA_TCD_CH28_ES_SOE_MASK (0x40U) 11556 #define DMA_TCD_CH28_ES_SOE_SHIFT (6U) 11557 #define DMA_TCD_CH28_ES_SOE_WIDTH (1U) 11558 #define DMA_TCD_CH28_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_ES_SOE_SHIFT)) & DMA_TCD_CH28_ES_SOE_MASK) 11559 11560 #define DMA_TCD_CH28_ES_SAE_MASK (0x80U) 11561 #define DMA_TCD_CH28_ES_SAE_SHIFT (7U) 11562 #define DMA_TCD_CH28_ES_SAE_WIDTH (1U) 11563 #define DMA_TCD_CH28_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_ES_SAE_SHIFT)) & DMA_TCD_CH28_ES_SAE_MASK) 11564 11565 #define DMA_TCD_CH28_ES_ERR_MASK (0x80000000U) 11566 #define DMA_TCD_CH28_ES_ERR_SHIFT (31U) 11567 #define DMA_TCD_CH28_ES_ERR_WIDTH (1U) 11568 #define DMA_TCD_CH28_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_ES_ERR_SHIFT)) & DMA_TCD_CH28_ES_ERR_MASK) 11569 /*! @} */ 11570 11571 /*! @name CH28_INT - Channel Interrupt Status */ 11572 /*! @{ */ 11573 11574 #define DMA_TCD_CH28_INT_INT_MASK (0x1U) 11575 #define DMA_TCD_CH28_INT_INT_SHIFT (0U) 11576 #define DMA_TCD_CH28_INT_INT_WIDTH (1U) 11577 #define DMA_TCD_CH28_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_INT_INT_SHIFT)) & DMA_TCD_CH28_INT_INT_MASK) 11578 /*! @} */ 11579 11580 /*! @name CH28_SBR - Channel System Bus */ 11581 /*! @{ */ 11582 11583 #define DMA_TCD_CH28_SBR_MID_MASK (0xFU) 11584 #define DMA_TCD_CH28_SBR_MID_SHIFT (0U) 11585 #define DMA_TCD_CH28_SBR_MID_WIDTH (4U) 11586 #define DMA_TCD_CH28_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_SBR_MID_SHIFT)) & DMA_TCD_CH28_SBR_MID_MASK) 11587 11588 #define DMA_TCD_CH28_SBR_PAL_MASK (0x8000U) 11589 #define DMA_TCD_CH28_SBR_PAL_SHIFT (15U) 11590 #define DMA_TCD_CH28_SBR_PAL_WIDTH (1U) 11591 #define DMA_TCD_CH28_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_SBR_PAL_SHIFT)) & DMA_TCD_CH28_SBR_PAL_MASK) 11592 11593 #define DMA_TCD_CH28_SBR_EMI_MASK (0x10000U) 11594 #define DMA_TCD_CH28_SBR_EMI_SHIFT (16U) 11595 #define DMA_TCD_CH28_SBR_EMI_WIDTH (1U) 11596 #define DMA_TCD_CH28_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_SBR_EMI_SHIFT)) & DMA_TCD_CH28_SBR_EMI_MASK) 11597 11598 #define DMA_TCD_CH28_SBR_ATTR_MASK (0xE0000U) 11599 #define DMA_TCD_CH28_SBR_ATTR_SHIFT (17U) 11600 #define DMA_TCD_CH28_SBR_ATTR_WIDTH (3U) 11601 #define DMA_TCD_CH28_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_SBR_ATTR_SHIFT)) & DMA_TCD_CH28_SBR_ATTR_MASK) 11602 /*! @} */ 11603 11604 /*! @name CH28_PRI - Channel Priority */ 11605 /*! @{ */ 11606 11607 #define DMA_TCD_CH28_PRI_APL_MASK (0x7U) 11608 #define DMA_TCD_CH28_PRI_APL_SHIFT (0U) 11609 #define DMA_TCD_CH28_PRI_APL_WIDTH (3U) 11610 #define DMA_TCD_CH28_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_PRI_APL_SHIFT)) & DMA_TCD_CH28_PRI_APL_MASK) 11611 11612 #define DMA_TCD_CH28_PRI_DPA_MASK (0x40000000U) 11613 #define DMA_TCD_CH28_PRI_DPA_SHIFT (30U) 11614 #define DMA_TCD_CH28_PRI_DPA_WIDTH (1U) 11615 #define DMA_TCD_CH28_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_PRI_DPA_SHIFT)) & DMA_TCD_CH28_PRI_DPA_MASK) 11616 11617 #define DMA_TCD_CH28_PRI_ECP_MASK (0x80000000U) 11618 #define DMA_TCD_CH28_PRI_ECP_SHIFT (31U) 11619 #define DMA_TCD_CH28_PRI_ECP_WIDTH (1U) 11620 #define DMA_TCD_CH28_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH28_PRI_ECP_SHIFT)) & DMA_TCD_CH28_PRI_ECP_MASK) 11621 /*! @} */ 11622 11623 /*! @name TCD28_SADDR - TCD Source Address */ 11624 /*! @{ */ 11625 11626 #define DMA_TCD_TCD28_SADDR_SADDR_MASK (0xFFFFFFFFU) 11627 #define DMA_TCD_TCD28_SADDR_SADDR_SHIFT (0U) 11628 #define DMA_TCD_TCD28_SADDR_SADDR_WIDTH (32U) 11629 #define DMA_TCD_TCD28_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD28_SADDR_SADDR_MASK) 11630 /*! @} */ 11631 11632 /*! @name TCD28_SOFF - TCD Signed Source Address Offset */ 11633 /*! @{ */ 11634 11635 #define DMA_TCD_TCD28_SOFF_SOFF_MASK (0xFFFFU) 11636 #define DMA_TCD_TCD28_SOFF_SOFF_SHIFT (0U) 11637 #define DMA_TCD_TCD28_SOFF_SOFF_WIDTH (16U) 11638 #define DMA_TCD_TCD28_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD28_SOFF_SOFF_MASK) 11639 /*! @} */ 11640 11641 /*! @name TCD28_ATTR - TCD Transfer Attributes */ 11642 /*! @{ */ 11643 11644 #define DMA_TCD_TCD28_ATTR_DSIZE_MASK (0x7U) 11645 #define DMA_TCD_TCD28_ATTR_DSIZE_SHIFT (0U) 11646 #define DMA_TCD_TCD28_ATTR_DSIZE_WIDTH (3U) 11647 #define DMA_TCD_TCD28_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD28_ATTR_DSIZE_MASK) 11648 11649 #define DMA_TCD_TCD28_ATTR_DMOD_MASK (0xF8U) 11650 #define DMA_TCD_TCD28_ATTR_DMOD_SHIFT (3U) 11651 #define DMA_TCD_TCD28_ATTR_DMOD_WIDTH (5U) 11652 #define DMA_TCD_TCD28_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD28_ATTR_DMOD_MASK) 11653 11654 #define DMA_TCD_TCD28_ATTR_SSIZE_MASK (0x700U) 11655 #define DMA_TCD_TCD28_ATTR_SSIZE_SHIFT (8U) 11656 #define DMA_TCD_TCD28_ATTR_SSIZE_WIDTH (3U) 11657 #define DMA_TCD_TCD28_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD28_ATTR_SSIZE_MASK) 11658 11659 #define DMA_TCD_TCD28_ATTR_SMOD_MASK (0xF800U) 11660 #define DMA_TCD_TCD28_ATTR_SMOD_SHIFT (11U) 11661 #define DMA_TCD_TCD28_ATTR_SMOD_WIDTH (5U) 11662 #define DMA_TCD_TCD28_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD28_ATTR_SMOD_MASK) 11663 /*! @} */ 11664 11665 /*! @name TCD28_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 11666 /*! @{ */ 11667 11668 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 11669 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 11670 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 11671 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD28_NBYTES_MLOFFNO_NBYTES_MASK) 11672 11673 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 11674 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 11675 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 11676 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD28_NBYTES_MLOFFNO_DMLOE_MASK) 11677 11678 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 11679 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 11680 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 11681 #define DMA_TCD_TCD28_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD28_NBYTES_MLOFFNO_SMLOE_MASK) 11682 /*! @} */ 11683 11684 /*! @name TCD28_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 11685 /*! @{ */ 11686 11687 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 11688 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 11689 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 11690 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD28_NBYTES_MLOFFYES_NBYTES_MASK) 11691 11692 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 11693 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 11694 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 11695 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD28_NBYTES_MLOFFYES_MLOFF_MASK) 11696 11697 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 11698 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 11699 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 11700 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD28_NBYTES_MLOFFYES_DMLOE_MASK) 11701 11702 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 11703 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 11704 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 11705 #define DMA_TCD_TCD28_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD28_NBYTES_MLOFFYES_SMLOE_MASK) 11706 /*! @} */ 11707 11708 /*! @name TCD28_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 11709 /*! @{ */ 11710 11711 #define DMA_TCD_TCD28_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 11712 #define DMA_TCD_TCD28_SLAST_SDA_SLAST_SDA_SHIFT (0U) 11713 #define DMA_TCD_TCD28_SLAST_SDA_SLAST_SDA_WIDTH (32U) 11714 #define DMA_TCD_TCD28_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD28_SLAST_SDA_SLAST_SDA_MASK) 11715 /*! @} */ 11716 11717 /*! @name TCD28_DADDR - TCD Destination Address */ 11718 /*! @{ */ 11719 11720 #define DMA_TCD_TCD28_DADDR_DADDR_MASK (0xFFFFFFFFU) 11721 #define DMA_TCD_TCD28_DADDR_DADDR_SHIFT (0U) 11722 #define DMA_TCD_TCD28_DADDR_DADDR_WIDTH (32U) 11723 #define DMA_TCD_TCD28_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD28_DADDR_DADDR_MASK) 11724 /*! @} */ 11725 11726 /*! @name TCD28_DOFF - TCD Signed Destination Address Offset */ 11727 /*! @{ */ 11728 11729 #define DMA_TCD_TCD28_DOFF_DOFF_MASK (0xFFFFU) 11730 #define DMA_TCD_TCD28_DOFF_DOFF_SHIFT (0U) 11731 #define DMA_TCD_TCD28_DOFF_DOFF_WIDTH (16U) 11732 #define DMA_TCD_TCD28_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD28_DOFF_DOFF_MASK) 11733 /*! @} */ 11734 11735 /*! @name TCD28_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 11736 /*! @{ */ 11737 11738 #define DMA_TCD_TCD28_CITER_ELINKNO_CITER_MASK (0x7FFFU) 11739 #define DMA_TCD_TCD28_CITER_ELINKNO_CITER_SHIFT (0U) 11740 #define DMA_TCD_TCD28_CITER_ELINKNO_CITER_WIDTH (15U) 11741 #define DMA_TCD_TCD28_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD28_CITER_ELINKNO_CITER_MASK) 11742 11743 #define DMA_TCD_TCD28_CITER_ELINKNO_ELINK_MASK (0x8000U) 11744 #define DMA_TCD_TCD28_CITER_ELINKNO_ELINK_SHIFT (15U) 11745 #define DMA_TCD_TCD28_CITER_ELINKNO_ELINK_WIDTH (1U) 11746 #define DMA_TCD_TCD28_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD28_CITER_ELINKNO_ELINK_MASK) 11747 /*! @} */ 11748 11749 /*! @name TCD28_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 11750 /*! @{ */ 11751 11752 #define DMA_TCD_TCD28_CITER_ELINKYES_CITER_MASK (0x1FFU) 11753 #define DMA_TCD_TCD28_CITER_ELINKYES_CITER_SHIFT (0U) 11754 #define DMA_TCD_TCD28_CITER_ELINKYES_CITER_WIDTH (9U) 11755 #define DMA_TCD_TCD28_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD28_CITER_ELINKYES_CITER_MASK) 11756 11757 #define DMA_TCD_TCD28_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 11758 #define DMA_TCD_TCD28_CITER_ELINKYES_LINKCH_SHIFT (9U) 11759 #define DMA_TCD_TCD28_CITER_ELINKYES_LINKCH_WIDTH (5U) 11760 #define DMA_TCD_TCD28_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD28_CITER_ELINKYES_LINKCH_MASK) 11761 11762 #define DMA_TCD_TCD28_CITER_ELINKYES_ELINK_MASK (0x8000U) 11763 #define DMA_TCD_TCD28_CITER_ELINKYES_ELINK_SHIFT (15U) 11764 #define DMA_TCD_TCD28_CITER_ELINKYES_ELINK_WIDTH (1U) 11765 #define DMA_TCD_TCD28_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD28_CITER_ELINKYES_ELINK_MASK) 11766 /*! @} */ 11767 11768 /*! @name TCD28_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 11769 /*! @{ */ 11770 11771 #define DMA_TCD_TCD28_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 11772 #define DMA_TCD_TCD28_DLAST_SGA_DLAST_SGA_SHIFT (0U) 11773 #define DMA_TCD_TCD28_DLAST_SGA_DLAST_SGA_WIDTH (32U) 11774 #define DMA_TCD_TCD28_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD28_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD28_DLAST_SGA_DLAST_SGA_MASK) 11775 /*! @} */ 11776 11777 /*! @name TCD28_CSR - TCD Control and Status */ 11778 /*! @{ */ 11779 11780 #define DMA_TCD_TCD28_CSR_START_MASK (0x1U) 11781 #define DMA_TCD_TCD28_CSR_START_SHIFT (0U) 11782 #define DMA_TCD_TCD28_CSR_START_WIDTH (1U) 11783 #define DMA_TCD_TCD28_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CSR_START_SHIFT)) & DMA_TCD_TCD28_CSR_START_MASK) 11784 11785 #define DMA_TCD_TCD28_CSR_INTMAJOR_MASK (0x2U) 11786 #define DMA_TCD_TCD28_CSR_INTMAJOR_SHIFT (1U) 11787 #define DMA_TCD_TCD28_CSR_INTMAJOR_WIDTH (1U) 11788 #define DMA_TCD_TCD28_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD28_CSR_INTMAJOR_MASK) 11789 11790 #define DMA_TCD_TCD28_CSR_INTHALF_MASK (0x4U) 11791 #define DMA_TCD_TCD28_CSR_INTHALF_SHIFT (2U) 11792 #define DMA_TCD_TCD28_CSR_INTHALF_WIDTH (1U) 11793 #define DMA_TCD_TCD28_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD28_CSR_INTHALF_MASK) 11794 11795 #define DMA_TCD_TCD28_CSR_DREQ_MASK (0x8U) 11796 #define DMA_TCD_TCD28_CSR_DREQ_SHIFT (3U) 11797 #define DMA_TCD_TCD28_CSR_DREQ_WIDTH (1U) 11798 #define DMA_TCD_TCD28_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CSR_DREQ_SHIFT)) & DMA_TCD_TCD28_CSR_DREQ_MASK) 11799 11800 #define DMA_TCD_TCD28_CSR_ESG_MASK (0x10U) 11801 #define DMA_TCD_TCD28_CSR_ESG_SHIFT (4U) 11802 #define DMA_TCD_TCD28_CSR_ESG_WIDTH (1U) 11803 #define DMA_TCD_TCD28_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CSR_ESG_SHIFT)) & DMA_TCD_TCD28_CSR_ESG_MASK) 11804 11805 #define DMA_TCD_TCD28_CSR_MAJORELINK_MASK (0x20U) 11806 #define DMA_TCD_TCD28_CSR_MAJORELINK_SHIFT (5U) 11807 #define DMA_TCD_TCD28_CSR_MAJORELINK_WIDTH (1U) 11808 #define DMA_TCD_TCD28_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD28_CSR_MAJORELINK_MASK) 11809 11810 #define DMA_TCD_TCD28_CSR_EEOP_MASK (0x40U) 11811 #define DMA_TCD_TCD28_CSR_EEOP_SHIFT (6U) 11812 #define DMA_TCD_TCD28_CSR_EEOP_WIDTH (1U) 11813 #define DMA_TCD_TCD28_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CSR_EEOP_SHIFT)) & DMA_TCD_TCD28_CSR_EEOP_MASK) 11814 11815 #define DMA_TCD_TCD28_CSR_ESDA_MASK (0x80U) 11816 #define DMA_TCD_TCD28_CSR_ESDA_SHIFT (7U) 11817 #define DMA_TCD_TCD28_CSR_ESDA_WIDTH (1U) 11818 #define DMA_TCD_TCD28_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CSR_ESDA_SHIFT)) & DMA_TCD_TCD28_CSR_ESDA_MASK) 11819 11820 #define DMA_TCD_TCD28_CSR_MAJORLINKCH_MASK (0x1F00U) 11821 #define DMA_TCD_TCD28_CSR_MAJORLINKCH_SHIFT (8U) 11822 #define DMA_TCD_TCD28_CSR_MAJORLINKCH_WIDTH (5U) 11823 #define DMA_TCD_TCD28_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD28_CSR_MAJORLINKCH_MASK) 11824 11825 #define DMA_TCD_TCD28_CSR_BWC_MASK (0xC000U) 11826 #define DMA_TCD_TCD28_CSR_BWC_SHIFT (14U) 11827 #define DMA_TCD_TCD28_CSR_BWC_WIDTH (2U) 11828 #define DMA_TCD_TCD28_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_CSR_BWC_SHIFT)) & DMA_TCD_TCD28_CSR_BWC_MASK) 11829 /*! @} */ 11830 11831 /*! @name TCD28_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 11832 /*! @{ */ 11833 11834 #define DMA_TCD_TCD28_BITER_ELINKNO_BITER_MASK (0x7FFFU) 11835 #define DMA_TCD_TCD28_BITER_ELINKNO_BITER_SHIFT (0U) 11836 #define DMA_TCD_TCD28_BITER_ELINKNO_BITER_WIDTH (15U) 11837 #define DMA_TCD_TCD28_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD28_BITER_ELINKNO_BITER_MASK) 11838 11839 #define DMA_TCD_TCD28_BITER_ELINKNO_ELINK_MASK (0x8000U) 11840 #define DMA_TCD_TCD28_BITER_ELINKNO_ELINK_SHIFT (15U) 11841 #define DMA_TCD_TCD28_BITER_ELINKNO_ELINK_WIDTH (1U) 11842 #define DMA_TCD_TCD28_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD28_BITER_ELINKNO_ELINK_MASK) 11843 /*! @} */ 11844 11845 /*! @name TCD28_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 11846 /*! @{ */ 11847 11848 #define DMA_TCD_TCD28_BITER_ELINKYES_BITER_MASK (0x1FFU) 11849 #define DMA_TCD_TCD28_BITER_ELINKYES_BITER_SHIFT (0U) 11850 #define DMA_TCD_TCD28_BITER_ELINKYES_BITER_WIDTH (9U) 11851 #define DMA_TCD_TCD28_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD28_BITER_ELINKYES_BITER_MASK) 11852 11853 #define DMA_TCD_TCD28_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 11854 #define DMA_TCD_TCD28_BITER_ELINKYES_LINKCH_SHIFT (9U) 11855 #define DMA_TCD_TCD28_BITER_ELINKYES_LINKCH_WIDTH (5U) 11856 #define DMA_TCD_TCD28_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD28_BITER_ELINKYES_LINKCH_MASK) 11857 11858 #define DMA_TCD_TCD28_BITER_ELINKYES_ELINK_MASK (0x8000U) 11859 #define DMA_TCD_TCD28_BITER_ELINKYES_ELINK_SHIFT (15U) 11860 #define DMA_TCD_TCD28_BITER_ELINKYES_ELINK_WIDTH (1U) 11861 #define DMA_TCD_TCD28_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD28_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD28_BITER_ELINKYES_ELINK_MASK) 11862 /*! @} */ 11863 11864 /*! @name CH29_CSR - Channel Control and Status */ 11865 /*! @{ */ 11866 11867 #define DMA_TCD_CH29_CSR_ERQ_MASK (0x1U) 11868 #define DMA_TCD_CH29_CSR_ERQ_SHIFT (0U) 11869 #define DMA_TCD_CH29_CSR_ERQ_WIDTH (1U) 11870 #define DMA_TCD_CH29_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_CSR_ERQ_SHIFT)) & DMA_TCD_CH29_CSR_ERQ_MASK) 11871 11872 #define DMA_TCD_CH29_CSR_EARQ_MASK (0x2U) 11873 #define DMA_TCD_CH29_CSR_EARQ_SHIFT (1U) 11874 #define DMA_TCD_CH29_CSR_EARQ_WIDTH (1U) 11875 #define DMA_TCD_CH29_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_CSR_EARQ_SHIFT)) & DMA_TCD_CH29_CSR_EARQ_MASK) 11876 11877 #define DMA_TCD_CH29_CSR_EEI_MASK (0x4U) 11878 #define DMA_TCD_CH29_CSR_EEI_SHIFT (2U) 11879 #define DMA_TCD_CH29_CSR_EEI_WIDTH (1U) 11880 #define DMA_TCD_CH29_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_CSR_EEI_SHIFT)) & DMA_TCD_CH29_CSR_EEI_MASK) 11881 11882 #define DMA_TCD_CH29_CSR_EBW_MASK (0x8U) 11883 #define DMA_TCD_CH29_CSR_EBW_SHIFT (3U) 11884 #define DMA_TCD_CH29_CSR_EBW_WIDTH (1U) 11885 #define DMA_TCD_CH29_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_CSR_EBW_SHIFT)) & DMA_TCD_CH29_CSR_EBW_MASK) 11886 11887 #define DMA_TCD_CH29_CSR_DONE_MASK (0x40000000U) 11888 #define DMA_TCD_CH29_CSR_DONE_SHIFT (30U) 11889 #define DMA_TCD_CH29_CSR_DONE_WIDTH (1U) 11890 #define DMA_TCD_CH29_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_CSR_DONE_SHIFT)) & DMA_TCD_CH29_CSR_DONE_MASK) 11891 11892 #define DMA_TCD_CH29_CSR_ACTIVE_MASK (0x80000000U) 11893 #define DMA_TCD_CH29_CSR_ACTIVE_SHIFT (31U) 11894 #define DMA_TCD_CH29_CSR_ACTIVE_WIDTH (1U) 11895 #define DMA_TCD_CH29_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH29_CSR_ACTIVE_MASK) 11896 /*! @} */ 11897 11898 /*! @name CH29_ES - Channel Error Status */ 11899 /*! @{ */ 11900 11901 #define DMA_TCD_CH29_ES_DBE_MASK (0x1U) 11902 #define DMA_TCD_CH29_ES_DBE_SHIFT (0U) 11903 #define DMA_TCD_CH29_ES_DBE_WIDTH (1U) 11904 #define DMA_TCD_CH29_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_ES_DBE_SHIFT)) & DMA_TCD_CH29_ES_DBE_MASK) 11905 11906 #define DMA_TCD_CH29_ES_SBE_MASK (0x2U) 11907 #define DMA_TCD_CH29_ES_SBE_SHIFT (1U) 11908 #define DMA_TCD_CH29_ES_SBE_WIDTH (1U) 11909 #define DMA_TCD_CH29_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_ES_SBE_SHIFT)) & DMA_TCD_CH29_ES_SBE_MASK) 11910 11911 #define DMA_TCD_CH29_ES_SGE_MASK (0x4U) 11912 #define DMA_TCD_CH29_ES_SGE_SHIFT (2U) 11913 #define DMA_TCD_CH29_ES_SGE_WIDTH (1U) 11914 #define DMA_TCD_CH29_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_ES_SGE_SHIFT)) & DMA_TCD_CH29_ES_SGE_MASK) 11915 11916 #define DMA_TCD_CH29_ES_NCE_MASK (0x8U) 11917 #define DMA_TCD_CH29_ES_NCE_SHIFT (3U) 11918 #define DMA_TCD_CH29_ES_NCE_WIDTH (1U) 11919 #define DMA_TCD_CH29_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_ES_NCE_SHIFT)) & DMA_TCD_CH29_ES_NCE_MASK) 11920 11921 #define DMA_TCD_CH29_ES_DOE_MASK (0x10U) 11922 #define DMA_TCD_CH29_ES_DOE_SHIFT (4U) 11923 #define DMA_TCD_CH29_ES_DOE_WIDTH (1U) 11924 #define DMA_TCD_CH29_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_ES_DOE_SHIFT)) & DMA_TCD_CH29_ES_DOE_MASK) 11925 11926 #define DMA_TCD_CH29_ES_DAE_MASK (0x20U) 11927 #define DMA_TCD_CH29_ES_DAE_SHIFT (5U) 11928 #define DMA_TCD_CH29_ES_DAE_WIDTH (1U) 11929 #define DMA_TCD_CH29_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_ES_DAE_SHIFT)) & DMA_TCD_CH29_ES_DAE_MASK) 11930 11931 #define DMA_TCD_CH29_ES_SOE_MASK (0x40U) 11932 #define DMA_TCD_CH29_ES_SOE_SHIFT (6U) 11933 #define DMA_TCD_CH29_ES_SOE_WIDTH (1U) 11934 #define DMA_TCD_CH29_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_ES_SOE_SHIFT)) & DMA_TCD_CH29_ES_SOE_MASK) 11935 11936 #define DMA_TCD_CH29_ES_SAE_MASK (0x80U) 11937 #define DMA_TCD_CH29_ES_SAE_SHIFT (7U) 11938 #define DMA_TCD_CH29_ES_SAE_WIDTH (1U) 11939 #define DMA_TCD_CH29_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_ES_SAE_SHIFT)) & DMA_TCD_CH29_ES_SAE_MASK) 11940 11941 #define DMA_TCD_CH29_ES_ERR_MASK (0x80000000U) 11942 #define DMA_TCD_CH29_ES_ERR_SHIFT (31U) 11943 #define DMA_TCD_CH29_ES_ERR_WIDTH (1U) 11944 #define DMA_TCD_CH29_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_ES_ERR_SHIFT)) & DMA_TCD_CH29_ES_ERR_MASK) 11945 /*! @} */ 11946 11947 /*! @name CH29_INT - Channel Interrupt Status */ 11948 /*! @{ */ 11949 11950 #define DMA_TCD_CH29_INT_INT_MASK (0x1U) 11951 #define DMA_TCD_CH29_INT_INT_SHIFT (0U) 11952 #define DMA_TCD_CH29_INT_INT_WIDTH (1U) 11953 #define DMA_TCD_CH29_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_INT_INT_SHIFT)) & DMA_TCD_CH29_INT_INT_MASK) 11954 /*! @} */ 11955 11956 /*! @name CH29_SBR - Channel System Bus */ 11957 /*! @{ */ 11958 11959 #define DMA_TCD_CH29_SBR_MID_MASK (0xFU) 11960 #define DMA_TCD_CH29_SBR_MID_SHIFT (0U) 11961 #define DMA_TCD_CH29_SBR_MID_WIDTH (4U) 11962 #define DMA_TCD_CH29_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_SBR_MID_SHIFT)) & DMA_TCD_CH29_SBR_MID_MASK) 11963 11964 #define DMA_TCD_CH29_SBR_PAL_MASK (0x8000U) 11965 #define DMA_TCD_CH29_SBR_PAL_SHIFT (15U) 11966 #define DMA_TCD_CH29_SBR_PAL_WIDTH (1U) 11967 #define DMA_TCD_CH29_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_SBR_PAL_SHIFT)) & DMA_TCD_CH29_SBR_PAL_MASK) 11968 11969 #define DMA_TCD_CH29_SBR_EMI_MASK (0x10000U) 11970 #define DMA_TCD_CH29_SBR_EMI_SHIFT (16U) 11971 #define DMA_TCD_CH29_SBR_EMI_WIDTH (1U) 11972 #define DMA_TCD_CH29_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_SBR_EMI_SHIFT)) & DMA_TCD_CH29_SBR_EMI_MASK) 11973 11974 #define DMA_TCD_CH29_SBR_ATTR_MASK (0xE0000U) 11975 #define DMA_TCD_CH29_SBR_ATTR_SHIFT (17U) 11976 #define DMA_TCD_CH29_SBR_ATTR_WIDTH (3U) 11977 #define DMA_TCD_CH29_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_SBR_ATTR_SHIFT)) & DMA_TCD_CH29_SBR_ATTR_MASK) 11978 /*! @} */ 11979 11980 /*! @name CH29_PRI - Channel Priority */ 11981 /*! @{ */ 11982 11983 #define DMA_TCD_CH29_PRI_APL_MASK (0x7U) 11984 #define DMA_TCD_CH29_PRI_APL_SHIFT (0U) 11985 #define DMA_TCD_CH29_PRI_APL_WIDTH (3U) 11986 #define DMA_TCD_CH29_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_PRI_APL_SHIFT)) & DMA_TCD_CH29_PRI_APL_MASK) 11987 11988 #define DMA_TCD_CH29_PRI_DPA_MASK (0x40000000U) 11989 #define DMA_TCD_CH29_PRI_DPA_SHIFT (30U) 11990 #define DMA_TCD_CH29_PRI_DPA_WIDTH (1U) 11991 #define DMA_TCD_CH29_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_PRI_DPA_SHIFT)) & DMA_TCD_CH29_PRI_DPA_MASK) 11992 11993 #define DMA_TCD_CH29_PRI_ECP_MASK (0x80000000U) 11994 #define DMA_TCD_CH29_PRI_ECP_SHIFT (31U) 11995 #define DMA_TCD_CH29_PRI_ECP_WIDTH (1U) 11996 #define DMA_TCD_CH29_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH29_PRI_ECP_SHIFT)) & DMA_TCD_CH29_PRI_ECP_MASK) 11997 /*! @} */ 11998 11999 /*! @name TCD29_SADDR - TCD Source Address */ 12000 /*! @{ */ 12001 12002 #define DMA_TCD_TCD29_SADDR_SADDR_MASK (0xFFFFFFFFU) 12003 #define DMA_TCD_TCD29_SADDR_SADDR_SHIFT (0U) 12004 #define DMA_TCD_TCD29_SADDR_SADDR_WIDTH (32U) 12005 #define DMA_TCD_TCD29_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD29_SADDR_SADDR_MASK) 12006 /*! @} */ 12007 12008 /*! @name TCD29_SOFF - TCD Signed Source Address Offset */ 12009 /*! @{ */ 12010 12011 #define DMA_TCD_TCD29_SOFF_SOFF_MASK (0xFFFFU) 12012 #define DMA_TCD_TCD29_SOFF_SOFF_SHIFT (0U) 12013 #define DMA_TCD_TCD29_SOFF_SOFF_WIDTH (16U) 12014 #define DMA_TCD_TCD29_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD29_SOFF_SOFF_MASK) 12015 /*! @} */ 12016 12017 /*! @name TCD29_ATTR - TCD Transfer Attributes */ 12018 /*! @{ */ 12019 12020 #define DMA_TCD_TCD29_ATTR_DSIZE_MASK (0x7U) 12021 #define DMA_TCD_TCD29_ATTR_DSIZE_SHIFT (0U) 12022 #define DMA_TCD_TCD29_ATTR_DSIZE_WIDTH (3U) 12023 #define DMA_TCD_TCD29_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD29_ATTR_DSIZE_MASK) 12024 12025 #define DMA_TCD_TCD29_ATTR_DMOD_MASK (0xF8U) 12026 #define DMA_TCD_TCD29_ATTR_DMOD_SHIFT (3U) 12027 #define DMA_TCD_TCD29_ATTR_DMOD_WIDTH (5U) 12028 #define DMA_TCD_TCD29_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD29_ATTR_DMOD_MASK) 12029 12030 #define DMA_TCD_TCD29_ATTR_SSIZE_MASK (0x700U) 12031 #define DMA_TCD_TCD29_ATTR_SSIZE_SHIFT (8U) 12032 #define DMA_TCD_TCD29_ATTR_SSIZE_WIDTH (3U) 12033 #define DMA_TCD_TCD29_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD29_ATTR_SSIZE_MASK) 12034 12035 #define DMA_TCD_TCD29_ATTR_SMOD_MASK (0xF800U) 12036 #define DMA_TCD_TCD29_ATTR_SMOD_SHIFT (11U) 12037 #define DMA_TCD_TCD29_ATTR_SMOD_WIDTH (5U) 12038 #define DMA_TCD_TCD29_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD29_ATTR_SMOD_MASK) 12039 /*! @} */ 12040 12041 /*! @name TCD29_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 12042 /*! @{ */ 12043 12044 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 12045 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 12046 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 12047 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD29_NBYTES_MLOFFNO_NBYTES_MASK) 12048 12049 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 12050 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 12051 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 12052 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD29_NBYTES_MLOFFNO_DMLOE_MASK) 12053 12054 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 12055 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 12056 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 12057 #define DMA_TCD_TCD29_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD29_NBYTES_MLOFFNO_SMLOE_MASK) 12058 /*! @} */ 12059 12060 /*! @name TCD29_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 12061 /*! @{ */ 12062 12063 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 12064 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 12065 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 12066 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD29_NBYTES_MLOFFYES_NBYTES_MASK) 12067 12068 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 12069 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 12070 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 12071 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD29_NBYTES_MLOFFYES_MLOFF_MASK) 12072 12073 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 12074 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 12075 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 12076 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD29_NBYTES_MLOFFYES_DMLOE_MASK) 12077 12078 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 12079 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 12080 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 12081 #define DMA_TCD_TCD29_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD29_NBYTES_MLOFFYES_SMLOE_MASK) 12082 /*! @} */ 12083 12084 /*! @name TCD29_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 12085 /*! @{ */ 12086 12087 #define DMA_TCD_TCD29_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 12088 #define DMA_TCD_TCD29_SLAST_SDA_SLAST_SDA_SHIFT (0U) 12089 #define DMA_TCD_TCD29_SLAST_SDA_SLAST_SDA_WIDTH (32U) 12090 #define DMA_TCD_TCD29_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD29_SLAST_SDA_SLAST_SDA_MASK) 12091 /*! @} */ 12092 12093 /*! @name TCD29_DADDR - TCD Destination Address */ 12094 /*! @{ */ 12095 12096 #define DMA_TCD_TCD29_DADDR_DADDR_MASK (0xFFFFFFFFU) 12097 #define DMA_TCD_TCD29_DADDR_DADDR_SHIFT (0U) 12098 #define DMA_TCD_TCD29_DADDR_DADDR_WIDTH (32U) 12099 #define DMA_TCD_TCD29_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD29_DADDR_DADDR_MASK) 12100 /*! @} */ 12101 12102 /*! @name TCD29_DOFF - TCD Signed Destination Address Offset */ 12103 /*! @{ */ 12104 12105 #define DMA_TCD_TCD29_DOFF_DOFF_MASK (0xFFFFU) 12106 #define DMA_TCD_TCD29_DOFF_DOFF_SHIFT (0U) 12107 #define DMA_TCD_TCD29_DOFF_DOFF_WIDTH (16U) 12108 #define DMA_TCD_TCD29_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD29_DOFF_DOFF_MASK) 12109 /*! @} */ 12110 12111 /*! @name TCD29_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 12112 /*! @{ */ 12113 12114 #define DMA_TCD_TCD29_CITER_ELINKNO_CITER_MASK (0x7FFFU) 12115 #define DMA_TCD_TCD29_CITER_ELINKNO_CITER_SHIFT (0U) 12116 #define DMA_TCD_TCD29_CITER_ELINKNO_CITER_WIDTH (15U) 12117 #define DMA_TCD_TCD29_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD29_CITER_ELINKNO_CITER_MASK) 12118 12119 #define DMA_TCD_TCD29_CITER_ELINKNO_ELINK_MASK (0x8000U) 12120 #define DMA_TCD_TCD29_CITER_ELINKNO_ELINK_SHIFT (15U) 12121 #define DMA_TCD_TCD29_CITER_ELINKNO_ELINK_WIDTH (1U) 12122 #define DMA_TCD_TCD29_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD29_CITER_ELINKNO_ELINK_MASK) 12123 /*! @} */ 12124 12125 /*! @name TCD29_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 12126 /*! @{ */ 12127 12128 #define DMA_TCD_TCD29_CITER_ELINKYES_CITER_MASK (0x1FFU) 12129 #define DMA_TCD_TCD29_CITER_ELINKYES_CITER_SHIFT (0U) 12130 #define DMA_TCD_TCD29_CITER_ELINKYES_CITER_WIDTH (9U) 12131 #define DMA_TCD_TCD29_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD29_CITER_ELINKYES_CITER_MASK) 12132 12133 #define DMA_TCD_TCD29_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 12134 #define DMA_TCD_TCD29_CITER_ELINKYES_LINKCH_SHIFT (9U) 12135 #define DMA_TCD_TCD29_CITER_ELINKYES_LINKCH_WIDTH (5U) 12136 #define DMA_TCD_TCD29_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD29_CITER_ELINKYES_LINKCH_MASK) 12137 12138 #define DMA_TCD_TCD29_CITER_ELINKYES_ELINK_MASK (0x8000U) 12139 #define DMA_TCD_TCD29_CITER_ELINKYES_ELINK_SHIFT (15U) 12140 #define DMA_TCD_TCD29_CITER_ELINKYES_ELINK_WIDTH (1U) 12141 #define DMA_TCD_TCD29_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD29_CITER_ELINKYES_ELINK_MASK) 12142 /*! @} */ 12143 12144 /*! @name TCD29_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 12145 /*! @{ */ 12146 12147 #define DMA_TCD_TCD29_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 12148 #define DMA_TCD_TCD29_DLAST_SGA_DLAST_SGA_SHIFT (0U) 12149 #define DMA_TCD_TCD29_DLAST_SGA_DLAST_SGA_WIDTH (32U) 12150 #define DMA_TCD_TCD29_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD29_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD29_DLAST_SGA_DLAST_SGA_MASK) 12151 /*! @} */ 12152 12153 /*! @name TCD29_CSR - TCD Control and Status */ 12154 /*! @{ */ 12155 12156 #define DMA_TCD_TCD29_CSR_START_MASK (0x1U) 12157 #define DMA_TCD_TCD29_CSR_START_SHIFT (0U) 12158 #define DMA_TCD_TCD29_CSR_START_WIDTH (1U) 12159 #define DMA_TCD_TCD29_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CSR_START_SHIFT)) & DMA_TCD_TCD29_CSR_START_MASK) 12160 12161 #define DMA_TCD_TCD29_CSR_INTMAJOR_MASK (0x2U) 12162 #define DMA_TCD_TCD29_CSR_INTMAJOR_SHIFT (1U) 12163 #define DMA_TCD_TCD29_CSR_INTMAJOR_WIDTH (1U) 12164 #define DMA_TCD_TCD29_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD29_CSR_INTMAJOR_MASK) 12165 12166 #define DMA_TCD_TCD29_CSR_INTHALF_MASK (0x4U) 12167 #define DMA_TCD_TCD29_CSR_INTHALF_SHIFT (2U) 12168 #define DMA_TCD_TCD29_CSR_INTHALF_WIDTH (1U) 12169 #define DMA_TCD_TCD29_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD29_CSR_INTHALF_MASK) 12170 12171 #define DMA_TCD_TCD29_CSR_DREQ_MASK (0x8U) 12172 #define DMA_TCD_TCD29_CSR_DREQ_SHIFT (3U) 12173 #define DMA_TCD_TCD29_CSR_DREQ_WIDTH (1U) 12174 #define DMA_TCD_TCD29_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CSR_DREQ_SHIFT)) & DMA_TCD_TCD29_CSR_DREQ_MASK) 12175 12176 #define DMA_TCD_TCD29_CSR_ESG_MASK (0x10U) 12177 #define DMA_TCD_TCD29_CSR_ESG_SHIFT (4U) 12178 #define DMA_TCD_TCD29_CSR_ESG_WIDTH (1U) 12179 #define DMA_TCD_TCD29_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CSR_ESG_SHIFT)) & DMA_TCD_TCD29_CSR_ESG_MASK) 12180 12181 #define DMA_TCD_TCD29_CSR_MAJORELINK_MASK (0x20U) 12182 #define DMA_TCD_TCD29_CSR_MAJORELINK_SHIFT (5U) 12183 #define DMA_TCD_TCD29_CSR_MAJORELINK_WIDTH (1U) 12184 #define DMA_TCD_TCD29_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD29_CSR_MAJORELINK_MASK) 12185 12186 #define DMA_TCD_TCD29_CSR_EEOP_MASK (0x40U) 12187 #define DMA_TCD_TCD29_CSR_EEOP_SHIFT (6U) 12188 #define DMA_TCD_TCD29_CSR_EEOP_WIDTH (1U) 12189 #define DMA_TCD_TCD29_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CSR_EEOP_SHIFT)) & DMA_TCD_TCD29_CSR_EEOP_MASK) 12190 12191 #define DMA_TCD_TCD29_CSR_ESDA_MASK (0x80U) 12192 #define DMA_TCD_TCD29_CSR_ESDA_SHIFT (7U) 12193 #define DMA_TCD_TCD29_CSR_ESDA_WIDTH (1U) 12194 #define DMA_TCD_TCD29_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CSR_ESDA_SHIFT)) & DMA_TCD_TCD29_CSR_ESDA_MASK) 12195 12196 #define DMA_TCD_TCD29_CSR_MAJORLINKCH_MASK (0x1F00U) 12197 #define DMA_TCD_TCD29_CSR_MAJORLINKCH_SHIFT (8U) 12198 #define DMA_TCD_TCD29_CSR_MAJORLINKCH_WIDTH (5U) 12199 #define DMA_TCD_TCD29_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD29_CSR_MAJORLINKCH_MASK) 12200 12201 #define DMA_TCD_TCD29_CSR_BWC_MASK (0xC000U) 12202 #define DMA_TCD_TCD29_CSR_BWC_SHIFT (14U) 12203 #define DMA_TCD_TCD29_CSR_BWC_WIDTH (2U) 12204 #define DMA_TCD_TCD29_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_CSR_BWC_SHIFT)) & DMA_TCD_TCD29_CSR_BWC_MASK) 12205 /*! @} */ 12206 12207 /*! @name TCD29_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 12208 /*! @{ */ 12209 12210 #define DMA_TCD_TCD29_BITER_ELINKNO_BITER_MASK (0x7FFFU) 12211 #define DMA_TCD_TCD29_BITER_ELINKNO_BITER_SHIFT (0U) 12212 #define DMA_TCD_TCD29_BITER_ELINKNO_BITER_WIDTH (15U) 12213 #define DMA_TCD_TCD29_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD29_BITER_ELINKNO_BITER_MASK) 12214 12215 #define DMA_TCD_TCD29_BITER_ELINKNO_ELINK_MASK (0x8000U) 12216 #define DMA_TCD_TCD29_BITER_ELINKNO_ELINK_SHIFT (15U) 12217 #define DMA_TCD_TCD29_BITER_ELINKNO_ELINK_WIDTH (1U) 12218 #define DMA_TCD_TCD29_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD29_BITER_ELINKNO_ELINK_MASK) 12219 /*! @} */ 12220 12221 /*! @name TCD29_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 12222 /*! @{ */ 12223 12224 #define DMA_TCD_TCD29_BITER_ELINKYES_BITER_MASK (0x1FFU) 12225 #define DMA_TCD_TCD29_BITER_ELINKYES_BITER_SHIFT (0U) 12226 #define DMA_TCD_TCD29_BITER_ELINKYES_BITER_WIDTH (9U) 12227 #define DMA_TCD_TCD29_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD29_BITER_ELINKYES_BITER_MASK) 12228 12229 #define DMA_TCD_TCD29_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 12230 #define DMA_TCD_TCD29_BITER_ELINKYES_LINKCH_SHIFT (9U) 12231 #define DMA_TCD_TCD29_BITER_ELINKYES_LINKCH_WIDTH (5U) 12232 #define DMA_TCD_TCD29_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD29_BITER_ELINKYES_LINKCH_MASK) 12233 12234 #define DMA_TCD_TCD29_BITER_ELINKYES_ELINK_MASK (0x8000U) 12235 #define DMA_TCD_TCD29_BITER_ELINKYES_ELINK_SHIFT (15U) 12236 #define DMA_TCD_TCD29_BITER_ELINKYES_ELINK_WIDTH (1U) 12237 #define DMA_TCD_TCD29_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD29_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD29_BITER_ELINKYES_ELINK_MASK) 12238 /*! @} */ 12239 12240 /*! @name CH30_CSR - Channel Control and Status */ 12241 /*! @{ */ 12242 12243 #define DMA_TCD_CH30_CSR_ERQ_MASK (0x1U) 12244 #define DMA_TCD_CH30_CSR_ERQ_SHIFT (0U) 12245 #define DMA_TCD_CH30_CSR_ERQ_WIDTH (1U) 12246 #define DMA_TCD_CH30_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_CSR_ERQ_SHIFT)) & DMA_TCD_CH30_CSR_ERQ_MASK) 12247 12248 #define DMA_TCD_CH30_CSR_EARQ_MASK (0x2U) 12249 #define DMA_TCD_CH30_CSR_EARQ_SHIFT (1U) 12250 #define DMA_TCD_CH30_CSR_EARQ_WIDTH (1U) 12251 #define DMA_TCD_CH30_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_CSR_EARQ_SHIFT)) & DMA_TCD_CH30_CSR_EARQ_MASK) 12252 12253 #define DMA_TCD_CH30_CSR_EEI_MASK (0x4U) 12254 #define DMA_TCD_CH30_CSR_EEI_SHIFT (2U) 12255 #define DMA_TCD_CH30_CSR_EEI_WIDTH (1U) 12256 #define DMA_TCD_CH30_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_CSR_EEI_SHIFT)) & DMA_TCD_CH30_CSR_EEI_MASK) 12257 12258 #define DMA_TCD_CH30_CSR_EBW_MASK (0x8U) 12259 #define DMA_TCD_CH30_CSR_EBW_SHIFT (3U) 12260 #define DMA_TCD_CH30_CSR_EBW_WIDTH (1U) 12261 #define DMA_TCD_CH30_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_CSR_EBW_SHIFT)) & DMA_TCD_CH30_CSR_EBW_MASK) 12262 12263 #define DMA_TCD_CH30_CSR_DONE_MASK (0x40000000U) 12264 #define DMA_TCD_CH30_CSR_DONE_SHIFT (30U) 12265 #define DMA_TCD_CH30_CSR_DONE_WIDTH (1U) 12266 #define DMA_TCD_CH30_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_CSR_DONE_SHIFT)) & DMA_TCD_CH30_CSR_DONE_MASK) 12267 12268 #define DMA_TCD_CH30_CSR_ACTIVE_MASK (0x80000000U) 12269 #define DMA_TCD_CH30_CSR_ACTIVE_SHIFT (31U) 12270 #define DMA_TCD_CH30_CSR_ACTIVE_WIDTH (1U) 12271 #define DMA_TCD_CH30_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH30_CSR_ACTIVE_MASK) 12272 /*! @} */ 12273 12274 /*! @name CH30_ES - Channel Error Status */ 12275 /*! @{ */ 12276 12277 #define DMA_TCD_CH30_ES_DBE_MASK (0x1U) 12278 #define DMA_TCD_CH30_ES_DBE_SHIFT (0U) 12279 #define DMA_TCD_CH30_ES_DBE_WIDTH (1U) 12280 #define DMA_TCD_CH30_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_ES_DBE_SHIFT)) & DMA_TCD_CH30_ES_DBE_MASK) 12281 12282 #define DMA_TCD_CH30_ES_SBE_MASK (0x2U) 12283 #define DMA_TCD_CH30_ES_SBE_SHIFT (1U) 12284 #define DMA_TCD_CH30_ES_SBE_WIDTH (1U) 12285 #define DMA_TCD_CH30_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_ES_SBE_SHIFT)) & DMA_TCD_CH30_ES_SBE_MASK) 12286 12287 #define DMA_TCD_CH30_ES_SGE_MASK (0x4U) 12288 #define DMA_TCD_CH30_ES_SGE_SHIFT (2U) 12289 #define DMA_TCD_CH30_ES_SGE_WIDTH (1U) 12290 #define DMA_TCD_CH30_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_ES_SGE_SHIFT)) & DMA_TCD_CH30_ES_SGE_MASK) 12291 12292 #define DMA_TCD_CH30_ES_NCE_MASK (0x8U) 12293 #define DMA_TCD_CH30_ES_NCE_SHIFT (3U) 12294 #define DMA_TCD_CH30_ES_NCE_WIDTH (1U) 12295 #define DMA_TCD_CH30_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_ES_NCE_SHIFT)) & DMA_TCD_CH30_ES_NCE_MASK) 12296 12297 #define DMA_TCD_CH30_ES_DOE_MASK (0x10U) 12298 #define DMA_TCD_CH30_ES_DOE_SHIFT (4U) 12299 #define DMA_TCD_CH30_ES_DOE_WIDTH (1U) 12300 #define DMA_TCD_CH30_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_ES_DOE_SHIFT)) & DMA_TCD_CH30_ES_DOE_MASK) 12301 12302 #define DMA_TCD_CH30_ES_DAE_MASK (0x20U) 12303 #define DMA_TCD_CH30_ES_DAE_SHIFT (5U) 12304 #define DMA_TCD_CH30_ES_DAE_WIDTH (1U) 12305 #define DMA_TCD_CH30_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_ES_DAE_SHIFT)) & DMA_TCD_CH30_ES_DAE_MASK) 12306 12307 #define DMA_TCD_CH30_ES_SOE_MASK (0x40U) 12308 #define DMA_TCD_CH30_ES_SOE_SHIFT (6U) 12309 #define DMA_TCD_CH30_ES_SOE_WIDTH (1U) 12310 #define DMA_TCD_CH30_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_ES_SOE_SHIFT)) & DMA_TCD_CH30_ES_SOE_MASK) 12311 12312 #define DMA_TCD_CH30_ES_SAE_MASK (0x80U) 12313 #define DMA_TCD_CH30_ES_SAE_SHIFT (7U) 12314 #define DMA_TCD_CH30_ES_SAE_WIDTH (1U) 12315 #define DMA_TCD_CH30_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_ES_SAE_SHIFT)) & DMA_TCD_CH30_ES_SAE_MASK) 12316 12317 #define DMA_TCD_CH30_ES_ERR_MASK (0x80000000U) 12318 #define DMA_TCD_CH30_ES_ERR_SHIFT (31U) 12319 #define DMA_TCD_CH30_ES_ERR_WIDTH (1U) 12320 #define DMA_TCD_CH30_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_ES_ERR_SHIFT)) & DMA_TCD_CH30_ES_ERR_MASK) 12321 /*! @} */ 12322 12323 /*! @name CH30_INT - Channel Interrupt Status */ 12324 /*! @{ */ 12325 12326 #define DMA_TCD_CH30_INT_INT_MASK (0x1U) 12327 #define DMA_TCD_CH30_INT_INT_SHIFT (0U) 12328 #define DMA_TCD_CH30_INT_INT_WIDTH (1U) 12329 #define DMA_TCD_CH30_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_INT_INT_SHIFT)) & DMA_TCD_CH30_INT_INT_MASK) 12330 /*! @} */ 12331 12332 /*! @name CH30_SBR - Channel System Bus */ 12333 /*! @{ */ 12334 12335 #define DMA_TCD_CH30_SBR_MID_MASK (0xFU) 12336 #define DMA_TCD_CH30_SBR_MID_SHIFT (0U) 12337 #define DMA_TCD_CH30_SBR_MID_WIDTH (4U) 12338 #define DMA_TCD_CH30_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_SBR_MID_SHIFT)) & DMA_TCD_CH30_SBR_MID_MASK) 12339 12340 #define DMA_TCD_CH30_SBR_PAL_MASK (0x8000U) 12341 #define DMA_TCD_CH30_SBR_PAL_SHIFT (15U) 12342 #define DMA_TCD_CH30_SBR_PAL_WIDTH (1U) 12343 #define DMA_TCD_CH30_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_SBR_PAL_SHIFT)) & DMA_TCD_CH30_SBR_PAL_MASK) 12344 12345 #define DMA_TCD_CH30_SBR_EMI_MASK (0x10000U) 12346 #define DMA_TCD_CH30_SBR_EMI_SHIFT (16U) 12347 #define DMA_TCD_CH30_SBR_EMI_WIDTH (1U) 12348 #define DMA_TCD_CH30_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_SBR_EMI_SHIFT)) & DMA_TCD_CH30_SBR_EMI_MASK) 12349 12350 #define DMA_TCD_CH30_SBR_ATTR_MASK (0xE0000U) 12351 #define DMA_TCD_CH30_SBR_ATTR_SHIFT (17U) 12352 #define DMA_TCD_CH30_SBR_ATTR_WIDTH (3U) 12353 #define DMA_TCD_CH30_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_SBR_ATTR_SHIFT)) & DMA_TCD_CH30_SBR_ATTR_MASK) 12354 /*! @} */ 12355 12356 /*! @name CH30_PRI - Channel Priority */ 12357 /*! @{ */ 12358 12359 #define DMA_TCD_CH30_PRI_APL_MASK (0x7U) 12360 #define DMA_TCD_CH30_PRI_APL_SHIFT (0U) 12361 #define DMA_TCD_CH30_PRI_APL_WIDTH (3U) 12362 #define DMA_TCD_CH30_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_PRI_APL_SHIFT)) & DMA_TCD_CH30_PRI_APL_MASK) 12363 12364 #define DMA_TCD_CH30_PRI_DPA_MASK (0x40000000U) 12365 #define DMA_TCD_CH30_PRI_DPA_SHIFT (30U) 12366 #define DMA_TCD_CH30_PRI_DPA_WIDTH (1U) 12367 #define DMA_TCD_CH30_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_PRI_DPA_SHIFT)) & DMA_TCD_CH30_PRI_DPA_MASK) 12368 12369 #define DMA_TCD_CH30_PRI_ECP_MASK (0x80000000U) 12370 #define DMA_TCD_CH30_PRI_ECP_SHIFT (31U) 12371 #define DMA_TCD_CH30_PRI_ECP_WIDTH (1U) 12372 #define DMA_TCD_CH30_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH30_PRI_ECP_SHIFT)) & DMA_TCD_CH30_PRI_ECP_MASK) 12373 /*! @} */ 12374 12375 /*! @name TCD30_SADDR - TCD Source Address */ 12376 /*! @{ */ 12377 12378 #define DMA_TCD_TCD30_SADDR_SADDR_MASK (0xFFFFFFFFU) 12379 #define DMA_TCD_TCD30_SADDR_SADDR_SHIFT (0U) 12380 #define DMA_TCD_TCD30_SADDR_SADDR_WIDTH (32U) 12381 #define DMA_TCD_TCD30_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD30_SADDR_SADDR_MASK) 12382 /*! @} */ 12383 12384 /*! @name TCD30_SOFF - TCD Signed Source Address Offset */ 12385 /*! @{ */ 12386 12387 #define DMA_TCD_TCD30_SOFF_SOFF_MASK (0xFFFFU) 12388 #define DMA_TCD_TCD30_SOFF_SOFF_SHIFT (0U) 12389 #define DMA_TCD_TCD30_SOFF_SOFF_WIDTH (16U) 12390 #define DMA_TCD_TCD30_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD30_SOFF_SOFF_MASK) 12391 /*! @} */ 12392 12393 /*! @name TCD30_ATTR - TCD Transfer Attributes */ 12394 /*! @{ */ 12395 12396 #define DMA_TCD_TCD30_ATTR_DSIZE_MASK (0x7U) 12397 #define DMA_TCD_TCD30_ATTR_DSIZE_SHIFT (0U) 12398 #define DMA_TCD_TCD30_ATTR_DSIZE_WIDTH (3U) 12399 #define DMA_TCD_TCD30_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD30_ATTR_DSIZE_MASK) 12400 12401 #define DMA_TCD_TCD30_ATTR_DMOD_MASK (0xF8U) 12402 #define DMA_TCD_TCD30_ATTR_DMOD_SHIFT (3U) 12403 #define DMA_TCD_TCD30_ATTR_DMOD_WIDTH (5U) 12404 #define DMA_TCD_TCD30_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD30_ATTR_DMOD_MASK) 12405 12406 #define DMA_TCD_TCD30_ATTR_SSIZE_MASK (0x700U) 12407 #define DMA_TCD_TCD30_ATTR_SSIZE_SHIFT (8U) 12408 #define DMA_TCD_TCD30_ATTR_SSIZE_WIDTH (3U) 12409 #define DMA_TCD_TCD30_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD30_ATTR_SSIZE_MASK) 12410 12411 #define DMA_TCD_TCD30_ATTR_SMOD_MASK (0xF800U) 12412 #define DMA_TCD_TCD30_ATTR_SMOD_SHIFT (11U) 12413 #define DMA_TCD_TCD30_ATTR_SMOD_WIDTH (5U) 12414 #define DMA_TCD_TCD30_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD30_ATTR_SMOD_MASK) 12415 /*! @} */ 12416 12417 /*! @name TCD30_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 12418 /*! @{ */ 12419 12420 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 12421 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 12422 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 12423 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD30_NBYTES_MLOFFNO_NBYTES_MASK) 12424 12425 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 12426 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 12427 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 12428 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD30_NBYTES_MLOFFNO_DMLOE_MASK) 12429 12430 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 12431 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 12432 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 12433 #define DMA_TCD_TCD30_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD30_NBYTES_MLOFFNO_SMLOE_MASK) 12434 /*! @} */ 12435 12436 /*! @name TCD30_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 12437 /*! @{ */ 12438 12439 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 12440 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 12441 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 12442 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD30_NBYTES_MLOFFYES_NBYTES_MASK) 12443 12444 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 12445 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 12446 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 12447 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD30_NBYTES_MLOFFYES_MLOFF_MASK) 12448 12449 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 12450 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 12451 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 12452 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD30_NBYTES_MLOFFYES_DMLOE_MASK) 12453 12454 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 12455 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 12456 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 12457 #define DMA_TCD_TCD30_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD30_NBYTES_MLOFFYES_SMLOE_MASK) 12458 /*! @} */ 12459 12460 /*! @name TCD30_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 12461 /*! @{ */ 12462 12463 #define DMA_TCD_TCD30_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 12464 #define DMA_TCD_TCD30_SLAST_SDA_SLAST_SDA_SHIFT (0U) 12465 #define DMA_TCD_TCD30_SLAST_SDA_SLAST_SDA_WIDTH (32U) 12466 #define DMA_TCD_TCD30_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD30_SLAST_SDA_SLAST_SDA_MASK) 12467 /*! @} */ 12468 12469 /*! @name TCD30_DADDR - TCD Destination Address */ 12470 /*! @{ */ 12471 12472 #define DMA_TCD_TCD30_DADDR_DADDR_MASK (0xFFFFFFFFU) 12473 #define DMA_TCD_TCD30_DADDR_DADDR_SHIFT (0U) 12474 #define DMA_TCD_TCD30_DADDR_DADDR_WIDTH (32U) 12475 #define DMA_TCD_TCD30_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD30_DADDR_DADDR_MASK) 12476 /*! @} */ 12477 12478 /*! @name TCD30_DOFF - TCD Signed Destination Address Offset */ 12479 /*! @{ */ 12480 12481 #define DMA_TCD_TCD30_DOFF_DOFF_MASK (0xFFFFU) 12482 #define DMA_TCD_TCD30_DOFF_DOFF_SHIFT (0U) 12483 #define DMA_TCD_TCD30_DOFF_DOFF_WIDTH (16U) 12484 #define DMA_TCD_TCD30_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD30_DOFF_DOFF_MASK) 12485 /*! @} */ 12486 12487 /*! @name TCD30_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 12488 /*! @{ */ 12489 12490 #define DMA_TCD_TCD30_CITER_ELINKNO_CITER_MASK (0x7FFFU) 12491 #define DMA_TCD_TCD30_CITER_ELINKNO_CITER_SHIFT (0U) 12492 #define DMA_TCD_TCD30_CITER_ELINKNO_CITER_WIDTH (15U) 12493 #define DMA_TCD_TCD30_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD30_CITER_ELINKNO_CITER_MASK) 12494 12495 #define DMA_TCD_TCD30_CITER_ELINKNO_ELINK_MASK (0x8000U) 12496 #define DMA_TCD_TCD30_CITER_ELINKNO_ELINK_SHIFT (15U) 12497 #define DMA_TCD_TCD30_CITER_ELINKNO_ELINK_WIDTH (1U) 12498 #define DMA_TCD_TCD30_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD30_CITER_ELINKNO_ELINK_MASK) 12499 /*! @} */ 12500 12501 /*! @name TCD30_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 12502 /*! @{ */ 12503 12504 #define DMA_TCD_TCD30_CITER_ELINKYES_CITER_MASK (0x1FFU) 12505 #define DMA_TCD_TCD30_CITER_ELINKYES_CITER_SHIFT (0U) 12506 #define DMA_TCD_TCD30_CITER_ELINKYES_CITER_WIDTH (9U) 12507 #define DMA_TCD_TCD30_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD30_CITER_ELINKYES_CITER_MASK) 12508 12509 #define DMA_TCD_TCD30_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 12510 #define DMA_TCD_TCD30_CITER_ELINKYES_LINKCH_SHIFT (9U) 12511 #define DMA_TCD_TCD30_CITER_ELINKYES_LINKCH_WIDTH (5U) 12512 #define DMA_TCD_TCD30_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD30_CITER_ELINKYES_LINKCH_MASK) 12513 12514 #define DMA_TCD_TCD30_CITER_ELINKYES_ELINK_MASK (0x8000U) 12515 #define DMA_TCD_TCD30_CITER_ELINKYES_ELINK_SHIFT (15U) 12516 #define DMA_TCD_TCD30_CITER_ELINKYES_ELINK_WIDTH (1U) 12517 #define DMA_TCD_TCD30_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD30_CITER_ELINKYES_ELINK_MASK) 12518 /*! @} */ 12519 12520 /*! @name TCD30_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 12521 /*! @{ */ 12522 12523 #define DMA_TCD_TCD30_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 12524 #define DMA_TCD_TCD30_DLAST_SGA_DLAST_SGA_SHIFT (0U) 12525 #define DMA_TCD_TCD30_DLAST_SGA_DLAST_SGA_WIDTH (32U) 12526 #define DMA_TCD_TCD30_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD30_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD30_DLAST_SGA_DLAST_SGA_MASK) 12527 /*! @} */ 12528 12529 /*! @name TCD30_CSR - TCD Control and Status */ 12530 /*! @{ */ 12531 12532 #define DMA_TCD_TCD30_CSR_START_MASK (0x1U) 12533 #define DMA_TCD_TCD30_CSR_START_SHIFT (0U) 12534 #define DMA_TCD_TCD30_CSR_START_WIDTH (1U) 12535 #define DMA_TCD_TCD30_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CSR_START_SHIFT)) & DMA_TCD_TCD30_CSR_START_MASK) 12536 12537 #define DMA_TCD_TCD30_CSR_INTMAJOR_MASK (0x2U) 12538 #define DMA_TCD_TCD30_CSR_INTMAJOR_SHIFT (1U) 12539 #define DMA_TCD_TCD30_CSR_INTMAJOR_WIDTH (1U) 12540 #define DMA_TCD_TCD30_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD30_CSR_INTMAJOR_MASK) 12541 12542 #define DMA_TCD_TCD30_CSR_INTHALF_MASK (0x4U) 12543 #define DMA_TCD_TCD30_CSR_INTHALF_SHIFT (2U) 12544 #define DMA_TCD_TCD30_CSR_INTHALF_WIDTH (1U) 12545 #define DMA_TCD_TCD30_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD30_CSR_INTHALF_MASK) 12546 12547 #define DMA_TCD_TCD30_CSR_DREQ_MASK (0x8U) 12548 #define DMA_TCD_TCD30_CSR_DREQ_SHIFT (3U) 12549 #define DMA_TCD_TCD30_CSR_DREQ_WIDTH (1U) 12550 #define DMA_TCD_TCD30_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CSR_DREQ_SHIFT)) & DMA_TCD_TCD30_CSR_DREQ_MASK) 12551 12552 #define DMA_TCD_TCD30_CSR_ESG_MASK (0x10U) 12553 #define DMA_TCD_TCD30_CSR_ESG_SHIFT (4U) 12554 #define DMA_TCD_TCD30_CSR_ESG_WIDTH (1U) 12555 #define DMA_TCD_TCD30_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CSR_ESG_SHIFT)) & DMA_TCD_TCD30_CSR_ESG_MASK) 12556 12557 #define DMA_TCD_TCD30_CSR_MAJORELINK_MASK (0x20U) 12558 #define DMA_TCD_TCD30_CSR_MAJORELINK_SHIFT (5U) 12559 #define DMA_TCD_TCD30_CSR_MAJORELINK_WIDTH (1U) 12560 #define DMA_TCD_TCD30_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD30_CSR_MAJORELINK_MASK) 12561 12562 #define DMA_TCD_TCD30_CSR_EEOP_MASK (0x40U) 12563 #define DMA_TCD_TCD30_CSR_EEOP_SHIFT (6U) 12564 #define DMA_TCD_TCD30_CSR_EEOP_WIDTH (1U) 12565 #define DMA_TCD_TCD30_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CSR_EEOP_SHIFT)) & DMA_TCD_TCD30_CSR_EEOP_MASK) 12566 12567 #define DMA_TCD_TCD30_CSR_ESDA_MASK (0x80U) 12568 #define DMA_TCD_TCD30_CSR_ESDA_SHIFT (7U) 12569 #define DMA_TCD_TCD30_CSR_ESDA_WIDTH (1U) 12570 #define DMA_TCD_TCD30_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CSR_ESDA_SHIFT)) & DMA_TCD_TCD30_CSR_ESDA_MASK) 12571 12572 #define DMA_TCD_TCD30_CSR_MAJORLINKCH_MASK (0x1F00U) 12573 #define DMA_TCD_TCD30_CSR_MAJORLINKCH_SHIFT (8U) 12574 #define DMA_TCD_TCD30_CSR_MAJORLINKCH_WIDTH (5U) 12575 #define DMA_TCD_TCD30_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD30_CSR_MAJORLINKCH_MASK) 12576 12577 #define DMA_TCD_TCD30_CSR_BWC_MASK (0xC000U) 12578 #define DMA_TCD_TCD30_CSR_BWC_SHIFT (14U) 12579 #define DMA_TCD_TCD30_CSR_BWC_WIDTH (2U) 12580 #define DMA_TCD_TCD30_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_CSR_BWC_SHIFT)) & DMA_TCD_TCD30_CSR_BWC_MASK) 12581 /*! @} */ 12582 12583 /*! @name TCD30_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 12584 /*! @{ */ 12585 12586 #define DMA_TCD_TCD30_BITER_ELINKNO_BITER_MASK (0x7FFFU) 12587 #define DMA_TCD_TCD30_BITER_ELINKNO_BITER_SHIFT (0U) 12588 #define DMA_TCD_TCD30_BITER_ELINKNO_BITER_WIDTH (15U) 12589 #define DMA_TCD_TCD30_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD30_BITER_ELINKNO_BITER_MASK) 12590 12591 #define DMA_TCD_TCD30_BITER_ELINKNO_ELINK_MASK (0x8000U) 12592 #define DMA_TCD_TCD30_BITER_ELINKNO_ELINK_SHIFT (15U) 12593 #define DMA_TCD_TCD30_BITER_ELINKNO_ELINK_WIDTH (1U) 12594 #define DMA_TCD_TCD30_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD30_BITER_ELINKNO_ELINK_MASK) 12595 /*! @} */ 12596 12597 /*! @name TCD30_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 12598 /*! @{ */ 12599 12600 #define DMA_TCD_TCD30_BITER_ELINKYES_BITER_MASK (0x1FFU) 12601 #define DMA_TCD_TCD30_BITER_ELINKYES_BITER_SHIFT (0U) 12602 #define DMA_TCD_TCD30_BITER_ELINKYES_BITER_WIDTH (9U) 12603 #define DMA_TCD_TCD30_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD30_BITER_ELINKYES_BITER_MASK) 12604 12605 #define DMA_TCD_TCD30_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 12606 #define DMA_TCD_TCD30_BITER_ELINKYES_LINKCH_SHIFT (9U) 12607 #define DMA_TCD_TCD30_BITER_ELINKYES_LINKCH_WIDTH (5U) 12608 #define DMA_TCD_TCD30_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD30_BITER_ELINKYES_LINKCH_MASK) 12609 12610 #define DMA_TCD_TCD30_BITER_ELINKYES_ELINK_MASK (0x8000U) 12611 #define DMA_TCD_TCD30_BITER_ELINKYES_ELINK_SHIFT (15U) 12612 #define DMA_TCD_TCD30_BITER_ELINKYES_ELINK_WIDTH (1U) 12613 #define DMA_TCD_TCD30_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD30_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD30_BITER_ELINKYES_ELINK_MASK) 12614 /*! @} */ 12615 12616 /*! @name CH31_CSR - Channel Control and Status */ 12617 /*! @{ */ 12618 12619 #define DMA_TCD_CH31_CSR_ERQ_MASK (0x1U) 12620 #define DMA_TCD_CH31_CSR_ERQ_SHIFT (0U) 12621 #define DMA_TCD_CH31_CSR_ERQ_WIDTH (1U) 12622 #define DMA_TCD_CH31_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_CSR_ERQ_SHIFT)) & DMA_TCD_CH31_CSR_ERQ_MASK) 12623 12624 #define DMA_TCD_CH31_CSR_EARQ_MASK (0x2U) 12625 #define DMA_TCD_CH31_CSR_EARQ_SHIFT (1U) 12626 #define DMA_TCD_CH31_CSR_EARQ_WIDTH (1U) 12627 #define DMA_TCD_CH31_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_CSR_EARQ_SHIFT)) & DMA_TCD_CH31_CSR_EARQ_MASK) 12628 12629 #define DMA_TCD_CH31_CSR_EEI_MASK (0x4U) 12630 #define DMA_TCD_CH31_CSR_EEI_SHIFT (2U) 12631 #define DMA_TCD_CH31_CSR_EEI_WIDTH (1U) 12632 #define DMA_TCD_CH31_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_CSR_EEI_SHIFT)) & DMA_TCD_CH31_CSR_EEI_MASK) 12633 12634 #define DMA_TCD_CH31_CSR_EBW_MASK (0x8U) 12635 #define DMA_TCD_CH31_CSR_EBW_SHIFT (3U) 12636 #define DMA_TCD_CH31_CSR_EBW_WIDTH (1U) 12637 #define DMA_TCD_CH31_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_CSR_EBW_SHIFT)) & DMA_TCD_CH31_CSR_EBW_MASK) 12638 12639 #define DMA_TCD_CH31_CSR_DONE_MASK (0x40000000U) 12640 #define DMA_TCD_CH31_CSR_DONE_SHIFT (30U) 12641 #define DMA_TCD_CH31_CSR_DONE_WIDTH (1U) 12642 #define DMA_TCD_CH31_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_CSR_DONE_SHIFT)) & DMA_TCD_CH31_CSR_DONE_MASK) 12643 12644 #define DMA_TCD_CH31_CSR_ACTIVE_MASK (0x80000000U) 12645 #define DMA_TCD_CH31_CSR_ACTIVE_SHIFT (31U) 12646 #define DMA_TCD_CH31_CSR_ACTIVE_WIDTH (1U) 12647 #define DMA_TCD_CH31_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_CSR_ACTIVE_SHIFT)) & DMA_TCD_CH31_CSR_ACTIVE_MASK) 12648 /*! @} */ 12649 12650 /*! @name CH31_ES - Channel Error Status */ 12651 /*! @{ */ 12652 12653 #define DMA_TCD_CH31_ES_DBE_MASK (0x1U) 12654 #define DMA_TCD_CH31_ES_DBE_SHIFT (0U) 12655 #define DMA_TCD_CH31_ES_DBE_WIDTH (1U) 12656 #define DMA_TCD_CH31_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_ES_DBE_SHIFT)) & DMA_TCD_CH31_ES_DBE_MASK) 12657 12658 #define DMA_TCD_CH31_ES_SBE_MASK (0x2U) 12659 #define DMA_TCD_CH31_ES_SBE_SHIFT (1U) 12660 #define DMA_TCD_CH31_ES_SBE_WIDTH (1U) 12661 #define DMA_TCD_CH31_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_ES_SBE_SHIFT)) & DMA_TCD_CH31_ES_SBE_MASK) 12662 12663 #define DMA_TCD_CH31_ES_SGE_MASK (0x4U) 12664 #define DMA_TCD_CH31_ES_SGE_SHIFT (2U) 12665 #define DMA_TCD_CH31_ES_SGE_WIDTH (1U) 12666 #define DMA_TCD_CH31_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_ES_SGE_SHIFT)) & DMA_TCD_CH31_ES_SGE_MASK) 12667 12668 #define DMA_TCD_CH31_ES_NCE_MASK (0x8U) 12669 #define DMA_TCD_CH31_ES_NCE_SHIFT (3U) 12670 #define DMA_TCD_CH31_ES_NCE_WIDTH (1U) 12671 #define DMA_TCD_CH31_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_ES_NCE_SHIFT)) & DMA_TCD_CH31_ES_NCE_MASK) 12672 12673 #define DMA_TCD_CH31_ES_DOE_MASK (0x10U) 12674 #define DMA_TCD_CH31_ES_DOE_SHIFT (4U) 12675 #define DMA_TCD_CH31_ES_DOE_WIDTH (1U) 12676 #define DMA_TCD_CH31_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_ES_DOE_SHIFT)) & DMA_TCD_CH31_ES_DOE_MASK) 12677 12678 #define DMA_TCD_CH31_ES_DAE_MASK (0x20U) 12679 #define DMA_TCD_CH31_ES_DAE_SHIFT (5U) 12680 #define DMA_TCD_CH31_ES_DAE_WIDTH (1U) 12681 #define DMA_TCD_CH31_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_ES_DAE_SHIFT)) & DMA_TCD_CH31_ES_DAE_MASK) 12682 12683 #define DMA_TCD_CH31_ES_SOE_MASK (0x40U) 12684 #define DMA_TCD_CH31_ES_SOE_SHIFT (6U) 12685 #define DMA_TCD_CH31_ES_SOE_WIDTH (1U) 12686 #define DMA_TCD_CH31_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_ES_SOE_SHIFT)) & DMA_TCD_CH31_ES_SOE_MASK) 12687 12688 #define DMA_TCD_CH31_ES_SAE_MASK (0x80U) 12689 #define DMA_TCD_CH31_ES_SAE_SHIFT (7U) 12690 #define DMA_TCD_CH31_ES_SAE_WIDTH (1U) 12691 #define DMA_TCD_CH31_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_ES_SAE_SHIFT)) & DMA_TCD_CH31_ES_SAE_MASK) 12692 12693 #define DMA_TCD_CH31_ES_ERR_MASK (0x80000000U) 12694 #define DMA_TCD_CH31_ES_ERR_SHIFT (31U) 12695 #define DMA_TCD_CH31_ES_ERR_WIDTH (1U) 12696 #define DMA_TCD_CH31_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_ES_ERR_SHIFT)) & DMA_TCD_CH31_ES_ERR_MASK) 12697 /*! @} */ 12698 12699 /*! @name CH31_INT - Channel Interrupt Status */ 12700 /*! @{ */ 12701 12702 #define DMA_TCD_CH31_INT_INT_MASK (0x1U) 12703 #define DMA_TCD_CH31_INT_INT_SHIFT (0U) 12704 #define DMA_TCD_CH31_INT_INT_WIDTH (1U) 12705 #define DMA_TCD_CH31_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_INT_INT_SHIFT)) & DMA_TCD_CH31_INT_INT_MASK) 12706 /*! @} */ 12707 12708 /*! @name CH31_SBR - Channel System Bus */ 12709 /*! @{ */ 12710 12711 #define DMA_TCD_CH31_SBR_MID_MASK (0xFU) 12712 #define DMA_TCD_CH31_SBR_MID_SHIFT (0U) 12713 #define DMA_TCD_CH31_SBR_MID_WIDTH (4U) 12714 #define DMA_TCD_CH31_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_SBR_MID_SHIFT)) & DMA_TCD_CH31_SBR_MID_MASK) 12715 12716 #define DMA_TCD_CH31_SBR_PAL_MASK (0x8000U) 12717 #define DMA_TCD_CH31_SBR_PAL_SHIFT (15U) 12718 #define DMA_TCD_CH31_SBR_PAL_WIDTH (1U) 12719 #define DMA_TCD_CH31_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_SBR_PAL_SHIFT)) & DMA_TCD_CH31_SBR_PAL_MASK) 12720 12721 #define DMA_TCD_CH31_SBR_EMI_MASK (0x10000U) 12722 #define DMA_TCD_CH31_SBR_EMI_SHIFT (16U) 12723 #define DMA_TCD_CH31_SBR_EMI_WIDTH (1U) 12724 #define DMA_TCD_CH31_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_SBR_EMI_SHIFT)) & DMA_TCD_CH31_SBR_EMI_MASK) 12725 12726 #define DMA_TCD_CH31_SBR_ATTR_MASK (0xE0000U) 12727 #define DMA_TCD_CH31_SBR_ATTR_SHIFT (17U) 12728 #define DMA_TCD_CH31_SBR_ATTR_WIDTH (3U) 12729 #define DMA_TCD_CH31_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_SBR_ATTR_SHIFT)) & DMA_TCD_CH31_SBR_ATTR_MASK) 12730 /*! @} */ 12731 12732 /*! @name CH31_PRI - Channel Priority */ 12733 /*! @{ */ 12734 12735 #define DMA_TCD_CH31_PRI_APL_MASK (0x7U) 12736 #define DMA_TCD_CH31_PRI_APL_SHIFT (0U) 12737 #define DMA_TCD_CH31_PRI_APL_WIDTH (3U) 12738 #define DMA_TCD_CH31_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_PRI_APL_SHIFT)) & DMA_TCD_CH31_PRI_APL_MASK) 12739 12740 #define DMA_TCD_CH31_PRI_DPA_MASK (0x40000000U) 12741 #define DMA_TCD_CH31_PRI_DPA_SHIFT (30U) 12742 #define DMA_TCD_CH31_PRI_DPA_WIDTH (1U) 12743 #define DMA_TCD_CH31_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_PRI_DPA_SHIFT)) & DMA_TCD_CH31_PRI_DPA_MASK) 12744 12745 #define DMA_TCD_CH31_PRI_ECP_MASK (0x80000000U) 12746 #define DMA_TCD_CH31_PRI_ECP_SHIFT (31U) 12747 #define DMA_TCD_CH31_PRI_ECP_WIDTH (1U) 12748 #define DMA_TCD_CH31_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_CH31_PRI_ECP_SHIFT)) & DMA_TCD_CH31_PRI_ECP_MASK) 12749 /*! @} */ 12750 12751 /*! @name TCD31_SADDR - TCD Source Address */ 12752 /*! @{ */ 12753 12754 #define DMA_TCD_TCD31_SADDR_SADDR_MASK (0xFFFFFFFFU) 12755 #define DMA_TCD_TCD31_SADDR_SADDR_SHIFT (0U) 12756 #define DMA_TCD_TCD31_SADDR_SADDR_WIDTH (32U) 12757 #define DMA_TCD_TCD31_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_SADDR_SADDR_SHIFT)) & DMA_TCD_TCD31_SADDR_SADDR_MASK) 12758 /*! @} */ 12759 12760 /*! @name TCD31_SOFF - TCD Signed Source Address Offset */ 12761 /*! @{ */ 12762 12763 #define DMA_TCD_TCD31_SOFF_SOFF_MASK (0xFFFFU) 12764 #define DMA_TCD_TCD31_SOFF_SOFF_SHIFT (0U) 12765 #define DMA_TCD_TCD31_SOFF_SOFF_WIDTH (16U) 12766 #define DMA_TCD_TCD31_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_SOFF_SOFF_SHIFT)) & DMA_TCD_TCD31_SOFF_SOFF_MASK) 12767 /*! @} */ 12768 12769 /*! @name TCD31_ATTR - TCD Transfer Attributes */ 12770 /*! @{ */ 12771 12772 #define DMA_TCD_TCD31_ATTR_DSIZE_MASK (0x7U) 12773 #define DMA_TCD_TCD31_ATTR_DSIZE_SHIFT (0U) 12774 #define DMA_TCD_TCD31_ATTR_DSIZE_WIDTH (3U) 12775 #define DMA_TCD_TCD31_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_ATTR_DSIZE_SHIFT)) & DMA_TCD_TCD31_ATTR_DSIZE_MASK) 12776 12777 #define DMA_TCD_TCD31_ATTR_DMOD_MASK (0xF8U) 12778 #define DMA_TCD_TCD31_ATTR_DMOD_SHIFT (3U) 12779 #define DMA_TCD_TCD31_ATTR_DMOD_WIDTH (5U) 12780 #define DMA_TCD_TCD31_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_ATTR_DMOD_SHIFT)) & DMA_TCD_TCD31_ATTR_DMOD_MASK) 12781 12782 #define DMA_TCD_TCD31_ATTR_SSIZE_MASK (0x700U) 12783 #define DMA_TCD_TCD31_ATTR_SSIZE_SHIFT (8U) 12784 #define DMA_TCD_TCD31_ATTR_SSIZE_WIDTH (3U) 12785 #define DMA_TCD_TCD31_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_ATTR_SSIZE_SHIFT)) & DMA_TCD_TCD31_ATTR_SSIZE_MASK) 12786 12787 #define DMA_TCD_TCD31_ATTR_SMOD_MASK (0xF800U) 12788 #define DMA_TCD_TCD31_ATTR_SMOD_SHIFT (11U) 12789 #define DMA_TCD_TCD31_ATTR_SMOD_WIDTH (5U) 12790 #define DMA_TCD_TCD31_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_ATTR_SMOD_SHIFT)) & DMA_TCD_TCD31_ATTR_SMOD_MASK) 12791 /*! @} */ 12792 12793 /*! @name TCD31_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 12794 /*! @{ */ 12795 12796 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 12797 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 12798 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 12799 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_TCD31_NBYTES_MLOFFNO_NBYTES_MASK) 12800 12801 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 12802 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 12803 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 12804 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_TCD31_NBYTES_MLOFFNO_DMLOE_MASK) 12805 12806 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 12807 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 12808 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 12809 #define DMA_TCD_TCD31_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_TCD31_NBYTES_MLOFFNO_SMLOE_MASK) 12810 /*! @} */ 12811 12812 /*! @name TCD31_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 12813 /*! @{ */ 12814 12815 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 12816 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 12817 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 12818 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_TCD31_NBYTES_MLOFFYES_NBYTES_MASK) 12819 12820 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 12821 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 12822 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 12823 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_TCD31_NBYTES_MLOFFYES_MLOFF_MASK) 12824 12825 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 12826 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 12827 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 12828 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_TCD31_NBYTES_MLOFFYES_DMLOE_MASK) 12829 12830 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 12831 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 12832 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 12833 #define DMA_TCD_TCD31_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_TCD31_NBYTES_MLOFFYES_SMLOE_MASK) 12834 /*! @} */ 12835 12836 /*! @name TCD31_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 12837 /*! @{ */ 12838 12839 #define DMA_TCD_TCD31_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 12840 #define DMA_TCD_TCD31_SLAST_SDA_SLAST_SDA_SHIFT (0U) 12841 #define DMA_TCD_TCD31_SLAST_SDA_SLAST_SDA_WIDTH (32U) 12842 #define DMA_TCD_TCD31_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_TCD31_SLAST_SDA_SLAST_SDA_MASK) 12843 /*! @} */ 12844 12845 /*! @name TCD31_DADDR - TCD Destination Address */ 12846 /*! @{ */ 12847 12848 #define DMA_TCD_TCD31_DADDR_DADDR_MASK (0xFFFFFFFFU) 12849 #define DMA_TCD_TCD31_DADDR_DADDR_SHIFT (0U) 12850 #define DMA_TCD_TCD31_DADDR_DADDR_WIDTH (32U) 12851 #define DMA_TCD_TCD31_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_DADDR_DADDR_SHIFT)) & DMA_TCD_TCD31_DADDR_DADDR_MASK) 12852 /*! @} */ 12853 12854 /*! @name TCD31_DOFF - TCD Signed Destination Address Offset */ 12855 /*! @{ */ 12856 12857 #define DMA_TCD_TCD31_DOFF_DOFF_MASK (0xFFFFU) 12858 #define DMA_TCD_TCD31_DOFF_DOFF_SHIFT (0U) 12859 #define DMA_TCD_TCD31_DOFF_DOFF_WIDTH (16U) 12860 #define DMA_TCD_TCD31_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_DOFF_DOFF_SHIFT)) & DMA_TCD_TCD31_DOFF_DOFF_MASK) 12861 /*! @} */ 12862 12863 /*! @name TCD31_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 12864 /*! @{ */ 12865 12866 #define DMA_TCD_TCD31_CITER_ELINKNO_CITER_MASK (0x7FFFU) 12867 #define DMA_TCD_TCD31_CITER_ELINKNO_CITER_SHIFT (0U) 12868 #define DMA_TCD_TCD31_CITER_ELINKNO_CITER_WIDTH (15U) 12869 #define DMA_TCD_TCD31_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_TCD31_CITER_ELINKNO_CITER_MASK) 12870 12871 #define DMA_TCD_TCD31_CITER_ELINKNO_ELINK_MASK (0x8000U) 12872 #define DMA_TCD_TCD31_CITER_ELINKNO_ELINK_SHIFT (15U) 12873 #define DMA_TCD_TCD31_CITER_ELINKNO_ELINK_WIDTH (1U) 12874 #define DMA_TCD_TCD31_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD31_CITER_ELINKNO_ELINK_MASK) 12875 /*! @} */ 12876 12877 /*! @name TCD31_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 12878 /*! @{ */ 12879 12880 #define DMA_TCD_TCD31_CITER_ELINKYES_CITER_MASK (0x1FFU) 12881 #define DMA_TCD_TCD31_CITER_ELINKYES_CITER_SHIFT (0U) 12882 #define DMA_TCD_TCD31_CITER_ELINKYES_CITER_WIDTH (9U) 12883 #define DMA_TCD_TCD31_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_TCD31_CITER_ELINKYES_CITER_MASK) 12884 12885 #define DMA_TCD_TCD31_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 12886 #define DMA_TCD_TCD31_CITER_ELINKYES_LINKCH_SHIFT (9U) 12887 #define DMA_TCD_TCD31_CITER_ELINKYES_LINKCH_WIDTH (5U) 12888 #define DMA_TCD_TCD31_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD31_CITER_ELINKYES_LINKCH_MASK) 12889 12890 #define DMA_TCD_TCD31_CITER_ELINKYES_ELINK_MASK (0x8000U) 12891 #define DMA_TCD_TCD31_CITER_ELINKYES_ELINK_SHIFT (15U) 12892 #define DMA_TCD_TCD31_CITER_ELINKYES_ELINK_WIDTH (1U) 12893 #define DMA_TCD_TCD31_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD31_CITER_ELINKYES_ELINK_MASK) 12894 /*! @} */ 12895 12896 /*! @name TCD31_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 12897 /*! @{ */ 12898 12899 #define DMA_TCD_TCD31_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 12900 #define DMA_TCD_TCD31_DLAST_SGA_DLAST_SGA_SHIFT (0U) 12901 #define DMA_TCD_TCD31_DLAST_SGA_DLAST_SGA_WIDTH (32U) 12902 #define DMA_TCD_TCD31_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_TCD31_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_TCD31_DLAST_SGA_DLAST_SGA_MASK) 12903 /*! @} */ 12904 12905 /*! @name TCD31_CSR - TCD Control and Status */ 12906 /*! @{ */ 12907 12908 #define DMA_TCD_TCD31_CSR_START_MASK (0x1U) 12909 #define DMA_TCD_TCD31_CSR_START_SHIFT (0U) 12910 #define DMA_TCD_TCD31_CSR_START_WIDTH (1U) 12911 #define DMA_TCD_TCD31_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CSR_START_SHIFT)) & DMA_TCD_TCD31_CSR_START_MASK) 12912 12913 #define DMA_TCD_TCD31_CSR_INTMAJOR_MASK (0x2U) 12914 #define DMA_TCD_TCD31_CSR_INTMAJOR_SHIFT (1U) 12915 #define DMA_TCD_TCD31_CSR_INTMAJOR_WIDTH (1U) 12916 #define DMA_TCD_TCD31_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CSR_INTMAJOR_SHIFT)) & DMA_TCD_TCD31_CSR_INTMAJOR_MASK) 12917 12918 #define DMA_TCD_TCD31_CSR_INTHALF_MASK (0x4U) 12919 #define DMA_TCD_TCD31_CSR_INTHALF_SHIFT (2U) 12920 #define DMA_TCD_TCD31_CSR_INTHALF_WIDTH (1U) 12921 #define DMA_TCD_TCD31_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CSR_INTHALF_SHIFT)) & DMA_TCD_TCD31_CSR_INTHALF_MASK) 12922 12923 #define DMA_TCD_TCD31_CSR_DREQ_MASK (0x8U) 12924 #define DMA_TCD_TCD31_CSR_DREQ_SHIFT (3U) 12925 #define DMA_TCD_TCD31_CSR_DREQ_WIDTH (1U) 12926 #define DMA_TCD_TCD31_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CSR_DREQ_SHIFT)) & DMA_TCD_TCD31_CSR_DREQ_MASK) 12927 12928 #define DMA_TCD_TCD31_CSR_ESG_MASK (0x10U) 12929 #define DMA_TCD_TCD31_CSR_ESG_SHIFT (4U) 12930 #define DMA_TCD_TCD31_CSR_ESG_WIDTH (1U) 12931 #define DMA_TCD_TCD31_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CSR_ESG_SHIFT)) & DMA_TCD_TCD31_CSR_ESG_MASK) 12932 12933 #define DMA_TCD_TCD31_CSR_MAJORELINK_MASK (0x20U) 12934 #define DMA_TCD_TCD31_CSR_MAJORELINK_SHIFT (5U) 12935 #define DMA_TCD_TCD31_CSR_MAJORELINK_WIDTH (1U) 12936 #define DMA_TCD_TCD31_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CSR_MAJORELINK_SHIFT)) & DMA_TCD_TCD31_CSR_MAJORELINK_MASK) 12937 12938 #define DMA_TCD_TCD31_CSR_EEOP_MASK (0x40U) 12939 #define DMA_TCD_TCD31_CSR_EEOP_SHIFT (6U) 12940 #define DMA_TCD_TCD31_CSR_EEOP_WIDTH (1U) 12941 #define DMA_TCD_TCD31_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CSR_EEOP_SHIFT)) & DMA_TCD_TCD31_CSR_EEOP_MASK) 12942 12943 #define DMA_TCD_TCD31_CSR_ESDA_MASK (0x80U) 12944 #define DMA_TCD_TCD31_CSR_ESDA_SHIFT (7U) 12945 #define DMA_TCD_TCD31_CSR_ESDA_WIDTH (1U) 12946 #define DMA_TCD_TCD31_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CSR_ESDA_SHIFT)) & DMA_TCD_TCD31_CSR_ESDA_MASK) 12947 12948 #define DMA_TCD_TCD31_CSR_MAJORLINKCH_MASK (0x1F00U) 12949 #define DMA_TCD_TCD31_CSR_MAJORLINKCH_SHIFT (8U) 12950 #define DMA_TCD_TCD31_CSR_MAJORLINKCH_WIDTH (5U) 12951 #define DMA_TCD_TCD31_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_TCD31_CSR_MAJORLINKCH_MASK) 12952 12953 #define DMA_TCD_TCD31_CSR_BWC_MASK (0xC000U) 12954 #define DMA_TCD_TCD31_CSR_BWC_SHIFT (14U) 12955 #define DMA_TCD_TCD31_CSR_BWC_WIDTH (2U) 12956 #define DMA_TCD_TCD31_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_CSR_BWC_SHIFT)) & DMA_TCD_TCD31_CSR_BWC_MASK) 12957 /*! @} */ 12958 12959 /*! @name TCD31_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 12960 /*! @{ */ 12961 12962 #define DMA_TCD_TCD31_BITER_ELINKNO_BITER_MASK (0x7FFFU) 12963 #define DMA_TCD_TCD31_BITER_ELINKNO_BITER_SHIFT (0U) 12964 #define DMA_TCD_TCD31_BITER_ELINKNO_BITER_WIDTH (15U) 12965 #define DMA_TCD_TCD31_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_TCD31_BITER_ELINKNO_BITER_MASK) 12966 12967 #define DMA_TCD_TCD31_BITER_ELINKNO_ELINK_MASK (0x8000U) 12968 #define DMA_TCD_TCD31_BITER_ELINKNO_ELINK_SHIFT (15U) 12969 #define DMA_TCD_TCD31_BITER_ELINKNO_ELINK_WIDTH (1U) 12970 #define DMA_TCD_TCD31_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_TCD31_BITER_ELINKNO_ELINK_MASK) 12971 /*! @} */ 12972 12973 /*! @name TCD31_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 12974 /*! @{ */ 12975 12976 #define DMA_TCD_TCD31_BITER_ELINKYES_BITER_MASK (0x1FFU) 12977 #define DMA_TCD_TCD31_BITER_ELINKYES_BITER_SHIFT (0U) 12978 #define DMA_TCD_TCD31_BITER_ELINKYES_BITER_WIDTH (9U) 12979 #define DMA_TCD_TCD31_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_TCD31_BITER_ELINKYES_BITER_MASK) 12980 12981 #define DMA_TCD_TCD31_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 12982 #define DMA_TCD_TCD31_BITER_ELINKYES_LINKCH_SHIFT (9U) 12983 #define DMA_TCD_TCD31_BITER_ELINKYES_LINKCH_WIDTH (5U) 12984 #define DMA_TCD_TCD31_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_TCD31_BITER_ELINKYES_LINKCH_MASK) 12985 12986 #define DMA_TCD_TCD31_BITER_ELINKYES_ELINK_MASK (0x8000U) 12987 #define DMA_TCD_TCD31_BITER_ELINKYES_ELINK_SHIFT (15U) 12988 #define DMA_TCD_TCD31_BITER_ELINKYES_ELINK_WIDTH (1U) 12989 #define DMA_TCD_TCD31_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_TCD31_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_TCD31_BITER_ELINKYES_ELINK_MASK) 12990 /*! @} */ 12991 12992 /*! 12993 * @} 12994 */ /* end of group DMA_TCD_Register_Masks */ 12995 12996 /*! 12997 * @} 12998 */ /* end of group DMA_TCD_Peripheral_Access_Layer */ 12999 13000 #endif /* #if !defined(S32K344_DMA_TCD_H_) */ 13001
