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Searched refs:CH_MBSTAT (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Platform/src/
DMru_Ip_Irq.c389 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
413 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
440 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
464 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
491 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
515 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
542 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
566 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
593 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
617 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_CANXL_MRU.h80 …__IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x… member
DS32Z2_SMU_MRU.h80 …__IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x… member
DS32Z2_RTU_MRU.h80 …__IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x… member
DS32Z2_CE_MRU.h80 …__IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x… member
/hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip.c187 if ((base->CHXCONFIG[0u].CH_MBSTAT & CANXL_MRU_CH_MBSTAT_MBS0_MASK) != 0U) in Canexcel_GetControllerMRU()
196 base->CHXCONFIG[0u].CH_MBSTAT |= CANXL_MRU_CH_MBSTAT_MBS3_MASK; in Canexcel_GetControllerMRU()
1388 if ((base->CHXCONFIG[0u].CH_MBSTAT & mask) != 0U) in Canexcel_Ip_MruIRQHandler()
1392 base->CHXCONFIG[0u].CH_MBSTAT |= mask; in Canexcel_Ip_MruIRQHandler()
1400 base->CHXCONFIG[0u].CH_MBSTAT = CANEXCEL_IP_CH1_MBSTAT_CLEAR_DEFAULT_VALUE_U32; in Canexcel_Ip_MruIRQHandler()