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Searched refs:CFGR1 (Results 1 – 25 of 136) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/lpspi/
Dfsl_lpspi.h768 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); in LPSPI_SetMasterSlaveMode()
813 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); in LPSPI_IsMaster()
836 uint32_t cfgr1 = base->CFGR1; in LPSPI_FlushFifo()
850 base->CFGR1 = cfgr1; in LPSPI_FlushFifo()
893 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); in LPSPI_SetAllPcsPolarity()
Dfsl_lpspi.c315 …base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOS… in LPSPI_MasterInit()
325 base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; in LPSPI_MasterInit()
420 base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | in LPSPI_SlaveInit()
425 base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; in LPSPI_SlaveInit()
517 cfgr1Value = base->CFGR1 & ~(1UL << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)pcs)); in LPSPI_SetOnePcsPolarity()
520 …base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)pcs… in LPSPI_SetOnePcsPolarity()
886 uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK);
1200 uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK);
1221 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
1365 uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK);
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Dfsl_lpspi_edma.c243 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); in LPSPI_MasterTransferPrepareEDMALite()
973 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); in LPSPI_SlaveTransferEDMA()
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpflexcomm/lpspi/
Dfsl_lpspi.h755 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); in LPSPI_SetMasterSlaveMode()
800 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); in LPSPI_IsMaster()
847 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); in LPSPI_SetAllPcsPolarity()
Dfsl_lpspi.c239 …base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOS… in LPSPI_MasterInit()
347 base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | in LPSPI_SlaveInit()
447 cfgr1Value = base->CFGR1 & ~(1UL << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)pcs)); in LPSPI_SetOnePcsPolarity()
450 …base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)pcs… in LPSPI_SetOnePcsPolarity()
829 uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK);
882 base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK;
951 uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK);
964 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
1209 uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK);
1273 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK);
Dfsl_lpspi_edma.c230 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); in LPSPI_MasterTransferPrepareEDMALite()
827 base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); in LPSPI_SlaveTransferEDMA()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_LPSPI.h81 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
DS32K148_LPSPI.h81 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
DS32K118_LPSPI.h81 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
DS32K144_LPSPI.h81 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
DS32K146_LPSPI.h81 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
DS32K142W_LPSPI.h81 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
DS32K142_LPSPI.h81 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
DS32K144W_LPSPI.h81 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_LPSPI.h85 __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h4902 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h4903 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h4901 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h7890 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h7781 __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h7894 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h7892 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h7466 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h7783 __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h7468 __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ member

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