1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2024 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_CE_L_VFCCU.h
10  * @version 2.3
11  * @date 2024-05-03
12  * @brief Peripheral Access Layer for S32Z2_CE_L_VFCCU
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_CE_L_VFCCU_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_CE_L_VFCCU_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- CE_L_VFCCU Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup CE_L_VFCCU_Peripheral_Access_Layer CE_L_VFCCU Peripheral Access Layer
68  * @{
69  */
70 
71 /** CE_L_VFCCU - Size of Registers Arrays */
72 #define CE_L_VFCCU_SW_RKN_COUNT                   6u
73 
74 /** CE_L_VFCCU - Register Layout Typedef */
75 typedef struct {
76   __IO uint32_t GDFHID_C0;                         /**< Global DID-FHID Map, offset: 0x0 */
77   __IO uint32_t GDFHID_C1;                         /**< Global DID-FHID Map, offset: 0x4 */
78   uint8_t RESERVED_0[24];
79   __IO uint32_t GFLTPO_C0;                         /**< Global Fault Polarity, offset: 0x20 */
80   __IO uint32_t GFLTPO_C1;                         /**< Global Fault Polarity, offset: 0x24 */
81   uint8_t RESERVED_1[56];
82   __IO uint32_t GFLTRC_C0;                         /**< Global Fault Recovery, offset: 0x60 */
83   __IO uint32_t GFLTRC_C1;                         /**< Global Fault Recovery, offset: 0x64 */
84   uint8_t RESERVED_2[56];
85   __IO uint32_t GFLTOVDC0;                         /**< Global Fault Overflow Detection, offset: 0xA0 */
86   __IO uint32_t GFLTOVDC1;                         /**< Global Fault Overflow Detection, offset: 0xA4 */
87   uint8_t RESERVED_3[104];
88   __IO uint32_t GSWFLODC;                          /**< Global Software Fault Overflow Detection Disable, offset: 0x110 */
89   uint8_t RESERVED_4[28];
90   __IO uint32_t GCTRL;                             /**< Global Space Control, offset: 0x130 */
91   __IO uint32_t GINTOVFS;                          /**< Global DID FSM Status, offset: 0x134 */
92   uint8_t RESERVED_5[428];
93   __IO uint32_t GDBGCFG;                           /**< Global Debug, offset: 0x2E4 */
94   __I  uint32_t GDBGSTAT;                          /**< Global Debug Status, offset: 0x2E8 */
95   uint8_t RESERVED_6[15636];
96   struct CE_L_VFCCU_SW_RKN {                       /* offset: 0x4000, array step: 0x20 */
97     __I  uint32_t SWRPTDID;                          /**< Software Fault Reported DID, array offset: 0x4000, array step: 0x20 */
98     __IO uint32_t SWRKSET_0;                         /**< Software Reaction Set, array offset: 0x4004, array step: 0x20 */
99     uint8_t RESERVED_0[4];
100     __IO uint32_t SWRKCLR_0;                         /**< Software Reaction Clear, array offset: 0x400C, array step: 0x20 */
101     uint8_t RESERVED_1[16];
102   } SW_RKN[CE_L_VFCCU_SW_RKN_COUNT];
103   uint8_t RESERVED_7[16192];
104   __IO uint32_t FHCFG0;                            /**< Fault Handler, offset: 0x8000 */
105   __I  uint32_t FHSRVDS0;                          /**< Fault Handler Status, offset: 0x8004 */
106   uint8_t RESERVED_8[8];
107   __IO uint32_t FHFLTENC00;                        /**< Fault Enable, offset: 0x8010 */
108   __IO uint32_t FHFLTENC01;                        /**< Fault Enable, offset: 0x8014 */
109   uint8_t RESERVED_9[56];
110   __IO uint32_t FHFLTS00;                          /**< Fault Status, offset: 0x8050 */
111   __IO uint32_t FHFLTS01;                          /**< Fault Status, offset: 0x8054 */
112   uint8_t RESERVED_10[56];
113   __IO uint32_t FHFLTRKC00;                        /**< Fault Reaction Set Configuration, offset: 0x8090 */
114   __IO uint32_t FHFLTRKC01;                        /**< Fault Reaction Set Configuration, offset: 0x8094 */
115   __IO uint32_t FHFLTRKC02;                        /**< Fault Reaction Set Configuration, offset: 0x8098 */
116   __IO uint32_t FHFLTRKC03;                        /**< Fault Reaction Set Configuration, offset: 0x809C */
117   __IO uint32_t FHFLTRKC04;                        /**< Fault Reaction Set Configuration, offset: 0x80A0 */
118   __IO uint32_t FHFLTRKC05;                        /**< Fault Reaction Set Configuration, offset: 0x80A4 */
119   __IO uint32_t FHFLTRKC06;                        /**< Fault Reaction Set Configuration, offset: 0x80A8 */
120   uint8_t RESERVED_11[228];
121   __IO uint32_t FHIMRKC0_00;                       /**< Immediate Reaction Configuration, offset: 0x8190 */
122   uint8_t RESERVED_12[12];
123   __IO uint32_t FHIMRKC0_10;                       /**< Immediate Reaction Configuration, offset: 0x81A0 */
124   uint8_t RESERVED_13[12];
125   __IO uint32_t FHIMRKC0_20;                       /**< Immediate Reaction Configuration, offset: 0x81B0 */
126   uint8_t RESERVED_14[12];
127   __IO uint32_t FHIMRKC0_30;                       /**< Immediate Reaction Configuration, offset: 0x81C0 */
128   uint8_t RESERVED_15[12];
129   __IO uint32_t FHIMRKC0_40;                       /**< Immediate Reaction Configuration, offset: 0x81D0 */
130   uint8_t RESERVED_16[12];
131   __IO uint32_t FHIMRKC0_50;                       /**< Immediate Reaction Configuration, offset: 0x81E0 */
132 } CE_L_VFCCU_Type, *CE_L_VFCCU_MemMapPtr;
133 
134 /** Number of instances of the CE_L_VFCCU module. */
135 #define CE_L_VFCCU_INSTANCE_COUNT                (1u)
136 
137 /* CE_L_VFCCU - Peripheral instance base addresses */
138 /** Peripheral CE_L_VFCCU base address */
139 #define IP_CE_L_VFCCU_BASE                       (0x44840000u)
140 /** Peripheral CE_L_VFCCU base pointer */
141 #define IP_CE_L_VFCCU                            ((CE_L_VFCCU_Type *)IP_CE_L_VFCCU_BASE)
142 /** Array initializer of CE_L_VFCCU peripheral base addresses */
143 #define IP_CE_L_VFCCU_BASE_ADDRS                 { IP_CE_L_VFCCU_BASE }
144 /** Array initializer of CE_L_VFCCU peripheral base pointers */
145 #define IP_CE_L_VFCCU_BASE_PTRS                  { IP_CE_L_VFCCU }
146 
147 /* ----------------------------------------------------------------------------
148    -- CE_L_VFCCU Register Masks
149    ---------------------------------------------------------------------------- */
150 
151 /*!
152  * @addtogroup CE_L_VFCCU_Register_Masks CE_L_VFCCU Register Masks
153  * @{
154  */
155 
156 /*! @name GDFHID_C0 - Global DID-FHID Map */
157 /*! @{ */
158 
159 #define CE_L_VFCCU_GDFHID_C0_FHDID0_MASK         (0x7U)
160 #define CE_L_VFCCU_GDFHID_C0_FHDID0_SHIFT        (0U)
161 #define CE_L_VFCCU_GDFHID_C0_FHDID0_WIDTH        (3U)
162 #define CE_L_VFCCU_GDFHID_C0_FHDID0(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C0_FHDID0_SHIFT)) & CE_L_VFCCU_GDFHID_C0_FHDID0_MASK)
163 
164 #define CE_L_VFCCU_GDFHID_C0_FHDID1_MASK         (0x70U)
165 #define CE_L_VFCCU_GDFHID_C0_FHDID1_SHIFT        (4U)
166 #define CE_L_VFCCU_GDFHID_C0_FHDID1_WIDTH        (3U)
167 #define CE_L_VFCCU_GDFHID_C0_FHDID1(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C0_FHDID1_SHIFT)) & CE_L_VFCCU_GDFHID_C0_FHDID1_MASK)
168 
169 #define CE_L_VFCCU_GDFHID_C0_FHDID2_MASK         (0x700U)
170 #define CE_L_VFCCU_GDFHID_C0_FHDID2_SHIFT        (8U)
171 #define CE_L_VFCCU_GDFHID_C0_FHDID2_WIDTH        (3U)
172 #define CE_L_VFCCU_GDFHID_C0_FHDID2(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C0_FHDID2_SHIFT)) & CE_L_VFCCU_GDFHID_C0_FHDID2_MASK)
173 
174 #define CE_L_VFCCU_GDFHID_C0_FHDID3_MASK         (0x7000U)
175 #define CE_L_VFCCU_GDFHID_C0_FHDID3_SHIFT        (12U)
176 #define CE_L_VFCCU_GDFHID_C0_FHDID3_WIDTH        (3U)
177 #define CE_L_VFCCU_GDFHID_C0_FHDID3(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C0_FHDID3_SHIFT)) & CE_L_VFCCU_GDFHID_C0_FHDID3_MASK)
178 
179 #define CE_L_VFCCU_GDFHID_C0_FHDID4_MASK         (0x70000U)
180 #define CE_L_VFCCU_GDFHID_C0_FHDID4_SHIFT        (16U)
181 #define CE_L_VFCCU_GDFHID_C0_FHDID4_WIDTH        (3U)
182 #define CE_L_VFCCU_GDFHID_C0_FHDID4(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C0_FHDID4_SHIFT)) & CE_L_VFCCU_GDFHID_C0_FHDID4_MASK)
183 
184 #define CE_L_VFCCU_GDFHID_C0_FHDID5_MASK         (0x700000U)
185 #define CE_L_VFCCU_GDFHID_C0_FHDID5_SHIFT        (20U)
186 #define CE_L_VFCCU_GDFHID_C0_FHDID5_WIDTH        (3U)
187 #define CE_L_VFCCU_GDFHID_C0_FHDID5(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C0_FHDID5_SHIFT)) & CE_L_VFCCU_GDFHID_C0_FHDID5_MASK)
188 
189 #define CE_L_VFCCU_GDFHID_C0_FHDID6_MASK         (0x7000000U)
190 #define CE_L_VFCCU_GDFHID_C0_FHDID6_SHIFT        (24U)
191 #define CE_L_VFCCU_GDFHID_C0_FHDID6_WIDTH        (3U)
192 #define CE_L_VFCCU_GDFHID_C0_FHDID6(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C0_FHDID6_SHIFT)) & CE_L_VFCCU_GDFHID_C0_FHDID6_MASK)
193 
194 #define CE_L_VFCCU_GDFHID_C0_FHDID7_MASK         (0x70000000U)
195 #define CE_L_VFCCU_GDFHID_C0_FHDID7_SHIFT        (28U)
196 #define CE_L_VFCCU_GDFHID_C0_FHDID7_WIDTH        (3U)
197 #define CE_L_VFCCU_GDFHID_C0_FHDID7(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C0_FHDID7_SHIFT)) & CE_L_VFCCU_GDFHID_C0_FHDID7_MASK)
198 /*! @} */
199 
200 /*! @name GDFHID_C1 - Global DID-FHID Map */
201 /*! @{ */
202 
203 #define CE_L_VFCCU_GDFHID_C1_FHDID8_MASK         (0x7U)
204 #define CE_L_VFCCU_GDFHID_C1_FHDID8_SHIFT        (0U)
205 #define CE_L_VFCCU_GDFHID_C1_FHDID8_WIDTH        (3U)
206 #define CE_L_VFCCU_GDFHID_C1_FHDID8(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C1_FHDID8_SHIFT)) & CE_L_VFCCU_GDFHID_C1_FHDID8_MASK)
207 
208 #define CE_L_VFCCU_GDFHID_C1_FHDID9_MASK         (0x70U)
209 #define CE_L_VFCCU_GDFHID_C1_FHDID9_SHIFT        (4U)
210 #define CE_L_VFCCU_GDFHID_C1_FHDID9_WIDTH        (3U)
211 #define CE_L_VFCCU_GDFHID_C1_FHDID9(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C1_FHDID9_SHIFT)) & CE_L_VFCCU_GDFHID_C1_FHDID9_MASK)
212 
213 #define CE_L_VFCCU_GDFHID_C1_FHDID10_MASK        (0x700U)
214 #define CE_L_VFCCU_GDFHID_C1_FHDID10_SHIFT       (8U)
215 #define CE_L_VFCCU_GDFHID_C1_FHDID10_WIDTH       (3U)
216 #define CE_L_VFCCU_GDFHID_C1_FHDID10(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C1_FHDID10_SHIFT)) & CE_L_VFCCU_GDFHID_C1_FHDID10_MASK)
217 
218 #define CE_L_VFCCU_GDFHID_C1_FHDID11_MASK        (0x7000U)
219 #define CE_L_VFCCU_GDFHID_C1_FHDID11_SHIFT       (12U)
220 #define CE_L_VFCCU_GDFHID_C1_FHDID11_WIDTH       (3U)
221 #define CE_L_VFCCU_GDFHID_C1_FHDID11(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C1_FHDID11_SHIFT)) & CE_L_VFCCU_GDFHID_C1_FHDID11_MASK)
222 
223 #define CE_L_VFCCU_GDFHID_C1_FHDID12_MASK        (0x70000U)
224 #define CE_L_VFCCU_GDFHID_C1_FHDID12_SHIFT       (16U)
225 #define CE_L_VFCCU_GDFHID_C1_FHDID12_WIDTH       (3U)
226 #define CE_L_VFCCU_GDFHID_C1_FHDID12(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C1_FHDID12_SHIFT)) & CE_L_VFCCU_GDFHID_C1_FHDID12_MASK)
227 
228 #define CE_L_VFCCU_GDFHID_C1_FHDID13_MASK        (0x700000U)
229 #define CE_L_VFCCU_GDFHID_C1_FHDID13_SHIFT       (20U)
230 #define CE_L_VFCCU_GDFHID_C1_FHDID13_WIDTH       (3U)
231 #define CE_L_VFCCU_GDFHID_C1_FHDID13(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C1_FHDID13_SHIFT)) & CE_L_VFCCU_GDFHID_C1_FHDID13_MASK)
232 
233 #define CE_L_VFCCU_GDFHID_C1_FHDID14_MASK        (0x7000000U)
234 #define CE_L_VFCCU_GDFHID_C1_FHDID14_SHIFT       (24U)
235 #define CE_L_VFCCU_GDFHID_C1_FHDID14_WIDTH       (3U)
236 #define CE_L_VFCCU_GDFHID_C1_FHDID14(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C1_FHDID14_SHIFT)) & CE_L_VFCCU_GDFHID_C1_FHDID14_MASK)
237 
238 #define CE_L_VFCCU_GDFHID_C1_FHDID15_MASK        (0x70000000U)
239 #define CE_L_VFCCU_GDFHID_C1_FHDID15_SHIFT       (28U)
240 #define CE_L_VFCCU_GDFHID_C1_FHDID15_WIDTH       (3U)
241 #define CE_L_VFCCU_GDFHID_C1_FHDID15(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDFHID_C1_FHDID15_SHIFT)) & CE_L_VFCCU_GDFHID_C1_FHDID15_MASK)
242 /*! @} */
243 
244 /*! @name GFLTPO_C0 - Global Fault Polarity */
245 /*! @{ */
246 
247 #define CE_L_VFCCU_GFLTPO_C0_PS0_MASK            (0x1U)
248 #define CE_L_VFCCU_GFLTPO_C0_PS0_SHIFT           (0U)
249 #define CE_L_VFCCU_GFLTPO_C0_PS0_WIDTH           (1U)
250 #define CE_L_VFCCU_GFLTPO_C0_PS0(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS0_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS0_MASK)
251 
252 #define CE_L_VFCCU_GFLTPO_C0_PS1_MASK            (0x2U)
253 #define CE_L_VFCCU_GFLTPO_C0_PS1_SHIFT           (1U)
254 #define CE_L_VFCCU_GFLTPO_C0_PS1_WIDTH           (1U)
255 #define CE_L_VFCCU_GFLTPO_C0_PS1(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS1_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS1_MASK)
256 
257 #define CE_L_VFCCU_GFLTPO_C0_PS2_MASK            (0x4U)
258 #define CE_L_VFCCU_GFLTPO_C0_PS2_SHIFT           (2U)
259 #define CE_L_VFCCU_GFLTPO_C0_PS2_WIDTH           (1U)
260 #define CE_L_VFCCU_GFLTPO_C0_PS2(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS2_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS2_MASK)
261 
262 #define CE_L_VFCCU_GFLTPO_C0_PS3_MASK            (0x8U)
263 #define CE_L_VFCCU_GFLTPO_C0_PS3_SHIFT           (3U)
264 #define CE_L_VFCCU_GFLTPO_C0_PS3_WIDTH           (1U)
265 #define CE_L_VFCCU_GFLTPO_C0_PS3(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS3_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS3_MASK)
266 
267 #define CE_L_VFCCU_GFLTPO_C0_PS4_MASK            (0x10U)
268 #define CE_L_VFCCU_GFLTPO_C0_PS4_SHIFT           (4U)
269 #define CE_L_VFCCU_GFLTPO_C0_PS4_WIDTH           (1U)
270 #define CE_L_VFCCU_GFLTPO_C0_PS4(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS4_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS4_MASK)
271 
272 #define CE_L_VFCCU_GFLTPO_C0_PS5_MASK            (0x20U)
273 #define CE_L_VFCCU_GFLTPO_C0_PS5_SHIFT           (5U)
274 #define CE_L_VFCCU_GFLTPO_C0_PS5_WIDTH           (1U)
275 #define CE_L_VFCCU_GFLTPO_C0_PS5(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS5_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS5_MASK)
276 
277 #define CE_L_VFCCU_GFLTPO_C0_PS6_MASK            (0x40U)
278 #define CE_L_VFCCU_GFLTPO_C0_PS6_SHIFT           (6U)
279 #define CE_L_VFCCU_GFLTPO_C0_PS6_WIDTH           (1U)
280 #define CE_L_VFCCU_GFLTPO_C0_PS6(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS6_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS6_MASK)
281 
282 #define CE_L_VFCCU_GFLTPO_C0_PS7_MASK            (0x80U)
283 #define CE_L_VFCCU_GFLTPO_C0_PS7_SHIFT           (7U)
284 #define CE_L_VFCCU_GFLTPO_C0_PS7_WIDTH           (1U)
285 #define CE_L_VFCCU_GFLTPO_C0_PS7(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS7_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS7_MASK)
286 
287 #define CE_L_VFCCU_GFLTPO_C0_PS8_MASK            (0x100U)
288 #define CE_L_VFCCU_GFLTPO_C0_PS8_SHIFT           (8U)
289 #define CE_L_VFCCU_GFLTPO_C0_PS8_WIDTH           (1U)
290 #define CE_L_VFCCU_GFLTPO_C0_PS8(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS8_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS8_MASK)
291 
292 #define CE_L_VFCCU_GFLTPO_C0_PS9_MASK            (0x200U)
293 #define CE_L_VFCCU_GFLTPO_C0_PS9_SHIFT           (9U)
294 #define CE_L_VFCCU_GFLTPO_C0_PS9_WIDTH           (1U)
295 #define CE_L_VFCCU_GFLTPO_C0_PS9(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS9_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS9_MASK)
296 
297 #define CE_L_VFCCU_GFLTPO_C0_PS10_MASK           (0x400U)
298 #define CE_L_VFCCU_GFLTPO_C0_PS10_SHIFT          (10U)
299 #define CE_L_VFCCU_GFLTPO_C0_PS10_WIDTH          (1U)
300 #define CE_L_VFCCU_GFLTPO_C0_PS10(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS10_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS10_MASK)
301 
302 #define CE_L_VFCCU_GFLTPO_C0_PS11_MASK           (0x800U)
303 #define CE_L_VFCCU_GFLTPO_C0_PS11_SHIFT          (11U)
304 #define CE_L_VFCCU_GFLTPO_C0_PS11_WIDTH          (1U)
305 #define CE_L_VFCCU_GFLTPO_C0_PS11(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS11_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS11_MASK)
306 
307 #define CE_L_VFCCU_GFLTPO_C0_PS12_MASK           (0x1000U)
308 #define CE_L_VFCCU_GFLTPO_C0_PS12_SHIFT          (12U)
309 #define CE_L_VFCCU_GFLTPO_C0_PS12_WIDTH          (1U)
310 #define CE_L_VFCCU_GFLTPO_C0_PS12(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS12_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS12_MASK)
311 
312 #define CE_L_VFCCU_GFLTPO_C0_PS13_MASK           (0x2000U)
313 #define CE_L_VFCCU_GFLTPO_C0_PS13_SHIFT          (13U)
314 #define CE_L_VFCCU_GFLTPO_C0_PS13_WIDTH          (1U)
315 #define CE_L_VFCCU_GFLTPO_C0_PS13(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS13_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS13_MASK)
316 
317 #define CE_L_VFCCU_GFLTPO_C0_PS14_MASK           (0x4000U)
318 #define CE_L_VFCCU_GFLTPO_C0_PS14_SHIFT          (14U)
319 #define CE_L_VFCCU_GFLTPO_C0_PS14_WIDTH          (1U)
320 #define CE_L_VFCCU_GFLTPO_C0_PS14(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS14_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS14_MASK)
321 
322 #define CE_L_VFCCU_GFLTPO_C0_PS15_MASK           (0x8000U)
323 #define CE_L_VFCCU_GFLTPO_C0_PS15_SHIFT          (15U)
324 #define CE_L_VFCCU_GFLTPO_C0_PS15_WIDTH          (1U)
325 #define CE_L_VFCCU_GFLTPO_C0_PS15(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS15_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS15_MASK)
326 
327 #define CE_L_VFCCU_GFLTPO_C0_PS16_MASK           (0x10000U)
328 #define CE_L_VFCCU_GFLTPO_C0_PS16_SHIFT          (16U)
329 #define CE_L_VFCCU_GFLTPO_C0_PS16_WIDTH          (1U)
330 #define CE_L_VFCCU_GFLTPO_C0_PS16(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS16_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS16_MASK)
331 
332 #define CE_L_VFCCU_GFLTPO_C0_PS17_MASK           (0x20000U)
333 #define CE_L_VFCCU_GFLTPO_C0_PS17_SHIFT          (17U)
334 #define CE_L_VFCCU_GFLTPO_C0_PS17_WIDTH          (1U)
335 #define CE_L_VFCCU_GFLTPO_C0_PS17(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS17_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS17_MASK)
336 
337 #define CE_L_VFCCU_GFLTPO_C0_PS18_MASK           (0x40000U)
338 #define CE_L_VFCCU_GFLTPO_C0_PS18_SHIFT          (18U)
339 #define CE_L_VFCCU_GFLTPO_C0_PS18_WIDTH          (1U)
340 #define CE_L_VFCCU_GFLTPO_C0_PS18(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS18_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS18_MASK)
341 
342 #define CE_L_VFCCU_GFLTPO_C0_PS19_MASK           (0x80000U)
343 #define CE_L_VFCCU_GFLTPO_C0_PS19_SHIFT          (19U)
344 #define CE_L_VFCCU_GFLTPO_C0_PS19_WIDTH          (1U)
345 #define CE_L_VFCCU_GFLTPO_C0_PS19(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS19_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS19_MASK)
346 
347 #define CE_L_VFCCU_GFLTPO_C0_PS20_MASK           (0x100000U)
348 #define CE_L_VFCCU_GFLTPO_C0_PS20_SHIFT          (20U)
349 #define CE_L_VFCCU_GFLTPO_C0_PS20_WIDTH          (1U)
350 #define CE_L_VFCCU_GFLTPO_C0_PS20(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS20_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS20_MASK)
351 
352 #define CE_L_VFCCU_GFLTPO_C0_PS21_MASK           (0x200000U)
353 #define CE_L_VFCCU_GFLTPO_C0_PS21_SHIFT          (21U)
354 #define CE_L_VFCCU_GFLTPO_C0_PS21_WIDTH          (1U)
355 #define CE_L_VFCCU_GFLTPO_C0_PS21(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS21_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS21_MASK)
356 
357 #define CE_L_VFCCU_GFLTPO_C0_PS22_MASK           (0x400000U)
358 #define CE_L_VFCCU_GFLTPO_C0_PS22_SHIFT          (22U)
359 #define CE_L_VFCCU_GFLTPO_C0_PS22_WIDTH          (1U)
360 #define CE_L_VFCCU_GFLTPO_C0_PS22(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS22_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS22_MASK)
361 
362 #define CE_L_VFCCU_GFLTPO_C0_PS23_MASK           (0x800000U)
363 #define CE_L_VFCCU_GFLTPO_C0_PS23_SHIFT          (23U)
364 #define CE_L_VFCCU_GFLTPO_C0_PS23_WIDTH          (1U)
365 #define CE_L_VFCCU_GFLTPO_C0_PS23(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS23_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS23_MASK)
366 
367 #define CE_L_VFCCU_GFLTPO_C0_PS24_MASK           (0x1000000U)
368 #define CE_L_VFCCU_GFLTPO_C0_PS24_SHIFT          (24U)
369 #define CE_L_VFCCU_GFLTPO_C0_PS24_WIDTH          (1U)
370 #define CE_L_VFCCU_GFLTPO_C0_PS24(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS24_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS24_MASK)
371 
372 #define CE_L_VFCCU_GFLTPO_C0_PS25_MASK           (0x2000000U)
373 #define CE_L_VFCCU_GFLTPO_C0_PS25_SHIFT          (25U)
374 #define CE_L_VFCCU_GFLTPO_C0_PS25_WIDTH          (1U)
375 #define CE_L_VFCCU_GFLTPO_C0_PS25(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS25_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS25_MASK)
376 
377 #define CE_L_VFCCU_GFLTPO_C0_PS26_MASK           (0x4000000U)
378 #define CE_L_VFCCU_GFLTPO_C0_PS26_SHIFT          (26U)
379 #define CE_L_VFCCU_GFLTPO_C0_PS26_WIDTH          (1U)
380 #define CE_L_VFCCU_GFLTPO_C0_PS26(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS26_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS26_MASK)
381 
382 #define CE_L_VFCCU_GFLTPO_C0_PS27_MASK           (0x8000000U)
383 #define CE_L_VFCCU_GFLTPO_C0_PS27_SHIFT          (27U)
384 #define CE_L_VFCCU_GFLTPO_C0_PS27_WIDTH          (1U)
385 #define CE_L_VFCCU_GFLTPO_C0_PS27(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS27_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS27_MASK)
386 
387 #define CE_L_VFCCU_GFLTPO_C0_PS28_MASK           (0x10000000U)
388 #define CE_L_VFCCU_GFLTPO_C0_PS28_SHIFT          (28U)
389 #define CE_L_VFCCU_GFLTPO_C0_PS28_WIDTH          (1U)
390 #define CE_L_VFCCU_GFLTPO_C0_PS28(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS28_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS28_MASK)
391 
392 #define CE_L_VFCCU_GFLTPO_C0_PS29_MASK           (0x20000000U)
393 #define CE_L_VFCCU_GFLTPO_C0_PS29_SHIFT          (29U)
394 #define CE_L_VFCCU_GFLTPO_C0_PS29_WIDTH          (1U)
395 #define CE_L_VFCCU_GFLTPO_C0_PS29(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS29_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS29_MASK)
396 
397 #define CE_L_VFCCU_GFLTPO_C0_PS30_MASK           (0x40000000U)
398 #define CE_L_VFCCU_GFLTPO_C0_PS30_SHIFT          (30U)
399 #define CE_L_VFCCU_GFLTPO_C0_PS30_WIDTH          (1U)
400 #define CE_L_VFCCU_GFLTPO_C0_PS30(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS30_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS30_MASK)
401 
402 #define CE_L_VFCCU_GFLTPO_C0_PS31_MASK           (0x80000000U)
403 #define CE_L_VFCCU_GFLTPO_C0_PS31_SHIFT          (31U)
404 #define CE_L_VFCCU_GFLTPO_C0_PS31_WIDTH          (1U)
405 #define CE_L_VFCCU_GFLTPO_C0_PS31(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C0_PS31_SHIFT)) & CE_L_VFCCU_GFLTPO_C0_PS31_MASK)
406 /*! @} */
407 
408 /*! @name GFLTPO_C1 - Global Fault Polarity */
409 /*! @{ */
410 
411 #define CE_L_VFCCU_GFLTPO_C1_PS32_MASK           (0x1U)
412 #define CE_L_VFCCU_GFLTPO_C1_PS32_SHIFT          (0U)
413 #define CE_L_VFCCU_GFLTPO_C1_PS32_WIDTH          (1U)
414 #define CE_L_VFCCU_GFLTPO_C1_PS32(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS32_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS32_MASK)
415 
416 #define CE_L_VFCCU_GFLTPO_C1_PS33_MASK           (0x2U)
417 #define CE_L_VFCCU_GFLTPO_C1_PS33_SHIFT          (1U)
418 #define CE_L_VFCCU_GFLTPO_C1_PS33_WIDTH          (1U)
419 #define CE_L_VFCCU_GFLTPO_C1_PS33(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS33_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS33_MASK)
420 
421 #define CE_L_VFCCU_GFLTPO_C1_PS34_MASK           (0x4U)
422 #define CE_L_VFCCU_GFLTPO_C1_PS34_SHIFT          (2U)
423 #define CE_L_VFCCU_GFLTPO_C1_PS34_WIDTH          (1U)
424 #define CE_L_VFCCU_GFLTPO_C1_PS34(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS34_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS34_MASK)
425 
426 #define CE_L_VFCCU_GFLTPO_C1_PS35_MASK           (0x8U)
427 #define CE_L_VFCCU_GFLTPO_C1_PS35_SHIFT          (3U)
428 #define CE_L_VFCCU_GFLTPO_C1_PS35_WIDTH          (1U)
429 #define CE_L_VFCCU_GFLTPO_C1_PS35(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS35_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS35_MASK)
430 
431 #define CE_L_VFCCU_GFLTPO_C1_PS36_MASK           (0x10U)
432 #define CE_L_VFCCU_GFLTPO_C1_PS36_SHIFT          (4U)
433 #define CE_L_VFCCU_GFLTPO_C1_PS36_WIDTH          (1U)
434 #define CE_L_VFCCU_GFLTPO_C1_PS36(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS36_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS36_MASK)
435 
436 #define CE_L_VFCCU_GFLTPO_C1_PS37_MASK           (0x20U)
437 #define CE_L_VFCCU_GFLTPO_C1_PS37_SHIFT          (5U)
438 #define CE_L_VFCCU_GFLTPO_C1_PS37_WIDTH          (1U)
439 #define CE_L_VFCCU_GFLTPO_C1_PS37(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS37_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS37_MASK)
440 
441 #define CE_L_VFCCU_GFLTPO_C1_PS38_MASK           (0x40U)
442 #define CE_L_VFCCU_GFLTPO_C1_PS38_SHIFT          (6U)
443 #define CE_L_VFCCU_GFLTPO_C1_PS38_WIDTH          (1U)
444 #define CE_L_VFCCU_GFLTPO_C1_PS38(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS38_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS38_MASK)
445 
446 #define CE_L_VFCCU_GFLTPO_C1_PS39_MASK           (0x80U)
447 #define CE_L_VFCCU_GFLTPO_C1_PS39_SHIFT          (7U)
448 #define CE_L_VFCCU_GFLTPO_C1_PS39_WIDTH          (1U)
449 #define CE_L_VFCCU_GFLTPO_C1_PS39(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS39_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS39_MASK)
450 
451 #define CE_L_VFCCU_GFLTPO_C1_PS40_MASK           (0x100U)
452 #define CE_L_VFCCU_GFLTPO_C1_PS40_SHIFT          (8U)
453 #define CE_L_VFCCU_GFLTPO_C1_PS40_WIDTH          (1U)
454 #define CE_L_VFCCU_GFLTPO_C1_PS40(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS40_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS40_MASK)
455 
456 #define CE_L_VFCCU_GFLTPO_C1_PS41_MASK           (0x200U)
457 #define CE_L_VFCCU_GFLTPO_C1_PS41_SHIFT          (9U)
458 #define CE_L_VFCCU_GFLTPO_C1_PS41_WIDTH          (1U)
459 #define CE_L_VFCCU_GFLTPO_C1_PS41(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS41_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS41_MASK)
460 
461 #define CE_L_VFCCU_GFLTPO_C1_PS42_MASK           (0x400U)
462 #define CE_L_VFCCU_GFLTPO_C1_PS42_SHIFT          (10U)
463 #define CE_L_VFCCU_GFLTPO_C1_PS42_WIDTH          (1U)
464 #define CE_L_VFCCU_GFLTPO_C1_PS42(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS42_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS42_MASK)
465 
466 #define CE_L_VFCCU_GFLTPO_C1_PS43_MASK           (0x800U)
467 #define CE_L_VFCCU_GFLTPO_C1_PS43_SHIFT          (11U)
468 #define CE_L_VFCCU_GFLTPO_C1_PS43_WIDTH          (1U)
469 #define CE_L_VFCCU_GFLTPO_C1_PS43(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS43_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS43_MASK)
470 
471 #define CE_L_VFCCU_GFLTPO_C1_PS44_MASK           (0x1000U)
472 #define CE_L_VFCCU_GFLTPO_C1_PS44_SHIFT          (12U)
473 #define CE_L_VFCCU_GFLTPO_C1_PS44_WIDTH          (1U)
474 #define CE_L_VFCCU_GFLTPO_C1_PS44(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS44_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS44_MASK)
475 
476 #define CE_L_VFCCU_GFLTPO_C1_PS45_MASK           (0x2000U)
477 #define CE_L_VFCCU_GFLTPO_C1_PS45_SHIFT          (13U)
478 #define CE_L_VFCCU_GFLTPO_C1_PS45_WIDTH          (1U)
479 #define CE_L_VFCCU_GFLTPO_C1_PS45(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS45_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS45_MASK)
480 
481 #define CE_L_VFCCU_GFLTPO_C1_PS46_MASK           (0x4000U)
482 #define CE_L_VFCCU_GFLTPO_C1_PS46_SHIFT          (14U)
483 #define CE_L_VFCCU_GFLTPO_C1_PS46_WIDTH          (1U)
484 #define CE_L_VFCCU_GFLTPO_C1_PS46(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS46_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS46_MASK)
485 
486 #define CE_L_VFCCU_GFLTPO_C1_PS47_MASK           (0x8000U)
487 #define CE_L_VFCCU_GFLTPO_C1_PS47_SHIFT          (15U)
488 #define CE_L_VFCCU_GFLTPO_C1_PS47_WIDTH          (1U)
489 #define CE_L_VFCCU_GFLTPO_C1_PS47(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS47_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS47_MASK)
490 
491 #define CE_L_VFCCU_GFLTPO_C1_PS48_MASK           (0x10000U)
492 #define CE_L_VFCCU_GFLTPO_C1_PS48_SHIFT          (16U)
493 #define CE_L_VFCCU_GFLTPO_C1_PS48_WIDTH          (1U)
494 #define CE_L_VFCCU_GFLTPO_C1_PS48(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS48_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS48_MASK)
495 
496 #define CE_L_VFCCU_GFLTPO_C1_PS49_MASK           (0x20000U)
497 #define CE_L_VFCCU_GFLTPO_C1_PS49_SHIFT          (17U)
498 #define CE_L_VFCCU_GFLTPO_C1_PS49_WIDTH          (1U)
499 #define CE_L_VFCCU_GFLTPO_C1_PS49(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS49_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS49_MASK)
500 
501 #define CE_L_VFCCU_GFLTPO_C1_PS50_MASK           (0x40000U)
502 #define CE_L_VFCCU_GFLTPO_C1_PS50_SHIFT          (18U)
503 #define CE_L_VFCCU_GFLTPO_C1_PS50_WIDTH          (1U)
504 #define CE_L_VFCCU_GFLTPO_C1_PS50(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS50_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS50_MASK)
505 
506 #define CE_L_VFCCU_GFLTPO_C1_PS51_MASK           (0x80000U)
507 #define CE_L_VFCCU_GFLTPO_C1_PS51_SHIFT          (19U)
508 #define CE_L_VFCCU_GFLTPO_C1_PS51_WIDTH          (1U)
509 #define CE_L_VFCCU_GFLTPO_C1_PS51(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS51_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS51_MASK)
510 
511 #define CE_L_VFCCU_GFLTPO_C1_PS52_MASK           (0x100000U)
512 #define CE_L_VFCCU_GFLTPO_C1_PS52_SHIFT          (20U)
513 #define CE_L_VFCCU_GFLTPO_C1_PS52_WIDTH          (1U)
514 #define CE_L_VFCCU_GFLTPO_C1_PS52(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTPO_C1_PS52_SHIFT)) & CE_L_VFCCU_GFLTPO_C1_PS52_MASK)
515 /*! @} */
516 
517 /*! @name GFLTRC_C0 - Global Fault Recovery */
518 /*! @{ */
519 
520 #define CE_L_VFCCU_GFLTRC_C0_RHWSW0_MASK         (0x1U)
521 #define CE_L_VFCCU_GFLTRC_C0_RHWSW0_SHIFT        (0U)
522 #define CE_L_VFCCU_GFLTRC_C0_RHWSW0_WIDTH        (1U)
523 #define CE_L_VFCCU_GFLTRC_C0_RHWSW0(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW0_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW0_MASK)
524 
525 #define CE_L_VFCCU_GFLTRC_C0_RHWSW1_MASK         (0x2U)
526 #define CE_L_VFCCU_GFLTRC_C0_RHWSW1_SHIFT        (1U)
527 #define CE_L_VFCCU_GFLTRC_C0_RHWSW1_WIDTH        (1U)
528 #define CE_L_VFCCU_GFLTRC_C0_RHWSW1(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW1_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW1_MASK)
529 
530 #define CE_L_VFCCU_GFLTRC_C0_RHWSW2_MASK         (0x4U)
531 #define CE_L_VFCCU_GFLTRC_C0_RHWSW2_SHIFT        (2U)
532 #define CE_L_VFCCU_GFLTRC_C0_RHWSW2_WIDTH        (1U)
533 #define CE_L_VFCCU_GFLTRC_C0_RHWSW2(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW2_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW2_MASK)
534 
535 #define CE_L_VFCCU_GFLTRC_C0_RHWSW3_MASK         (0x8U)
536 #define CE_L_VFCCU_GFLTRC_C0_RHWSW3_SHIFT        (3U)
537 #define CE_L_VFCCU_GFLTRC_C0_RHWSW3_WIDTH        (1U)
538 #define CE_L_VFCCU_GFLTRC_C0_RHWSW3(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW3_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW3_MASK)
539 
540 #define CE_L_VFCCU_GFLTRC_C0_RHWSW4_MASK         (0x10U)
541 #define CE_L_VFCCU_GFLTRC_C0_RHWSW4_SHIFT        (4U)
542 #define CE_L_VFCCU_GFLTRC_C0_RHWSW4_WIDTH        (1U)
543 #define CE_L_VFCCU_GFLTRC_C0_RHWSW4(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW4_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW4_MASK)
544 
545 #define CE_L_VFCCU_GFLTRC_C0_RHWSW5_MASK         (0x20U)
546 #define CE_L_VFCCU_GFLTRC_C0_RHWSW5_SHIFT        (5U)
547 #define CE_L_VFCCU_GFLTRC_C0_RHWSW5_WIDTH        (1U)
548 #define CE_L_VFCCU_GFLTRC_C0_RHWSW5(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW5_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW5_MASK)
549 
550 #define CE_L_VFCCU_GFLTRC_C0_RHWSW6_MASK         (0x40U)
551 #define CE_L_VFCCU_GFLTRC_C0_RHWSW6_SHIFT        (6U)
552 #define CE_L_VFCCU_GFLTRC_C0_RHWSW6_WIDTH        (1U)
553 #define CE_L_VFCCU_GFLTRC_C0_RHWSW6(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW6_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW6_MASK)
554 
555 #define CE_L_VFCCU_GFLTRC_C0_RHWSW7_MASK         (0x80U)
556 #define CE_L_VFCCU_GFLTRC_C0_RHWSW7_SHIFT        (7U)
557 #define CE_L_VFCCU_GFLTRC_C0_RHWSW7_WIDTH        (1U)
558 #define CE_L_VFCCU_GFLTRC_C0_RHWSW7(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW7_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW7_MASK)
559 
560 #define CE_L_VFCCU_GFLTRC_C0_RHWSW8_MASK         (0x100U)
561 #define CE_L_VFCCU_GFLTRC_C0_RHWSW8_SHIFT        (8U)
562 #define CE_L_VFCCU_GFLTRC_C0_RHWSW8_WIDTH        (1U)
563 #define CE_L_VFCCU_GFLTRC_C0_RHWSW8(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW8_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW8_MASK)
564 
565 #define CE_L_VFCCU_GFLTRC_C0_RHWSW9_MASK         (0x200U)
566 #define CE_L_VFCCU_GFLTRC_C0_RHWSW9_SHIFT        (9U)
567 #define CE_L_VFCCU_GFLTRC_C0_RHWSW9_WIDTH        (1U)
568 #define CE_L_VFCCU_GFLTRC_C0_RHWSW9(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW9_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW9_MASK)
569 
570 #define CE_L_VFCCU_GFLTRC_C0_RHWSW10_MASK        (0x400U)
571 #define CE_L_VFCCU_GFLTRC_C0_RHWSW10_SHIFT       (10U)
572 #define CE_L_VFCCU_GFLTRC_C0_RHWSW10_WIDTH       (1U)
573 #define CE_L_VFCCU_GFLTRC_C0_RHWSW10(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW10_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW10_MASK)
574 
575 #define CE_L_VFCCU_GFLTRC_C0_RHWSW11_MASK        (0x800U)
576 #define CE_L_VFCCU_GFLTRC_C0_RHWSW11_SHIFT       (11U)
577 #define CE_L_VFCCU_GFLTRC_C0_RHWSW11_WIDTH       (1U)
578 #define CE_L_VFCCU_GFLTRC_C0_RHWSW11(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW11_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW11_MASK)
579 
580 #define CE_L_VFCCU_GFLTRC_C0_RHWSW12_MASK        (0x1000U)
581 #define CE_L_VFCCU_GFLTRC_C0_RHWSW12_SHIFT       (12U)
582 #define CE_L_VFCCU_GFLTRC_C0_RHWSW12_WIDTH       (1U)
583 #define CE_L_VFCCU_GFLTRC_C0_RHWSW12(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW12_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW12_MASK)
584 
585 #define CE_L_VFCCU_GFLTRC_C0_RHWSW13_MASK        (0x2000U)
586 #define CE_L_VFCCU_GFLTRC_C0_RHWSW13_SHIFT       (13U)
587 #define CE_L_VFCCU_GFLTRC_C0_RHWSW13_WIDTH       (1U)
588 #define CE_L_VFCCU_GFLTRC_C0_RHWSW13(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW13_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW13_MASK)
589 
590 #define CE_L_VFCCU_GFLTRC_C0_RHWSW14_MASK        (0x4000U)
591 #define CE_L_VFCCU_GFLTRC_C0_RHWSW14_SHIFT       (14U)
592 #define CE_L_VFCCU_GFLTRC_C0_RHWSW14_WIDTH       (1U)
593 #define CE_L_VFCCU_GFLTRC_C0_RHWSW14(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW14_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW14_MASK)
594 
595 #define CE_L_VFCCU_GFLTRC_C0_RHWSW15_MASK        (0x8000U)
596 #define CE_L_VFCCU_GFLTRC_C0_RHWSW15_SHIFT       (15U)
597 #define CE_L_VFCCU_GFLTRC_C0_RHWSW15_WIDTH       (1U)
598 #define CE_L_VFCCU_GFLTRC_C0_RHWSW15(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW15_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW15_MASK)
599 
600 #define CE_L_VFCCU_GFLTRC_C0_RHWSW16_MASK        (0x10000U)
601 #define CE_L_VFCCU_GFLTRC_C0_RHWSW16_SHIFT       (16U)
602 #define CE_L_VFCCU_GFLTRC_C0_RHWSW16_WIDTH       (1U)
603 #define CE_L_VFCCU_GFLTRC_C0_RHWSW16(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW16_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW16_MASK)
604 
605 #define CE_L_VFCCU_GFLTRC_C0_RHWSW17_MASK        (0x20000U)
606 #define CE_L_VFCCU_GFLTRC_C0_RHWSW17_SHIFT       (17U)
607 #define CE_L_VFCCU_GFLTRC_C0_RHWSW17_WIDTH       (1U)
608 #define CE_L_VFCCU_GFLTRC_C0_RHWSW17(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW17_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW17_MASK)
609 
610 #define CE_L_VFCCU_GFLTRC_C0_RHWSW18_MASK        (0x40000U)
611 #define CE_L_VFCCU_GFLTRC_C0_RHWSW18_SHIFT       (18U)
612 #define CE_L_VFCCU_GFLTRC_C0_RHWSW18_WIDTH       (1U)
613 #define CE_L_VFCCU_GFLTRC_C0_RHWSW18(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW18_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW18_MASK)
614 
615 #define CE_L_VFCCU_GFLTRC_C0_RHWSW19_MASK        (0x80000U)
616 #define CE_L_VFCCU_GFLTRC_C0_RHWSW19_SHIFT       (19U)
617 #define CE_L_VFCCU_GFLTRC_C0_RHWSW19_WIDTH       (1U)
618 #define CE_L_VFCCU_GFLTRC_C0_RHWSW19(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW19_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW19_MASK)
619 
620 #define CE_L_VFCCU_GFLTRC_C0_RHWSW20_MASK        (0x100000U)
621 #define CE_L_VFCCU_GFLTRC_C0_RHWSW20_SHIFT       (20U)
622 #define CE_L_VFCCU_GFLTRC_C0_RHWSW20_WIDTH       (1U)
623 #define CE_L_VFCCU_GFLTRC_C0_RHWSW20(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW20_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW20_MASK)
624 
625 #define CE_L_VFCCU_GFLTRC_C0_RHWSW21_MASK        (0x200000U)
626 #define CE_L_VFCCU_GFLTRC_C0_RHWSW21_SHIFT       (21U)
627 #define CE_L_VFCCU_GFLTRC_C0_RHWSW21_WIDTH       (1U)
628 #define CE_L_VFCCU_GFLTRC_C0_RHWSW21(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW21_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW21_MASK)
629 
630 #define CE_L_VFCCU_GFLTRC_C0_RHWSW22_MASK        (0x400000U)
631 #define CE_L_VFCCU_GFLTRC_C0_RHWSW22_SHIFT       (22U)
632 #define CE_L_VFCCU_GFLTRC_C0_RHWSW22_WIDTH       (1U)
633 #define CE_L_VFCCU_GFLTRC_C0_RHWSW22(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW22_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW22_MASK)
634 
635 #define CE_L_VFCCU_GFLTRC_C0_RHWSW23_MASK        (0x800000U)
636 #define CE_L_VFCCU_GFLTRC_C0_RHWSW23_SHIFT       (23U)
637 #define CE_L_VFCCU_GFLTRC_C0_RHWSW23_WIDTH       (1U)
638 #define CE_L_VFCCU_GFLTRC_C0_RHWSW23(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW23_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW23_MASK)
639 
640 #define CE_L_VFCCU_GFLTRC_C0_RHWSW24_MASK        (0x1000000U)
641 #define CE_L_VFCCU_GFLTRC_C0_RHWSW24_SHIFT       (24U)
642 #define CE_L_VFCCU_GFLTRC_C0_RHWSW24_WIDTH       (1U)
643 #define CE_L_VFCCU_GFLTRC_C0_RHWSW24(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW24_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW24_MASK)
644 
645 #define CE_L_VFCCU_GFLTRC_C0_RHWSW25_MASK        (0x2000000U)
646 #define CE_L_VFCCU_GFLTRC_C0_RHWSW25_SHIFT       (25U)
647 #define CE_L_VFCCU_GFLTRC_C0_RHWSW25_WIDTH       (1U)
648 #define CE_L_VFCCU_GFLTRC_C0_RHWSW25(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW25_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW25_MASK)
649 
650 #define CE_L_VFCCU_GFLTRC_C0_RHWSW26_MASK        (0x4000000U)
651 #define CE_L_VFCCU_GFLTRC_C0_RHWSW26_SHIFT       (26U)
652 #define CE_L_VFCCU_GFLTRC_C0_RHWSW26_WIDTH       (1U)
653 #define CE_L_VFCCU_GFLTRC_C0_RHWSW26(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW26_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW26_MASK)
654 
655 #define CE_L_VFCCU_GFLTRC_C0_RHWSW27_MASK        (0x8000000U)
656 #define CE_L_VFCCU_GFLTRC_C0_RHWSW27_SHIFT       (27U)
657 #define CE_L_VFCCU_GFLTRC_C0_RHWSW27_WIDTH       (1U)
658 #define CE_L_VFCCU_GFLTRC_C0_RHWSW27(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW27_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW27_MASK)
659 
660 #define CE_L_VFCCU_GFLTRC_C0_RHWSW28_MASK        (0x10000000U)
661 #define CE_L_VFCCU_GFLTRC_C0_RHWSW28_SHIFT       (28U)
662 #define CE_L_VFCCU_GFLTRC_C0_RHWSW28_WIDTH       (1U)
663 #define CE_L_VFCCU_GFLTRC_C0_RHWSW28(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW28_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW28_MASK)
664 
665 #define CE_L_VFCCU_GFLTRC_C0_RHWSW29_MASK        (0x20000000U)
666 #define CE_L_VFCCU_GFLTRC_C0_RHWSW29_SHIFT       (29U)
667 #define CE_L_VFCCU_GFLTRC_C0_RHWSW29_WIDTH       (1U)
668 #define CE_L_VFCCU_GFLTRC_C0_RHWSW29(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW29_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW29_MASK)
669 
670 #define CE_L_VFCCU_GFLTRC_C0_RHWSW30_MASK        (0x40000000U)
671 #define CE_L_VFCCU_GFLTRC_C0_RHWSW30_SHIFT       (30U)
672 #define CE_L_VFCCU_GFLTRC_C0_RHWSW30_WIDTH       (1U)
673 #define CE_L_VFCCU_GFLTRC_C0_RHWSW30(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW30_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW30_MASK)
674 
675 #define CE_L_VFCCU_GFLTRC_C0_RHWSW31_MASK        (0x80000000U)
676 #define CE_L_VFCCU_GFLTRC_C0_RHWSW31_SHIFT       (31U)
677 #define CE_L_VFCCU_GFLTRC_C0_RHWSW31_WIDTH       (1U)
678 #define CE_L_VFCCU_GFLTRC_C0_RHWSW31(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C0_RHWSW31_SHIFT)) & CE_L_VFCCU_GFLTRC_C0_RHWSW31_MASK)
679 /*! @} */
680 
681 /*! @name GFLTRC_C1 - Global Fault Recovery */
682 /*! @{ */
683 
684 #define CE_L_VFCCU_GFLTRC_C1_RHWSW32_MASK        (0x1U)
685 #define CE_L_VFCCU_GFLTRC_C1_RHWSW32_SHIFT       (0U)
686 #define CE_L_VFCCU_GFLTRC_C1_RHWSW32_WIDTH       (1U)
687 #define CE_L_VFCCU_GFLTRC_C1_RHWSW32(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW32_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW32_MASK)
688 
689 #define CE_L_VFCCU_GFLTRC_C1_RHWSW33_MASK        (0x2U)
690 #define CE_L_VFCCU_GFLTRC_C1_RHWSW33_SHIFT       (1U)
691 #define CE_L_VFCCU_GFLTRC_C1_RHWSW33_WIDTH       (1U)
692 #define CE_L_VFCCU_GFLTRC_C1_RHWSW33(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW33_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW33_MASK)
693 
694 #define CE_L_VFCCU_GFLTRC_C1_RHWSW34_MASK        (0x4U)
695 #define CE_L_VFCCU_GFLTRC_C1_RHWSW34_SHIFT       (2U)
696 #define CE_L_VFCCU_GFLTRC_C1_RHWSW34_WIDTH       (1U)
697 #define CE_L_VFCCU_GFLTRC_C1_RHWSW34(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW34_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW34_MASK)
698 
699 #define CE_L_VFCCU_GFLTRC_C1_RHWSW35_MASK        (0x8U)
700 #define CE_L_VFCCU_GFLTRC_C1_RHWSW35_SHIFT       (3U)
701 #define CE_L_VFCCU_GFLTRC_C1_RHWSW35_WIDTH       (1U)
702 #define CE_L_VFCCU_GFLTRC_C1_RHWSW35(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW35_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW35_MASK)
703 
704 #define CE_L_VFCCU_GFLTRC_C1_RHWSW36_MASK        (0x10U)
705 #define CE_L_VFCCU_GFLTRC_C1_RHWSW36_SHIFT       (4U)
706 #define CE_L_VFCCU_GFLTRC_C1_RHWSW36_WIDTH       (1U)
707 #define CE_L_VFCCU_GFLTRC_C1_RHWSW36(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW36_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW36_MASK)
708 
709 #define CE_L_VFCCU_GFLTRC_C1_RHWSW37_MASK        (0x20U)
710 #define CE_L_VFCCU_GFLTRC_C1_RHWSW37_SHIFT       (5U)
711 #define CE_L_VFCCU_GFLTRC_C1_RHWSW37_WIDTH       (1U)
712 #define CE_L_VFCCU_GFLTRC_C1_RHWSW37(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW37_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW37_MASK)
713 
714 #define CE_L_VFCCU_GFLTRC_C1_RHWSW38_MASK        (0x40U)
715 #define CE_L_VFCCU_GFLTRC_C1_RHWSW38_SHIFT       (6U)
716 #define CE_L_VFCCU_GFLTRC_C1_RHWSW38_WIDTH       (1U)
717 #define CE_L_VFCCU_GFLTRC_C1_RHWSW38(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW38_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW38_MASK)
718 
719 #define CE_L_VFCCU_GFLTRC_C1_RHWSW39_MASK        (0x80U)
720 #define CE_L_VFCCU_GFLTRC_C1_RHWSW39_SHIFT       (7U)
721 #define CE_L_VFCCU_GFLTRC_C1_RHWSW39_WIDTH       (1U)
722 #define CE_L_VFCCU_GFLTRC_C1_RHWSW39(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW39_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW39_MASK)
723 
724 #define CE_L_VFCCU_GFLTRC_C1_RHWSW40_MASK        (0x100U)
725 #define CE_L_VFCCU_GFLTRC_C1_RHWSW40_SHIFT       (8U)
726 #define CE_L_VFCCU_GFLTRC_C1_RHWSW40_WIDTH       (1U)
727 #define CE_L_VFCCU_GFLTRC_C1_RHWSW40(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW40_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW40_MASK)
728 
729 #define CE_L_VFCCU_GFLTRC_C1_RHWSW41_MASK        (0x200U)
730 #define CE_L_VFCCU_GFLTRC_C1_RHWSW41_SHIFT       (9U)
731 #define CE_L_VFCCU_GFLTRC_C1_RHWSW41_WIDTH       (1U)
732 #define CE_L_VFCCU_GFLTRC_C1_RHWSW41(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW41_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW41_MASK)
733 
734 #define CE_L_VFCCU_GFLTRC_C1_RHWSW42_MASK        (0x400U)
735 #define CE_L_VFCCU_GFLTRC_C1_RHWSW42_SHIFT       (10U)
736 #define CE_L_VFCCU_GFLTRC_C1_RHWSW42_WIDTH       (1U)
737 #define CE_L_VFCCU_GFLTRC_C1_RHWSW42(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW42_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW42_MASK)
738 
739 #define CE_L_VFCCU_GFLTRC_C1_RHWSW43_MASK        (0x800U)
740 #define CE_L_VFCCU_GFLTRC_C1_RHWSW43_SHIFT       (11U)
741 #define CE_L_VFCCU_GFLTRC_C1_RHWSW43_WIDTH       (1U)
742 #define CE_L_VFCCU_GFLTRC_C1_RHWSW43(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW43_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW43_MASK)
743 
744 #define CE_L_VFCCU_GFLTRC_C1_RHWSW44_MASK        (0x1000U)
745 #define CE_L_VFCCU_GFLTRC_C1_RHWSW44_SHIFT       (12U)
746 #define CE_L_VFCCU_GFLTRC_C1_RHWSW44_WIDTH       (1U)
747 #define CE_L_VFCCU_GFLTRC_C1_RHWSW44(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW44_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW44_MASK)
748 
749 #define CE_L_VFCCU_GFLTRC_C1_RHWSW45_MASK        (0x2000U)
750 #define CE_L_VFCCU_GFLTRC_C1_RHWSW45_SHIFT       (13U)
751 #define CE_L_VFCCU_GFLTRC_C1_RHWSW45_WIDTH       (1U)
752 #define CE_L_VFCCU_GFLTRC_C1_RHWSW45(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW45_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW45_MASK)
753 
754 #define CE_L_VFCCU_GFLTRC_C1_RHWSW46_MASK        (0x4000U)
755 #define CE_L_VFCCU_GFLTRC_C1_RHWSW46_SHIFT       (14U)
756 #define CE_L_VFCCU_GFLTRC_C1_RHWSW46_WIDTH       (1U)
757 #define CE_L_VFCCU_GFLTRC_C1_RHWSW46(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW46_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW46_MASK)
758 
759 #define CE_L_VFCCU_GFLTRC_C1_RHWSW47_MASK        (0x8000U)
760 #define CE_L_VFCCU_GFLTRC_C1_RHWSW47_SHIFT       (15U)
761 #define CE_L_VFCCU_GFLTRC_C1_RHWSW47_WIDTH       (1U)
762 #define CE_L_VFCCU_GFLTRC_C1_RHWSW47(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW47_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW47_MASK)
763 
764 #define CE_L_VFCCU_GFLTRC_C1_RHWSW48_MASK        (0x10000U)
765 #define CE_L_VFCCU_GFLTRC_C1_RHWSW48_SHIFT       (16U)
766 #define CE_L_VFCCU_GFLTRC_C1_RHWSW48_WIDTH       (1U)
767 #define CE_L_VFCCU_GFLTRC_C1_RHWSW48(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW48_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW48_MASK)
768 
769 #define CE_L_VFCCU_GFLTRC_C1_RHWSW49_MASK        (0x20000U)
770 #define CE_L_VFCCU_GFLTRC_C1_RHWSW49_SHIFT       (17U)
771 #define CE_L_VFCCU_GFLTRC_C1_RHWSW49_WIDTH       (1U)
772 #define CE_L_VFCCU_GFLTRC_C1_RHWSW49(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW49_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW49_MASK)
773 
774 #define CE_L_VFCCU_GFLTRC_C1_RHWSW50_MASK        (0x40000U)
775 #define CE_L_VFCCU_GFLTRC_C1_RHWSW50_SHIFT       (18U)
776 #define CE_L_VFCCU_GFLTRC_C1_RHWSW50_WIDTH       (1U)
777 #define CE_L_VFCCU_GFLTRC_C1_RHWSW50(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW50_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW50_MASK)
778 
779 #define CE_L_VFCCU_GFLTRC_C1_RHWSW51_MASK        (0x80000U)
780 #define CE_L_VFCCU_GFLTRC_C1_RHWSW51_SHIFT       (19U)
781 #define CE_L_VFCCU_GFLTRC_C1_RHWSW51_WIDTH       (1U)
782 #define CE_L_VFCCU_GFLTRC_C1_RHWSW51(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW51_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW51_MASK)
783 
784 #define CE_L_VFCCU_GFLTRC_C1_RHWSW52_MASK        (0x100000U)
785 #define CE_L_VFCCU_GFLTRC_C1_RHWSW52_SHIFT       (20U)
786 #define CE_L_VFCCU_GFLTRC_C1_RHWSW52_WIDTH       (1U)
787 #define CE_L_VFCCU_GFLTRC_C1_RHWSW52(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTRC_C1_RHWSW52_SHIFT)) & CE_L_VFCCU_GFLTRC_C1_RHWSW52_MASK)
788 /*! @} */
789 
790 /*! @name GFLTOVDC0 - Global Fault Overflow Detection */
791 /*! @{ */
792 
793 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS0_MASK       (0x1U)
794 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS0_SHIFT      (0U)
795 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS0_WIDTH      (1U)
796 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS0(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS0_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS0_MASK)
797 
798 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS1_MASK       (0x2U)
799 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS1_SHIFT      (1U)
800 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS1_WIDTH      (1U)
801 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS1(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS1_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS1_MASK)
802 
803 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS2_MASK       (0x4U)
804 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS2_SHIFT      (2U)
805 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS2_WIDTH      (1U)
806 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS2(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS2_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS2_MASK)
807 
808 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS3_MASK       (0x8U)
809 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS3_SHIFT      (3U)
810 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS3_WIDTH      (1U)
811 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS3(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS3_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS3_MASK)
812 
813 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS4_MASK       (0x10U)
814 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS4_SHIFT      (4U)
815 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS4_WIDTH      (1U)
816 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS4(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS4_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS4_MASK)
817 
818 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS5_MASK       (0x20U)
819 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS5_SHIFT      (5U)
820 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS5_WIDTH      (1U)
821 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS5(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS5_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS5_MASK)
822 
823 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS6_MASK       (0x40U)
824 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS6_SHIFT      (6U)
825 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS6_WIDTH      (1U)
826 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS6(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS6_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS6_MASK)
827 
828 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS7_MASK       (0x80U)
829 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS7_SHIFT      (7U)
830 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS7_WIDTH      (1U)
831 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS7(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS7_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS7_MASK)
832 
833 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS8_MASK       (0x100U)
834 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS8_SHIFT      (8U)
835 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS8_WIDTH      (1U)
836 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS8(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS8_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS8_MASK)
837 
838 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS9_MASK       (0x200U)
839 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS9_SHIFT      (9U)
840 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS9_WIDTH      (1U)
841 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS9(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS9_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS9_MASK)
842 
843 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS10_MASK      (0x400U)
844 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS10_SHIFT     (10U)
845 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS10_WIDTH     (1U)
846 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS10(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS10_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS10_MASK)
847 
848 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS11_MASK      (0x800U)
849 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS11_SHIFT     (11U)
850 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS11_WIDTH     (1U)
851 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS11(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS11_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS11_MASK)
852 
853 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS12_MASK      (0x1000U)
854 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS12_SHIFT     (12U)
855 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS12_WIDTH     (1U)
856 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS12(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS12_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS12_MASK)
857 
858 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS13_MASK      (0x2000U)
859 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS13_SHIFT     (13U)
860 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS13_WIDTH     (1U)
861 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS13(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS13_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS13_MASK)
862 
863 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS14_MASK      (0x4000U)
864 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS14_SHIFT     (14U)
865 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS14_WIDTH     (1U)
866 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS14(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS14_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS14_MASK)
867 
868 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS15_MASK      (0x8000U)
869 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS15_SHIFT     (15U)
870 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS15_WIDTH     (1U)
871 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS15(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS15_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS15_MASK)
872 
873 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS16_MASK      (0x10000U)
874 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS16_SHIFT     (16U)
875 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS16_WIDTH     (1U)
876 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS16(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS16_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS16_MASK)
877 
878 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS17_MASK      (0x20000U)
879 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS17_SHIFT     (17U)
880 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS17_WIDTH     (1U)
881 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS17(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS17_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS17_MASK)
882 
883 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS18_MASK      (0x40000U)
884 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS18_SHIFT     (18U)
885 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS18_WIDTH     (1U)
886 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS18(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS18_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS18_MASK)
887 
888 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS19_MASK      (0x80000U)
889 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS19_SHIFT     (19U)
890 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS19_WIDTH     (1U)
891 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS19(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS19_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS19_MASK)
892 
893 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS20_MASK      (0x100000U)
894 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS20_SHIFT     (20U)
895 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS20_WIDTH     (1U)
896 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS20(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS20_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS20_MASK)
897 
898 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS21_MASK      (0x200000U)
899 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS21_SHIFT     (21U)
900 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS21_WIDTH     (1U)
901 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS21(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS21_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS21_MASK)
902 
903 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS22_MASK      (0x400000U)
904 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS22_SHIFT     (22U)
905 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS22_WIDTH     (1U)
906 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS22(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS22_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS22_MASK)
907 
908 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS23_MASK      (0x800000U)
909 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS23_SHIFT     (23U)
910 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS23_WIDTH     (1U)
911 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS23(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS23_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS23_MASK)
912 
913 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS24_MASK      (0x1000000U)
914 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS24_SHIFT     (24U)
915 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS24_WIDTH     (1U)
916 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS24(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS24_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS24_MASK)
917 
918 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS25_MASK      (0x2000000U)
919 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS25_SHIFT     (25U)
920 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS25_WIDTH     (1U)
921 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS25(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS25_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS25_MASK)
922 
923 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS26_MASK      (0x4000000U)
924 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS26_SHIFT     (26U)
925 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS26_WIDTH     (1U)
926 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS26(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS26_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS26_MASK)
927 
928 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS27_MASK      (0x8000000U)
929 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS27_SHIFT     (27U)
930 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS27_WIDTH     (1U)
931 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS27(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS27_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS27_MASK)
932 
933 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS28_MASK      (0x10000000U)
934 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS28_SHIFT     (28U)
935 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS28_WIDTH     (1U)
936 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS28(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS28_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS28_MASK)
937 
938 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS29_MASK      (0x20000000U)
939 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS29_SHIFT     (29U)
940 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS29_WIDTH     (1U)
941 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS29(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS29_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS29_MASK)
942 
943 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS30_MASK      (0x40000000U)
944 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS30_SHIFT     (30U)
945 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS30_WIDTH     (1U)
946 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS30(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS30_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS30_MASK)
947 
948 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS31_MASK      (0x80000000U)
949 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS31_SHIFT     (31U)
950 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS31_WIDTH     (1U)
951 #define CE_L_VFCCU_GFLTOVDC0_OVF_DIS31(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC0_OVF_DIS31_SHIFT)) & CE_L_VFCCU_GFLTOVDC0_OVF_DIS31_MASK)
952 /*! @} */
953 
954 /*! @name GFLTOVDC1 - Global Fault Overflow Detection */
955 /*! @{ */
956 
957 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS32_MASK      (0x1U)
958 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS32_SHIFT     (0U)
959 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS32_WIDTH     (1U)
960 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS32(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS32_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS32_MASK)
961 
962 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS33_MASK      (0x2U)
963 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS33_SHIFT     (1U)
964 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS33_WIDTH     (1U)
965 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS33(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS33_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS33_MASK)
966 
967 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS34_MASK      (0x4U)
968 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS34_SHIFT     (2U)
969 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS34_WIDTH     (1U)
970 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS34(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS34_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS34_MASK)
971 
972 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS35_MASK      (0x8U)
973 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS35_SHIFT     (3U)
974 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS35_WIDTH     (1U)
975 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS35(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS35_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS35_MASK)
976 
977 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS36_MASK      (0x10U)
978 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS36_SHIFT     (4U)
979 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS36_WIDTH     (1U)
980 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS36(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS36_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS36_MASK)
981 
982 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS37_MASK      (0x20U)
983 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS37_SHIFT     (5U)
984 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS37_WIDTH     (1U)
985 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS37(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS37_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS37_MASK)
986 
987 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS38_MASK      (0x40U)
988 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS38_SHIFT     (6U)
989 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS38_WIDTH     (1U)
990 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS38(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS38_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS38_MASK)
991 
992 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS39_MASK      (0x80U)
993 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS39_SHIFT     (7U)
994 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS39_WIDTH     (1U)
995 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS39(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS39_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS39_MASK)
996 
997 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS40_MASK      (0x100U)
998 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS40_SHIFT     (8U)
999 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS40_WIDTH     (1U)
1000 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS40(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS40_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS40_MASK)
1001 
1002 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS41_MASK      (0x200U)
1003 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS41_SHIFT     (9U)
1004 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS41_WIDTH     (1U)
1005 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS41(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS41_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS41_MASK)
1006 
1007 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS42_MASK      (0x400U)
1008 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS42_SHIFT     (10U)
1009 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS42_WIDTH     (1U)
1010 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS42(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS42_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS42_MASK)
1011 
1012 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS43_MASK      (0x800U)
1013 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS43_SHIFT     (11U)
1014 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS43_WIDTH     (1U)
1015 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS43(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS43_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS43_MASK)
1016 
1017 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS44_MASK      (0x1000U)
1018 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS44_SHIFT     (12U)
1019 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS44_WIDTH     (1U)
1020 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS44(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS44_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS44_MASK)
1021 
1022 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS45_MASK      (0x2000U)
1023 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS45_SHIFT     (13U)
1024 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS45_WIDTH     (1U)
1025 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS45(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS45_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS45_MASK)
1026 
1027 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS46_MASK      (0x4000U)
1028 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS46_SHIFT     (14U)
1029 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS46_WIDTH     (1U)
1030 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS46(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS46_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS46_MASK)
1031 
1032 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS47_MASK      (0x8000U)
1033 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS47_SHIFT     (15U)
1034 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS47_WIDTH     (1U)
1035 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS47(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS47_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS47_MASK)
1036 
1037 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS48_MASK      (0x10000U)
1038 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS48_SHIFT     (16U)
1039 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS48_WIDTH     (1U)
1040 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS48(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS48_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS48_MASK)
1041 
1042 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS49_MASK      (0x20000U)
1043 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS49_SHIFT     (17U)
1044 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS49_WIDTH     (1U)
1045 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS49(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS49_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS49_MASK)
1046 
1047 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS50_MASK      (0x40000U)
1048 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS50_SHIFT     (18U)
1049 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS50_WIDTH     (1U)
1050 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS50(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS50_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS50_MASK)
1051 
1052 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS51_MASK      (0x80000U)
1053 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS51_SHIFT     (19U)
1054 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS51_WIDTH     (1U)
1055 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS51(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS51_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS51_MASK)
1056 
1057 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS52_MASK      (0x100000U)
1058 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS52_SHIFT     (20U)
1059 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS52_WIDTH     (1U)
1060 #define CE_L_VFCCU_GFLTOVDC1_OVF_DIS52(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GFLTOVDC1_OVF_DIS52_SHIFT)) & CE_L_VFCCU_GFLTOVDC1_OVF_DIS52_MASK)
1061 /*! @} */
1062 
1063 /*! @name GSWFLODC - Global Software Fault Overflow Detection Disable */
1064 /*! @{ */
1065 
1066 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS0_MASK      (0x1U)
1067 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS0_SHIFT     (0U)
1068 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS0_WIDTH     (1U)
1069 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS0(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GSWFLODC_SWOVF_DIS0_SHIFT)) & CE_L_VFCCU_GSWFLODC_SWOVF_DIS0_MASK)
1070 
1071 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS1_MASK      (0x2U)
1072 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS1_SHIFT     (1U)
1073 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS1_WIDTH     (1U)
1074 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS1(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GSWFLODC_SWOVF_DIS1_SHIFT)) & CE_L_VFCCU_GSWFLODC_SWOVF_DIS1_MASK)
1075 
1076 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS2_MASK      (0x4U)
1077 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS2_SHIFT     (2U)
1078 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS2_WIDTH     (1U)
1079 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS2(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GSWFLODC_SWOVF_DIS2_SHIFT)) & CE_L_VFCCU_GSWFLODC_SWOVF_DIS2_MASK)
1080 
1081 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS3_MASK      (0x8U)
1082 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS3_SHIFT     (3U)
1083 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS3_WIDTH     (1U)
1084 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS3(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GSWFLODC_SWOVF_DIS3_SHIFT)) & CE_L_VFCCU_GSWFLODC_SWOVF_DIS3_MASK)
1085 
1086 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS4_MASK      (0x10U)
1087 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS4_SHIFT     (4U)
1088 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS4_WIDTH     (1U)
1089 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS4(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GSWFLODC_SWOVF_DIS4_SHIFT)) & CE_L_VFCCU_GSWFLODC_SWOVF_DIS4_MASK)
1090 
1091 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS5_MASK      (0x20U)
1092 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS5_SHIFT     (5U)
1093 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS5_WIDTH     (1U)
1094 #define CE_L_VFCCU_GSWFLODC_SWOVF_DIS5(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GSWFLODC_SWOVF_DIS5_SHIFT)) & CE_L_VFCCU_GSWFLODC_SWOVF_DIS5_MASK)
1095 /*! @} */
1096 
1097 /*! @name GCTRL - Global Space Control */
1098 /*! @{ */
1099 
1100 #define CE_L_VFCCU_GCTRL_OVF_EN_MASK             (0x1U)
1101 #define CE_L_VFCCU_GCTRL_OVF_EN_SHIFT            (0U)
1102 #define CE_L_VFCCU_GCTRL_OVF_EN_WIDTH            (1U)
1103 #define CE_L_VFCCU_GCTRL_OVF_EN(x)               (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GCTRL_OVF_EN_SHIFT)) & CE_L_VFCCU_GCTRL_OVF_EN_MASK)
1104 /*! @} */
1105 
1106 /*! @name GINTOVFS - Global DID FSM Status */
1107 /*! @{ */
1108 
1109 #define CE_L_VFCCU_GINTOVFS_FLTSERV_MASK         (0x80U)
1110 #define CE_L_VFCCU_GINTOVFS_FLTSERV_SHIFT        (7U)
1111 #define CE_L_VFCCU_GINTOVFS_FLTSERV_WIDTH        (1U)
1112 #define CE_L_VFCCU_GINTOVFS_FLTSERV(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GINTOVFS_FLTSERV_SHIFT)) & CE_L_VFCCU_GINTOVFS_FLTSERV_MASK)
1113 
1114 #define CE_L_VFCCU_GINTOVFS_OVF_DET_MASK         (0x100U)
1115 #define CE_L_VFCCU_GINTOVFS_OVF_DET_SHIFT        (8U)
1116 #define CE_L_VFCCU_GINTOVFS_OVF_DET_WIDTH        (1U)
1117 #define CE_L_VFCCU_GINTOVFS_OVF_DET(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GINTOVFS_OVF_DET_SHIFT)) & CE_L_VFCCU_GINTOVFS_OVF_DET_MASK)
1118 
1119 #define CE_L_VFCCU_GINTOVFS_SERV_DID_MASK        (0xF0000U)
1120 #define CE_L_VFCCU_GINTOVFS_SERV_DID_SHIFT       (16U)
1121 #define CE_L_VFCCU_GINTOVFS_SERV_DID_WIDTH       (4U)
1122 #define CE_L_VFCCU_GINTOVFS_SERV_DID(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GINTOVFS_SERV_DID_SHIFT)) & CE_L_VFCCU_GINTOVFS_SERV_DID_MASK)
1123 
1124 #define CE_L_VFCCU_GINTOVFS_OVF_DID_MASK         (0xF000000U)
1125 #define CE_L_VFCCU_GINTOVFS_OVF_DID_SHIFT        (24U)
1126 #define CE_L_VFCCU_GINTOVFS_OVF_DID_WIDTH        (4U)
1127 #define CE_L_VFCCU_GINTOVFS_OVF_DID(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GINTOVFS_OVF_DID_SHIFT)) & CE_L_VFCCU_GINTOVFS_OVF_DID_MASK)
1128 /*! @} */
1129 
1130 /*! @name GDBGCFG - Global Debug */
1131 /*! @{ */
1132 
1133 #define CE_L_VFCCU_GDBGCFG_FRZ_MASK              (0x10000U)
1134 #define CE_L_VFCCU_GDBGCFG_FRZ_SHIFT             (16U)
1135 #define CE_L_VFCCU_GDBGCFG_FRZ_WIDTH             (1U)
1136 #define CE_L_VFCCU_GDBGCFG_FRZ(x)                (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDBGCFG_FRZ_SHIFT)) & CE_L_VFCCU_GDBGCFG_FRZ_MASK)
1137 /*! @} */
1138 
1139 /*! @name GDBGSTAT - Global Debug Status */
1140 /*! @{ */
1141 
1142 #define CE_L_VFCCU_GDBGSTAT_FLTIND_MASK          (0xFFU)
1143 #define CE_L_VFCCU_GDBGSTAT_FLTIND_SHIFT         (0U)
1144 #define CE_L_VFCCU_GDBGSTAT_FLTIND_WIDTH         (8U)
1145 #define CE_L_VFCCU_GDBGSTAT_FLTIND(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_GDBGSTAT_FLTIND_SHIFT)) & CE_L_VFCCU_GDBGSTAT_FLTIND_MASK)
1146 /*! @} */
1147 
1148 /*! @name SWRPTDID - Software Fault Reported DID */
1149 /*! @{ */
1150 
1151 #define CE_L_VFCCU_SWRPTDID_DID_MASK             (0xFU)
1152 #define CE_L_VFCCU_SWRPTDID_DID_SHIFT            (0U)
1153 #define CE_L_VFCCU_SWRPTDID_DID_WIDTH            (4U)
1154 #define CE_L_VFCCU_SWRPTDID_DID(x)               (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRPTDID_DID_SHIFT)) & CE_L_VFCCU_SWRPTDID_DID_MASK)
1155 /*! @} */
1156 
1157 /*! @name SWRKSET_0 - Software Reaction Set */
1158 /*! @{ */
1159 
1160 #define CE_L_VFCCU_SWRKSET_0_RKNEN0_MASK         (0x1U)
1161 #define CE_L_VFCCU_SWRKSET_0_RKNEN0_SHIFT        (0U)
1162 #define CE_L_VFCCU_SWRKSET_0_RKNEN0_WIDTH        (1U)
1163 #define CE_L_VFCCU_SWRKSET_0_RKNEN0(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKSET_0_RKNEN0_SHIFT)) & CE_L_VFCCU_SWRKSET_0_RKNEN0_MASK)
1164 
1165 #define CE_L_VFCCU_SWRKSET_0_RKNEN1_MASK         (0x2U)
1166 #define CE_L_VFCCU_SWRKSET_0_RKNEN1_SHIFT        (1U)
1167 #define CE_L_VFCCU_SWRKSET_0_RKNEN1_WIDTH        (1U)
1168 #define CE_L_VFCCU_SWRKSET_0_RKNEN1(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKSET_0_RKNEN1_SHIFT)) & CE_L_VFCCU_SWRKSET_0_RKNEN1_MASK)
1169 
1170 #define CE_L_VFCCU_SWRKSET_0_RKNEN2_MASK         (0x4U)
1171 #define CE_L_VFCCU_SWRKSET_0_RKNEN2_SHIFT        (2U)
1172 #define CE_L_VFCCU_SWRKSET_0_RKNEN2_WIDTH        (1U)
1173 #define CE_L_VFCCU_SWRKSET_0_RKNEN2(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKSET_0_RKNEN2_SHIFT)) & CE_L_VFCCU_SWRKSET_0_RKNEN2_MASK)
1174 
1175 #define CE_L_VFCCU_SWRKSET_0_RKNEN3_MASK         (0x8U)
1176 #define CE_L_VFCCU_SWRKSET_0_RKNEN3_SHIFT        (3U)
1177 #define CE_L_VFCCU_SWRKSET_0_RKNEN3_WIDTH        (1U)
1178 #define CE_L_VFCCU_SWRKSET_0_RKNEN3(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKSET_0_RKNEN3_SHIFT)) & CE_L_VFCCU_SWRKSET_0_RKNEN3_MASK)
1179 
1180 #define CE_L_VFCCU_SWRKSET_0_RKNEN4_MASK         (0x10U)
1181 #define CE_L_VFCCU_SWRKSET_0_RKNEN4_SHIFT        (4U)
1182 #define CE_L_VFCCU_SWRKSET_0_RKNEN4_WIDTH        (1U)
1183 #define CE_L_VFCCU_SWRKSET_0_RKNEN4(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKSET_0_RKNEN4_SHIFT)) & CE_L_VFCCU_SWRKSET_0_RKNEN4_MASK)
1184 
1185 #define CE_L_VFCCU_SWRKSET_0_RKNEN5_MASK         (0x20U)
1186 #define CE_L_VFCCU_SWRKSET_0_RKNEN5_SHIFT        (5U)
1187 #define CE_L_VFCCU_SWRKSET_0_RKNEN5_WIDTH        (1U)
1188 #define CE_L_VFCCU_SWRKSET_0_RKNEN5(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKSET_0_RKNEN5_SHIFT)) & CE_L_VFCCU_SWRKSET_0_RKNEN5_MASK)
1189 /*! @} */
1190 
1191 /*! @name SWRKCLR_0 - Software Reaction Clear */
1192 /*! @{ */
1193 
1194 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR0_MASK        (0x1U)
1195 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR0_SHIFT       (0U)
1196 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR0_WIDTH       (1U)
1197 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR0(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKCLR_0_RKNCLR0_SHIFT)) & CE_L_VFCCU_SWRKCLR_0_RKNCLR0_MASK)
1198 
1199 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR1_MASK        (0x2U)
1200 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR1_SHIFT       (1U)
1201 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR1_WIDTH       (1U)
1202 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR1(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKCLR_0_RKNCLR1_SHIFT)) & CE_L_VFCCU_SWRKCLR_0_RKNCLR1_MASK)
1203 
1204 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR2_MASK        (0x4U)
1205 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR2_SHIFT       (2U)
1206 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR2_WIDTH       (1U)
1207 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR2(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKCLR_0_RKNCLR2_SHIFT)) & CE_L_VFCCU_SWRKCLR_0_RKNCLR2_MASK)
1208 
1209 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR3_MASK        (0x8U)
1210 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR3_SHIFT       (3U)
1211 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR3_WIDTH       (1U)
1212 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR3(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKCLR_0_RKNCLR3_SHIFT)) & CE_L_VFCCU_SWRKCLR_0_RKNCLR3_MASK)
1213 
1214 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR4_MASK        (0x10U)
1215 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR4_SHIFT       (4U)
1216 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR4_WIDTH       (1U)
1217 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR4(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKCLR_0_RKNCLR4_SHIFT)) & CE_L_VFCCU_SWRKCLR_0_RKNCLR4_MASK)
1218 
1219 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR5_MASK        (0x20U)
1220 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR5_SHIFT       (5U)
1221 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR5_WIDTH       (1U)
1222 #define CE_L_VFCCU_SWRKCLR_0_RKNCLR5(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_SWRKCLR_0_RKNCLR5_SHIFT)) & CE_L_VFCCU_SWRKCLR_0_RKNCLR5_MASK)
1223 /*! @} */
1224 
1225 /*! @name FHCFG0 - Fault Handler */
1226 /*! @{ */
1227 
1228 #define CE_L_VFCCU_FHCFG0_FHIDEN_MASK            (0x1U)
1229 #define CE_L_VFCCU_FHCFG0_FHIDEN_SHIFT           (0U)
1230 #define CE_L_VFCCU_FHCFG0_FHIDEN_WIDTH           (1U)
1231 #define CE_L_VFCCU_FHCFG0_FHIDEN(x)              (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHCFG0_FHIDEN_SHIFT)) & CE_L_VFCCU_FHCFG0_FHIDEN_MASK)
1232 /*! @} */
1233 
1234 /*! @name FHSRVDS0 - Fault Handler Status */
1235 /*! @{ */
1236 
1237 #define CE_L_VFCCU_FHSRVDS0_SERV_DID_MASK        (0xFU)
1238 #define CE_L_VFCCU_FHSRVDS0_SERV_DID_SHIFT       (0U)
1239 #define CE_L_VFCCU_FHSRVDS0_SERV_DID_WIDTH       (4U)
1240 #define CE_L_VFCCU_FHSRVDS0_SERV_DID(x)          (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHSRVDS0_SERV_DID_SHIFT)) & CE_L_VFCCU_FHSRVDS0_SERV_DID_MASK)
1241 
1242 #define CE_L_VFCCU_FHSRVDS0_AGGFLTS_MASK         (0x10U)
1243 #define CE_L_VFCCU_FHSRVDS0_AGGFLTS_SHIFT        (4U)
1244 #define CE_L_VFCCU_FHSRVDS0_AGGFLTS_WIDTH        (1U)
1245 #define CE_L_VFCCU_FHSRVDS0_AGGFLTS(x)           (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHSRVDS0_AGGFLTS_SHIFT)) & CE_L_VFCCU_FHSRVDS0_AGGFLTS_MASK)
1246 /*! @} */
1247 
1248 /*! @name FHFLTENC00 - Fault Enable */
1249 /*! @{ */
1250 
1251 #define CE_L_VFCCU_FHFLTENC00_EN0_MASK           (0x1U)
1252 #define CE_L_VFCCU_FHFLTENC00_EN0_SHIFT          (0U)
1253 #define CE_L_VFCCU_FHFLTENC00_EN0_WIDTH          (1U)
1254 #define CE_L_VFCCU_FHFLTENC00_EN0(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN0_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN0_MASK)
1255 
1256 #define CE_L_VFCCU_FHFLTENC00_EN1_MASK           (0x2U)
1257 #define CE_L_VFCCU_FHFLTENC00_EN1_SHIFT          (1U)
1258 #define CE_L_VFCCU_FHFLTENC00_EN1_WIDTH          (1U)
1259 #define CE_L_VFCCU_FHFLTENC00_EN1(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN1_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN1_MASK)
1260 
1261 #define CE_L_VFCCU_FHFLTENC00_EN2_MASK           (0x4U)
1262 #define CE_L_VFCCU_FHFLTENC00_EN2_SHIFT          (2U)
1263 #define CE_L_VFCCU_FHFLTENC00_EN2_WIDTH          (1U)
1264 #define CE_L_VFCCU_FHFLTENC00_EN2(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN2_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN2_MASK)
1265 
1266 #define CE_L_VFCCU_FHFLTENC00_EN3_MASK           (0x8U)
1267 #define CE_L_VFCCU_FHFLTENC00_EN3_SHIFT          (3U)
1268 #define CE_L_VFCCU_FHFLTENC00_EN3_WIDTH          (1U)
1269 #define CE_L_VFCCU_FHFLTENC00_EN3(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN3_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN3_MASK)
1270 
1271 #define CE_L_VFCCU_FHFLTENC00_EN4_MASK           (0x10U)
1272 #define CE_L_VFCCU_FHFLTENC00_EN4_SHIFT          (4U)
1273 #define CE_L_VFCCU_FHFLTENC00_EN4_WIDTH          (1U)
1274 #define CE_L_VFCCU_FHFLTENC00_EN4(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN4_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN4_MASK)
1275 
1276 #define CE_L_VFCCU_FHFLTENC00_EN5_MASK           (0x20U)
1277 #define CE_L_VFCCU_FHFLTENC00_EN5_SHIFT          (5U)
1278 #define CE_L_VFCCU_FHFLTENC00_EN5_WIDTH          (1U)
1279 #define CE_L_VFCCU_FHFLTENC00_EN5(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN5_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN5_MASK)
1280 
1281 #define CE_L_VFCCU_FHFLTENC00_EN6_MASK           (0x40U)
1282 #define CE_L_VFCCU_FHFLTENC00_EN6_SHIFT          (6U)
1283 #define CE_L_VFCCU_FHFLTENC00_EN6_WIDTH          (1U)
1284 #define CE_L_VFCCU_FHFLTENC00_EN6(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN6_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN6_MASK)
1285 
1286 #define CE_L_VFCCU_FHFLTENC00_EN7_MASK           (0x80U)
1287 #define CE_L_VFCCU_FHFLTENC00_EN7_SHIFT          (7U)
1288 #define CE_L_VFCCU_FHFLTENC00_EN7_WIDTH          (1U)
1289 #define CE_L_VFCCU_FHFLTENC00_EN7(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN7_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN7_MASK)
1290 
1291 #define CE_L_VFCCU_FHFLTENC00_EN8_MASK           (0x100U)
1292 #define CE_L_VFCCU_FHFLTENC00_EN8_SHIFT          (8U)
1293 #define CE_L_VFCCU_FHFLTENC00_EN8_WIDTH          (1U)
1294 #define CE_L_VFCCU_FHFLTENC00_EN8(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN8_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN8_MASK)
1295 
1296 #define CE_L_VFCCU_FHFLTENC00_EN9_MASK           (0x200U)
1297 #define CE_L_VFCCU_FHFLTENC00_EN9_SHIFT          (9U)
1298 #define CE_L_VFCCU_FHFLTENC00_EN9_WIDTH          (1U)
1299 #define CE_L_VFCCU_FHFLTENC00_EN9(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN9_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN9_MASK)
1300 
1301 #define CE_L_VFCCU_FHFLTENC00_EN10_MASK          (0x400U)
1302 #define CE_L_VFCCU_FHFLTENC00_EN10_SHIFT         (10U)
1303 #define CE_L_VFCCU_FHFLTENC00_EN10_WIDTH         (1U)
1304 #define CE_L_VFCCU_FHFLTENC00_EN10(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN10_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN10_MASK)
1305 
1306 #define CE_L_VFCCU_FHFLTENC00_EN11_MASK          (0x800U)
1307 #define CE_L_VFCCU_FHFLTENC00_EN11_SHIFT         (11U)
1308 #define CE_L_VFCCU_FHFLTENC00_EN11_WIDTH         (1U)
1309 #define CE_L_VFCCU_FHFLTENC00_EN11(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN11_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN11_MASK)
1310 
1311 #define CE_L_VFCCU_FHFLTENC00_EN12_MASK          (0x1000U)
1312 #define CE_L_VFCCU_FHFLTENC00_EN12_SHIFT         (12U)
1313 #define CE_L_VFCCU_FHFLTENC00_EN12_WIDTH         (1U)
1314 #define CE_L_VFCCU_FHFLTENC00_EN12(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN12_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN12_MASK)
1315 
1316 #define CE_L_VFCCU_FHFLTENC00_EN13_MASK          (0x2000U)
1317 #define CE_L_VFCCU_FHFLTENC00_EN13_SHIFT         (13U)
1318 #define CE_L_VFCCU_FHFLTENC00_EN13_WIDTH         (1U)
1319 #define CE_L_VFCCU_FHFLTENC00_EN13(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN13_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN13_MASK)
1320 
1321 #define CE_L_VFCCU_FHFLTENC00_EN14_MASK          (0x4000U)
1322 #define CE_L_VFCCU_FHFLTENC00_EN14_SHIFT         (14U)
1323 #define CE_L_VFCCU_FHFLTENC00_EN14_WIDTH         (1U)
1324 #define CE_L_VFCCU_FHFLTENC00_EN14(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN14_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN14_MASK)
1325 
1326 #define CE_L_VFCCU_FHFLTENC00_EN15_MASK          (0x8000U)
1327 #define CE_L_VFCCU_FHFLTENC00_EN15_SHIFT         (15U)
1328 #define CE_L_VFCCU_FHFLTENC00_EN15_WIDTH         (1U)
1329 #define CE_L_VFCCU_FHFLTENC00_EN15(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN15_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN15_MASK)
1330 
1331 #define CE_L_VFCCU_FHFLTENC00_EN16_MASK          (0x10000U)
1332 #define CE_L_VFCCU_FHFLTENC00_EN16_SHIFT         (16U)
1333 #define CE_L_VFCCU_FHFLTENC00_EN16_WIDTH         (1U)
1334 #define CE_L_VFCCU_FHFLTENC00_EN16(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN16_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN16_MASK)
1335 
1336 #define CE_L_VFCCU_FHFLTENC00_EN17_MASK          (0x20000U)
1337 #define CE_L_VFCCU_FHFLTENC00_EN17_SHIFT         (17U)
1338 #define CE_L_VFCCU_FHFLTENC00_EN17_WIDTH         (1U)
1339 #define CE_L_VFCCU_FHFLTENC00_EN17(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN17_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN17_MASK)
1340 
1341 #define CE_L_VFCCU_FHFLTENC00_EN18_MASK          (0x40000U)
1342 #define CE_L_VFCCU_FHFLTENC00_EN18_SHIFT         (18U)
1343 #define CE_L_VFCCU_FHFLTENC00_EN18_WIDTH         (1U)
1344 #define CE_L_VFCCU_FHFLTENC00_EN18(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN18_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN18_MASK)
1345 
1346 #define CE_L_VFCCU_FHFLTENC00_EN19_MASK          (0x80000U)
1347 #define CE_L_VFCCU_FHFLTENC00_EN19_SHIFT         (19U)
1348 #define CE_L_VFCCU_FHFLTENC00_EN19_WIDTH         (1U)
1349 #define CE_L_VFCCU_FHFLTENC00_EN19(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN19_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN19_MASK)
1350 
1351 #define CE_L_VFCCU_FHFLTENC00_EN20_MASK          (0x100000U)
1352 #define CE_L_VFCCU_FHFLTENC00_EN20_SHIFT         (20U)
1353 #define CE_L_VFCCU_FHFLTENC00_EN20_WIDTH         (1U)
1354 #define CE_L_VFCCU_FHFLTENC00_EN20(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN20_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN20_MASK)
1355 
1356 #define CE_L_VFCCU_FHFLTENC00_EN21_MASK          (0x200000U)
1357 #define CE_L_VFCCU_FHFLTENC00_EN21_SHIFT         (21U)
1358 #define CE_L_VFCCU_FHFLTENC00_EN21_WIDTH         (1U)
1359 #define CE_L_VFCCU_FHFLTENC00_EN21(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN21_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN21_MASK)
1360 
1361 #define CE_L_VFCCU_FHFLTENC00_EN22_MASK          (0x400000U)
1362 #define CE_L_VFCCU_FHFLTENC00_EN22_SHIFT         (22U)
1363 #define CE_L_VFCCU_FHFLTENC00_EN22_WIDTH         (1U)
1364 #define CE_L_VFCCU_FHFLTENC00_EN22(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN22_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN22_MASK)
1365 
1366 #define CE_L_VFCCU_FHFLTENC00_EN23_MASK          (0x800000U)
1367 #define CE_L_VFCCU_FHFLTENC00_EN23_SHIFT         (23U)
1368 #define CE_L_VFCCU_FHFLTENC00_EN23_WIDTH         (1U)
1369 #define CE_L_VFCCU_FHFLTENC00_EN23(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN23_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN23_MASK)
1370 
1371 #define CE_L_VFCCU_FHFLTENC00_EN24_MASK          (0x1000000U)
1372 #define CE_L_VFCCU_FHFLTENC00_EN24_SHIFT         (24U)
1373 #define CE_L_VFCCU_FHFLTENC00_EN24_WIDTH         (1U)
1374 #define CE_L_VFCCU_FHFLTENC00_EN24(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN24_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN24_MASK)
1375 
1376 #define CE_L_VFCCU_FHFLTENC00_EN25_MASK          (0x2000000U)
1377 #define CE_L_VFCCU_FHFLTENC00_EN25_SHIFT         (25U)
1378 #define CE_L_VFCCU_FHFLTENC00_EN25_WIDTH         (1U)
1379 #define CE_L_VFCCU_FHFLTENC00_EN25(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN25_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN25_MASK)
1380 
1381 #define CE_L_VFCCU_FHFLTENC00_EN26_MASK          (0x4000000U)
1382 #define CE_L_VFCCU_FHFLTENC00_EN26_SHIFT         (26U)
1383 #define CE_L_VFCCU_FHFLTENC00_EN26_WIDTH         (1U)
1384 #define CE_L_VFCCU_FHFLTENC00_EN26(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN26_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN26_MASK)
1385 
1386 #define CE_L_VFCCU_FHFLTENC00_EN27_MASK          (0x8000000U)
1387 #define CE_L_VFCCU_FHFLTENC00_EN27_SHIFT         (27U)
1388 #define CE_L_VFCCU_FHFLTENC00_EN27_WIDTH         (1U)
1389 #define CE_L_VFCCU_FHFLTENC00_EN27(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN27_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN27_MASK)
1390 
1391 #define CE_L_VFCCU_FHFLTENC00_EN28_MASK          (0x10000000U)
1392 #define CE_L_VFCCU_FHFLTENC00_EN28_SHIFT         (28U)
1393 #define CE_L_VFCCU_FHFLTENC00_EN28_WIDTH         (1U)
1394 #define CE_L_VFCCU_FHFLTENC00_EN28(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN28_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN28_MASK)
1395 
1396 #define CE_L_VFCCU_FHFLTENC00_EN29_MASK          (0x20000000U)
1397 #define CE_L_VFCCU_FHFLTENC00_EN29_SHIFT         (29U)
1398 #define CE_L_VFCCU_FHFLTENC00_EN29_WIDTH         (1U)
1399 #define CE_L_VFCCU_FHFLTENC00_EN29(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN29_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN29_MASK)
1400 
1401 #define CE_L_VFCCU_FHFLTENC00_EN30_MASK          (0x40000000U)
1402 #define CE_L_VFCCU_FHFLTENC00_EN30_SHIFT         (30U)
1403 #define CE_L_VFCCU_FHFLTENC00_EN30_WIDTH         (1U)
1404 #define CE_L_VFCCU_FHFLTENC00_EN30(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN30_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN30_MASK)
1405 
1406 #define CE_L_VFCCU_FHFLTENC00_EN31_MASK          (0x80000000U)
1407 #define CE_L_VFCCU_FHFLTENC00_EN31_SHIFT         (31U)
1408 #define CE_L_VFCCU_FHFLTENC00_EN31_WIDTH         (1U)
1409 #define CE_L_VFCCU_FHFLTENC00_EN31(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC00_EN31_SHIFT)) & CE_L_VFCCU_FHFLTENC00_EN31_MASK)
1410 /*! @} */
1411 
1412 /*! @name FHFLTENC01 - Fault Enable */
1413 /*! @{ */
1414 
1415 #define CE_L_VFCCU_FHFLTENC01_EN32_MASK          (0x1U)
1416 #define CE_L_VFCCU_FHFLTENC01_EN32_SHIFT         (0U)
1417 #define CE_L_VFCCU_FHFLTENC01_EN32_WIDTH         (1U)
1418 #define CE_L_VFCCU_FHFLTENC01_EN32(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN32_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN32_MASK)
1419 
1420 #define CE_L_VFCCU_FHFLTENC01_EN33_MASK          (0x2U)
1421 #define CE_L_VFCCU_FHFLTENC01_EN33_SHIFT         (1U)
1422 #define CE_L_VFCCU_FHFLTENC01_EN33_WIDTH         (1U)
1423 #define CE_L_VFCCU_FHFLTENC01_EN33(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN33_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN33_MASK)
1424 
1425 #define CE_L_VFCCU_FHFLTENC01_EN34_MASK          (0x4U)
1426 #define CE_L_VFCCU_FHFLTENC01_EN34_SHIFT         (2U)
1427 #define CE_L_VFCCU_FHFLTENC01_EN34_WIDTH         (1U)
1428 #define CE_L_VFCCU_FHFLTENC01_EN34(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN34_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN34_MASK)
1429 
1430 #define CE_L_VFCCU_FHFLTENC01_EN35_MASK          (0x8U)
1431 #define CE_L_VFCCU_FHFLTENC01_EN35_SHIFT         (3U)
1432 #define CE_L_VFCCU_FHFLTENC01_EN35_WIDTH         (1U)
1433 #define CE_L_VFCCU_FHFLTENC01_EN35(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN35_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN35_MASK)
1434 
1435 #define CE_L_VFCCU_FHFLTENC01_EN36_MASK          (0x10U)
1436 #define CE_L_VFCCU_FHFLTENC01_EN36_SHIFT         (4U)
1437 #define CE_L_VFCCU_FHFLTENC01_EN36_WIDTH         (1U)
1438 #define CE_L_VFCCU_FHFLTENC01_EN36(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN36_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN36_MASK)
1439 
1440 #define CE_L_VFCCU_FHFLTENC01_EN37_MASK          (0x20U)
1441 #define CE_L_VFCCU_FHFLTENC01_EN37_SHIFT         (5U)
1442 #define CE_L_VFCCU_FHFLTENC01_EN37_WIDTH         (1U)
1443 #define CE_L_VFCCU_FHFLTENC01_EN37(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN37_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN37_MASK)
1444 
1445 #define CE_L_VFCCU_FHFLTENC01_EN38_MASK          (0x40U)
1446 #define CE_L_VFCCU_FHFLTENC01_EN38_SHIFT         (6U)
1447 #define CE_L_VFCCU_FHFLTENC01_EN38_WIDTH         (1U)
1448 #define CE_L_VFCCU_FHFLTENC01_EN38(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN38_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN38_MASK)
1449 
1450 #define CE_L_VFCCU_FHFLTENC01_EN39_MASK          (0x80U)
1451 #define CE_L_VFCCU_FHFLTENC01_EN39_SHIFT         (7U)
1452 #define CE_L_VFCCU_FHFLTENC01_EN39_WIDTH         (1U)
1453 #define CE_L_VFCCU_FHFLTENC01_EN39(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN39_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN39_MASK)
1454 
1455 #define CE_L_VFCCU_FHFLTENC01_EN40_MASK          (0x100U)
1456 #define CE_L_VFCCU_FHFLTENC01_EN40_SHIFT         (8U)
1457 #define CE_L_VFCCU_FHFLTENC01_EN40_WIDTH         (1U)
1458 #define CE_L_VFCCU_FHFLTENC01_EN40(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN40_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN40_MASK)
1459 
1460 #define CE_L_VFCCU_FHFLTENC01_EN41_MASK          (0x200U)
1461 #define CE_L_VFCCU_FHFLTENC01_EN41_SHIFT         (9U)
1462 #define CE_L_VFCCU_FHFLTENC01_EN41_WIDTH         (1U)
1463 #define CE_L_VFCCU_FHFLTENC01_EN41(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN41_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN41_MASK)
1464 
1465 #define CE_L_VFCCU_FHFLTENC01_EN42_MASK          (0x400U)
1466 #define CE_L_VFCCU_FHFLTENC01_EN42_SHIFT         (10U)
1467 #define CE_L_VFCCU_FHFLTENC01_EN42_WIDTH         (1U)
1468 #define CE_L_VFCCU_FHFLTENC01_EN42(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN42_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN42_MASK)
1469 
1470 #define CE_L_VFCCU_FHFLTENC01_EN43_MASK          (0x800U)
1471 #define CE_L_VFCCU_FHFLTENC01_EN43_SHIFT         (11U)
1472 #define CE_L_VFCCU_FHFLTENC01_EN43_WIDTH         (1U)
1473 #define CE_L_VFCCU_FHFLTENC01_EN43(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN43_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN43_MASK)
1474 
1475 #define CE_L_VFCCU_FHFLTENC01_EN44_MASK          (0x1000U)
1476 #define CE_L_VFCCU_FHFLTENC01_EN44_SHIFT         (12U)
1477 #define CE_L_VFCCU_FHFLTENC01_EN44_WIDTH         (1U)
1478 #define CE_L_VFCCU_FHFLTENC01_EN44(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN44_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN44_MASK)
1479 
1480 #define CE_L_VFCCU_FHFLTENC01_EN45_MASK          (0x2000U)
1481 #define CE_L_VFCCU_FHFLTENC01_EN45_SHIFT         (13U)
1482 #define CE_L_VFCCU_FHFLTENC01_EN45_WIDTH         (1U)
1483 #define CE_L_VFCCU_FHFLTENC01_EN45(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN45_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN45_MASK)
1484 
1485 #define CE_L_VFCCU_FHFLTENC01_EN46_MASK          (0x4000U)
1486 #define CE_L_VFCCU_FHFLTENC01_EN46_SHIFT         (14U)
1487 #define CE_L_VFCCU_FHFLTENC01_EN46_WIDTH         (1U)
1488 #define CE_L_VFCCU_FHFLTENC01_EN46(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN46_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN46_MASK)
1489 
1490 #define CE_L_VFCCU_FHFLTENC01_EN47_MASK          (0x8000U)
1491 #define CE_L_VFCCU_FHFLTENC01_EN47_SHIFT         (15U)
1492 #define CE_L_VFCCU_FHFLTENC01_EN47_WIDTH         (1U)
1493 #define CE_L_VFCCU_FHFLTENC01_EN47(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN47_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN47_MASK)
1494 
1495 #define CE_L_VFCCU_FHFLTENC01_EN48_MASK          (0x10000U)
1496 #define CE_L_VFCCU_FHFLTENC01_EN48_SHIFT         (16U)
1497 #define CE_L_VFCCU_FHFLTENC01_EN48_WIDTH         (1U)
1498 #define CE_L_VFCCU_FHFLTENC01_EN48(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN48_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN48_MASK)
1499 
1500 #define CE_L_VFCCU_FHFLTENC01_EN49_MASK          (0x20000U)
1501 #define CE_L_VFCCU_FHFLTENC01_EN49_SHIFT         (17U)
1502 #define CE_L_VFCCU_FHFLTENC01_EN49_WIDTH         (1U)
1503 #define CE_L_VFCCU_FHFLTENC01_EN49(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN49_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN49_MASK)
1504 
1505 #define CE_L_VFCCU_FHFLTENC01_EN50_MASK          (0x40000U)
1506 #define CE_L_VFCCU_FHFLTENC01_EN50_SHIFT         (18U)
1507 #define CE_L_VFCCU_FHFLTENC01_EN50_WIDTH         (1U)
1508 #define CE_L_VFCCU_FHFLTENC01_EN50(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN50_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN50_MASK)
1509 
1510 #define CE_L_VFCCU_FHFLTENC01_EN51_MASK          (0x80000U)
1511 #define CE_L_VFCCU_FHFLTENC01_EN51_SHIFT         (19U)
1512 #define CE_L_VFCCU_FHFLTENC01_EN51_WIDTH         (1U)
1513 #define CE_L_VFCCU_FHFLTENC01_EN51(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN51_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN51_MASK)
1514 
1515 #define CE_L_VFCCU_FHFLTENC01_EN52_MASK          (0x100000U)
1516 #define CE_L_VFCCU_FHFLTENC01_EN52_SHIFT         (20U)
1517 #define CE_L_VFCCU_FHFLTENC01_EN52_WIDTH         (1U)
1518 #define CE_L_VFCCU_FHFLTENC01_EN52(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTENC01_EN52_SHIFT)) & CE_L_VFCCU_FHFLTENC01_EN52_MASK)
1519 /*! @} */
1520 
1521 /*! @name FHFLTS00 - Fault Status */
1522 /*! @{ */
1523 
1524 #define CE_L_VFCCU_FHFLTS00_STAT0_MASK           (0x1U)
1525 #define CE_L_VFCCU_FHFLTS00_STAT0_SHIFT          (0U)
1526 #define CE_L_VFCCU_FHFLTS00_STAT0_WIDTH          (1U)
1527 #define CE_L_VFCCU_FHFLTS00_STAT0(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT0_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT0_MASK)
1528 
1529 #define CE_L_VFCCU_FHFLTS00_STAT1_MASK           (0x2U)
1530 #define CE_L_VFCCU_FHFLTS00_STAT1_SHIFT          (1U)
1531 #define CE_L_VFCCU_FHFLTS00_STAT1_WIDTH          (1U)
1532 #define CE_L_VFCCU_FHFLTS00_STAT1(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT1_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT1_MASK)
1533 
1534 #define CE_L_VFCCU_FHFLTS00_STAT2_MASK           (0x4U)
1535 #define CE_L_VFCCU_FHFLTS00_STAT2_SHIFT          (2U)
1536 #define CE_L_VFCCU_FHFLTS00_STAT2_WIDTH          (1U)
1537 #define CE_L_VFCCU_FHFLTS00_STAT2(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT2_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT2_MASK)
1538 
1539 #define CE_L_VFCCU_FHFLTS00_STAT3_MASK           (0x8U)
1540 #define CE_L_VFCCU_FHFLTS00_STAT3_SHIFT          (3U)
1541 #define CE_L_VFCCU_FHFLTS00_STAT3_WIDTH          (1U)
1542 #define CE_L_VFCCU_FHFLTS00_STAT3(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT3_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT3_MASK)
1543 
1544 #define CE_L_VFCCU_FHFLTS00_STAT4_MASK           (0x10U)
1545 #define CE_L_VFCCU_FHFLTS00_STAT4_SHIFT          (4U)
1546 #define CE_L_VFCCU_FHFLTS00_STAT4_WIDTH          (1U)
1547 #define CE_L_VFCCU_FHFLTS00_STAT4(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT4_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT4_MASK)
1548 
1549 #define CE_L_VFCCU_FHFLTS00_STAT5_MASK           (0x20U)
1550 #define CE_L_VFCCU_FHFLTS00_STAT5_SHIFT          (5U)
1551 #define CE_L_VFCCU_FHFLTS00_STAT5_WIDTH          (1U)
1552 #define CE_L_VFCCU_FHFLTS00_STAT5(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT5_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT5_MASK)
1553 
1554 #define CE_L_VFCCU_FHFLTS00_STAT6_MASK           (0x40U)
1555 #define CE_L_VFCCU_FHFLTS00_STAT6_SHIFT          (6U)
1556 #define CE_L_VFCCU_FHFLTS00_STAT6_WIDTH          (1U)
1557 #define CE_L_VFCCU_FHFLTS00_STAT6(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT6_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT6_MASK)
1558 
1559 #define CE_L_VFCCU_FHFLTS00_STAT7_MASK           (0x80U)
1560 #define CE_L_VFCCU_FHFLTS00_STAT7_SHIFT          (7U)
1561 #define CE_L_VFCCU_FHFLTS00_STAT7_WIDTH          (1U)
1562 #define CE_L_VFCCU_FHFLTS00_STAT7(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT7_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT7_MASK)
1563 
1564 #define CE_L_VFCCU_FHFLTS00_STAT8_MASK           (0x100U)
1565 #define CE_L_VFCCU_FHFLTS00_STAT8_SHIFT          (8U)
1566 #define CE_L_VFCCU_FHFLTS00_STAT8_WIDTH          (1U)
1567 #define CE_L_VFCCU_FHFLTS00_STAT8(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT8_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT8_MASK)
1568 
1569 #define CE_L_VFCCU_FHFLTS00_STAT9_MASK           (0x200U)
1570 #define CE_L_VFCCU_FHFLTS00_STAT9_SHIFT          (9U)
1571 #define CE_L_VFCCU_FHFLTS00_STAT9_WIDTH          (1U)
1572 #define CE_L_VFCCU_FHFLTS00_STAT9(x)             (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT9_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT9_MASK)
1573 
1574 #define CE_L_VFCCU_FHFLTS00_STAT10_MASK          (0x400U)
1575 #define CE_L_VFCCU_FHFLTS00_STAT10_SHIFT         (10U)
1576 #define CE_L_VFCCU_FHFLTS00_STAT10_WIDTH         (1U)
1577 #define CE_L_VFCCU_FHFLTS00_STAT10(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT10_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT10_MASK)
1578 
1579 #define CE_L_VFCCU_FHFLTS00_STAT11_MASK          (0x800U)
1580 #define CE_L_VFCCU_FHFLTS00_STAT11_SHIFT         (11U)
1581 #define CE_L_VFCCU_FHFLTS00_STAT11_WIDTH         (1U)
1582 #define CE_L_VFCCU_FHFLTS00_STAT11(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT11_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT11_MASK)
1583 
1584 #define CE_L_VFCCU_FHFLTS00_STAT12_MASK          (0x1000U)
1585 #define CE_L_VFCCU_FHFLTS00_STAT12_SHIFT         (12U)
1586 #define CE_L_VFCCU_FHFLTS00_STAT12_WIDTH         (1U)
1587 #define CE_L_VFCCU_FHFLTS00_STAT12(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT12_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT12_MASK)
1588 
1589 #define CE_L_VFCCU_FHFLTS00_STAT13_MASK          (0x2000U)
1590 #define CE_L_VFCCU_FHFLTS00_STAT13_SHIFT         (13U)
1591 #define CE_L_VFCCU_FHFLTS00_STAT13_WIDTH         (1U)
1592 #define CE_L_VFCCU_FHFLTS00_STAT13(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT13_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT13_MASK)
1593 
1594 #define CE_L_VFCCU_FHFLTS00_STAT14_MASK          (0x4000U)
1595 #define CE_L_VFCCU_FHFLTS00_STAT14_SHIFT         (14U)
1596 #define CE_L_VFCCU_FHFLTS00_STAT14_WIDTH         (1U)
1597 #define CE_L_VFCCU_FHFLTS00_STAT14(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT14_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT14_MASK)
1598 
1599 #define CE_L_VFCCU_FHFLTS00_STAT15_MASK          (0x8000U)
1600 #define CE_L_VFCCU_FHFLTS00_STAT15_SHIFT         (15U)
1601 #define CE_L_VFCCU_FHFLTS00_STAT15_WIDTH         (1U)
1602 #define CE_L_VFCCU_FHFLTS00_STAT15(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT15_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT15_MASK)
1603 
1604 #define CE_L_VFCCU_FHFLTS00_STAT16_MASK          (0x10000U)
1605 #define CE_L_VFCCU_FHFLTS00_STAT16_SHIFT         (16U)
1606 #define CE_L_VFCCU_FHFLTS00_STAT16_WIDTH         (1U)
1607 #define CE_L_VFCCU_FHFLTS00_STAT16(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT16_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT16_MASK)
1608 
1609 #define CE_L_VFCCU_FHFLTS00_STAT17_MASK          (0x20000U)
1610 #define CE_L_VFCCU_FHFLTS00_STAT17_SHIFT         (17U)
1611 #define CE_L_VFCCU_FHFLTS00_STAT17_WIDTH         (1U)
1612 #define CE_L_VFCCU_FHFLTS00_STAT17(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT17_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT17_MASK)
1613 
1614 #define CE_L_VFCCU_FHFLTS00_STAT18_MASK          (0x40000U)
1615 #define CE_L_VFCCU_FHFLTS00_STAT18_SHIFT         (18U)
1616 #define CE_L_VFCCU_FHFLTS00_STAT18_WIDTH         (1U)
1617 #define CE_L_VFCCU_FHFLTS00_STAT18(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT18_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT18_MASK)
1618 
1619 #define CE_L_VFCCU_FHFLTS00_STAT19_MASK          (0x80000U)
1620 #define CE_L_VFCCU_FHFLTS00_STAT19_SHIFT         (19U)
1621 #define CE_L_VFCCU_FHFLTS00_STAT19_WIDTH         (1U)
1622 #define CE_L_VFCCU_FHFLTS00_STAT19(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT19_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT19_MASK)
1623 
1624 #define CE_L_VFCCU_FHFLTS00_STAT20_MASK          (0x100000U)
1625 #define CE_L_VFCCU_FHFLTS00_STAT20_SHIFT         (20U)
1626 #define CE_L_VFCCU_FHFLTS00_STAT20_WIDTH         (1U)
1627 #define CE_L_VFCCU_FHFLTS00_STAT20(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT20_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT20_MASK)
1628 
1629 #define CE_L_VFCCU_FHFLTS00_STAT21_MASK          (0x200000U)
1630 #define CE_L_VFCCU_FHFLTS00_STAT21_SHIFT         (21U)
1631 #define CE_L_VFCCU_FHFLTS00_STAT21_WIDTH         (1U)
1632 #define CE_L_VFCCU_FHFLTS00_STAT21(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT21_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT21_MASK)
1633 
1634 #define CE_L_VFCCU_FHFLTS00_STAT22_MASK          (0x400000U)
1635 #define CE_L_VFCCU_FHFLTS00_STAT22_SHIFT         (22U)
1636 #define CE_L_VFCCU_FHFLTS00_STAT22_WIDTH         (1U)
1637 #define CE_L_VFCCU_FHFLTS00_STAT22(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT22_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT22_MASK)
1638 
1639 #define CE_L_VFCCU_FHFLTS00_STAT23_MASK          (0x800000U)
1640 #define CE_L_VFCCU_FHFLTS00_STAT23_SHIFT         (23U)
1641 #define CE_L_VFCCU_FHFLTS00_STAT23_WIDTH         (1U)
1642 #define CE_L_VFCCU_FHFLTS00_STAT23(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT23_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT23_MASK)
1643 
1644 #define CE_L_VFCCU_FHFLTS00_STAT24_MASK          (0x1000000U)
1645 #define CE_L_VFCCU_FHFLTS00_STAT24_SHIFT         (24U)
1646 #define CE_L_VFCCU_FHFLTS00_STAT24_WIDTH         (1U)
1647 #define CE_L_VFCCU_FHFLTS00_STAT24(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT24_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT24_MASK)
1648 
1649 #define CE_L_VFCCU_FHFLTS00_STAT25_MASK          (0x2000000U)
1650 #define CE_L_VFCCU_FHFLTS00_STAT25_SHIFT         (25U)
1651 #define CE_L_VFCCU_FHFLTS00_STAT25_WIDTH         (1U)
1652 #define CE_L_VFCCU_FHFLTS00_STAT25(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT25_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT25_MASK)
1653 
1654 #define CE_L_VFCCU_FHFLTS00_STAT26_MASK          (0x4000000U)
1655 #define CE_L_VFCCU_FHFLTS00_STAT26_SHIFT         (26U)
1656 #define CE_L_VFCCU_FHFLTS00_STAT26_WIDTH         (1U)
1657 #define CE_L_VFCCU_FHFLTS00_STAT26(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT26_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT26_MASK)
1658 
1659 #define CE_L_VFCCU_FHFLTS00_STAT27_MASK          (0x8000000U)
1660 #define CE_L_VFCCU_FHFLTS00_STAT27_SHIFT         (27U)
1661 #define CE_L_VFCCU_FHFLTS00_STAT27_WIDTH         (1U)
1662 #define CE_L_VFCCU_FHFLTS00_STAT27(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT27_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT27_MASK)
1663 
1664 #define CE_L_VFCCU_FHFLTS00_STAT28_MASK          (0x10000000U)
1665 #define CE_L_VFCCU_FHFLTS00_STAT28_SHIFT         (28U)
1666 #define CE_L_VFCCU_FHFLTS00_STAT28_WIDTH         (1U)
1667 #define CE_L_VFCCU_FHFLTS00_STAT28(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT28_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT28_MASK)
1668 
1669 #define CE_L_VFCCU_FHFLTS00_STAT29_MASK          (0x20000000U)
1670 #define CE_L_VFCCU_FHFLTS00_STAT29_SHIFT         (29U)
1671 #define CE_L_VFCCU_FHFLTS00_STAT29_WIDTH         (1U)
1672 #define CE_L_VFCCU_FHFLTS00_STAT29(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT29_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT29_MASK)
1673 
1674 #define CE_L_VFCCU_FHFLTS00_STAT30_MASK          (0x40000000U)
1675 #define CE_L_VFCCU_FHFLTS00_STAT30_SHIFT         (30U)
1676 #define CE_L_VFCCU_FHFLTS00_STAT30_WIDTH         (1U)
1677 #define CE_L_VFCCU_FHFLTS00_STAT30(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT30_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT30_MASK)
1678 
1679 #define CE_L_VFCCU_FHFLTS00_STAT31_MASK          (0x80000000U)
1680 #define CE_L_VFCCU_FHFLTS00_STAT31_SHIFT         (31U)
1681 #define CE_L_VFCCU_FHFLTS00_STAT31_WIDTH         (1U)
1682 #define CE_L_VFCCU_FHFLTS00_STAT31(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS00_STAT31_SHIFT)) & CE_L_VFCCU_FHFLTS00_STAT31_MASK)
1683 /*! @} */
1684 
1685 /*! @name FHFLTS01 - Fault Status */
1686 /*! @{ */
1687 
1688 #define CE_L_VFCCU_FHFLTS01_STAT32_MASK          (0x1U)
1689 #define CE_L_VFCCU_FHFLTS01_STAT32_SHIFT         (0U)
1690 #define CE_L_VFCCU_FHFLTS01_STAT32_WIDTH         (1U)
1691 #define CE_L_VFCCU_FHFLTS01_STAT32(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT32_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT32_MASK)
1692 
1693 #define CE_L_VFCCU_FHFLTS01_STAT33_MASK          (0x2U)
1694 #define CE_L_VFCCU_FHFLTS01_STAT33_SHIFT         (1U)
1695 #define CE_L_VFCCU_FHFLTS01_STAT33_WIDTH         (1U)
1696 #define CE_L_VFCCU_FHFLTS01_STAT33(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT33_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT33_MASK)
1697 
1698 #define CE_L_VFCCU_FHFLTS01_STAT34_MASK          (0x4U)
1699 #define CE_L_VFCCU_FHFLTS01_STAT34_SHIFT         (2U)
1700 #define CE_L_VFCCU_FHFLTS01_STAT34_WIDTH         (1U)
1701 #define CE_L_VFCCU_FHFLTS01_STAT34(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT34_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT34_MASK)
1702 
1703 #define CE_L_VFCCU_FHFLTS01_STAT35_MASK          (0x8U)
1704 #define CE_L_VFCCU_FHFLTS01_STAT35_SHIFT         (3U)
1705 #define CE_L_VFCCU_FHFLTS01_STAT35_WIDTH         (1U)
1706 #define CE_L_VFCCU_FHFLTS01_STAT35(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT35_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT35_MASK)
1707 
1708 #define CE_L_VFCCU_FHFLTS01_STAT36_MASK          (0x10U)
1709 #define CE_L_VFCCU_FHFLTS01_STAT36_SHIFT         (4U)
1710 #define CE_L_VFCCU_FHFLTS01_STAT36_WIDTH         (1U)
1711 #define CE_L_VFCCU_FHFLTS01_STAT36(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT36_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT36_MASK)
1712 
1713 #define CE_L_VFCCU_FHFLTS01_STAT37_MASK          (0x20U)
1714 #define CE_L_VFCCU_FHFLTS01_STAT37_SHIFT         (5U)
1715 #define CE_L_VFCCU_FHFLTS01_STAT37_WIDTH         (1U)
1716 #define CE_L_VFCCU_FHFLTS01_STAT37(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT37_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT37_MASK)
1717 
1718 #define CE_L_VFCCU_FHFLTS01_STAT38_MASK          (0x40U)
1719 #define CE_L_VFCCU_FHFLTS01_STAT38_SHIFT         (6U)
1720 #define CE_L_VFCCU_FHFLTS01_STAT38_WIDTH         (1U)
1721 #define CE_L_VFCCU_FHFLTS01_STAT38(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT38_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT38_MASK)
1722 
1723 #define CE_L_VFCCU_FHFLTS01_STAT39_MASK          (0x80U)
1724 #define CE_L_VFCCU_FHFLTS01_STAT39_SHIFT         (7U)
1725 #define CE_L_VFCCU_FHFLTS01_STAT39_WIDTH         (1U)
1726 #define CE_L_VFCCU_FHFLTS01_STAT39(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT39_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT39_MASK)
1727 
1728 #define CE_L_VFCCU_FHFLTS01_STAT40_MASK          (0x100U)
1729 #define CE_L_VFCCU_FHFLTS01_STAT40_SHIFT         (8U)
1730 #define CE_L_VFCCU_FHFLTS01_STAT40_WIDTH         (1U)
1731 #define CE_L_VFCCU_FHFLTS01_STAT40(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT40_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT40_MASK)
1732 
1733 #define CE_L_VFCCU_FHFLTS01_STAT41_MASK          (0x200U)
1734 #define CE_L_VFCCU_FHFLTS01_STAT41_SHIFT         (9U)
1735 #define CE_L_VFCCU_FHFLTS01_STAT41_WIDTH         (1U)
1736 #define CE_L_VFCCU_FHFLTS01_STAT41(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT41_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT41_MASK)
1737 
1738 #define CE_L_VFCCU_FHFLTS01_STAT42_MASK          (0x400U)
1739 #define CE_L_VFCCU_FHFLTS01_STAT42_SHIFT         (10U)
1740 #define CE_L_VFCCU_FHFLTS01_STAT42_WIDTH         (1U)
1741 #define CE_L_VFCCU_FHFLTS01_STAT42(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT42_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT42_MASK)
1742 
1743 #define CE_L_VFCCU_FHFLTS01_STAT43_MASK          (0x800U)
1744 #define CE_L_VFCCU_FHFLTS01_STAT43_SHIFT         (11U)
1745 #define CE_L_VFCCU_FHFLTS01_STAT43_WIDTH         (1U)
1746 #define CE_L_VFCCU_FHFLTS01_STAT43(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT43_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT43_MASK)
1747 
1748 #define CE_L_VFCCU_FHFLTS01_STAT44_MASK          (0x1000U)
1749 #define CE_L_VFCCU_FHFLTS01_STAT44_SHIFT         (12U)
1750 #define CE_L_VFCCU_FHFLTS01_STAT44_WIDTH         (1U)
1751 #define CE_L_VFCCU_FHFLTS01_STAT44(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT44_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT44_MASK)
1752 
1753 #define CE_L_VFCCU_FHFLTS01_STAT45_MASK          (0x2000U)
1754 #define CE_L_VFCCU_FHFLTS01_STAT45_SHIFT         (13U)
1755 #define CE_L_VFCCU_FHFLTS01_STAT45_WIDTH         (1U)
1756 #define CE_L_VFCCU_FHFLTS01_STAT45(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT45_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT45_MASK)
1757 
1758 #define CE_L_VFCCU_FHFLTS01_STAT46_MASK          (0x4000U)
1759 #define CE_L_VFCCU_FHFLTS01_STAT46_SHIFT         (14U)
1760 #define CE_L_VFCCU_FHFLTS01_STAT46_WIDTH         (1U)
1761 #define CE_L_VFCCU_FHFLTS01_STAT46(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT46_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT46_MASK)
1762 
1763 #define CE_L_VFCCU_FHFLTS01_STAT47_MASK          (0x8000U)
1764 #define CE_L_VFCCU_FHFLTS01_STAT47_SHIFT         (15U)
1765 #define CE_L_VFCCU_FHFLTS01_STAT47_WIDTH         (1U)
1766 #define CE_L_VFCCU_FHFLTS01_STAT47(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT47_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT47_MASK)
1767 
1768 #define CE_L_VFCCU_FHFLTS01_STAT48_MASK          (0x10000U)
1769 #define CE_L_VFCCU_FHFLTS01_STAT48_SHIFT         (16U)
1770 #define CE_L_VFCCU_FHFLTS01_STAT48_WIDTH         (1U)
1771 #define CE_L_VFCCU_FHFLTS01_STAT48(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT48_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT48_MASK)
1772 
1773 #define CE_L_VFCCU_FHFLTS01_STAT49_MASK          (0x20000U)
1774 #define CE_L_VFCCU_FHFLTS01_STAT49_SHIFT         (17U)
1775 #define CE_L_VFCCU_FHFLTS01_STAT49_WIDTH         (1U)
1776 #define CE_L_VFCCU_FHFLTS01_STAT49(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT49_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT49_MASK)
1777 
1778 #define CE_L_VFCCU_FHFLTS01_STAT50_MASK          (0x40000U)
1779 #define CE_L_VFCCU_FHFLTS01_STAT50_SHIFT         (18U)
1780 #define CE_L_VFCCU_FHFLTS01_STAT50_WIDTH         (1U)
1781 #define CE_L_VFCCU_FHFLTS01_STAT50(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT50_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT50_MASK)
1782 
1783 #define CE_L_VFCCU_FHFLTS01_STAT51_MASK          (0x80000U)
1784 #define CE_L_VFCCU_FHFLTS01_STAT51_SHIFT         (19U)
1785 #define CE_L_VFCCU_FHFLTS01_STAT51_WIDTH         (1U)
1786 #define CE_L_VFCCU_FHFLTS01_STAT51(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT51_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT51_MASK)
1787 
1788 #define CE_L_VFCCU_FHFLTS01_STAT52_MASK          (0x100000U)
1789 #define CE_L_VFCCU_FHFLTS01_STAT52_SHIFT         (20U)
1790 #define CE_L_VFCCU_FHFLTS01_STAT52_WIDTH         (1U)
1791 #define CE_L_VFCCU_FHFLTS01_STAT52(x)            (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTS01_STAT52_SHIFT)) & CE_L_VFCCU_FHFLTS01_STAT52_MASK)
1792 /*! @} */
1793 
1794 /*! @name FHFLTRKC00 - Fault Reaction Set Configuration */
1795 /*! @{ */
1796 
1797 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL0_MASK       (0x7U)
1798 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL0_SHIFT      (0U)
1799 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL0_WIDTH      (3U)
1800 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL0(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC00_RKNSEL0_SHIFT)) & CE_L_VFCCU_FHFLTRKC00_RKNSEL0_MASK)
1801 
1802 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL1_MASK       (0x70U)
1803 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL1_SHIFT      (4U)
1804 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL1_WIDTH      (3U)
1805 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL1(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC00_RKNSEL1_SHIFT)) & CE_L_VFCCU_FHFLTRKC00_RKNSEL1_MASK)
1806 
1807 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL2_MASK       (0x700U)
1808 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL2_SHIFT      (8U)
1809 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL2_WIDTH      (3U)
1810 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL2(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC00_RKNSEL2_SHIFT)) & CE_L_VFCCU_FHFLTRKC00_RKNSEL2_MASK)
1811 
1812 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL3_MASK       (0x7000U)
1813 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL3_SHIFT      (12U)
1814 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL3_WIDTH      (3U)
1815 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL3(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC00_RKNSEL3_SHIFT)) & CE_L_VFCCU_FHFLTRKC00_RKNSEL3_MASK)
1816 
1817 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL4_MASK       (0x70000U)
1818 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL4_SHIFT      (16U)
1819 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL4_WIDTH      (3U)
1820 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL4(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC00_RKNSEL4_SHIFT)) & CE_L_VFCCU_FHFLTRKC00_RKNSEL4_MASK)
1821 
1822 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL5_MASK       (0x700000U)
1823 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL5_SHIFT      (20U)
1824 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL5_WIDTH      (3U)
1825 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL5(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC00_RKNSEL5_SHIFT)) & CE_L_VFCCU_FHFLTRKC00_RKNSEL5_MASK)
1826 
1827 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL6_MASK       (0x7000000U)
1828 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL6_SHIFT      (24U)
1829 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL6_WIDTH      (3U)
1830 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL6(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC00_RKNSEL6_SHIFT)) & CE_L_VFCCU_FHFLTRKC00_RKNSEL6_MASK)
1831 
1832 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL7_MASK       (0x70000000U)
1833 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL7_SHIFT      (28U)
1834 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL7_WIDTH      (3U)
1835 #define CE_L_VFCCU_FHFLTRKC00_RKNSEL7(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC00_RKNSEL7_SHIFT)) & CE_L_VFCCU_FHFLTRKC00_RKNSEL7_MASK)
1836 /*! @} */
1837 
1838 /*! @name FHFLTRKC01 - Fault Reaction Set Configuration */
1839 /*! @{ */
1840 
1841 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL8_MASK       (0x7U)
1842 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL8_SHIFT      (0U)
1843 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL8_WIDTH      (3U)
1844 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL8(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC01_RKNSEL8_SHIFT)) & CE_L_VFCCU_FHFLTRKC01_RKNSEL8_MASK)
1845 
1846 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL9_MASK       (0x70U)
1847 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL9_SHIFT      (4U)
1848 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL9_WIDTH      (3U)
1849 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL9(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC01_RKNSEL9_SHIFT)) & CE_L_VFCCU_FHFLTRKC01_RKNSEL9_MASK)
1850 
1851 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL10_MASK      (0x700U)
1852 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL10_SHIFT     (8U)
1853 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL10_WIDTH     (3U)
1854 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL10(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC01_RKNSEL10_SHIFT)) & CE_L_VFCCU_FHFLTRKC01_RKNSEL10_MASK)
1855 
1856 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL11_MASK      (0x7000U)
1857 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL11_SHIFT     (12U)
1858 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL11_WIDTH     (3U)
1859 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL11(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC01_RKNSEL11_SHIFT)) & CE_L_VFCCU_FHFLTRKC01_RKNSEL11_MASK)
1860 
1861 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL12_MASK      (0x70000U)
1862 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL12_SHIFT     (16U)
1863 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL12_WIDTH     (3U)
1864 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL12(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC01_RKNSEL12_SHIFT)) & CE_L_VFCCU_FHFLTRKC01_RKNSEL12_MASK)
1865 
1866 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL13_MASK      (0x700000U)
1867 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL13_SHIFT     (20U)
1868 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL13_WIDTH     (3U)
1869 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL13(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC01_RKNSEL13_SHIFT)) & CE_L_VFCCU_FHFLTRKC01_RKNSEL13_MASK)
1870 
1871 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL14_MASK      (0x7000000U)
1872 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL14_SHIFT     (24U)
1873 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL14_WIDTH     (3U)
1874 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL14(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC01_RKNSEL14_SHIFT)) & CE_L_VFCCU_FHFLTRKC01_RKNSEL14_MASK)
1875 
1876 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL15_MASK      (0x70000000U)
1877 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL15_SHIFT     (28U)
1878 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL15_WIDTH     (3U)
1879 #define CE_L_VFCCU_FHFLTRKC01_RKNSEL15(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC01_RKNSEL15_SHIFT)) & CE_L_VFCCU_FHFLTRKC01_RKNSEL15_MASK)
1880 /*! @} */
1881 
1882 /*! @name FHFLTRKC02 - Fault Reaction Set Configuration */
1883 /*! @{ */
1884 
1885 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL16_MASK      (0x7U)
1886 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL16_SHIFT     (0U)
1887 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL16_WIDTH     (3U)
1888 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL16(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC02_RKNSEL16_SHIFT)) & CE_L_VFCCU_FHFLTRKC02_RKNSEL16_MASK)
1889 
1890 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL17_MASK      (0x70U)
1891 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL17_SHIFT     (4U)
1892 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL17_WIDTH     (3U)
1893 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL17(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC02_RKNSEL17_SHIFT)) & CE_L_VFCCU_FHFLTRKC02_RKNSEL17_MASK)
1894 
1895 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL18_MASK      (0x700U)
1896 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL18_SHIFT     (8U)
1897 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL18_WIDTH     (3U)
1898 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL18(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC02_RKNSEL18_SHIFT)) & CE_L_VFCCU_FHFLTRKC02_RKNSEL18_MASK)
1899 
1900 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL19_MASK      (0x7000U)
1901 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL19_SHIFT     (12U)
1902 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL19_WIDTH     (3U)
1903 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL19(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC02_RKNSEL19_SHIFT)) & CE_L_VFCCU_FHFLTRKC02_RKNSEL19_MASK)
1904 
1905 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL20_MASK      (0x70000U)
1906 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL20_SHIFT     (16U)
1907 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL20_WIDTH     (3U)
1908 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL20(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC02_RKNSEL20_SHIFT)) & CE_L_VFCCU_FHFLTRKC02_RKNSEL20_MASK)
1909 
1910 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL21_MASK      (0x700000U)
1911 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL21_SHIFT     (20U)
1912 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL21_WIDTH     (3U)
1913 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL21(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC02_RKNSEL21_SHIFT)) & CE_L_VFCCU_FHFLTRKC02_RKNSEL21_MASK)
1914 
1915 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL22_MASK      (0x7000000U)
1916 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL22_SHIFT     (24U)
1917 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL22_WIDTH     (3U)
1918 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL22(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC02_RKNSEL22_SHIFT)) & CE_L_VFCCU_FHFLTRKC02_RKNSEL22_MASK)
1919 
1920 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL23_MASK      (0x70000000U)
1921 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL23_SHIFT     (28U)
1922 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL23_WIDTH     (3U)
1923 #define CE_L_VFCCU_FHFLTRKC02_RKNSEL23(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC02_RKNSEL23_SHIFT)) & CE_L_VFCCU_FHFLTRKC02_RKNSEL23_MASK)
1924 /*! @} */
1925 
1926 /*! @name FHFLTRKC03 - Fault Reaction Set Configuration */
1927 /*! @{ */
1928 
1929 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL24_MASK      (0x7U)
1930 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL24_SHIFT     (0U)
1931 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL24_WIDTH     (3U)
1932 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL24(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC03_RKNSEL24_SHIFT)) & CE_L_VFCCU_FHFLTRKC03_RKNSEL24_MASK)
1933 
1934 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL25_MASK      (0x70U)
1935 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL25_SHIFT     (4U)
1936 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL25_WIDTH     (3U)
1937 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL25(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC03_RKNSEL25_SHIFT)) & CE_L_VFCCU_FHFLTRKC03_RKNSEL25_MASK)
1938 
1939 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL26_MASK      (0x700U)
1940 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL26_SHIFT     (8U)
1941 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL26_WIDTH     (3U)
1942 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL26(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC03_RKNSEL26_SHIFT)) & CE_L_VFCCU_FHFLTRKC03_RKNSEL26_MASK)
1943 
1944 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL27_MASK      (0x7000U)
1945 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL27_SHIFT     (12U)
1946 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL27_WIDTH     (3U)
1947 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL27(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC03_RKNSEL27_SHIFT)) & CE_L_VFCCU_FHFLTRKC03_RKNSEL27_MASK)
1948 
1949 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL28_MASK      (0x70000U)
1950 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL28_SHIFT     (16U)
1951 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL28_WIDTH     (3U)
1952 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL28(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC03_RKNSEL28_SHIFT)) & CE_L_VFCCU_FHFLTRKC03_RKNSEL28_MASK)
1953 
1954 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL29_MASK      (0x700000U)
1955 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL29_SHIFT     (20U)
1956 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL29_WIDTH     (3U)
1957 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL29(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC03_RKNSEL29_SHIFT)) & CE_L_VFCCU_FHFLTRKC03_RKNSEL29_MASK)
1958 
1959 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL30_MASK      (0x7000000U)
1960 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL30_SHIFT     (24U)
1961 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL30_WIDTH     (3U)
1962 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL30(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC03_RKNSEL30_SHIFT)) & CE_L_VFCCU_FHFLTRKC03_RKNSEL30_MASK)
1963 
1964 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL31_MASK      (0x70000000U)
1965 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL31_SHIFT     (28U)
1966 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL31_WIDTH     (3U)
1967 #define CE_L_VFCCU_FHFLTRKC03_RKNSEL31(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC03_RKNSEL31_SHIFT)) & CE_L_VFCCU_FHFLTRKC03_RKNSEL31_MASK)
1968 /*! @} */
1969 
1970 /*! @name FHFLTRKC04 - Fault Reaction Set Configuration */
1971 /*! @{ */
1972 
1973 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL32_MASK      (0x7U)
1974 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL32_SHIFT     (0U)
1975 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL32_WIDTH     (3U)
1976 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL32(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC04_RKNSEL32_SHIFT)) & CE_L_VFCCU_FHFLTRKC04_RKNSEL32_MASK)
1977 
1978 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL33_MASK      (0x70U)
1979 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL33_SHIFT     (4U)
1980 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL33_WIDTH     (3U)
1981 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL33(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC04_RKNSEL33_SHIFT)) & CE_L_VFCCU_FHFLTRKC04_RKNSEL33_MASK)
1982 
1983 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL34_MASK      (0x700U)
1984 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL34_SHIFT     (8U)
1985 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL34_WIDTH     (3U)
1986 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL34(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC04_RKNSEL34_SHIFT)) & CE_L_VFCCU_FHFLTRKC04_RKNSEL34_MASK)
1987 
1988 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL35_MASK      (0x7000U)
1989 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL35_SHIFT     (12U)
1990 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL35_WIDTH     (3U)
1991 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL35(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC04_RKNSEL35_SHIFT)) & CE_L_VFCCU_FHFLTRKC04_RKNSEL35_MASK)
1992 
1993 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL36_MASK      (0x70000U)
1994 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL36_SHIFT     (16U)
1995 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL36_WIDTH     (3U)
1996 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL36(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC04_RKNSEL36_SHIFT)) & CE_L_VFCCU_FHFLTRKC04_RKNSEL36_MASK)
1997 
1998 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL37_MASK      (0x700000U)
1999 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL37_SHIFT     (20U)
2000 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL37_WIDTH     (3U)
2001 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL37(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC04_RKNSEL37_SHIFT)) & CE_L_VFCCU_FHFLTRKC04_RKNSEL37_MASK)
2002 
2003 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL38_MASK      (0x7000000U)
2004 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL38_SHIFT     (24U)
2005 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL38_WIDTH     (3U)
2006 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL38(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC04_RKNSEL38_SHIFT)) & CE_L_VFCCU_FHFLTRKC04_RKNSEL38_MASK)
2007 
2008 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL39_MASK      (0x70000000U)
2009 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL39_SHIFT     (28U)
2010 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL39_WIDTH     (3U)
2011 #define CE_L_VFCCU_FHFLTRKC04_RKNSEL39(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC04_RKNSEL39_SHIFT)) & CE_L_VFCCU_FHFLTRKC04_RKNSEL39_MASK)
2012 /*! @} */
2013 
2014 /*! @name FHFLTRKC05 - Fault Reaction Set Configuration */
2015 /*! @{ */
2016 
2017 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL40_MASK      (0x7U)
2018 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL40_SHIFT     (0U)
2019 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL40_WIDTH     (3U)
2020 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL40(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC05_RKNSEL40_SHIFT)) & CE_L_VFCCU_FHFLTRKC05_RKNSEL40_MASK)
2021 
2022 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL41_MASK      (0x70U)
2023 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL41_SHIFT     (4U)
2024 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL41_WIDTH     (3U)
2025 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL41(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC05_RKNSEL41_SHIFT)) & CE_L_VFCCU_FHFLTRKC05_RKNSEL41_MASK)
2026 
2027 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL42_MASK      (0x700U)
2028 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL42_SHIFT     (8U)
2029 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL42_WIDTH     (3U)
2030 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL42(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC05_RKNSEL42_SHIFT)) & CE_L_VFCCU_FHFLTRKC05_RKNSEL42_MASK)
2031 
2032 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL43_MASK      (0x7000U)
2033 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL43_SHIFT     (12U)
2034 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL43_WIDTH     (3U)
2035 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL43(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC05_RKNSEL43_SHIFT)) & CE_L_VFCCU_FHFLTRKC05_RKNSEL43_MASK)
2036 
2037 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL44_MASK      (0x70000U)
2038 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL44_SHIFT     (16U)
2039 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL44_WIDTH     (3U)
2040 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL44(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC05_RKNSEL44_SHIFT)) & CE_L_VFCCU_FHFLTRKC05_RKNSEL44_MASK)
2041 
2042 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL45_MASK      (0x700000U)
2043 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL45_SHIFT     (20U)
2044 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL45_WIDTH     (3U)
2045 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL45(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC05_RKNSEL45_SHIFT)) & CE_L_VFCCU_FHFLTRKC05_RKNSEL45_MASK)
2046 
2047 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL46_MASK      (0x7000000U)
2048 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL46_SHIFT     (24U)
2049 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL46_WIDTH     (3U)
2050 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL46(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC05_RKNSEL46_SHIFT)) & CE_L_VFCCU_FHFLTRKC05_RKNSEL46_MASK)
2051 
2052 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL47_MASK      (0x70000000U)
2053 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL47_SHIFT     (28U)
2054 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL47_WIDTH     (3U)
2055 #define CE_L_VFCCU_FHFLTRKC05_RKNSEL47(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC05_RKNSEL47_SHIFT)) & CE_L_VFCCU_FHFLTRKC05_RKNSEL47_MASK)
2056 /*! @} */
2057 
2058 /*! @name FHFLTRKC06 - Fault Reaction Set Configuration */
2059 /*! @{ */
2060 
2061 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL48_MASK      (0x7U)
2062 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL48_SHIFT     (0U)
2063 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL48_WIDTH     (3U)
2064 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL48(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC06_RKNSEL48_SHIFT)) & CE_L_VFCCU_FHFLTRKC06_RKNSEL48_MASK)
2065 
2066 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL49_MASK      (0x70U)
2067 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL49_SHIFT     (4U)
2068 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL49_WIDTH     (3U)
2069 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL49(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC06_RKNSEL49_SHIFT)) & CE_L_VFCCU_FHFLTRKC06_RKNSEL49_MASK)
2070 
2071 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL50_MASK      (0x700U)
2072 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL50_SHIFT     (8U)
2073 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL50_WIDTH     (3U)
2074 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL50(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC06_RKNSEL50_SHIFT)) & CE_L_VFCCU_FHFLTRKC06_RKNSEL50_MASK)
2075 
2076 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL51_MASK      (0x7000U)
2077 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL51_SHIFT     (12U)
2078 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL51_WIDTH     (3U)
2079 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL51(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC06_RKNSEL51_SHIFT)) & CE_L_VFCCU_FHFLTRKC06_RKNSEL51_MASK)
2080 
2081 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL52_MASK      (0x70000U)
2082 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL52_SHIFT     (16U)
2083 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL52_WIDTH     (3U)
2084 #define CE_L_VFCCU_FHFLTRKC06_RKNSEL52(x)        (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHFLTRKC06_RKNSEL52_SHIFT)) & CE_L_VFCCU_FHFLTRKC06_RKNSEL52_MASK)
2085 /*! @} */
2086 
2087 /*! @name FHIMRKC0_00 - Immediate Reaction Configuration */
2088 /*! @{ */
2089 
2090 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN0_MASK       (0x1U)
2091 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN0_SHIFT      (0U)
2092 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN0_WIDTH      (1U)
2093 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN0(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_00_RKNEN0_SHIFT)) & CE_L_VFCCU_FHIMRKC0_00_RKNEN0_MASK)
2094 
2095 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN1_MASK       (0x2U)
2096 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN1_SHIFT      (1U)
2097 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN1_WIDTH      (1U)
2098 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN1(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_00_RKNEN1_SHIFT)) & CE_L_VFCCU_FHIMRKC0_00_RKNEN1_MASK)
2099 
2100 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN2_MASK       (0x4U)
2101 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN2_SHIFT      (2U)
2102 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN2_WIDTH      (1U)
2103 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN2(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_00_RKNEN2_SHIFT)) & CE_L_VFCCU_FHIMRKC0_00_RKNEN2_MASK)
2104 
2105 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN3_MASK       (0x8U)
2106 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN3_SHIFT      (3U)
2107 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN3_WIDTH      (1U)
2108 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN3(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_00_RKNEN3_SHIFT)) & CE_L_VFCCU_FHIMRKC0_00_RKNEN3_MASK)
2109 
2110 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN4_MASK       (0x10U)
2111 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN4_SHIFT      (4U)
2112 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN4_WIDTH      (1U)
2113 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN4(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_00_RKNEN4_SHIFT)) & CE_L_VFCCU_FHIMRKC0_00_RKNEN4_MASK)
2114 
2115 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN5_MASK       (0x20U)
2116 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN5_SHIFT      (5U)
2117 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN5_WIDTH      (1U)
2118 #define CE_L_VFCCU_FHIMRKC0_00_RKNEN5(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_00_RKNEN5_SHIFT)) & CE_L_VFCCU_FHIMRKC0_00_RKNEN5_MASK)
2119 /*! @} */
2120 
2121 /*! @name FHIMRKC0_10 - Immediate Reaction Configuration */
2122 /*! @{ */
2123 
2124 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN0_MASK       (0x1U)
2125 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN0_SHIFT      (0U)
2126 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN0_WIDTH      (1U)
2127 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN0(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_10_RKNEN0_SHIFT)) & CE_L_VFCCU_FHIMRKC0_10_RKNEN0_MASK)
2128 
2129 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN1_MASK       (0x2U)
2130 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN1_SHIFT      (1U)
2131 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN1_WIDTH      (1U)
2132 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN1(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_10_RKNEN1_SHIFT)) & CE_L_VFCCU_FHIMRKC0_10_RKNEN1_MASK)
2133 
2134 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN2_MASK       (0x4U)
2135 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN2_SHIFT      (2U)
2136 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN2_WIDTH      (1U)
2137 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN2(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_10_RKNEN2_SHIFT)) & CE_L_VFCCU_FHIMRKC0_10_RKNEN2_MASK)
2138 
2139 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN3_MASK       (0x8U)
2140 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN3_SHIFT      (3U)
2141 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN3_WIDTH      (1U)
2142 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN3(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_10_RKNEN3_SHIFT)) & CE_L_VFCCU_FHIMRKC0_10_RKNEN3_MASK)
2143 
2144 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN4_MASK       (0x10U)
2145 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN4_SHIFT      (4U)
2146 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN4_WIDTH      (1U)
2147 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN4(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_10_RKNEN4_SHIFT)) & CE_L_VFCCU_FHIMRKC0_10_RKNEN4_MASK)
2148 
2149 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN5_MASK       (0x20U)
2150 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN5_SHIFT      (5U)
2151 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN5_WIDTH      (1U)
2152 #define CE_L_VFCCU_FHIMRKC0_10_RKNEN5(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_10_RKNEN5_SHIFT)) & CE_L_VFCCU_FHIMRKC0_10_RKNEN5_MASK)
2153 /*! @} */
2154 
2155 /*! @name FHIMRKC0_20 - Immediate Reaction Configuration */
2156 /*! @{ */
2157 
2158 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN0_MASK       (0x1U)
2159 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN0_SHIFT      (0U)
2160 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN0_WIDTH      (1U)
2161 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN0(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_20_RKNEN0_SHIFT)) & CE_L_VFCCU_FHIMRKC0_20_RKNEN0_MASK)
2162 
2163 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN1_MASK       (0x2U)
2164 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN1_SHIFT      (1U)
2165 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN1_WIDTH      (1U)
2166 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN1(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_20_RKNEN1_SHIFT)) & CE_L_VFCCU_FHIMRKC0_20_RKNEN1_MASK)
2167 
2168 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN2_MASK       (0x4U)
2169 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN2_SHIFT      (2U)
2170 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN2_WIDTH      (1U)
2171 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN2(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_20_RKNEN2_SHIFT)) & CE_L_VFCCU_FHIMRKC0_20_RKNEN2_MASK)
2172 
2173 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN3_MASK       (0x8U)
2174 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN3_SHIFT      (3U)
2175 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN3_WIDTH      (1U)
2176 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN3(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_20_RKNEN3_SHIFT)) & CE_L_VFCCU_FHIMRKC0_20_RKNEN3_MASK)
2177 
2178 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN4_MASK       (0x10U)
2179 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN4_SHIFT      (4U)
2180 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN4_WIDTH      (1U)
2181 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN4(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_20_RKNEN4_SHIFT)) & CE_L_VFCCU_FHIMRKC0_20_RKNEN4_MASK)
2182 
2183 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN5_MASK       (0x20U)
2184 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN5_SHIFT      (5U)
2185 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN5_WIDTH      (1U)
2186 #define CE_L_VFCCU_FHIMRKC0_20_RKNEN5(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_20_RKNEN5_SHIFT)) & CE_L_VFCCU_FHIMRKC0_20_RKNEN5_MASK)
2187 /*! @} */
2188 
2189 /*! @name FHIMRKC0_30 - Immediate Reaction Configuration */
2190 /*! @{ */
2191 
2192 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN0_MASK       (0x1U)
2193 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN0_SHIFT      (0U)
2194 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN0_WIDTH      (1U)
2195 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN0(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_30_RKNEN0_SHIFT)) & CE_L_VFCCU_FHIMRKC0_30_RKNEN0_MASK)
2196 
2197 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN1_MASK       (0x2U)
2198 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN1_SHIFT      (1U)
2199 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN1_WIDTH      (1U)
2200 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN1(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_30_RKNEN1_SHIFT)) & CE_L_VFCCU_FHIMRKC0_30_RKNEN1_MASK)
2201 
2202 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN2_MASK       (0x4U)
2203 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN2_SHIFT      (2U)
2204 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN2_WIDTH      (1U)
2205 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN2(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_30_RKNEN2_SHIFT)) & CE_L_VFCCU_FHIMRKC0_30_RKNEN2_MASK)
2206 
2207 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN3_MASK       (0x8U)
2208 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN3_SHIFT      (3U)
2209 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN3_WIDTH      (1U)
2210 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN3(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_30_RKNEN3_SHIFT)) & CE_L_VFCCU_FHIMRKC0_30_RKNEN3_MASK)
2211 
2212 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN4_MASK       (0x10U)
2213 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN4_SHIFT      (4U)
2214 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN4_WIDTH      (1U)
2215 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN4(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_30_RKNEN4_SHIFT)) & CE_L_VFCCU_FHIMRKC0_30_RKNEN4_MASK)
2216 
2217 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN5_MASK       (0x20U)
2218 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN5_SHIFT      (5U)
2219 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN5_WIDTH      (1U)
2220 #define CE_L_VFCCU_FHIMRKC0_30_RKNEN5(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_30_RKNEN5_SHIFT)) & CE_L_VFCCU_FHIMRKC0_30_RKNEN5_MASK)
2221 /*! @} */
2222 
2223 /*! @name FHIMRKC0_40 - Immediate Reaction Configuration */
2224 /*! @{ */
2225 
2226 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN0_MASK       (0x1U)
2227 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN0_SHIFT      (0U)
2228 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN0_WIDTH      (1U)
2229 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN0(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_40_RKNEN0_SHIFT)) & CE_L_VFCCU_FHIMRKC0_40_RKNEN0_MASK)
2230 
2231 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN1_MASK       (0x2U)
2232 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN1_SHIFT      (1U)
2233 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN1_WIDTH      (1U)
2234 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN1(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_40_RKNEN1_SHIFT)) & CE_L_VFCCU_FHIMRKC0_40_RKNEN1_MASK)
2235 
2236 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN2_MASK       (0x4U)
2237 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN2_SHIFT      (2U)
2238 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN2_WIDTH      (1U)
2239 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN2(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_40_RKNEN2_SHIFT)) & CE_L_VFCCU_FHIMRKC0_40_RKNEN2_MASK)
2240 
2241 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN3_MASK       (0x8U)
2242 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN3_SHIFT      (3U)
2243 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN3_WIDTH      (1U)
2244 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN3(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_40_RKNEN3_SHIFT)) & CE_L_VFCCU_FHIMRKC0_40_RKNEN3_MASK)
2245 
2246 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN4_MASK       (0x10U)
2247 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN4_SHIFT      (4U)
2248 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN4_WIDTH      (1U)
2249 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN4(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_40_RKNEN4_SHIFT)) & CE_L_VFCCU_FHIMRKC0_40_RKNEN4_MASK)
2250 
2251 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN5_MASK       (0x20U)
2252 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN5_SHIFT      (5U)
2253 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN5_WIDTH      (1U)
2254 #define CE_L_VFCCU_FHIMRKC0_40_RKNEN5(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_40_RKNEN5_SHIFT)) & CE_L_VFCCU_FHIMRKC0_40_RKNEN5_MASK)
2255 /*! @} */
2256 
2257 /*! @name FHIMRKC0_50 - Immediate Reaction Configuration */
2258 /*! @{ */
2259 
2260 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN0_MASK       (0x1U)
2261 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN0_SHIFT      (0U)
2262 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN0_WIDTH      (1U)
2263 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN0(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_50_RKNEN0_SHIFT)) & CE_L_VFCCU_FHIMRKC0_50_RKNEN0_MASK)
2264 
2265 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN1_MASK       (0x2U)
2266 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN1_SHIFT      (1U)
2267 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN1_WIDTH      (1U)
2268 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN1(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_50_RKNEN1_SHIFT)) & CE_L_VFCCU_FHIMRKC0_50_RKNEN1_MASK)
2269 
2270 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN2_MASK       (0x4U)
2271 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN2_SHIFT      (2U)
2272 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN2_WIDTH      (1U)
2273 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN2(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_50_RKNEN2_SHIFT)) & CE_L_VFCCU_FHIMRKC0_50_RKNEN2_MASK)
2274 
2275 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN3_MASK       (0x8U)
2276 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN3_SHIFT      (3U)
2277 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN3_WIDTH      (1U)
2278 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN3(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_50_RKNEN3_SHIFT)) & CE_L_VFCCU_FHIMRKC0_50_RKNEN3_MASK)
2279 
2280 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN4_MASK       (0x10U)
2281 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN4_SHIFT      (4U)
2282 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN4_WIDTH      (1U)
2283 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN4(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_50_RKNEN4_SHIFT)) & CE_L_VFCCU_FHIMRKC0_50_RKNEN4_MASK)
2284 
2285 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN5_MASK       (0x20U)
2286 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN5_SHIFT      (5U)
2287 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN5_WIDTH      (1U)
2288 #define CE_L_VFCCU_FHIMRKC0_50_RKNEN5(x)         (((uint32_t)(((uint32_t)(x)) << CE_L_VFCCU_FHIMRKC0_50_RKNEN5_SHIFT)) & CE_L_VFCCU_FHIMRKC0_50_RKNEN5_MASK)
2289 /*! @} */
2290 
2291 /*!
2292  * @}
2293  */ /* end of group CE_L_VFCCU_Register_Masks */
2294 
2295 /*!
2296  * @}
2297  */ /* end of group CE_L_VFCCU_Peripheral_Access_Layer */
2298 
2299 #endif  /* #if !defined(S32Z2_CE_L_VFCCU_H_) */
2300