1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_LLC_CSR.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_LLC_CSR 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_LLC_CSR_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_LLC_CSR_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LLC_CSR Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LLC_CSR_Peripheral_Access_Layer LLC_CSR Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LLC_CSR - Size of Registers Arrays */ 72 #define LLC_CSR_CCUWPCR_COUNT 8u 73 74 /** LLC_CSR - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t CCUTCR; /**< Transaction Control, offset: 0x0 */ 77 __I uint32_t CCUTAR; /**< Transaction Activity, offset: 0x4 */ 78 uint8_t RESERVED_0[8]; 79 __IO uint32_t CCUCTCR; /**< Cache Transaction Control, offset: 0x10 */ 80 __I uint32_t CCUCTAR; /**< Cache Transaction Activity, offset: 0x14 */ 81 __IO uint32_t CCUCAOR; /**< Allocation Override, offset: 0x18 */ 82 uint8_t RESERVED_1[4]; 83 __IO uint32_t CCUSPCR0; /**< Scratchpad Configuration 0, offset: 0x20 */ 84 __IO uint32_t CCUSPCR1; /**< Scratchpad Configuration 1, offset: 0x24 */ 85 __IO uint32_t CCUSPBR0; /**< Scratchpad Base Address 0, offset: 0x28 */ 86 uint8_t RESERVED_2[20]; 87 struct LLC_CSR_CCUWPCR { /* offset: 0x40, array step: 0x8 */ 88 __IO uint32_t CCUWPCRA; /**< Way Partitioning Control A 0..Way Partitioning Control A 7, array offset: 0x40, array step: 0x8 */ 89 __IO uint32_t CCUWPCRB; /**< Way Partitioning Control B 0..Way Partitioning Control B 7, array offset: 0x44, array step: 0x8 */ 90 } CCUWPCR[LLC_CSR_CCUWPCR_COUNT]; 91 uint8_t RESERVED_3[128]; 92 __IO uint32_t CCUCMCR; /**< Maintenance Control, offset: 0x100 */ 93 __I uint32_t CCUCMAR; /**< Maintenance Activity, offset: 0x104 */ 94 __IO uint32_t CCUCMLR0; /**< Maintenance Location 0, offset: 0x108 */ 95 __IO uint32_t CCUCMLR1; /**< Maintenance Location 1, offset: 0x10C */ 96 __IO uint32_t CCUCMLR2; /**< Maintenance Location 2, offset: 0x110 */ 97 __IO uint32_t CCUCMDR; /**< Maintenance Data, offset: 0x114 */ 98 uint8_t RESERVED_4[40]; 99 __IO uint32_t CCUCECR; /**< Correctable Error Control, offset: 0x140 */ 100 __IO uint32_t CCUCESR; /**< Correctable Error Status, offset: 0x144 */ 101 __IO uint32_t CCUCESAR; /**< Correctable Error Status Alias, offset: 0x148 */ 102 __I uint32_t CCUCELR0; /**< Correctable Error Location 0, offset: 0x14C */ 103 __I uint32_t CCUCELR1; /**< Correctable Error Location 1, offset: 0x150 */ 104 __IO uint32_t CCUUEDR; /**< Uncorrectable Error Detect, offset: 0x154 */ 105 __IO uint32_t CCUUEIR; /**< Uncorrectable Error Interrupt, offset: 0x158 */ 106 __IO uint32_t CCUUESR; /**< Uncorrectable Error Status, offset: 0x15C */ 107 __IO uint32_t CCUUESAR; /**< Uncorrectable Error Status Alias, offset: 0x160 */ 108 __I uint32_t CCUUELR0; /**< Uncorrectable Error Location 0, offset: 0x164 */ 109 __I uint32_t CCUUELR1; /**< Uncorrectable Error Location 1, offset: 0x168 */ 110 uint8_t RESERVED_5[84]; 111 __I uint32_t CCUIDR; /**< Identification, offset: 0x1C0 */ 112 __IO uint32_t CCUCRTR; /**< Correctable Resiliency Threshold, offset: 0x1C4 */ 113 } LLC_CSR_Type, *LLC_CSR_MemMapPtr; 114 115 /** Number of instances of the LLC_CSR module. */ 116 #define LLC_CSR_INSTANCE_COUNT (2u) 117 118 /* LLC_CSR - Peripheral instance base addresses */ 119 /** Peripheral RTU0__LLC_CSR base address */ 120 #define IP_RTU0__LLC_CSR_BASE (0x76050000u) 121 /** Peripheral RTU0__LLC_CSR base pointer */ 122 #define IP_RTU0__LLC_CSR ((LLC_CSR_Type *)IP_RTU0__LLC_CSR_BASE) 123 /** Peripheral RTU1__LLC_CSR base address */ 124 #define IP_RTU1__LLC_CSR_BASE (0x76850000u) 125 /** Peripheral RTU1__LLC_CSR base pointer */ 126 #define IP_RTU1__LLC_CSR ((LLC_CSR_Type *)IP_RTU1__LLC_CSR_BASE) 127 /** Array initializer of LLC_CSR peripheral base addresses */ 128 #define IP_LLC_CSR_BASE_ADDRS { IP_RTU0__LLC_CSR_BASE, IP_RTU1__LLC_CSR_BASE } 129 /** Array initializer of LLC_CSR peripheral base pointers */ 130 #define IP_LLC_CSR_BASE_PTRS { IP_RTU0__LLC_CSR, IP_RTU1__LLC_CSR } 131 132 /* ---------------------------------------------------------------------------- 133 -- LLC_CSR Register Masks 134 ---------------------------------------------------------------------------- */ 135 136 /*! 137 * @addtogroup LLC_CSR_Register_Masks LLC_CSR Register Masks 138 * @{ 139 */ 140 141 /*! @name CCUTCR - Transaction Control */ 142 /*! @{ */ 143 144 #define LLC_CSR_CCUTCR_TransEn_MASK (0x1U) 145 #define LLC_CSR_CCUTCR_TransEn_SHIFT (0U) 146 #define LLC_CSR_CCUTCR_TransEn_WIDTH (1U) 147 #define LLC_CSR_CCUTCR_TransEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUTCR_TransEn_SHIFT)) & LLC_CSR_CCUTCR_TransEn_MASK) 148 /*! @} */ 149 150 /*! @name CCUTAR - Transaction Activity */ 151 /*! @{ */ 152 153 #define LLC_CSR_CCUTAR_TransActv_MASK (0x1U) 154 #define LLC_CSR_CCUTAR_TransActv_SHIFT (0U) 155 #define LLC_CSR_CCUTAR_TransActv_WIDTH (1U) 156 #define LLC_CSR_CCUTAR_TransActv(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUTAR_TransActv_SHIFT)) & LLC_CSR_CCUTAR_TransActv_MASK) 157 /*! @} */ 158 159 /*! @name CCUCTCR - Cache Transaction Control */ 160 /*! @{ */ 161 162 #define LLC_CSR_CCUCTCR_LookupEn_MASK (0x1U) 163 #define LLC_CSR_CCUCTCR_LookupEn_SHIFT (0U) 164 #define LLC_CSR_CCUCTCR_LookupEn_WIDTH (1U) 165 #define LLC_CSR_CCUCTCR_LookupEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCTCR_LookupEn_SHIFT)) & LLC_CSR_CCUCTCR_LookupEn_MASK) 166 167 #define LLC_CSR_CCUCTCR_FillEn_MASK (0x2U) 168 #define LLC_CSR_CCUCTCR_FillEn_SHIFT (1U) 169 #define LLC_CSR_CCUCTCR_FillEn_WIDTH (1U) 170 #define LLC_CSR_CCUCTCR_FillEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCTCR_FillEn_SHIFT)) & LLC_CSR_CCUCTCR_FillEn_MASK) 171 /*! @} */ 172 173 /*! @name CCUCTAR - Cache Transaction Activity */ 174 /*! @{ */ 175 176 #define LLC_CSR_CCUCTAR_EvictActv_MASK (0x1U) 177 #define LLC_CSR_CCUCTAR_EvictActv_SHIFT (0U) 178 #define LLC_CSR_CCUCTAR_EvictActv_WIDTH (1U) 179 #define LLC_CSR_CCUCTAR_EvictActv(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCTAR_EvictActv_SHIFT)) & LLC_CSR_CCUCTAR_EvictActv_MASK) 180 181 #define LLC_CSR_CCUCTAR_FillActv_MASK (0x2U) 182 #define LLC_CSR_CCUCTAR_FillActv_SHIFT (1U) 183 #define LLC_CSR_CCUCTAR_FillActv_WIDTH (1U) 184 #define LLC_CSR_CCUCTAR_FillActv(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCTAR_FillActv_SHIFT)) & LLC_CSR_CCUCTAR_FillActv_MASK) 185 186 #define LLC_CSR_CCUCTAR_FlushActv_MASK (0x4U) 187 #define LLC_CSR_CCUCTAR_FlushActv_SHIFT (2U) 188 #define LLC_CSR_CCUCTAR_FlushActv_WIDTH (1U) 189 #define LLC_CSR_CCUCTAR_FlushActv(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCTAR_FlushActv_SHIFT)) & LLC_CSR_CCUCTAR_FlushActv_MASK) 190 /*! @} */ 191 192 /*! @name CCUCAOR - Allocation Override */ 193 /*! @{ */ 194 195 #define LLC_CSR_CCUCAOR_AwAllocEn_MASK (0x1U) 196 #define LLC_CSR_CCUCAOR_AwAllocEn_SHIFT (0U) 197 #define LLC_CSR_CCUCAOR_AwAllocEn_WIDTH (1U) 198 #define LLC_CSR_CCUCAOR_AwAllocEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCAOR_AwAllocEn_SHIFT)) & LLC_CSR_CCUCAOR_AwAllocEn_MASK) 199 200 #define LLC_CSR_CCUCAOR_ArAllocEn_MASK (0x2U) 201 #define LLC_CSR_CCUCAOR_ArAllocEn_SHIFT (1U) 202 #define LLC_CSR_CCUCAOR_ArAllocEn_WIDTH (1U) 203 #define LLC_CSR_CCUCAOR_ArAllocEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCAOR_ArAllocEn_SHIFT)) & LLC_CSR_CCUCAOR_ArAllocEn_MASK) 204 205 #define LLC_CSR_CCUCAOR_WrAllocPartialEn_MASK (0x4U) 206 #define LLC_CSR_CCUCAOR_WrAllocPartialEn_SHIFT (2U) 207 #define LLC_CSR_CCUCAOR_WrAllocPartialEn_WIDTH (1U) 208 #define LLC_CSR_CCUCAOR_WrAllocPartialEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCAOR_WrAllocPartialEn_SHIFT)) & LLC_CSR_CCUCAOR_WrAllocPartialEn_MASK) 209 210 #define LLC_CSR_CCUCAOR_AwAllocValue_MASK (0xF0000U) 211 #define LLC_CSR_CCUCAOR_AwAllocValue_SHIFT (16U) 212 #define LLC_CSR_CCUCAOR_AwAllocValue_WIDTH (4U) 213 #define LLC_CSR_CCUCAOR_AwAllocValue(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCAOR_AwAllocValue_SHIFT)) & LLC_CSR_CCUCAOR_AwAllocValue_MASK) 214 215 #define LLC_CSR_CCUCAOR_ArAllocValue_MASK (0xF00000U) 216 #define LLC_CSR_CCUCAOR_ArAllocValue_SHIFT (20U) 217 #define LLC_CSR_CCUCAOR_ArAllocValue_WIDTH (4U) 218 #define LLC_CSR_CCUCAOR_ArAllocValue(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCAOR_ArAllocValue_SHIFT)) & LLC_CSR_CCUCAOR_ArAllocValue_MASK) 219 /*! @} */ 220 221 /*! @name CCUSPCR0 - Scratchpad Configuration 0 */ 222 /*! @{ */ 223 224 #define LLC_CSR_CCUSPCR0_ScPadEn_MASK (0x1U) 225 #define LLC_CSR_CCUSPCR0_ScPadEn_SHIFT (0U) 226 #define LLC_CSR_CCUSPCR0_ScPadEn_WIDTH (1U) 227 #define LLC_CSR_CCUSPCR0_ScPadEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUSPCR0_ScPadEn_SHIFT)) & LLC_CSR_CCUSPCR0_ScPadEn_MASK) 228 229 #define LLC_CSR_CCUSPCR0_NumScPadWays_MASK (0x70000U) 230 #define LLC_CSR_CCUSPCR0_NumScPadWays_SHIFT (16U) 231 #define LLC_CSR_CCUSPCR0_NumScPadWays_WIDTH (3U) 232 #define LLC_CSR_CCUSPCR0_NumScPadWays(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUSPCR0_NumScPadWays_SHIFT)) & LLC_CSR_CCUSPCR0_NumScPadWays_MASK) 233 /*! @} */ 234 235 /*! @name CCUSPCR1 - Scratchpad Configuration 1 */ 236 /*! @{ */ 237 238 #define LLC_CSR_CCUSPCR1_ScPadSize_MASK (0xFFFFFFFFU) 239 #define LLC_CSR_CCUSPCR1_ScPadSize_SHIFT (0U) 240 #define LLC_CSR_CCUSPCR1_ScPadSize_WIDTH (32U) 241 #define LLC_CSR_CCUSPCR1_ScPadSize(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUSPCR1_ScPadSize_SHIFT)) & LLC_CSR_CCUSPCR1_ScPadSize_MASK) 242 /*! @} */ 243 244 /*! @name CCUSPBR0 - Scratchpad Base Address 0 */ 245 /*! @{ */ 246 247 #define LLC_CSR_CCUSPBR0_ScPadBaseAddr_MASK (0xFFFFFFFFU) 248 #define LLC_CSR_CCUSPBR0_ScPadBaseAddr_SHIFT (0U) 249 #define LLC_CSR_CCUSPBR0_ScPadBaseAddr_WIDTH (32U) 250 #define LLC_CSR_CCUSPBR0_ScPadBaseAddr(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUSPBR0_ScPadBaseAddr_SHIFT)) & LLC_CSR_CCUSPBR0_ScPadBaseAddr_MASK) 251 /*! @} */ 252 253 /*! @name CCUWPCRA - Way Partitioning Control A 0..Way Partitioning Control A 7 */ 254 /*! @{ */ 255 256 #define LLC_CSR_CCUWPCRA_WpAgentId_MASK (0xFU) 257 #define LLC_CSR_CCUWPCRA_WpAgentId_SHIFT (0U) 258 #define LLC_CSR_CCUWPCRA_WpAgentId_WIDTH (4U) 259 #define LLC_CSR_CCUWPCRA_WpAgentId(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUWPCRA_WpAgentId_SHIFT)) & LLC_CSR_CCUWPCRA_WpAgentId_MASK) 260 261 #define LLC_CSR_CCUWPCRA_WpAgentIdValid_MASK (0x80000000U) 262 #define LLC_CSR_CCUWPCRA_WpAgentIdValid_SHIFT (31U) 263 #define LLC_CSR_CCUWPCRA_WpAgentIdValid_WIDTH (1U) 264 #define LLC_CSR_CCUWPCRA_WpAgentIdValid(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUWPCRA_WpAgentIdValid_SHIFT)) & LLC_CSR_CCUWPCRA_WpAgentIdValid_MASK) 265 /*! @} */ 266 267 /*! @name CCUWPCRB - Way Partitioning Control B 0..Way Partitioning Control B 7 */ 268 /*! @{ */ 269 270 #define LLC_CSR_CCUWPCRB_WpWayVector_MASK (0xFFU) 271 #define LLC_CSR_CCUWPCRB_WpWayVector_SHIFT (0U) 272 #define LLC_CSR_CCUWPCRB_WpWayVector_WIDTH (8U) 273 #define LLC_CSR_CCUWPCRB_WpWayVector(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUWPCRB_WpWayVector_SHIFT)) & LLC_CSR_CCUWPCRB_WpWayVector_MASK) 274 /*! @} */ 275 276 /*! @name CCUCMCR - Maintenance Control */ 277 /*! @{ */ 278 279 #define LLC_CSR_CCUCMCR_MntOp_MASK (0xFU) 280 #define LLC_CSR_CCUCMCR_MntOp_SHIFT (0U) 281 #define LLC_CSR_CCUCMCR_MntOp_WIDTH (4U) 282 #define LLC_CSR_CCUCMCR_MntOp(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCMCR_MntOp_SHIFT)) & LLC_CSR_CCUCMCR_MntOp_MASK) 283 284 #define LLC_CSR_CCUCMCR_ArrayID_MASK (0x3F0000U) 285 #define LLC_CSR_CCUCMCR_ArrayID_SHIFT (16U) 286 #define LLC_CSR_CCUCMCR_ArrayID_WIDTH (6U) 287 #define LLC_CSR_CCUCMCR_ArrayID(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCMCR_ArrayID_SHIFT)) & LLC_CSR_CCUCMCR_ArrayID_MASK) 288 289 #define LLC_CSR_CCUCMCR_SecAttr_MASK (0x400000U) 290 #define LLC_CSR_CCUCMCR_SecAttr_SHIFT (22U) 291 #define LLC_CSR_CCUCMCR_SecAttr_WIDTH (1U) 292 #define LLC_CSR_CCUCMCR_SecAttr(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCMCR_SecAttr_SHIFT)) & LLC_CSR_CCUCMCR_SecAttr_MASK) 293 /*! @} */ 294 295 /*! @name CCUCMAR - Maintenance Activity */ 296 /*! @{ */ 297 298 #define LLC_CSR_CCUCMAR_MntOpActv_MASK (0x1U) 299 #define LLC_CSR_CCUCMAR_MntOpActv_SHIFT (0U) 300 #define LLC_CSR_CCUCMAR_MntOpActv_WIDTH (1U) 301 #define LLC_CSR_CCUCMAR_MntOpActv(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCMAR_MntOpActv_SHIFT)) & LLC_CSR_CCUCMAR_MntOpActv_MASK) 302 /*! @} */ 303 304 /*! @name CCUCMLR0 - Maintenance Location 0 */ 305 /*! @{ */ 306 307 #define LLC_CSR_CCUCMLR0_MntSet_MASK (0x7FFFU) 308 #define LLC_CSR_CCUCMLR0_MntSet_SHIFT (0U) 309 #define LLC_CSR_CCUCMLR0_MntSet_WIDTH (15U) 310 #define LLC_CSR_CCUCMLR0_MntSet(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCMLR0_MntSet_SHIFT)) & LLC_CSR_CCUCMLR0_MntSet_MASK) 311 312 #define LLC_CSR_CCUCMLR0_MntWay_MASK (0x1F8000U) 313 #define LLC_CSR_CCUCMLR0_MntWay_SHIFT (15U) 314 #define LLC_CSR_CCUCMLR0_MntWay_WIDTH (6U) 315 #define LLC_CSR_CCUCMLR0_MntWay(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCMLR0_MntWay_SHIFT)) & LLC_CSR_CCUCMLR0_MntWay_MASK) 316 317 #define LLC_CSR_CCUCMLR0_MntWord_MASK (0xFFE00000U) 318 #define LLC_CSR_CCUCMLR0_MntWord_SHIFT (21U) 319 #define LLC_CSR_CCUCMLR0_MntWord_WIDTH (11U) 320 #define LLC_CSR_CCUCMLR0_MntWord(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCMLR0_MntWord_SHIFT)) & LLC_CSR_CCUCMLR0_MntWord_MASK) 321 /*! @} */ 322 323 /*! @name CCUCMLR1 - Maintenance Location 1 */ 324 /*! @{ */ 325 326 #define LLC_CSR_CCUCMLR1_MntAddr_MASK (0xFFFFU) 327 #define LLC_CSR_CCUCMLR1_MntAddr_SHIFT (0U) 328 #define LLC_CSR_CCUCMLR1_MntAddr_WIDTH (16U) 329 #define LLC_CSR_CCUCMLR1_MntAddr(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCMLR1_MntAddr_SHIFT)) & LLC_CSR_CCUCMLR1_MntAddr_MASK) 330 /*! @} */ 331 332 /*! @name CCUCMLR2 - Maintenance Location 2 */ 333 /*! @{ */ 334 335 #define LLC_CSR_CCUCMLR2_MntRange_MASK (0xFFFFU) 336 #define LLC_CSR_CCUCMLR2_MntRange_SHIFT (0U) 337 #define LLC_CSR_CCUCMLR2_MntRange_WIDTH (16U) 338 #define LLC_CSR_CCUCMLR2_MntRange(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCMLR2_MntRange_SHIFT)) & LLC_CSR_CCUCMLR2_MntRange_MASK) 339 /*! @} */ 340 341 /*! @name CCUCMDR - Maintenance Data */ 342 /*! @{ */ 343 344 #define LLC_CSR_CCUCMDR_MntData_MASK (0xFFFFFFFFU) 345 #define LLC_CSR_CCUCMDR_MntData_SHIFT (0U) 346 #define LLC_CSR_CCUCMDR_MntData_WIDTH (32U) 347 #define LLC_CSR_CCUCMDR_MntData(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCMDR_MntData_SHIFT)) & LLC_CSR_CCUCMDR_MntData_MASK) 348 /*! @} */ 349 350 /*! @name CCUCECR - Correctable Error Control */ 351 /*! @{ */ 352 353 #define LLC_CSR_CCUCECR_ErrDetEn_MASK (0x1U) 354 #define LLC_CSR_CCUCECR_ErrDetEn_SHIFT (0U) 355 #define LLC_CSR_CCUCECR_ErrDetEn_WIDTH (1U) 356 #define LLC_CSR_CCUCECR_ErrDetEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCECR_ErrDetEn_SHIFT)) & LLC_CSR_CCUCECR_ErrDetEn_MASK) 357 358 #define LLC_CSR_CCUCECR_ErrIntEn_MASK (0x2U) 359 #define LLC_CSR_CCUCECR_ErrIntEn_SHIFT (1U) 360 #define LLC_CSR_CCUCECR_ErrIntEn_WIDTH (1U) 361 #define LLC_CSR_CCUCECR_ErrIntEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCECR_ErrIntEn_SHIFT)) & LLC_CSR_CCUCECR_ErrIntEn_MASK) 362 363 #define LLC_CSR_CCUCECR_ErrThreshold_MASK (0xFF0U) 364 #define LLC_CSR_CCUCECR_ErrThreshold_SHIFT (4U) 365 #define LLC_CSR_CCUCECR_ErrThreshold_WIDTH (8U) 366 #define LLC_CSR_CCUCECR_ErrThreshold(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCECR_ErrThreshold_SHIFT)) & LLC_CSR_CCUCECR_ErrThreshold_MASK) 367 /*! @} */ 368 369 /*! @name CCUCESR - Correctable Error Status */ 370 /*! @{ */ 371 372 #define LLC_CSR_CCUCESR_CErrVld_MASK (0x1U) 373 #define LLC_CSR_CCUCESR_CErrVld_SHIFT (0U) 374 #define LLC_CSR_CCUCESR_CErrVld_WIDTH (1U) 375 #define LLC_CSR_CCUCESR_CErrVld(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCESR_CErrVld_SHIFT)) & LLC_CSR_CCUCESR_CErrVld_MASK) 376 377 #define LLC_CSR_CCUCESR_CErrCountOverflow_MASK (0x2U) 378 #define LLC_CSR_CCUCESR_CErrCountOverflow_SHIFT (1U) 379 #define LLC_CSR_CCUCESR_CErrCountOverflow_WIDTH (1U) 380 #define LLC_CSR_CCUCESR_CErrCountOverflow(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCESR_CErrCountOverflow_SHIFT)) & LLC_CSR_CCUCESR_CErrCountOverflow_MASK) 381 382 #define LLC_CSR_CCUCESR_CErrCount_MASK (0x3FCU) 383 #define LLC_CSR_CCUCESR_CErrCount_SHIFT (2U) 384 #define LLC_CSR_CCUCESR_CErrCount_WIDTH (8U) 385 #define LLC_CSR_CCUCESR_CErrCount(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCESR_CErrCount_SHIFT)) & LLC_CSR_CCUCESR_CErrCount_MASK) 386 387 #define LLC_CSR_CCUCESR_CErrType_MASK (0xF800U) 388 #define LLC_CSR_CCUCESR_CErrType_SHIFT (11U) 389 #define LLC_CSR_CCUCESR_CErrType_WIDTH (5U) 390 #define LLC_CSR_CCUCESR_CErrType(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCESR_CErrType_SHIFT)) & LLC_CSR_CCUCESR_CErrType_MASK) 391 392 #define LLC_CSR_CCUCESR_CErrInfo_MASK (0xFFFF0000U) 393 #define LLC_CSR_CCUCESR_CErrInfo_SHIFT (16U) 394 #define LLC_CSR_CCUCESR_CErrInfo_WIDTH (16U) 395 #define LLC_CSR_CCUCESR_CErrInfo(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCESR_CErrInfo_SHIFT)) & LLC_CSR_CCUCESR_CErrInfo_MASK) 396 /*! @} */ 397 398 /*! @name CCUCESAR - Correctable Error Status Alias */ 399 /*! @{ */ 400 401 #define LLC_CSR_CCUCESAR_CErrVld_MASK (0x1U) 402 #define LLC_CSR_CCUCESAR_CErrVld_SHIFT (0U) 403 #define LLC_CSR_CCUCESAR_CErrVld_WIDTH (1U) 404 #define LLC_CSR_CCUCESAR_CErrVld(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCESAR_CErrVld_SHIFT)) & LLC_CSR_CCUCESAR_CErrVld_MASK) 405 406 #define LLC_CSR_CCUCESAR_CErrCountOverflow_MASK (0x2U) 407 #define LLC_CSR_CCUCESAR_CErrCountOverflow_SHIFT (1U) 408 #define LLC_CSR_CCUCESAR_CErrCountOverflow_WIDTH (1U) 409 #define LLC_CSR_CCUCESAR_CErrCountOverflow(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCESAR_CErrCountOverflow_SHIFT)) & LLC_CSR_CCUCESAR_CErrCountOverflow_MASK) 410 411 #define LLC_CSR_CCUCESAR_CErrCount_MASK (0x3FCU) 412 #define LLC_CSR_CCUCESAR_CErrCount_SHIFT (2U) 413 #define LLC_CSR_CCUCESAR_CErrCount_WIDTH (8U) 414 #define LLC_CSR_CCUCESAR_CErrCount(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCESAR_CErrCount_SHIFT)) & LLC_CSR_CCUCESAR_CErrCount_MASK) 415 416 #define LLC_CSR_CCUCESAR_CErrType_MASK (0xF800U) 417 #define LLC_CSR_CCUCESAR_CErrType_SHIFT (11U) 418 #define LLC_CSR_CCUCESAR_CErrType_WIDTH (5U) 419 #define LLC_CSR_CCUCESAR_CErrType(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCESAR_CErrType_SHIFT)) & LLC_CSR_CCUCESAR_CErrType_MASK) 420 421 #define LLC_CSR_CCUCESAR_CErrInfo_MASK (0xFFFF0000U) 422 #define LLC_CSR_CCUCESAR_CErrInfo_SHIFT (16U) 423 #define LLC_CSR_CCUCESAR_CErrInfo_WIDTH (16U) 424 #define LLC_CSR_CCUCESAR_CErrInfo(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCESAR_CErrInfo_SHIFT)) & LLC_CSR_CCUCESAR_CErrInfo_MASK) 425 /*! @} */ 426 427 /*! @name CCUCELR0 - Correctable Error Location 0 */ 428 /*! @{ */ 429 430 #define LLC_CSR_CCUCELR0_ErrEntry_MASK (0x7FFFU) 431 #define LLC_CSR_CCUCELR0_ErrEntry_SHIFT (0U) 432 #define LLC_CSR_CCUCELR0_ErrEntry_WIDTH (15U) 433 #define LLC_CSR_CCUCELR0_ErrEntry(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCELR0_ErrEntry_SHIFT)) & LLC_CSR_CCUCELR0_ErrEntry_MASK) 434 435 #define LLC_CSR_CCUCELR0_ErrWay_MASK (0x1F8000U) 436 #define LLC_CSR_CCUCELR0_ErrWay_SHIFT (15U) 437 #define LLC_CSR_CCUCELR0_ErrWay_WIDTH (6U) 438 #define LLC_CSR_CCUCELR0_ErrWay(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCELR0_ErrWay_SHIFT)) & LLC_CSR_CCUCELR0_ErrWay_MASK) 439 440 #define LLC_CSR_CCUCELR0_ErrWord_MASK (0xFFE00000U) 441 #define LLC_CSR_CCUCELR0_ErrWord_SHIFT (21U) 442 #define LLC_CSR_CCUCELR0_ErrWord_WIDTH (11U) 443 #define LLC_CSR_CCUCELR0_ErrWord(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCELR0_ErrWord_SHIFT)) & LLC_CSR_CCUCELR0_ErrWord_MASK) 444 /*! @} */ 445 446 /*! @name CCUCELR1 - Correctable Error Location 1 */ 447 /*! @{ */ 448 449 #define LLC_CSR_CCUCELR1_ErrAddr_MASK (0xFFFFU) 450 #define LLC_CSR_CCUCELR1_ErrAddr_SHIFT (0U) 451 #define LLC_CSR_CCUCELR1_ErrAddr_WIDTH (16U) 452 #define LLC_CSR_CCUCELR1_ErrAddr(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCELR1_ErrAddr_SHIFT)) & LLC_CSR_CCUCELR1_ErrAddr_MASK) 453 /*! @} */ 454 455 /*! @name CCUUEDR - Uncorrectable Error Detect */ 456 /*! @{ */ 457 458 #define LLC_CSR_CCUUEDR_ProtErrDetEn_MASK (0x1U) 459 #define LLC_CSR_CCUUEDR_ProtErrDetEn_SHIFT (0U) 460 #define LLC_CSR_CCUUEDR_ProtErrDetEn_WIDTH (1U) 461 #define LLC_CSR_CCUUEDR_ProtErrDetEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUEDR_ProtErrDetEn_SHIFT)) & LLC_CSR_CCUUEDR_ProtErrDetEn_MASK) 462 463 #define LLC_CSR_CCUUEDR_MemErrDetEn_MASK (0x2U) 464 #define LLC_CSR_CCUUEDR_MemErrDetEn_SHIFT (1U) 465 #define LLC_CSR_CCUUEDR_MemErrDetEn_WIDTH (1U) 466 #define LLC_CSR_CCUUEDR_MemErrDetEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUEDR_MemErrDetEn_SHIFT)) & LLC_CSR_CCUUEDR_MemErrDetEn_MASK) 467 /*! @} */ 468 469 /*! @name CCUUEIR - Uncorrectable Error Interrupt */ 470 /*! @{ */ 471 472 #define LLC_CSR_CCUUEIR_ProtErrIntEn_MASK (0x1U) 473 #define LLC_CSR_CCUUEIR_ProtErrIntEn_SHIFT (0U) 474 #define LLC_CSR_CCUUEIR_ProtErrIntEn_WIDTH (1U) 475 #define LLC_CSR_CCUUEIR_ProtErrIntEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUEIR_ProtErrIntEn_SHIFT)) & LLC_CSR_CCUUEIR_ProtErrIntEn_MASK) 476 477 #define LLC_CSR_CCUUEIR_MemErrIntEn_MASK (0x2U) 478 #define LLC_CSR_CCUUEIR_MemErrIntEn_SHIFT (1U) 479 #define LLC_CSR_CCUUEIR_MemErrIntEn_WIDTH (1U) 480 #define LLC_CSR_CCUUEIR_MemErrIntEn(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUEIR_MemErrIntEn_SHIFT)) & LLC_CSR_CCUUEIR_MemErrIntEn_MASK) 481 /*! @} */ 482 483 /*! @name CCUUESR - Uncorrectable Error Status */ 484 /*! @{ */ 485 486 #define LLC_CSR_CCUUESR_UErrVld_MASK (0x1U) 487 #define LLC_CSR_CCUUESR_UErrVld_SHIFT (0U) 488 #define LLC_CSR_CCUUESR_UErrVld_WIDTH (1U) 489 #define LLC_CSR_CCUUESR_UErrVld(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUESR_UErrVld_SHIFT)) & LLC_CSR_CCUUESR_UErrVld_MASK) 490 491 #define LLC_CSR_CCUUESR_UErrType_MASK (0x1F0U) 492 #define LLC_CSR_CCUUESR_UErrType_SHIFT (4U) 493 #define LLC_CSR_CCUUESR_UErrType_WIDTH (5U) 494 #define LLC_CSR_CCUUESR_UErrType(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUESR_UErrType_SHIFT)) & LLC_CSR_CCUUESR_UErrType_MASK) 495 496 #define LLC_CSR_CCUUESR_UErrInfo_MASK (0xFFFF0000U) 497 #define LLC_CSR_CCUUESR_UErrInfo_SHIFT (16U) 498 #define LLC_CSR_CCUUESR_UErrInfo_WIDTH (16U) 499 #define LLC_CSR_CCUUESR_UErrInfo(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUESR_UErrInfo_SHIFT)) & LLC_CSR_CCUUESR_UErrInfo_MASK) 500 /*! @} */ 501 502 /*! @name CCUUESAR - Uncorrectable Error Status Alias */ 503 /*! @{ */ 504 505 #define LLC_CSR_CCUUESAR_UErrVld_MASK (0x1U) 506 #define LLC_CSR_CCUUESAR_UErrVld_SHIFT (0U) 507 #define LLC_CSR_CCUUESAR_UErrVld_WIDTH (1U) 508 #define LLC_CSR_CCUUESAR_UErrVld(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUESAR_UErrVld_SHIFT)) & LLC_CSR_CCUUESAR_UErrVld_MASK) 509 510 #define LLC_CSR_CCUUESAR_UErrType_MASK (0x1F0U) 511 #define LLC_CSR_CCUUESAR_UErrType_SHIFT (4U) 512 #define LLC_CSR_CCUUESAR_UErrType_WIDTH (5U) 513 #define LLC_CSR_CCUUESAR_UErrType(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUESAR_UErrType_SHIFT)) & LLC_CSR_CCUUESAR_UErrType_MASK) 514 515 #define LLC_CSR_CCUUESAR_UErrInfo_MASK (0xFFFF0000U) 516 #define LLC_CSR_CCUUESAR_UErrInfo_SHIFT (16U) 517 #define LLC_CSR_CCUUESAR_UErrInfo_WIDTH (16U) 518 #define LLC_CSR_CCUUESAR_UErrInfo(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUESAR_UErrInfo_SHIFT)) & LLC_CSR_CCUUESAR_UErrInfo_MASK) 519 /*! @} */ 520 521 /*! @name CCUUELR0 - Uncorrectable Error Location 0 */ 522 /*! @{ */ 523 524 #define LLC_CSR_CCUUELR0_ErrEntry_MASK (0x7FFFU) 525 #define LLC_CSR_CCUUELR0_ErrEntry_SHIFT (0U) 526 #define LLC_CSR_CCUUELR0_ErrEntry_WIDTH (15U) 527 #define LLC_CSR_CCUUELR0_ErrEntry(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUELR0_ErrEntry_SHIFT)) & LLC_CSR_CCUUELR0_ErrEntry_MASK) 528 529 #define LLC_CSR_CCUUELR0_ErrWay_MASK (0x1F8000U) 530 #define LLC_CSR_CCUUELR0_ErrWay_SHIFT (15U) 531 #define LLC_CSR_CCUUELR0_ErrWay_WIDTH (6U) 532 #define LLC_CSR_CCUUELR0_ErrWay(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUELR0_ErrWay_SHIFT)) & LLC_CSR_CCUUELR0_ErrWay_MASK) 533 534 #define LLC_CSR_CCUUELR0_ErrWord_MASK (0xFFE00000U) 535 #define LLC_CSR_CCUUELR0_ErrWord_SHIFT (21U) 536 #define LLC_CSR_CCUUELR0_ErrWord_WIDTH (11U) 537 #define LLC_CSR_CCUUELR0_ErrWord(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUELR0_ErrWord_SHIFT)) & LLC_CSR_CCUUELR0_ErrWord_MASK) 538 /*! @} */ 539 540 /*! @name CCUUELR1 - Uncorrectable Error Location 1 */ 541 /*! @{ */ 542 543 #define LLC_CSR_CCUUELR1_ErrAddr_MASK (0xFFFFU) 544 #define LLC_CSR_CCUUELR1_ErrAddr_SHIFT (0U) 545 #define LLC_CSR_CCUUELR1_ErrAddr_WIDTH (16U) 546 #define LLC_CSR_CCUUELR1_ErrAddr(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUUELR1_ErrAddr_SHIFT)) & LLC_CSR_CCUUELR1_ErrAddr_MASK) 547 /*! @} */ 548 549 /*! @name CCUIDR - Identification */ 550 /*! @{ */ 551 552 #define LLC_CSR_CCUIDR_PatchRelVer_MASK (0xFU) 553 #define LLC_CSR_CCUIDR_PatchRelVer_SHIFT (0U) 554 #define LLC_CSR_CCUIDR_PatchRelVer_WIDTH (4U) 555 #define LLC_CSR_CCUIDR_PatchRelVer(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUIDR_PatchRelVer_SHIFT)) & LLC_CSR_CCUIDR_PatchRelVer_MASK) 556 557 #define LLC_CSR_CCUIDR_MinRelVer_MASK (0xF0U) 558 #define LLC_CSR_CCUIDR_MinRelVer_SHIFT (4U) 559 #define LLC_CSR_CCUIDR_MinRelVer_WIDTH (4U) 560 #define LLC_CSR_CCUIDR_MinRelVer(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUIDR_MinRelVer_SHIFT)) & LLC_CSR_CCUIDR_MinRelVer_MASK) 561 562 #define LLC_CSR_CCUIDR_MajRelVer_MASK (0xF00U) 563 #define LLC_CSR_CCUIDR_MajRelVer_SHIFT (8U) 564 #define LLC_CSR_CCUIDR_MajRelVer_WIDTH (4U) 565 #define LLC_CSR_CCUIDR_MajRelVer(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUIDR_MajRelVer_SHIFT)) & LLC_CSR_CCUIDR_MajRelVer_MASK) 566 /*! @} */ 567 568 /*! @name CCUCRTR - Correctable Resiliency Threshold */ 569 /*! @{ */ 570 571 #define LLC_CSR_CCUCRTR_ResThreshold_MASK (0xFFU) 572 #define LLC_CSR_CCUCRTR_ResThreshold_SHIFT (0U) 573 #define LLC_CSR_CCUCRTR_ResThreshold_WIDTH (8U) 574 #define LLC_CSR_CCUCRTR_ResThreshold(x) (((uint32_t)(((uint32_t)(x)) << LLC_CSR_CCUCRTR_ResThreshold_SHIFT)) & LLC_CSR_CCUCRTR_ResThreshold_MASK) 575 /*! @} */ 576 577 /*! 578 * @} 579 */ /* end of group LLC_CSR_Register_Masks */ 580 581 /*! 582 * @} 583 */ /* end of group LLC_CSR_Peripheral_Access_Layer */ 584 585 #endif /* #if !defined(S32Z2_LLC_CSR_H_) */ 586
