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Searched refs:CCM_TUPLE (Results 1 – 25 of 44) sorted by relevance

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/hal_nxp-latest/imx/drivers/
Dccm_imx6sx.h48 #define CCM_TUPLE(reg, shift, mask) ((offsetof(CCM_Type, reg) & 0xFF) | ((shift) << 8) | (((mask >>… macro
63 …ccmRootPll1SwClkSel = CCM_TUPLE(CCSR, CCM_CCSR_pll1_sw_clk_sel_SHIFT, CCM_CCSR_pll1_sw_clk_sel…
64 …ccmRootStepSel = CCM_TUPLE(CCSR, CCM_CCSR_step_sel_SHIFT, CCM_CCSR_step_sel_MASK), …
65 …ccmRootPeriph2ClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_periph2_clk_sel_SHIFT, CCM_CBCDR_periph2_clk_…
66 …ccmRootPrePeriph2ClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pre_periph2_clk_sel_SHIFT, CCM_CBCMR_pre_peri…
67 …ccmRootPeriph2Clk2Sel = CCM_TUPLE(CBCMR, CCM_CBCMR_periph2_clk2_sel_SHIFT, CCM_CBCMR_periph2_clk…
68 …ccmRootPll3SwClkSel = CCM_TUPLE(CCSR, CCM_CCSR_pll3_sw_clk_sel_SHIFT, CCM_CCSR_pll3_sw_clk_sel…
69 …ccmRootOcramClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_clk_sel_SHIFT, CCM_CBCDR_ocram_clk_sel_…
70 …ccmRootOcramAltClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_alt_clk_sel_SHIFT, CCM_CBCDR_ocram_alt_…
71 …ccmRootPeriphClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_periph_clk_sel_SHIFT, CCM_CBCDR_periph_clk_se…
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/drivers/
Dfsl_clock.h207 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
404 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
406 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
408 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
409 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
410 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
412 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
414 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
415 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
416 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
397 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
399 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
401 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
402 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
403 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
405 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
407 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
408 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
409 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/drivers/
Dfsl_clock.h207 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
404 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
406 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
408 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
409 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
410 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
412 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
414 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
415 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
416 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/drivers/
Dfsl_clock.h207 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
404 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
406 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
408 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
409 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
410 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
412 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
414 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
415 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
416 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
397 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
399 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
401 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
402 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
403 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
405 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
407 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
408 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
409 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/drivers/
Dfsl_clock.h207 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
404 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
406 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
408 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
409 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
410 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
412 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
414 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
415 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
416 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
397 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
399 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
401 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
402 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
403 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
405 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
407 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
408 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
409 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
397 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
399 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
401 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
402 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
403 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
405 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
407 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
408 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
409 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/drivers/
Dfsl_clock.h207 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
404 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
406 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
408 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
409 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
410 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
412 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
414 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
415 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
416 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
397 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
399 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
401 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
402 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
403 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
405 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
407 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
408 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
409 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
397 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
399 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
401 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
402 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
403 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
405 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
407 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
408 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
409 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/drivers/
Dfsl_clock.h207 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
404 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
406 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
408 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
409 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
410 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
412 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
414 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
415 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
416 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/drivers/
Dfsl_clock.h234 #define CCM_TUPLE(ccgr, root) ((((ccgr)&0xFFFFU) << 16U) | (root)) macro
513 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
515 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
517 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
518 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
519 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
521 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
523 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
524 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
525 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
394 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
396 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
398 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
399 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
400 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
402 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
403 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
404 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
405 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
394 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
396 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
398 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
399 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
400 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
402 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
403 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
404 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
405 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
394 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
396 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
398 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
399 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
400 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
402 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
403 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
404 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
405 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
394 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
396 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
398 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
399 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
400 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
402 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
403 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
404 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
405 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/drivers/
Dfsl_clock.h200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root)) macro
394 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
396 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
398 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
399 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
400 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
402 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
403 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
404 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
405 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/drivers/
Dfsl_clock.h228 #define CCM_TUPLE(ccgr, root) ((((ccgr)&0xFFFFU) << 16U) | (root)) macro
507 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
509 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
511 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
512 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
513 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
515 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
517 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
518 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
519 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/drivers/
Dfsl_clock.h228 #define CCM_TUPLE(ccgr, root) ((((ccgr)&0xFFFFU) << 16U) | (root)) macro
507 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
509 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
511 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
512 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
513 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
515 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
517 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
518 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
519 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/drivers/
Dfsl_clock.h228 #define CCM_TUPLE(ccgr, root) ((((ccgr)&0xFFFFU) << 16U) | (root)) macro
507 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
509 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
511 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
512 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
513 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
515 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
517 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
518 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
519 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/drivers/
Dfsl_clock.h84 #define CCM_TUPLE(reg, shift, mask, busyShift) \ macro
672 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
677 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
681 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
685 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
690 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
694 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
698 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
702 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
707 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/drivers/
Dfsl_clock.h84 #define CCM_TUPLE(reg, shift, mask, busyShift) \ macro
667 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
672 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
676 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
680 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
685 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
689 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
693 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
697 kCLOCK_Flexspi2Mux = CCM_TUPLE(CBCMR_OFFSET,
701 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/drivers/
Dfsl_clock.h84 #define CCM_TUPLE(reg, shift, mask, busyShift) \ macro
673 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
678 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
682 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
686 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
691 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
695 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
699 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
703 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
708 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
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