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Searched refs:CCM_REG (Results 1 – 25 of 46) sorted by relevance

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/hal_nxp-latest/imx/drivers/
Dccm_imx7d.c48 CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & in CCM_SetRootDivider()
63 *pre = (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT; in CCM_GetRootDivider()
64 *post = (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT; in CCM_GetRootDivider()
78 CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & in CCM_UpdateRoot()
Dccm_imx7d.h49 #define CCM_REG(root) CCM_REG_OFF(root, 0) macro
357 CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & (~CCM_TARGET_ROOT_MUX_MASK)) | in CCM_SetRootMux()
370 return (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CCM_GetRootMux()
406 return (bool)(CCM_REG(ccmRoot) & CCM_TARGET_ROOT_ENABLE_MASK); in CCM_IsRootEnabled()
456 CCM_REG(ccmGate) = control; in CCM_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/drivers/
Dfsl_clock.h168 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1038 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1051 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1084 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1118 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1131 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1186 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/drivers/
Dfsl_clock.h177 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1086 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1099 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1132 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1166 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1179 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1195 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
Dfsl_clock.c883 …CCM_REG(ccmRootClk) = (CCM_REG(ccmRootClk) & (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_PO… in CLOCK_SetRootDivider()
901 CCM_REG(ccmRootClk) = in CLOCK_UpdateRoot()
902 (CCM_REG(ccmRootClk) & in CLOCK_UpdateRoot()
944 CCM_REG(ccgr) = (uintptr_t)kCLOCK_ClockNotNeeded; in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/drivers/
Dfsl_clock.h170 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1093 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1106 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1139 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1173 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1186 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1202 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
Dfsl_clock.c889 …CCM_REG(ccmRootClk) = (CCM_REG(ccmRootClk) & (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_PO… in CLOCK_SetRootDivider()
907 CCM_REG(ccmRootClk) = in CLOCK_UpdateRoot()
908 (CCM_REG(ccmRootClk) & in CLOCK_UpdateRoot()
950 CCM_REG(ccgr) = (uintptr_t)kCLOCK_ClockNotNeeded; in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/drivers/
Dfsl_clock.h177 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1086 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1099 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1132 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1166 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1179 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1195 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
Dfsl_clock.c883 …CCM_REG(ccmRootClk) = (CCM_REG(ccmRootClk) & (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_PO… in CLOCK_SetRootDivider()
901 CCM_REG(ccmRootClk) = in CLOCK_UpdateRoot()
902 (CCM_REG(ccmRootClk) & in CLOCK_UpdateRoot()
944 CCM_REG(ccgr) = (uintptr_t)kCLOCK_ClockNotNeeded; in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/drivers/
Dfsl_clock.h168 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1038 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1051 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1084 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1118 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1131 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1186 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/drivers/
Dfsl_clock.h177 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1086 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1099 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1132 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1166 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1179 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1195 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/drivers/
Dfsl_clock.h170 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1093 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1106 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1139 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1173 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1186 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1202 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
Dfsl_clock.c889 …CCM_REG(ccmRootClk) = (CCM_REG(ccmRootClk) & (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_PO… in CLOCK_SetRootDivider()
907 CCM_REG(ccmRootClk) = in CLOCK_UpdateRoot()
908 (CCM_REG(ccmRootClk) & in CLOCK_UpdateRoot()
950 CCM_REG(ccgr) = (uintptr_t)kCLOCK_ClockNotNeeded; in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/drivers/
Dfsl_clock.h177 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1086 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1099 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1132 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1166 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1179 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1195 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/drivers/
Dfsl_clock.h168 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1038 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1051 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1084 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1118 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1131 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1186 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/drivers/
Dfsl_clock.h170 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1093 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1106 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1139 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1173 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1186 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1202 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/drivers/
Dfsl_clock.h170 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1093 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1106 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1139 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1173 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1186 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1202 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/drivers/
Dfsl_clock.h177 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1086 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1099 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1132 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1166 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1179 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1195 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/drivers/
Dfsl_clock.h170 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1093 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1106 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1139 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1173 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1186 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1202 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/drivers/
Dfsl_clock.h170 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1093 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1106 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1139 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1173 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1186 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1202 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/drivers/
Dfsl_clock.h168 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1038 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1051 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1084 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1118 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1131 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1186 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/drivers/
Dfsl_clock.h177 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1086 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1099 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1132 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1166 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1179 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1195 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
Dfsl_clock.c883 …CCM_REG(ccmRootClk) = (CCM_REG(ccmRootClk) & (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_PO… in CLOCK_SetRootDivider()
901 CCM_REG(ccmRootClk) = in CLOCK_UpdateRoot()
902 (CCM_REG(ccmRootClk) & in CLOCK_UpdateRoot()
944 CCM_REG(ccgr) = (uintptr_t)kCLOCK_ClockNotNeeded; in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/drivers/
Dfsl_clock.h168 #define CCM_REG(root) CCM_REG_OFF(root, 0U) macro
1038 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux); in CLOCK_SetRootMux()
1051 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; in CLOCK_GetRootMux()
1084 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK); in CLOCK_IsRootEnabled()
1118 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U; in CLOCK_GetRootPreDivider()
1131 …return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + … in CLOCK_GetRootPostDivider()
1186 CCM_REG(ccmGate) = (uint32_t)control; in CLOCK_ControlGate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/drivers/
Dfsl_clock.c886 …CCM_REG(ccmRootClk) = (CCM_REG(ccmRootClk) & (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_PO… in CLOCK_SetRootDivider()
904 CCM_REG(ccmRootClk) = in CLOCK_UpdateRoot()
905 (CCM_REG(ccmRootClk) & in CLOCK_UpdateRoot()
971 CCM_REG(ccgr) = (uint32_t)kCLOCK_ClockNotNeeded; in CLOCK_DisableClock()

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