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Searched refs:CCM_LPCG_STATUS1_CPU0_MODE_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h23737 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23745 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
DMIMXRT1175_cm7.h23740 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23748 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h23428 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23436 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
DMIMXRT1165_cm4.h23425 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23433 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h23740 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23748 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h23440 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23448 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
DMIMXRT1166_cm7.h23443 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23451 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h23749 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23757 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
DMIMXRT1173_cm7.h23752 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23760 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h23755 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23763 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h23757 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23765 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
DMIMXRT1176_cm4.h23754 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) macro
23762 …(uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)