1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2024 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_GTM_gtm_cls3.h
10  * @version 2.3
11  * @date 2024-05-03
12  * @brief Peripheral Access Layer for S32Z2_GTM_gtm_cls3
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_GTM_gtm_cls3_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_GTM_gtm_cls3_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- GTM_gtm_cls3 Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup GTM_gtm_cls3_Peripheral_Access_Layer GTM_gtm_cls3 Peripheral Access Layer
68  * @{
69  */
70 
71 /** GTM_gtm_cls3 - Size of Registers Arrays */
72 #define GTM_gtm_cls3_CDTM3_DTM4_CH4_DTV_COUNT     4u
73 #define GTM_gtm_cls3_CDTM3_DTM5_CH4_DTV_COUNT     4u
74 #define GTM_gtm_cls3_MCS3_MEM_COUNT               3072u
75 
76 /** GTM_gtm_cls3 - Register Layout Typedef */
77 typedef struct {
78   uint8_t RESERVED_0[6144];
79   __IO uint32_t ATOM3_CH0_RDADDR;                  /**< ATOM[i] channel[x] ARU read address register, offset: 0x1800 */
80   __IO uint32_t ATOM3_CH0_CTRL;                    /**< ATOM[i] channel [x] control register, offset: 0x1804 */
81   __IO uint32_t ATOM3_CH0_SR0;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1808 */
82   __IO uint32_t ATOM3_CH0_SR1;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x180C */
83   __IO uint32_t ATOM3_CH0_CM0;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1810 */
84   __IO uint32_t ATOM3_CH0_CM1;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1814 */
85   __IO uint32_t ATOM3_CH0_CN0;                     /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1818 */
86   __IO uint32_t ATOM3_CH0_STAT;                    /**< ATOM[i] channel [x] status register, offset: 0x181C */
87   __IO uint32_t ATOM3_CH0_IRQ_NOTIFY;              /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1820 */
88   __IO uint32_t ATOM3_CH0_IRQ_EN;                  /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1824 */
89   __IO uint32_t ATOM3_CH0_IRQ_FORCINT;             /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1828 */
90   __IO uint32_t ATOM3_CH0_IRQ_MODE;                /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x182C */
91   uint8_t RESERVED_1[4];
92   __IO uint32_t ATOM3_CH0_CTRL_SR;                 /**< ATOM[i] channel [x] control shadow register, offset: 0x1834 */
93   uint8_t RESERVED_2[72];
94   __IO uint32_t ATOM3_CH1_RDADDR;                  /**< ATOM[i] channel[x] ARU read address register, offset: 0x1880 */
95   __IO uint32_t ATOM3_CH1_CTRL;                    /**< ATOM[i] channel [x] control register, offset: 0x1884 */
96   __IO uint32_t ATOM3_CH1_SR0;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1888 */
97   __IO uint32_t ATOM3_CH1_SR1;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x188C */
98   __IO uint32_t ATOM3_CH1_CM0;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1890 */
99   __IO uint32_t ATOM3_CH1_CM1;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1894 */
100   __IO uint32_t ATOM3_CH1_CN0;                     /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1898 */
101   __IO uint32_t ATOM3_CH1_STAT;                    /**< ATOM[i] channel [x] status register, offset: 0x189C */
102   __IO uint32_t ATOM3_CH1_IRQ_NOTIFY;              /**< ATOM[i] channel [x] interrupt notification register, offset: 0x18A0 */
103   __IO uint32_t ATOM3_CH1_IRQ_EN;                  /**< ATOM[i] channel [x] interrupt enable register, offset: 0x18A4 */
104   __IO uint32_t ATOM3_CH1_IRQ_FORCINT;             /**< ATOM[i] channel [x] software interrupt generation, offset: 0x18A8 */
105   __IO uint32_t ATOM3_CH1_IRQ_MODE;                /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x18AC */
106   uint8_t RESERVED_3[4];
107   __IO uint32_t ATOM3_CH1_CTRL_SR;                 /**< ATOM[i] channel [x] control shadow register, offset: 0x18B4 */
108   uint8_t RESERVED_4[72];
109   __IO uint32_t ATOM3_CH2_RDADDR;                  /**< ATOM[i] channel[x] ARU read address register, offset: 0x1900 */
110   __IO uint32_t ATOM3_CH2_CTRL;                    /**< ATOM[i] channel [x] control register, offset: 0x1904 */
111   __IO uint32_t ATOM3_CH2_SR0;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1908 */
112   __IO uint32_t ATOM3_CH2_SR1;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x190C */
113   __IO uint32_t ATOM3_CH2_CM0;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1910 */
114   __IO uint32_t ATOM3_CH2_CM1;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1914 */
115   __IO uint32_t ATOM3_CH2_CN0;                     /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1918 */
116   __IO uint32_t ATOM3_CH2_STAT;                    /**< ATOM[i] channel [x] status register, offset: 0x191C */
117   __IO uint32_t ATOM3_CH2_IRQ_NOTIFY;              /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1920 */
118   __IO uint32_t ATOM3_CH2_IRQ_EN;                  /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1924 */
119   __IO uint32_t ATOM3_CH2_IRQ_FORCINT;             /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1928 */
120   __IO uint32_t ATOM3_CH2_IRQ_MODE;                /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x192C */
121   uint8_t RESERVED_5[4];
122   __IO uint32_t ATOM3_CH2_CTRL_SR;                 /**< ATOM[i] channel [x] control shadow register, offset: 0x1934 */
123   uint8_t RESERVED_6[72];
124   __IO uint32_t ATOM3_CH3_RDADDR;                  /**< ATOM[i] channel[x] ARU read address register, offset: 0x1980 */
125   __IO uint32_t ATOM3_CH3_CTRL;                    /**< ATOM[i] channel [x] control register, offset: 0x1984 */
126   __IO uint32_t ATOM3_CH3_SR0;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1988 */
127   __IO uint32_t ATOM3_CH3_SR1;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x198C */
128   __IO uint32_t ATOM3_CH3_CM0;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1990 */
129   __IO uint32_t ATOM3_CH3_CM1;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1994 */
130   __IO uint32_t ATOM3_CH3_CN0;                     /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1998 */
131   __IO uint32_t ATOM3_CH3_STAT;                    /**< ATOM[i] channel [x] status register, offset: 0x199C */
132   __IO uint32_t ATOM3_CH3_IRQ_NOTIFY;              /**< ATOM[i] channel [x] interrupt notification register, offset: 0x19A0 */
133   __IO uint32_t ATOM3_CH3_IRQ_EN;                  /**< ATOM[i] channel [x] interrupt enable register, offset: 0x19A4 */
134   __IO uint32_t ATOM3_CH3_IRQ_FORCINT;             /**< ATOM[i] channel [x] software interrupt generation, offset: 0x19A8 */
135   __IO uint32_t ATOM3_CH3_IRQ_MODE;                /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x19AC */
136   uint8_t RESERVED_7[4];
137   __IO uint32_t ATOM3_CH3_CTRL_SR;                 /**< ATOM[i] channel [x] control shadow register, offset: 0x19B4 */
138   uint8_t RESERVED_8[72];
139   __IO uint32_t ATOM3_CH4_RDADDR;                  /**< ATOM[i] channel[x] ARU read address register, offset: 0x1A00 */
140   __IO uint32_t ATOM3_CH4_CTRL;                    /**< ATOM[i] channel [x] control register, offset: 0x1A04 */
141   __IO uint32_t ATOM3_CH4_SR0;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A08 */
142   __IO uint32_t ATOM3_CH4_SR1;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A0C */
143   __IO uint32_t ATOM3_CH4_CM0;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A10 */
144   __IO uint32_t ATOM3_CH4_CM1;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A14 */
145   __IO uint32_t ATOM3_CH4_CN0;                     /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1A18 */
146   __IO uint32_t ATOM3_CH4_STAT;                    /**< ATOM[i] channel [x] status register, offset: 0x1A1C */
147   __IO uint32_t ATOM3_CH4_IRQ_NOTIFY;              /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1A20 */
148   __IO uint32_t ATOM3_CH4_IRQ_EN;                  /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1A24 */
149   __IO uint32_t ATOM3_CH4_IRQ_FORCINT;             /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1A28 */
150   __IO uint32_t ATOM3_CH4_IRQ_MODE;                /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1A2C */
151   uint8_t RESERVED_9[4];
152   __IO uint32_t ATOM3_CH4_CTRL_SR;                 /**< ATOM[i] channel [x] control shadow register, offset: 0x1A34 */
153   uint8_t RESERVED_10[72];
154   __IO uint32_t ATOM3_CH5_RDADDR;                  /**< ATOM[i] channel[x] ARU read address register, offset: 0x1A80 */
155   __IO uint32_t ATOM3_CH5_CTRL;                    /**< ATOM[i] channel [x] control register, offset: 0x1A84 */
156   __IO uint32_t ATOM3_CH5_SR0;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A88 */
157   __IO uint32_t ATOM3_CH5_SR1;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1A8C */
158   __IO uint32_t ATOM3_CH5_CM0;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A90 */
159   __IO uint32_t ATOM3_CH5_CM1;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1A94 */
160   __IO uint32_t ATOM3_CH5_CN0;                     /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1A98 */
161   __IO uint32_t ATOM3_CH5_STAT;                    /**< ATOM[i] channel [x] status register, offset: 0x1A9C */
162   __IO uint32_t ATOM3_CH5_IRQ_NOTIFY;              /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1AA0 */
163   __IO uint32_t ATOM3_CH5_IRQ_EN;                  /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1AA4 */
164   __IO uint32_t ATOM3_CH5_IRQ_FORCINT;             /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1AA8 */
165   __IO uint32_t ATOM3_CH5_IRQ_MODE;                /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1AAC */
166   uint8_t RESERVED_11[4];
167   __IO uint32_t ATOM3_CH5_CTRL_SR;                 /**< ATOM[i] channel [x] control shadow register, offset: 0x1AB4 */
168   uint8_t RESERVED_12[72];
169   __IO uint32_t ATOM3_CH6_RDADDR;                  /**< ATOM[i] channel[x] ARU read address register, offset: 0x1B00 */
170   __IO uint32_t ATOM3_CH6_CTRL;                    /**< ATOM[i] channel [x] control register, offset: 0x1B04 */
171   __IO uint32_t ATOM3_CH6_SR0;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B08 */
172   __IO uint32_t ATOM3_CH6_SR1;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B0C */
173   __IO uint32_t ATOM3_CH6_CM0;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B10 */
174   __IO uint32_t ATOM3_CH6_CM1;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B14 */
175   __IO uint32_t ATOM3_CH6_CN0;                     /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1B18 */
176   __IO uint32_t ATOM3_CH6_STAT;                    /**< ATOM[i] channel [x] status register, offset: 0x1B1C */
177   __IO uint32_t ATOM3_CH6_IRQ_NOTIFY;              /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1B20 */
178   __IO uint32_t ATOM3_CH6_IRQ_EN;                  /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1B24 */
179   __IO uint32_t ATOM3_CH6_IRQ_FORCINT;             /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1B28 */
180   __IO uint32_t ATOM3_CH6_IRQ_MODE;                /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1B2C */
181   uint8_t RESERVED_13[4];
182   __IO uint32_t ATOM3_CH6_CTRL_SR;                 /**< ATOM[i] channel [x] control shadow register, offset: 0x1B34 */
183   uint8_t RESERVED_14[72];
184   __IO uint32_t ATOM3_CH7_RDADDR;                  /**< ATOM[i] channel[x] ARU read address register, offset: 0x1B80 */
185   __IO uint32_t ATOM3_CH7_CTRL;                    /**< ATOM[i] channel [x] control register, offset: 0x1B84 */
186   __IO uint32_t ATOM3_CH7_SR0;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B88 */
187   __IO uint32_t ATOM3_CH7_SR1;                     /**< ATOM[i] channel [x] CCU0 compare shadow register, offset: 0x1B8C */
188   __IO uint32_t ATOM3_CH7_CM0;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B90 */
189   __IO uint32_t ATOM3_CH7_CM1;                     /**< ATOM[i] channel [x] CCU0 compare register, offset: 0x1B94 */
190   __IO uint32_t ATOM3_CH7_CN0;                     /**< ATOM[i] channel [x] CCU0 counter register, offset: 0x1B98 */
191   __IO uint32_t ATOM3_CH7_STAT;                    /**< ATOM[i] channel [x] status register, offset: 0x1B9C */
192   __IO uint32_t ATOM3_CH7_IRQ_NOTIFY;              /**< ATOM[i] channel [x] interrupt notification register, offset: 0x1BA0 */
193   __IO uint32_t ATOM3_CH7_IRQ_EN;                  /**< ATOM[i] channel [x] interrupt enable register, offset: 0x1BA4 */
194   __IO uint32_t ATOM3_CH7_IRQ_FORCINT;             /**< ATOM[i] channel [x] software interrupt generation, offset: 0x1BA8 */
195   __IO uint32_t ATOM3_CH7_IRQ_MODE;                /**< ATOM[i] channel [x] interrupt mode configuration register, offset: 0x1BAC */
196   uint8_t RESERVED_15[4];
197   __IO uint32_t ATOM3_CH7_CTRL_SR;                 /**< ATOM[i] channel [x] control shadow register, offset: 0x1BB4 */
198   uint8_t RESERVED_16[136];
199   __IO uint32_t ATOM3_AGC_GLB_CTRL;                /**< ATOM[i] AGC global control register, offset: 0x1C40 */
200   __IO uint32_t ATOM3_AGC_ENDIS_CTRL;              /**< ATOM[i] AGC enable/disable control register, offset: 0x1C44 */
201   __IO uint32_t ATOM3_AGC_ENDIS_STAT;              /**< ATOM[i] AGC enable/disable status register, offset: 0x1C48 */
202   __IO uint32_t ATOM3_AGC_ACT_TB;                  /**< ATOM[i] AGC action time base register, offset: 0x1C4C */
203   __IO uint32_t ATOM3_AGC_OUTEN_CTRL;              /**< ATOM[i] AGC output enable control register, offset: 0x1C50 */
204   __IO uint32_t ATOM3_AGC_OUTEN_STAT;              /**< ATOM[i] AGC output enable status register, offset: 0x1C54 */
205   __IO uint32_t ATOM3_AGC_FUPD_CTRL;               /**< ATOM[i] AGC force update control register, offset: 0x1C58 */
206   __IO uint32_t ATOM3_AGC_INT_TRIG;                /**< ATOM[i] AGC internal trigger control register, offset: 0x1C5C */
207   uint8_t RESERVED_17[928];
208   __IO uint32_t MCS3_CH0_R0;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2000 */
209   __IO uint32_t MCS3_CH0_R1;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2004 */
210   __IO uint32_t MCS3_CH0_R2;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2008 */
211   __IO uint32_t MCS3_CH0_R3;                       /**< MCS[i] channel x general purpose register [y], offset: 0x200C */
212   __IO uint32_t MCS3_CH0_R4;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2010 */
213   __IO uint32_t MCS3_CH0_R5;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2014 */
214   __IO uint32_t MCS3_CH0_R6;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2018 */
215   __IO uint32_t MCS3_CH0_R7;                       /**< MCS[i] channel x general purpose register [y], offset: 0x201C */
216   __IO uint32_t MCS3_CH0_CTRL;                     /**< MCS[i] channel x control register, offset: 0x2020 */
217   __I  uint32_t MCS3_CH0_ACB;                      /**< MCS[i] channel x ARU control Bit register, offset: 0x2024 */
218   uint8_t RESERVED_18[20];
219   __I  uint32_t MCS3_CH0_MHB;                      /**< MCS[i] channel x memory high byte register, offset: 0x203C */
220   uint8_t RESERVED_19[160];
221   __IO uint32_t MCS3_CH0_PC;                       /**< MCS[i] channel x program counter register, offset: 0x20E0 */
222   __IO uint32_t MCS3_CH0_IRQ_NOTIFY;               /**< MCS[i] channel x interrupt notification register, offset: 0x20E4 */
223   __IO uint32_t MCS3_CH0_IRQ_EN;                   /**< MCS[i] channel x interrupt enable register, offset: 0x20E8 */
224   __IO uint32_t MCS3_CH0_IRQ_FORCINT;              /**< MCS[i] channel x force interrupt register, offset: 0x20EC */
225   __IO uint32_t MCS3_CH0_IRQ_MODE;                 /**< MCS[i] channel x IRQ mode configuration register, offset: 0x20F0 */
226   __IO uint32_t MCS3_CH0_EIRQ_EN;                  /**< MCS[i] channel x error interrupt enable register, offset: 0x20F4 */
227   uint8_t RESERVED_20[8];
228   __IO uint32_t MCS3_CH1_R0;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2100 */
229   __IO uint32_t MCS3_CH1_R1;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2104 */
230   __IO uint32_t MCS3_CH1_R2;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2108 */
231   __IO uint32_t MCS3_CH1_R3;                       /**< MCS[i] channel x general purpose register [y], offset: 0x210C */
232   __IO uint32_t MCS3_CH1_R4;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2110 */
233   __IO uint32_t MCS3_CH1_R5;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2114 */
234   __IO uint32_t MCS3_CH1_R6;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2118 */
235   __IO uint32_t MCS3_CH1_R7;                       /**< MCS[i] channel x general purpose register [y], offset: 0x211C */
236   __IO uint32_t MCS3_CH1_CTRL;                     /**< MCS[i] channel x control register, offset: 0x2120 */
237   __I  uint32_t MCS3_CH1_ACB;                      /**< MCS[i] channel x ARU control Bit register, offset: 0x2124 */
238   uint8_t RESERVED_21[20];
239   __I  uint32_t MCS3_CH1_MHB;                      /**< MCS[i] channel x memory high byte register, offset: 0x213C */
240   uint8_t RESERVED_22[160];
241   __IO uint32_t MCS3_CH1_PC;                       /**< MCS[i] channel x program counter register, offset: 0x21E0 */
242   __IO uint32_t MCS3_CH1_IRQ_NOTIFY;               /**< MCS[i] channel x interrupt notification register, offset: 0x21E4 */
243   __IO uint32_t MCS3_CH1_IRQ_EN;                   /**< MCS[i] channel x interrupt enable register, offset: 0x21E8 */
244   __IO uint32_t MCS3_CH1_IRQ_FORCINT;              /**< MCS[i] channel x force interrupt register, offset: 0x21EC */
245   __IO uint32_t MCS3_CH1_IRQ_MODE;                 /**< MCS[i] channel x IRQ mode configuration register, offset: 0x21F0 */
246   __IO uint32_t MCS3_CH1_EIRQ_EN;                  /**< MCS[i] channel x error interrupt enable register, offset: 0x21F4 */
247   uint8_t RESERVED_23[8];
248   __IO uint32_t MCS3_CH2_R0;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2200 */
249   __IO uint32_t MCS3_CH2_R1;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2204 */
250   __IO uint32_t MCS3_CH2_R2;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2208 */
251   __IO uint32_t MCS3_CH2_R3;                       /**< MCS[i] channel x general purpose register [y], offset: 0x220C */
252   __IO uint32_t MCS3_CH2_R4;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2210 */
253   __IO uint32_t MCS3_CH2_R5;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2214 */
254   __IO uint32_t MCS3_CH2_R6;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2218 */
255   __IO uint32_t MCS3_CH2_R7;                       /**< MCS[i] channel x general purpose register [y], offset: 0x221C */
256   __IO uint32_t MCS3_CH2_CTRL;                     /**< MCS[i] channel x control register, offset: 0x2220 */
257   __I  uint32_t MCS3_CH2_ACB;                      /**< MCS[i] channel x ARU control Bit register, offset: 0x2224 */
258   uint8_t RESERVED_24[20];
259   __I  uint32_t MCS3_CH2_MHB;                      /**< MCS[i] channel x memory high byte register, offset: 0x223C */
260   uint8_t RESERVED_25[160];
261   __IO uint32_t MCS3_CH2_PC;                       /**< MCS[i] channel x program counter register, offset: 0x22E0 */
262   __IO uint32_t MCS3_CH2_IRQ_NOTIFY;               /**< MCS[i] channel x interrupt notification register, offset: 0x22E4 */
263   __IO uint32_t MCS3_CH2_IRQ_EN;                   /**< MCS[i] channel x interrupt enable register, offset: 0x22E8 */
264   __IO uint32_t MCS3_CH2_IRQ_FORCINT;              /**< MCS[i] channel x force interrupt register, offset: 0x22EC */
265   __IO uint32_t MCS3_CH2_IRQ_MODE;                 /**< MCS[i] channel x IRQ mode configuration register, offset: 0x22F0 */
266   __IO uint32_t MCS3_CH2_EIRQ_EN;                  /**< MCS[i] channel x error interrupt enable register, offset: 0x22F4 */
267   uint8_t RESERVED_26[8];
268   __IO uint32_t MCS3_CH3_R0;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2300 */
269   __IO uint32_t MCS3_CH3_R1;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2304 */
270   __IO uint32_t MCS3_CH3_R2;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2308 */
271   __IO uint32_t MCS3_CH3_R3;                       /**< MCS[i] channel x general purpose register [y], offset: 0x230C */
272   __IO uint32_t MCS3_CH3_R4;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2310 */
273   __IO uint32_t MCS3_CH3_R5;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2314 */
274   __IO uint32_t MCS3_CH3_R6;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2318 */
275   __IO uint32_t MCS3_CH3_R7;                       /**< MCS[i] channel x general purpose register [y], offset: 0x231C */
276   __IO uint32_t MCS3_CH3_CTRL;                     /**< MCS[i] channel x control register, offset: 0x2320 */
277   __I  uint32_t MCS3_CH3_ACB;                      /**< MCS[i] channel x ARU control Bit register, offset: 0x2324 */
278   uint8_t RESERVED_27[20];
279   __I  uint32_t MCS3_CH3_MHB;                      /**< MCS[i] channel x memory high byte register, offset: 0x233C */
280   uint8_t RESERVED_28[160];
281   __IO uint32_t MCS3_CH3_PC;                       /**< MCS[i] channel x program counter register, offset: 0x23E0 */
282   __IO uint32_t MCS3_CH3_IRQ_NOTIFY;               /**< MCS[i] channel x interrupt notification register, offset: 0x23E4 */
283   __IO uint32_t MCS3_CH3_IRQ_EN;                   /**< MCS[i] channel x interrupt enable register, offset: 0x23E8 */
284   __IO uint32_t MCS3_CH3_IRQ_FORCINT;              /**< MCS[i] channel x force interrupt register, offset: 0x23EC */
285   __IO uint32_t MCS3_CH3_IRQ_MODE;                 /**< MCS[i] channel x IRQ mode configuration register, offset: 0x23F0 */
286   __IO uint32_t MCS3_CH3_EIRQ_EN;                  /**< MCS[i] channel x error interrupt enable register, offset: 0x23F4 */
287   uint8_t RESERVED_29[8];
288   __IO uint32_t MCS3_CH4_R0;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2400 */
289   __IO uint32_t MCS3_CH4_R1;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2404 */
290   __IO uint32_t MCS3_CH4_R2;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2408 */
291   __IO uint32_t MCS3_CH4_R3;                       /**< MCS[i] channel x general purpose register [y], offset: 0x240C */
292   __IO uint32_t MCS3_CH4_R4;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2410 */
293   __IO uint32_t MCS3_CH4_R5;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2414 */
294   __IO uint32_t MCS3_CH4_R6;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2418 */
295   __IO uint32_t MCS3_CH4_R7;                       /**< MCS[i] channel x general purpose register [y], offset: 0x241C */
296   __IO uint32_t MCS3_CH4_CTRL;                     /**< MCS[i] channel x control register, offset: 0x2420 */
297   __I  uint32_t MCS3_CH4_ACB;                      /**< MCS[i] channel x ARU control Bit register, offset: 0x2424 */
298   uint8_t RESERVED_30[20];
299   __I  uint32_t MCS3_CH4_MHB;                      /**< MCS[i] channel x memory high byte register, offset: 0x243C */
300   uint8_t RESERVED_31[160];
301   __IO uint32_t MCS3_CH4_PC;                       /**< MCS[i] channel x program counter register, offset: 0x24E0 */
302   __IO uint32_t MCS3_CH4_IRQ_NOTIFY;               /**< MCS[i] channel x interrupt notification register, offset: 0x24E4 */
303   __IO uint32_t MCS3_CH4_IRQ_EN;                   /**< MCS[i] channel x interrupt enable register, offset: 0x24E8 */
304   __IO uint32_t MCS3_CH4_IRQ_FORCINT;              /**< MCS[i] channel x force interrupt register, offset: 0x24EC */
305   __IO uint32_t MCS3_CH4_IRQ_MODE;                 /**< MCS[i] channel x IRQ mode configuration register, offset: 0x24F0 */
306   __IO uint32_t MCS3_CH4_EIRQ_EN;                  /**< MCS[i] channel x error interrupt enable register, offset: 0x24F4 */
307   uint8_t RESERVED_32[8];
308   __IO uint32_t MCS3_CH5_R0;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2500 */
309   __IO uint32_t MCS3_CH5_R1;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2504 */
310   __IO uint32_t MCS3_CH5_R2;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2508 */
311   __IO uint32_t MCS3_CH5_R3;                       /**< MCS[i] channel x general purpose register [y], offset: 0x250C */
312   __IO uint32_t MCS3_CH5_R4;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2510 */
313   __IO uint32_t MCS3_CH5_R5;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2514 */
314   __IO uint32_t MCS3_CH5_R6;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2518 */
315   __IO uint32_t MCS3_CH5_R7;                       /**< MCS[i] channel x general purpose register [y], offset: 0x251C */
316   __IO uint32_t MCS3_CH5_CTRL;                     /**< MCS[i] channel x control register, offset: 0x2520 */
317   __I  uint32_t MCS3_CH5_ACB;                      /**< MCS[i] channel x ARU control Bit register, offset: 0x2524 */
318   uint8_t RESERVED_33[20];
319   __I  uint32_t MCS3_CH5_MHB;                      /**< MCS[i] channel x memory high byte register, offset: 0x253C */
320   uint8_t RESERVED_34[160];
321   __IO uint32_t MCS3_CH5_PC;                       /**< MCS[i] channel x program counter register, offset: 0x25E0 */
322   __IO uint32_t MCS3_CH5_IRQ_NOTIFY;               /**< MCS[i] channel x interrupt notification register, offset: 0x25E4 */
323   __IO uint32_t MCS3_CH5_IRQ_EN;                   /**< MCS[i] channel x interrupt enable register, offset: 0x25E8 */
324   __IO uint32_t MCS3_CH5_IRQ_FORCINT;              /**< MCS[i] channel x force interrupt register, offset: 0x25EC */
325   __IO uint32_t MCS3_CH5_IRQ_MODE;                 /**< MCS[i] channel x IRQ mode configuration register, offset: 0x25F0 */
326   __IO uint32_t MCS3_CH5_EIRQ_EN;                  /**< MCS[i] channel x error interrupt enable register, offset: 0x25F4 */
327   uint8_t RESERVED_35[8];
328   __IO uint32_t MCS3_CH6_R0;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2600 */
329   __IO uint32_t MCS3_CH6_R1;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2604 */
330   __IO uint32_t MCS3_CH6_R2;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2608 */
331   __IO uint32_t MCS3_CH6_R3;                       /**< MCS[i] channel x general purpose register [y], offset: 0x260C */
332   __IO uint32_t MCS3_CH6_R4;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2610 */
333   __IO uint32_t MCS3_CH6_R5;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2614 */
334   __IO uint32_t MCS3_CH6_R6;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2618 */
335   __IO uint32_t MCS3_CH6_R7;                       /**< MCS[i] channel x general purpose register [y], offset: 0x261C */
336   __IO uint32_t MCS3_CH6_CTRL;                     /**< MCS[i] channel x control register, offset: 0x2620 */
337   __I  uint32_t MCS3_CH6_ACB;                      /**< MCS[i] channel x ARU control Bit register, offset: 0x2624 */
338   uint8_t RESERVED_36[20];
339   __I  uint32_t MCS3_CH6_MHB;                      /**< MCS[i] channel x memory high byte register, offset: 0x263C */
340   uint8_t RESERVED_37[160];
341   __IO uint32_t MCS3_CH6_PC;                       /**< MCS[i] channel x program counter register, offset: 0x26E0 */
342   __IO uint32_t MCS3_CH6_IRQ_NOTIFY;               /**< MCS[i] channel x interrupt notification register, offset: 0x26E4 */
343   __IO uint32_t MCS3_CH6_IRQ_EN;                   /**< MCS[i] channel x interrupt enable register, offset: 0x26E8 */
344   __IO uint32_t MCS3_CH6_IRQ_FORCINT;              /**< MCS[i] channel x force interrupt register, offset: 0x26EC */
345   __IO uint32_t MCS3_CH6_IRQ_MODE;                 /**< MCS[i] channel x IRQ mode configuration register, offset: 0x26F0 */
346   __IO uint32_t MCS3_CH6_EIRQ_EN;                  /**< MCS[i] channel x error interrupt enable register, offset: 0x26F4 */
347   uint8_t RESERVED_38[8];
348   __IO uint32_t MCS3_CH7_R0;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2700 */
349   __IO uint32_t MCS3_CH7_R1;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2704 */
350   __IO uint32_t MCS3_CH7_R2;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2708 */
351   __IO uint32_t MCS3_CH7_R3;                       /**< MCS[i] channel x general purpose register [y], offset: 0x270C */
352   __IO uint32_t MCS3_CH7_R4;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2710 */
353   __IO uint32_t MCS3_CH7_R5;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2714 */
354   __IO uint32_t MCS3_CH7_R6;                       /**< MCS[i] channel x general purpose register [y], offset: 0x2718 */
355   __IO uint32_t MCS3_CH7_R7;                       /**< MCS[i] channel x general purpose register [y], offset: 0x271C */
356   __IO uint32_t MCS3_CH7_CTRL;                     /**< MCS[i] channel x control register, offset: 0x2720 */
357   __I  uint32_t MCS3_CH7_ACB;                      /**< MCS[i] channel x ARU control Bit register, offset: 0x2724 */
358   uint8_t RESERVED_39[20];
359   __I  uint32_t MCS3_CH7_MHB;                      /**< MCS[i] channel x memory high byte register, offset: 0x273C */
360   uint8_t RESERVED_40[160];
361   __IO uint32_t MCS3_CH7_PC;                       /**< MCS[i] channel x program counter register, offset: 0x27E0 */
362   __IO uint32_t MCS3_CH7_IRQ_NOTIFY;               /**< MCS[i] channel x interrupt notification register, offset: 0x27E4 */
363   __IO uint32_t MCS3_CH7_IRQ_EN;                   /**< MCS[i] channel x interrupt enable register, offset: 0x27E8 */
364   __IO uint32_t MCS3_CH7_IRQ_FORCINT;              /**< MCS[i] channel x force interrupt register, offset: 0x27EC */
365   __IO uint32_t MCS3_CH7_IRQ_MODE;                 /**< MCS[i] channel x IRQ mode configuration register, offset: 0x27F0 */
366   __IO uint32_t MCS3_CH7_EIRQ_EN;                  /**< MCS[i] channel x error interrupt enable register, offset: 0x27F4 */
367   uint8_t RESERVED_41[1584];
368   __IO uint32_t MCS3_CTRG;                         /**< MCS[i] clear trigger control register, offset: 0x2E28 */
369   __IO uint32_t MCS3_STRG;                         /**< MCS[i] set trigger control register, offset: 0x2E2C */
370   uint8_t RESERVED_42[208];
371   __IO uint32_t MCS3_CTRL_STAT;                    /**< MCS[i] control and status register, offset: 0x2F00 */
372   __IO uint32_t MCS3_RESET;                        /**< MCS[i] reset register, offset: 0x2F04 */
373   __IO uint32_t MCS3_CAT;                          /**< MCS[i] cancel ARU transfer instruction, offset: 0x2F08 */
374   __IO uint32_t MCS3_CWT;                          /**< MCS[i] cancel waiting instruction, offset: 0x2F0C */
375   __IO uint32_t MCS3_ERR;                          /**< MCS[i] error register, offset: 0x2F10 */
376   uint8_t RESERVED_43[8];
377   __IO uint32_t MCS3_REG_PROT;                     /**< MCS[i] write protection register, offset: 0x2F1C */
378   __IO uint32_t MCS3_SINT_IRQ_NOTIFY;              /**< MCS[i] shared interrupt notification register, offset: 0x2F20 */
379   __IO uint32_t MCS3_SINT_IRQ_EN;                  /**< MCS[i] shared interrupt enable register, offset: 0x2F24 */
380   __IO uint32_t MCS3_SINT_IRQ_FORCINT;             /**< MCS[i] force shared interrupt register, offset: 0x2F28 */
381   __IO uint32_t MCS3_SINT_IRQ_MODE;                /**< MCS[i] shared interrupt mode configuration register, offset: 0x2F2C */
382   uint8_t RESERVED_44[16];
383   __IO uint32_t MCS3_HBP0_CTRL;                    /**< MCS[i] hardware break point h control register, offset: 0x2F40 */
384   __IO uint32_t MCS3_HBP0_PATTERN;                 /**< MCS[i] hardware break point pattern register, offset: 0x2F44 */
385   __IO uint32_t MCS3_HBP0_STATUS;                  /**< MCS[i] hardware break point status register, offset: 0x2F48 */
386   __IO uint32_t MCS3_HBP0_IRQ_NOTIFY;              /**< MCS[i] hardware break point interrupt notification register, offset: 0x2F4C */
387   __IO uint32_t MCS3_HBP0_IRQ_EN;                  /**< MCS[i] hardware break point interrupt enable register, offset: 0x2F50 */
388   __IO uint32_t MCS3_HBP0_IRQ_FORCINT;             /**< MCS[i] force hardware break point interrupt register, offset: 0x2F54 */
389   __IO uint32_t MCS3_HBP0_IRQ_MODE;                /**< MCS[i] break point h interrupt mode configuration register, offset: 0x2F58 */
390   uint8_t RESERVED_45[4];
391   __IO uint32_t MCS3_HBP1_CTRL;                    /**< MCS[i] hardware break point h control register, offset: 0x2F60 */
392   __IO uint32_t MCS3_HBP1_PATTERN;                 /**< MCS[i] hardware break point pattern register, offset: 0x2F64 */
393   __IO uint32_t MCS3_HBP1_STATUS;                  /**< MCS[i] hardware break point status register, offset: 0x2F68 */
394   __IO uint32_t MCS3_HBP1_IRQ_NOTIFY;              /**< MCS[i] hardware break point interrupt notification register, offset: 0x2F6C */
395   __IO uint32_t MCS3_HBP1_IRQ_EN;                  /**< MCS[i] hardware break point interrupt enable register, offset: 0x2F70 */
396   __IO uint32_t MCS3_HBP1_IRQ_FORCINT;             /**< MCS[i] force hardware break point interrupt register, offset: 0x2F74 */
397   __IO uint32_t MCS3_HBP1_IRQ_MODE;                /**< MCS[i] break point h interrupt mode configuration register, offset: 0x2F78 */
398   uint8_t RESERVED_46[132];
399   __IO uint32_t TIO3_G0_CH0_CTRL;                  /**< TIO[i] group [g] channel [c] control register, offset: 0x3000 */
400   __IO uint32_t TIO3_G0_CH0_IRQ_NOTIFY;            /**< TIO[i] channel [c] interrupt notification register, offset: 0x3004 */
401   __IO uint32_t TIO3_G0_CH0_IRQ_EN;                /**< TIO[i] channel [c] interrupt enable register, offset: 0x3008 */
402   __IO uint32_t TIO3_G0_CH0_IRQ_FORCINT;           /**< TIO[i] channel [c] force interrupt register, offset: 0x300C */
403   __IO uint32_t TIO3_G0_CH0_IRQ_MODE;              /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3010 */
404   __IO uint32_t TIO3_G0_CH0_CTRL2;                 /**< TIO[i] group [g] channel [c] control register, offset: 0x3014 */
405   uint8_t RESERVED_47[8];
406   __IO uint32_t TIO3_G0_CH0_SINST;                 /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3020 */
407   __IO uint32_t TIO3_G0_CH0_SCMD;                  /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3024 */
408   __IO uint32_t TIO3_G0_CH0_SOP;                   /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x3028 */
409   uint8_t RESERVED_48[4];
410   __IO uint32_t TIO3_G0_CH0_OINST;                 /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x3030 */
411   __IO uint32_t TIO3_G0_CH0_OCMD;                  /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x3034 */
412   __IO uint32_t TIO3_G0_CH0_OOP;                   /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x3038 */
413   __I  uint32_t TIO3_G0_CH0_SHIFTCNT;              /**< TIO[i] channel [c] resource shift count register, offset: 0x303C */
414   __IO uint32_t TIO3_G0_CH1_CTRL;                  /**< TIO[i] group [g] channel [c] control register, offset: 0x3040 */
415   __IO uint32_t TIO3_G0_CH1_IRQ_NOTIFY;            /**< TIO[i] channel [c] interrupt notification register, offset: 0x3044 */
416   __IO uint32_t TIO3_G0_CH1_IRQ_EN;                /**< TIO[i] channel [c] interrupt enable register, offset: 0x3048 */
417   __IO uint32_t TIO3_G0_CH1_IRQ_FORCINT;           /**< TIO[i] channel [c] force interrupt register, offset: 0x304C */
418   __IO uint32_t TIO3_G0_CH1_IRQ_MODE;              /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3050 */
419   __IO uint32_t TIO3_G0_CH1_CTRL2;                 /**< TIO[i] group [g] channel [c] control register, offset: 0x3054 */
420   uint8_t RESERVED_49[8];
421   __IO uint32_t TIO3_G0_CH1_SINST;                 /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3060 */
422   __IO uint32_t TIO3_G0_CH1_SCMD;                  /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3064 */
423   __IO uint32_t TIO3_G0_CH1_SOP;                   /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x3068 */
424   uint8_t RESERVED_50[4];
425   __IO uint32_t TIO3_G0_CH1_OINST;                 /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x3070 */
426   __IO uint32_t TIO3_G0_CH1_OCMD;                  /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x3074 */
427   __IO uint32_t TIO3_G0_CH1_OOP;                   /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x3078 */
428   __I  uint32_t TIO3_G0_CH1_SHIFTCNT;              /**< TIO[i] channel [c] resource shift count register, offset: 0x307C */
429   __IO uint32_t TIO3_G0_CH2_CTRL;                  /**< TIO[i] group [g] channel [c] control register, offset: 0x3080 */
430   __IO uint32_t TIO3_G0_CH2_IRQ_NOTIFY;            /**< TIO[i] channel [c] interrupt notification register, offset: 0x3084 */
431   __IO uint32_t TIO3_G0_CH2_IRQ_EN;                /**< TIO[i] channel [c] interrupt enable register, offset: 0x3088 */
432   __IO uint32_t TIO3_G0_CH2_IRQ_FORCINT;           /**< TIO[i] channel [c] force interrupt register, offset: 0x308C */
433   __IO uint32_t TIO3_G0_CH2_IRQ_MODE;              /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3090 */
434   __IO uint32_t TIO3_G0_CH2_CTRL2;                 /**< TIO[i] group [g] channel [c] control register, offset: 0x3094 */
435   uint8_t RESERVED_51[8];
436   __IO uint32_t TIO3_G0_CH2_SINST;                 /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x30A0 */
437   __IO uint32_t TIO3_G0_CH2_SCMD;                  /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x30A4 */
438   __IO uint32_t TIO3_G0_CH2_SOP;                   /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x30A8 */
439   uint8_t RESERVED_52[4];
440   __IO uint32_t TIO3_G0_CH2_OINST;                 /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x30B0 */
441   __IO uint32_t TIO3_G0_CH2_OCMD;                  /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x30B4 */
442   __IO uint32_t TIO3_G0_CH2_OOP;                   /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x30B8 */
443   __I  uint32_t TIO3_G0_CH2_SHIFTCNT;              /**< TIO[i] channel [c] resource shift count register, offset: 0x30BC */
444   __IO uint32_t TIO3_G0_CH3_CTRL;                  /**< TIO[i] group [g] channel [c] control register, offset: 0x30C0 */
445   __IO uint32_t TIO3_G0_CH3_IRQ_NOTIFY;            /**< TIO[i] channel [c] interrupt notification register, offset: 0x30C4 */
446   __IO uint32_t TIO3_G0_CH3_IRQ_EN;                /**< TIO[i] channel [c] interrupt enable register, offset: 0x30C8 */
447   __IO uint32_t TIO3_G0_CH3_IRQ_FORCINT;           /**< TIO[i] channel [c] force interrupt register, offset: 0x30CC */
448   __IO uint32_t TIO3_G0_CH3_IRQ_MODE;              /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x30D0 */
449   __IO uint32_t TIO3_G0_CH3_CTRL2;                 /**< TIO[i] group [g] channel [c] control register, offset: 0x30D4 */
450   uint8_t RESERVED_53[8];
451   __IO uint32_t TIO3_G0_CH3_SINST;                 /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x30E0 */
452   __IO uint32_t TIO3_G0_CH3_SCMD;                  /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x30E4 */
453   __IO uint32_t TIO3_G0_CH3_SOP;                   /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x30E8 */
454   uint8_t RESERVED_54[4];
455   __IO uint32_t TIO3_G0_CH3_OINST;                 /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x30F0 */
456   __IO uint32_t TIO3_G0_CH3_OCMD;                  /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x30F4 */
457   __IO uint32_t TIO3_G0_CH3_OOP;                   /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x30F8 */
458   __I  uint32_t TIO3_G0_CH3_SHIFTCNT;              /**< TIO[i] channel [c] resource shift count register, offset: 0x30FC */
459   __IO uint32_t TIO3_G0_CH4_CTRL;                  /**< TIO[i] group [g] channel [c] control register, offset: 0x3100 */
460   __IO uint32_t TIO3_G0_CH4_IRQ_NOTIFY;            /**< TIO[i] channel [c] interrupt notification register, offset: 0x3104 */
461   __IO uint32_t TIO3_G0_CH4_IRQ_EN;                /**< TIO[i] channel [c] interrupt enable register, offset: 0x3108 */
462   __IO uint32_t TIO3_G0_CH4_IRQ_FORCINT;           /**< TIO[i] channel [c] force interrupt register, offset: 0x310C */
463   __IO uint32_t TIO3_G0_CH4_IRQ_MODE;              /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3110 */
464   __IO uint32_t TIO3_G0_CH4_CTRL2;                 /**< TIO[i] group [g] channel [c] control register, offset: 0x3114 */
465   uint8_t RESERVED_55[8];
466   __IO uint32_t TIO3_G0_CH4_SINST;                 /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3120 */
467   __IO uint32_t TIO3_G0_CH4_SCMD;                  /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3124 */
468   __IO uint32_t TIO3_G0_CH4_SOP;                   /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x3128 */
469   uint8_t RESERVED_56[4];
470   __IO uint32_t TIO3_G0_CH4_OINST;                 /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x3130 */
471   __IO uint32_t TIO3_G0_CH4_OCMD;                  /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x3134 */
472   __IO uint32_t TIO3_G0_CH4_OOP;                   /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x3138 */
473   __I  uint32_t TIO3_G0_CH4_SHIFTCNT;              /**< TIO[i] channel [c] resource shift count register, offset: 0x313C */
474   __IO uint32_t TIO3_G0_CH5_CTRL;                  /**< TIO[i] group [g] channel [c] control register, offset: 0x3140 */
475   __IO uint32_t TIO3_G0_CH5_IRQ_NOTIFY;            /**< TIO[i] channel [c] interrupt notification register, offset: 0x3144 */
476   __IO uint32_t TIO3_G0_CH5_IRQ_EN;                /**< TIO[i] channel [c] interrupt enable register, offset: 0x3148 */
477   __IO uint32_t TIO3_G0_CH5_IRQ_FORCINT;           /**< TIO[i] channel [c] force interrupt register, offset: 0x314C */
478   __IO uint32_t TIO3_G0_CH5_IRQ_MODE;              /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3150 */
479   __IO uint32_t TIO3_G0_CH5_CTRL2;                 /**< TIO[i] group [g] channel [c] control register, offset: 0x3154 */
480   uint8_t RESERVED_57[8];
481   __IO uint32_t TIO3_G0_CH5_SINST;                 /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3160 */
482   __IO uint32_t TIO3_G0_CH5_SCMD;                  /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x3164 */
483   __IO uint32_t TIO3_G0_CH5_SOP;                   /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x3168 */
484   uint8_t RESERVED_58[4];
485   __IO uint32_t TIO3_G0_CH5_OINST;                 /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x3170 */
486   __IO uint32_t TIO3_G0_CH5_OCMD;                  /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x3174 */
487   __IO uint32_t TIO3_G0_CH5_OOP;                   /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x3178 */
488   __I  uint32_t TIO3_G0_CH5_SHIFTCNT;              /**< TIO[i] channel [c] resource shift count register, offset: 0x317C */
489   __IO uint32_t TIO3_G0_CH6_CTRL;                  /**< TIO[i] group [g] channel [c] control register, offset: 0x3180 */
490   __IO uint32_t TIO3_G0_CH6_IRQ_NOTIFY;            /**< TIO[i] channel [c] interrupt notification register, offset: 0x3184 */
491   __IO uint32_t TIO3_G0_CH6_IRQ_EN;                /**< TIO[i] channel [c] interrupt enable register, offset: 0x3188 */
492   __IO uint32_t TIO3_G0_CH6_IRQ_FORCINT;           /**< TIO[i] channel [c] force interrupt register, offset: 0x318C */
493   __IO uint32_t TIO3_G0_CH6_IRQ_MODE;              /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x3190 */
494   __IO uint32_t TIO3_G0_CH6_CTRL2;                 /**< TIO[i] group [g] channel [c] control register, offset: 0x3194 */
495   uint8_t RESERVED_59[8];
496   __IO uint32_t TIO3_G0_CH6_SINST;                 /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x31A0 */
497   __IO uint32_t TIO3_G0_CH6_SCMD;                  /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x31A4 */
498   __IO uint32_t TIO3_G0_CH6_SOP;                   /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x31A8 */
499   uint8_t RESERVED_60[4];
500   __IO uint32_t TIO3_G0_CH6_OINST;                 /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x31B0 */
501   __IO uint32_t TIO3_G0_CH6_OCMD;                  /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x31B4 */
502   __IO uint32_t TIO3_G0_CH6_OOP;                   /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x31B8 */
503   __I  uint32_t TIO3_G0_CH6_SHIFTCNT;              /**< TIO[i] channel [c] resource shift count register, offset: 0x31BC */
504   __IO uint32_t TIO3_G0_CH7_CTRL;                  /**< TIO[i] group [g] channel [c] control register, offset: 0x31C0 */
505   __IO uint32_t TIO3_G0_CH7_IRQ_NOTIFY;            /**< TIO[i] channel [c] interrupt notification register, offset: 0x31C4 */
506   __IO uint32_t TIO3_G0_CH7_IRQ_EN;                /**< TIO[i] channel [c] interrupt enable register, offset: 0x31C8 */
507   __IO uint32_t TIO3_G0_CH7_IRQ_FORCINT;           /**< TIO[i] channel [c] force interrupt register, offset: 0x31CC */
508   __IO uint32_t TIO3_G0_CH7_IRQ_MODE;              /**< TIO[i] channel [c] IRQ mode configuration register, offset: 0x31D0 */
509   __IO uint32_t TIO3_G0_CH7_CTRL2;                 /**< TIO[i] group [g] channel [c] control register, offset: 0x31D4 */
510   uint8_t RESERVED_61[8];
511   __IO uint32_t TIO3_G0_CH7_SINST;                 /**< TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x31E0 */
512   __IO uint32_t TIO3_G0_CH7_SCMD;                  /**< TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0-, offset: 0x31E4 */
513   __IO uint32_t TIO3_G0_CH7_SOP;                   /**< TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ), offset: 0x31E8 */
514   uint8_t RESERVED_62[4];
515   __IO uint32_t TIO3_G0_CH7_OINST;                 /**< TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00-, offset: 0x31F0 */
516   __IO uint32_t TIO3_G0_CH7_OCMD;                  /**< TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00-, offset: 0x31F4 */
517   __IO uint32_t TIO3_G0_CH7_OOP;                   /**< TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-), offset: 0x31F8 */
518   __I  uint32_t TIO3_G0_CH7_SHIFTCNT;              /**< TIO[i] channel [c] resource shift count register, offset: 0x31FC */
519   __IO uint32_t TIO3_G0_ISEL0_CTRL1;               /**< TIO[i] input selection register 1, offset: 0x3200 */
520   __IO uint32_t TIO3_G0_ISEL0_CTRL2;               /**< TIO[i] input selection register 2, offset: 0x3204 */
521   uint8_t RESERVED_63[24];
522   __IO uint32_t TIO3_G0_ISEL1_CTRL1;               /**< TIO[i] input selection register 1, offset: 0x3220 */
523   __IO uint32_t TIO3_G0_ISEL1_CTRL2;               /**< TIO[i] input selection register 2, offset: 0x3224 */
524   uint8_t RESERVED_64[24];
525   __IO uint32_t TIO3_G0_OP_USAGE;                  /**< TIO[i] operand usage selection register, offset: 0x3240 */
526   uint8_t RESERVED_65[2492];
527   __IO uint32_t TIO3_S;                            /**< TIO[i] signal sampling register, offset: 0x3C00 */
528   __IO uint32_t TIO3_O;                            /**< TIO[i] output register, offset: 0x3C04 */
529   __IO uint32_t TIO3_ENDIS;                        /**< TIO[i] enable/disable register, offset: 0x3C08 */
530   __IO uint32_t TIO3_INVERT;                       /**< TIO[i] signal invert register, offset: 0x3C0C */
531   __IO uint32_t TIO3_INPUT_MODE;                   /**< TIO[i] input mode register, offset: 0x3C10 */
532   __IO uint32_t TIO3_CYCLIC_MODE;                  /**< TIO[i] cyclic mode register, offset: 0x3C14 */
533   __IO uint32_t TIO3_TRIG_OUT_GATE_EN;             /**< TIO[i] enable Trigger Output, output gating register, offset: 0x3C18 */
534   __IO uint32_t TIO3_PLTRIG_OUT_GATE_EN;           /**< TIO[i] enable PL_TRIG_OUT output gating register, offset: 0x3C1C */
535   uint8_t RESERVED_66[32];
536   __IO uint32_t TIO3_CS;                           /**< TIO[i] clear signal sampling register, offset: 0x3C40 */
537   __IO uint32_t TIO3_CO;                           /**< TIO[i] clear output register, offset: 0x3C44 */
538   __IO uint32_t TIO3_CENDIS;                       /**< TIO[i] disable register, offset: 0x3C48 */
539   __IO uint32_t TIO3_CINVERT;                      /**< TIO[i] clear signal invert register, offset: 0x3C4C */
540   __IO uint32_t TIO3_CINPUT_MODE;                  /**< TIO[i] disable input mode register, offset: 0x3C50 */
541   __IO uint32_t TIO3_CCYCLIC_MODE;                 /**< TIO[i] disable cyclic mode register, offset: 0x3C54 */
542   __IO uint32_t TIO3_CTRIG_OUT_GATE_EN;            /**< TIO[i] clear Trigger Output, output gating register, offset: 0x3C58 */
543   __IO uint32_t TIO3_CPLTRIG_OUT_GATE_EN;          /**< TIO[i] clear PL_TRIG_OUT output gating register, offset: 0x3C5C */
544   uint8_t RESERVED_67[32];
545   __IO uint32_t TIO3_SS;                           /**< TIO[i] set signal sampling register, offset: 0x3C80 */
546   __IO uint32_t TIO3_SO;                           /**< TIO[i] set output register, offset: 0x3C84 */
547   __IO uint32_t TIO3_SENDIS;                       /**< TIO[i] enable register, offset: 0x3C88 */
548   __IO uint32_t TIO3_SINVERT;                      /**< TIO[i] set signal invert register, offset: 0x3C8C */
549   __IO uint32_t TIO3_SINPUT_MODE;                  /**< TIO[i] enable input mode register, offset: 0x3C90 */
550   __IO uint32_t TIO3_SCYCLIC_MODE;                 /**< TIO[i] enable cyclic mode register, offset: 0x3C94 */
551   __IO uint32_t TIO3_STRIG_OUT_GATE_EN;            /**< TIO[i] set Trigger Output, output gating register, offset: 0x3C98 */
552   __IO uint32_t TIO3_SPLTRIG_OUT_GATE_EN;          /**< TIO[i] set PL_TRIG_OUT output gating register, offset: 0x3C9C */
553   uint8_t RESERVED_68[32];
554   __IO uint32_t TIO3_IS;                           /**< TIO[i] invert signal sampling register, offset: 0x3CC0 */
555   __IO uint32_t TIO3_IO;                           /**< TIO[i] invert output register, offset: 0x3CC4 */
556   __IO uint32_t TIO3_IENDIS;                       /**< TIO[i] toggle enable/disable register, offset: 0x3CC8 */
557   __IO uint32_t TIO3_IINVERT;                      /**< TIO[i] toggle signal invert register, offset: 0x3CCC */
558   __IO uint32_t TIO3_IINPUT_MODE;                  /**< TIO[i] enable input mode register, offset: 0x3CD0 */
559   __IO uint32_t TIO3_ICYCLIC_MODE;                 /**< TIO[i] enable cyclic mode register, offset: 0x3CD4 */
560   uint8_t RESERVED_69[40];
561   __IO uint32_t TIO3_FUPD;                         /**< TIO[i] force update register, offset: 0x3D00 */
562   __I  uint32_t TIO3_HW_CONF;                      /**< TIO[i] configuration register, offset: 0x3D04 */
563   __IO uint32_t TIO3_RSEL_CTRL1;                   /**< TIO[i] resource selection control register 1, offset: 0x3D08 */
564   __IO uint32_t TIO3_RSEL_CTRL2;                   /**< TIO[i] resource selection control register 2, offset: 0x3D0C */
565   __IO uint32_t TIO3_PL_SWRST;                     /**< TIO[i] software reset for TIO Plus functionality, offset: 0x3D10 */
566   uint8_t RESERVED_70[748];
567   __IO uint32_t CCM3_ARP0_CTRL;                    /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4000 */
568   __IO uint32_t CCM3_ARP0_PROT;                    /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4004 */
569   __IO uint32_t CCM3_ARP1_CTRL;                    /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4008 */
570   __IO uint32_t CCM3_ARP1_PROT;                    /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x400C */
571   __IO uint32_t CCM3_ARP2_CTRL;                    /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4010 */
572   __IO uint32_t CCM3_ARP2_PROT;                    /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4014 */
573   __IO uint32_t CCM3_ARP3_CTRL;                    /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4018 */
574   __IO uint32_t CCM3_ARP3_PROT;                    /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x401C */
575   __IO uint32_t CCM3_ARP4_CTRL;                    /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4020 */
576   __IO uint32_t CCM3_ARP4_PROT;                    /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4024 */
577   __IO uint32_t CCM3_ARP5_CTRL;                    /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4028 */
578   __IO uint32_t CCM3_ARP5_PROT;                    /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x402C */
579   __IO uint32_t CCM3_ARP6_CTRL;                    /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4030 */
580   __IO uint32_t CCM3_ARP6_PROT;                    /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4034 */
581   __IO uint32_t CCM3_ARP7_CTRL;                    /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4038 */
582   __IO uint32_t CCM3_ARP7_PROT;                    /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x403C */
583   __IO uint32_t CCM3_ARP8_CTRL;                    /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4040 */
584   __IO uint32_t CCM3_ARP8_PROT;                    /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x4044 */
585   __IO uint32_t CCM3_ARP9_CTRL;                    /**< CCM[i] Address Range Protector [a] Control Register, offset: 0x4048 */
586   __IO uint32_t CCM3_ARP9_PROT;                    /**< CCM[i] Address Range Protector [a] Protection Register, offset: 0x404C */
587   uint8_t RESERVED_71[380];
588   __I  uint32_t CCM3_TIO_G0_OUT;                   /**< CCM[i] TIO Group 0,1 Output Register, offset: 0x41CC */
589   uint8_t RESERVED_72[4];
590   __I  uint32_t CCM3_HW_CONF2;                     /**< CCM[i] 2. Hardware Configuration Register, offset: 0x41D4 */
591   __IO uint32_t CCM3_AEIM_STA;                     /**< CCM[i] MCS Bus Master Status Register, offset: 0x41D8 */
592   __I  uint32_t CCM3_HW_CONF;                      /**< CCM[i] Hardware Configuration Register, offset: 0x41DC */
593   uint8_t RESERVED_73[12];
594   __I  uint32_t CCM3_ATOM_OUT;                     /**< CCM[i] ATOM Output Register, offset: 0x41EC */
595   __IO uint32_t CCM3_CMU_CLK_CFG;                  /**< CCM[i] CMU Clock Configuration Register, offset: 0x41F0 */
596   uint8_t RESERVED_74[4];
597   __IO uint32_t CCM3_CFG;                          /**< CCM[i] Configuration Register, offset: 0x41F8 */
598   __IO uint32_t CCM3_PROT;                         /**< CCM[i] Protection Register, offset: 0x41FC */
599   uint8_t RESERVED_75[768];
600   __IO uint32_t CDTM3_DTM4_CTRL;                   /**< CDTM[i]_DTM[d] global configuration and control register, offset: 0x4500 */
601   __IO uint32_t CDTM3_DTM4_CH_CTRL1;               /**< CDTM[i]_DTM[d] channel control register 1, offset: 0x4504 */
602   __IO uint32_t CDTM3_DTM4_CH_CTRL2;               /**< CDTM[i]_DTM[d] channel control register 2, offset: 0x4508 */
603   __IO uint32_t CDTM3_DTM4_CH_CTRL2_SR;            /**< CDTM[i] DTM[j] channel control register 2 shadow, offset: 0x450C */
604   __IO uint32_t CDTM3_DTM4_PS_CTRL;                /**< CDTM[i]_DTM[d] phase shift unit configuration and control register, offset: 0x4510 */
605   __IO uint32_t CDTM3_DTM4_CH_DTV[GTM_gtm_cls3_CDTM3_DTM4_CH4_DTV_COUNT]; /**< CDTM[i]_DTM[d] channel [x] dead time reload values, array offset: 0x4514, array step: 0x4 */
606   __IO uint32_t CDTM3_DTM4_CH_SR;                  /**< CDTM[i]_DTM[d] channel shadow register, offset: 0x4524 */
607   __IO uint32_t CDTM3_DTM4_CH_CTRL3;               /**< CDTM[i]_DTM[d] channel control register 3, offset: 0x4528 */
608   __IO uint32_t CDTM3_DTM4_CTRL2;                  /**< CDTM[i]_DTM[d] global configuration and control register 2, offset: 0x452C */
609   __IO uint32_t CDTM3_DTM4_CH0_DTV_SR;             /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4530 */
610   __IO uint32_t CDTM3_DTM4_CH1_DTV_SR;             /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4534 */
611   __IO uint32_t CDTM3_DTM4_CH2_DTV_SR;             /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4538 */
612   __IO uint32_t CDTM3_DTM4_CH3_DTV_SR;             /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x453C */
613   __IO uint32_t CDTM3_DTM5_CTRL;                   /**< CDTM[i]_DTM[d] global configuration and control register, offset: 0x4540 */
614   __IO uint32_t CDTM3_DTM5_CH_CTRL1;               /**< CDTM[i]_DTM[d] channel control register 1, offset: 0x4544 */
615   __IO uint32_t CDTM3_DTM5_CH_CTRL2;               /**< CDTM[i]_DTM[d] channel control register 2, offset: 0x4548 */
616   __IO uint32_t CDTM3_DTM5_CH_CTRL2_SR;            /**< CDTM[i] DTM[j] channel control register 2 shadow, offset: 0x454C */
617   __IO uint32_t CDTM3_DTM5_PS_CTRL;                /**< CDTM[i]_DTM[d] phase shift unit configuration and control register, offset: 0x4550 */
618   __IO uint32_t CDTM3_DTM5_CH_DTV[GTM_gtm_cls3_CDTM3_DTM5_CH4_DTV_COUNT]; /**< CDTM[i]_DTM[d] channel [x] dead time reload values, array offset: 0x4554, array step: 0x4 */
619   __IO uint32_t CDTM3_DTM5_CH_SR;                  /**< CDTM[i]_DTM[d] channel shadow register, offset: 0x4564 */
620   __IO uint32_t CDTM3_DTM5_CH_CTRL3;               /**< CDTM[i]_DTM[d] channel control register 3, offset: 0x4568 */
621   __IO uint32_t CDTM3_DTM5_CTRL2;                  /**< CDTM[i]_DTM[d] global configuration and control register 2, offset: 0x456C */
622   __IO uint32_t CDTM3_DTM5_CH0_DTV_SR;             /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4570 */
623   __IO uint32_t CDTM3_DTM5_CH1_DTV_SR;             /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4574 */
624   __IO uint32_t CDTM3_DTM5_CH2_DTV_SR;             /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x4578 */
625   __IO uint32_t CDTM3_DTM5_CH3_DTV_SR;             /**< CDTM[i]_DTM[d] channel [x] dead time shadow values, offset: 0x457C */
626   uint8_t RESERVED_76[2688];
627   __I  uint32_t AXIM3_FREE;                        /**< AXIM[i] slot allocation status., offset: 0x5000 */
628   __I  uint32_t AXIM3_REQUEST;                     /**< AXIM[i] slot request (allocation)., offset: 0x5004 */
629   __IO uint32_t AXIM3_RELEASE;                     /**< AXIM[i] slot release (de-allocation)., offset: 0x5008 */
630   uint8_t RESERVED_77[20];
631   __IO uint32_t AXIM3_SLOT0_ADDR_LOW;              /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5020 */
632   uint8_t RESERVED_78[4];
633   __IO uint32_t AXIM3_SLOT0_DATA_LOW;              /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5028 */
634   uint8_t RESERVED_79[4];
635   __IO uint32_t AXIM3_SLOT0_CFG1;                  /**< AXIM[i] slot [s] configuration 1, offset: 0x5030 */
636   __IO uint32_t AXIM3_SLOT0_CFG2;                  /**< AXIM[i] slot[s] configuration 2, offset: 0x5034 */
637   __I  uint32_t AXIM3_SLOT0_STATUS;                /**< AXIM[i] slot[s] status, offset: 0x5038 */
638   uint8_t RESERVED_80[4];
639   __IO uint32_t AXIM3_SLOT1_ADDR_LOW;              /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5040 */
640   uint8_t RESERVED_81[4];
641   __IO uint32_t AXIM3_SLOT1_DATA_LOW;              /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5048 */
642   uint8_t RESERVED_82[4];
643   __IO uint32_t AXIM3_SLOT1_CFG1;                  /**< AXIM[i] slot [s] configuration 1, offset: 0x5050 */
644   __IO uint32_t AXIM3_SLOT1_CFG2;                  /**< AXIM[i] slot[s] configuration 2, offset: 0x5054 */
645   __I  uint32_t AXIM3_SLOT1_STATUS;                /**< AXIM[i] slot[s] status, offset: 0x5058 */
646   uint8_t RESERVED_83[4];
647   __IO uint32_t AXIM3_SLOT2_ADDR_LOW;              /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5060 */
648   uint8_t RESERVED_84[4];
649   __IO uint32_t AXIM3_SLOT2_DATA_LOW;              /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5068 */
650   uint8_t RESERVED_85[4];
651   __IO uint32_t AXIM3_SLOT2_CFG1;                  /**< AXIM[i] slot [s] configuration 1, offset: 0x5070 */
652   __IO uint32_t AXIM3_SLOT2_CFG2;                  /**< AXIM[i] slot[s] configuration 2, offset: 0x5074 */
653   __I  uint32_t AXIM3_SLOT2_STATUS;                /**< AXIM[i] slot[s] status, offset: 0x5078 */
654   uint8_t RESERVED_86[4];
655   __IO uint32_t AXIM3_SLOT3_ADDR_LOW;              /**< AXIM[i] slot[s] address bits 31:0 of AXI transaction., offset: 0x5080 */
656   uint8_t RESERVED_87[4];
657   __IO uint32_t AXIM3_SLOT3_DATA_LOW;              /**< AXIM[i] slot[s] data bits 31:0 of AXI transaction., offset: 0x5088 */
658   uint8_t RESERVED_88[4];
659   __IO uint32_t AXIM3_SLOT3_CFG1;                  /**< AXIM[i] slot [s] configuration 1, offset: 0x5090 */
660   __IO uint32_t AXIM3_SLOT3_CFG2;                  /**< AXIM[i] slot[s] configuration 2, offset: 0x5094 */
661   __I  uint32_t AXIM3_SLOT3_STATUS;                /**< AXIM[i] slot[s] status, offset: 0x5098 */
662   uint8_t RESERVED_89[44900];
663   __IO uint32_t MCS3_MEM[GTM_gtm_cls3_MCS3_MEM_COUNT]; /**< MCS[i] memory region, array offset: 0x10000, array step: 0x4 */
664 } GTM_gtm_cls3_Type, *GTM_gtm_cls3_MemMapPtr;
665 
666 /** Number of instances of the GTM_gtm_cls3 module. */
667 #define GTM_gtm_cls3_INSTANCE_COUNT              (1u)
668 
669 /* GTM_gtm_cls3 - Peripheral instance base addresses */
670 /** Peripheral GTM_gtm_cls3 base address */
671 #define IP_GTM_gtm_cls3_BASE                     (0x73060000u)
672 /** Peripheral GTM_gtm_cls3 base pointer */
673 #define IP_GTM_gtm_cls3                          ((GTM_gtm_cls3_Type *)IP_GTM_gtm_cls3_BASE)
674 /** Array initializer of GTM_gtm_cls3 peripheral base addresses */
675 #define IP_GTM_gtm_cls3_BASE_ADDRS               { IP_GTM_gtm_cls3_BASE }
676 /** Array initializer of GTM_gtm_cls3 peripheral base pointers */
677 #define IP_GTM_gtm_cls3_BASE_PTRS                { IP_GTM_gtm_cls3 }
678 
679 /* ----------------------------------------------------------------------------
680    -- GTM_gtm_cls3 Register Masks
681    ---------------------------------------------------------------------------- */
682 
683 /*!
684  * @addtogroup GTM_gtm_cls3_Register_Masks GTM_gtm_cls3 Register Masks
685  * @{
686  */
687 
688 /*! @name ATOM3_CH0_RDADDR - ATOM[i] channel[x] ARU read address register */
689 /*! @{ */
690 
691 #define GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR0_MASK (0x1FFU)
692 #define GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR0_SHIFT (0U)
693 #define GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR0_WIDTH (9U)
694 #define GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR0_MASK)
695 
696 #define GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR1_MASK (0x1FF0000U)
697 #define GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR1_SHIFT (16U)
698 #define GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR1_WIDTH (9U)
699 #define GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_RDADDR_RDADDR1_MASK)
700 /*! @} */
701 
702 /*! @name ATOM3_CH0_CTRL - ATOM[i] channel [x] control register */
703 /*! @{ */
704 
705 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_MODE_MASK    (0x3U)
706 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_MODE_SHIFT   (0U)
707 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_MODE_WIDTH   (2U)
708 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_MODE_MASK)
709 
710 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TB12_SEL_MASK (0x4U)
711 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TB12_SEL_SHIFT (2U)
712 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TB12_SEL_WIDTH (1U)
713 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TB12_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_TB12_SEL_MASK)
714 
715 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ARU_EN_MASK  (0x8U)
716 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ARU_EN_SHIFT (3U)
717 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ARU_EN_WIDTH (1U)
718 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ARU_EN(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_ARU_EN_MASK)
719 
720 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ACB_MASK     (0x1F0U)
721 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ACB_SHIFT    (4U)
722 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ACB_WIDTH    (5U)
723 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ACB(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_ACB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_ACB_MASK)
724 
725 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_CMP_CTRL_MASK (0x200U)
726 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_CMP_CTRL_SHIFT (9U)
727 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_CMP_CTRL_WIDTH (1U)
728 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_CMP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_CMP_CTRL_MASK)
729 
730 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EUPM_MASK    (0x400U)
731 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EUPM_SHIFT   (10U)
732 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EUPM_WIDTH   (1U)
733 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EUPM(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_EUPM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_EUPM_MASK)
734 
735 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SL_MASK      (0x800U)
736 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SL_SHIFT     (11U)
737 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SL_WIDTH     (1U)
738 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_SL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_SL_MASK)
739 
740 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_CLK_SRC_MASK (0xF000U)
741 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_CLK_SRC_SHIFT (12U)
742 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_CLK_SRC_WIDTH (4U)
743 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_CLK_SRC_MASK)
744 
745 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_WR_REQ_MASK  (0x10000U)
746 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_WR_REQ_SHIFT (16U)
747 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_WR_REQ_WIDTH (1U)
748 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_WR_REQ(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_WR_REQ_MASK)
749 
750 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIG_PULSE_MASK (0x20000U)
751 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIG_PULSE_SHIFT (17U)
752 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIG_PULSE_WIDTH (1U)
753 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIG_PULSE_MASK)
754 
755 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_UDMODE_MASK  (0xC0000U)
756 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_UDMODE_SHIFT (18U)
757 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_UDMODE_WIDTH (2U)
758 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_UDMODE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_UDMODE_MASK)
759 
760 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_RST_CCU0_MASK (0x100000U)
761 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_RST_CCU0_SHIFT (20U)
762 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_RST_CCU0_WIDTH (1U)
763 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_RST_CCU0(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_RST_CCU0_MASK)
764 
765 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_TRIG_MASK (0x200000U)
766 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_TRIG_SHIFT (21U)
767 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_TRIG_WIDTH (1U)
768 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_TRIG_MASK)
769 
770 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_TRIG_MASK (0x400000U)
771 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_TRIG_SHIFT (22U)
772 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_TRIG_WIDTH (1U)
773 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_TRIG_MASK)
774 
775 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXTTRIGOUT_MASK (0x800000U)
776 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXTTRIGOUT_SHIFT (23U)
777 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXTTRIGOUT_WIDTH (1U)
778 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_EXTTRIGOUT_MASK)
779 
780 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIGOUT_MASK (0x1000000U)
781 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIGOUT_SHIFT (24U)
782 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIGOUT_WIDTH (1U)
783 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIGOUT(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_TRIGOUT_MASK)
784 
785 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SLA_MASK     (0x2000000U)
786 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SLA_SHIFT    (25U)
787 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SLA_WIDTH    (1U)
788 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SLA(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_SLA_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_SLA_MASK)
789 
790 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_MASK     (0x4000000U)
791 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_SHIFT    (26U)
792 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_WIDTH    (1U)
793 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_OSM_MASK)
794 
795 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ABM_MASK     (0x8000000U)
796 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ABM_SHIFT    (27U)
797 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ABM_WIDTH    (1U)
798 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_ABM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_ABM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_ABM_MASK)
799 
800 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_FUPD_MASK (0x20000000U)
801 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_FUPD_SHIFT (29U)
802 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_FUPD_WIDTH (1U)
803 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_FUPD(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_EXT_FUPD_MASK)
804 
805 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SOMB_MASK    (0x40000000U)
806 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SOMB_SHIFT   (30U)
807 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SOMB_WIDTH   (1U)
808 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SOMB(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_SOMB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_SOMB_MASK)
809 
810 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_FREEZE_MASK  (0x80000000U)
811 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_FREEZE_SHIFT (31U)
812 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_FREEZE_WIDTH (1U)
813 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_FREEZE_MASK)
814 /*! @} */
815 
816 /*! @name ATOM3_CH0_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */
817 /*! @{ */
818 
819 #define GTM_gtm_cls3_ATOM3_CH0_SR0_SR0_MASK      (0xFFFFFFU)
820 #define GTM_gtm_cls3_ATOM3_CH0_SR0_SR0_SHIFT     (0U)
821 #define GTM_gtm_cls3_ATOM3_CH0_SR0_SR0_WIDTH     (24U)
822 #define GTM_gtm_cls3_ATOM3_CH0_SR0_SR0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_SR0_SR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_SR0_SR0_MASK)
823 /*! @} */
824 
825 /*! @name ATOM3_CH0_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */
826 /*! @{ */
827 
828 #define GTM_gtm_cls3_ATOM3_CH0_SR1_SR1_MASK      (0xFFFFFFU)
829 #define GTM_gtm_cls3_ATOM3_CH0_SR1_SR1_SHIFT     (0U)
830 #define GTM_gtm_cls3_ATOM3_CH0_SR1_SR1_WIDTH     (24U)
831 #define GTM_gtm_cls3_ATOM3_CH0_SR1_SR1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_SR1_SR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_SR1_SR1_MASK)
832 /*! @} */
833 
834 /*! @name ATOM3_CH0_CM0 - ATOM[i] channel [x] CCU0 compare register */
835 /*! @{ */
836 
837 #define GTM_gtm_cls3_ATOM3_CH0_CM0_CM0_MASK      (0xFFFFFFU)
838 #define GTM_gtm_cls3_ATOM3_CH0_CM0_CM0_SHIFT     (0U)
839 #define GTM_gtm_cls3_ATOM3_CH0_CM0_CM0_WIDTH     (24U)
840 #define GTM_gtm_cls3_ATOM3_CH0_CM0_CM0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CM0_CM0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CM0_CM0_MASK)
841 /*! @} */
842 
843 /*! @name ATOM3_CH0_CM1 - ATOM[i] channel [x] CCU0 compare register */
844 /*! @{ */
845 
846 #define GTM_gtm_cls3_ATOM3_CH0_CM1_CM1_MASK      (0xFFFFFFU)
847 #define GTM_gtm_cls3_ATOM3_CH0_CM1_CM1_SHIFT     (0U)
848 #define GTM_gtm_cls3_ATOM3_CH0_CM1_CM1_WIDTH     (24U)
849 #define GTM_gtm_cls3_ATOM3_CH0_CM1_CM1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CM1_CM1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CM1_CM1_MASK)
850 /*! @} */
851 
852 /*! @name ATOM3_CH0_CN0 - ATOM[i] channel [x] CCU0 counter register */
853 /*! @{ */
854 
855 #define GTM_gtm_cls3_ATOM3_CH0_CN0_CN0_MASK      (0xFFFFFFU)
856 #define GTM_gtm_cls3_ATOM3_CH0_CN0_CN0_SHIFT     (0U)
857 #define GTM_gtm_cls3_ATOM3_CH0_CN0_CN0_WIDTH     (24U)
858 #define GTM_gtm_cls3_ATOM3_CH0_CN0_CN0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CN0_CN0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CN0_CN0_MASK)
859 /*! @} */
860 
861 /*! @name ATOM3_CH0_STAT - ATOM[i] channel [x] status register */
862 /*! @{ */
863 
864 #define GTM_gtm_cls3_ATOM3_CH0_STAT_OL_MASK      (0x1U)
865 #define GTM_gtm_cls3_ATOM3_CH0_STAT_OL_SHIFT     (0U)
866 #define GTM_gtm_cls3_ATOM3_CH0_STAT_OL_WIDTH     (1U)
867 #define GTM_gtm_cls3_ATOM3_CH0_STAT_OL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_STAT_OL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_STAT_OL_MASK)
868 
869 #define GTM_gtm_cls3_ATOM3_CH0_STAT_ACBI_MASK    (0x1F0000U)
870 #define GTM_gtm_cls3_ATOM3_CH0_STAT_ACBI_SHIFT   (16U)
871 #define GTM_gtm_cls3_ATOM3_CH0_STAT_ACBI_WIDTH   (5U)
872 #define GTM_gtm_cls3_ATOM3_CH0_STAT_ACBI(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_STAT_ACBI_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_STAT_ACBI_MASK)
873 
874 #define GTM_gtm_cls3_ATOM3_CH0_STAT_DV_MASK      (0x200000U)
875 #define GTM_gtm_cls3_ATOM3_CH0_STAT_DV_SHIFT     (21U)
876 #define GTM_gtm_cls3_ATOM3_CH0_STAT_DV_WIDTH     (1U)
877 #define GTM_gtm_cls3_ATOM3_CH0_STAT_DV(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_STAT_DV_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_STAT_DV_MASK)
878 
879 #define GTM_gtm_cls3_ATOM3_CH0_STAT_WRF_MASK     (0x400000U)
880 #define GTM_gtm_cls3_ATOM3_CH0_STAT_WRF_SHIFT    (22U)
881 #define GTM_gtm_cls3_ATOM3_CH0_STAT_WRF_WIDTH    (1U)
882 #define GTM_gtm_cls3_ATOM3_CH0_STAT_WRF(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_STAT_WRF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_STAT_WRF_MASK)
883 
884 #define GTM_gtm_cls3_ATOM3_CH0_STAT_DR_MASK      (0x800000U)
885 #define GTM_gtm_cls3_ATOM3_CH0_STAT_DR_SHIFT     (23U)
886 #define GTM_gtm_cls3_ATOM3_CH0_STAT_DR_WIDTH     (1U)
887 #define GTM_gtm_cls3_ATOM3_CH0_STAT_DR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_STAT_DR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_STAT_DR_MASK)
888 
889 #define GTM_gtm_cls3_ATOM3_CH0_STAT_ACBO_MASK    (0x1F000000U)
890 #define GTM_gtm_cls3_ATOM3_CH0_STAT_ACBO_SHIFT   (24U)
891 #define GTM_gtm_cls3_ATOM3_CH0_STAT_ACBO_WIDTH   (5U)
892 #define GTM_gtm_cls3_ATOM3_CH0_STAT_ACBO(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_STAT_ACBO_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_STAT_ACBO_MASK)
893 
894 #define GTM_gtm_cls3_ATOM3_CH0_STAT_OSM_RTF_MASK (0x20000000U)
895 #define GTM_gtm_cls3_ATOM3_CH0_STAT_OSM_RTF_SHIFT (29U)
896 #define GTM_gtm_cls3_ATOM3_CH0_STAT_OSM_RTF_WIDTH (1U)
897 #define GTM_gtm_cls3_ATOM3_CH0_STAT_OSM_RTF(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_STAT_OSM_RTF_MASK)
898 /*! @} */
899 
900 /*! @name ATOM3_CH0_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */
901 /*! @{ */
902 
903 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU0TC_MASK (0x1U)
904 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU0TC_SHIFT (0U)
905 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU0TC_WIDTH (1U)
906 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU0TC_MASK)
907 
908 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU1TC_MASK (0x2U)
909 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU1TC_SHIFT (1U)
910 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU1TC_WIDTH (1U)
911 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_IRQ_NOTIFY_CCU1TC_MASK)
912 /*! @} */
913 
914 /*! @name ATOM3_CH0_IRQ_EN - ATOM[i] channel [x] interrupt enable register */
915 /*! @{ */
916 
917 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U)
918 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U)
919 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U)
920 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU0TC_IRQ_EN_MASK)
921 
922 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U)
923 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U)
924 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U)
925 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_IRQ_EN_CCU1TC_IRQ_EN_MASK)
926 /*! @} */
927 
928 /*! @name ATOM3_CH0_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */
929 /*! @{ */
930 
931 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U)
932 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U)
933 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U)
934 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU0TC_MASK)
935 
936 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U)
937 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U)
938 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U)
939 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_IRQ_FORCINT_TRG_CCU1TC_MASK)
940 /*! @} */
941 
942 /*! @name ATOM3_CH0_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */
943 /*! @{ */
944 
945 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U)
946 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U)
947 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U)
948 #define GTM_gtm_cls3_ATOM3_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_IRQ_MODE_IRQ_MODE_MASK)
949 /*! @} */
950 
951 /*! @name ATOM3_CH0_CTRL_SR - ATOM[i] channel [x] control shadow register */
952 /*! @{ */
953 
954 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_SL_SR_MASK (0x800U)
955 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_SL_SR_SHIFT (11U)
956 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_SL_SR_WIDTH (1U)
957 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_SL_SR(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_SL_SR_MASK)
958 
959 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_CLK_SRC_SR_MASK (0xF000U)
960 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_CLK_SRC_SR_SHIFT (12U)
961 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_CLK_SRC_SR_WIDTH (4U)
962 #define GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH0_CTRL_SR_CLK_SRC_SR_MASK)
963 /*! @} */
964 
965 /*! @name ATOM3_CH1_RDADDR - ATOM[i] channel[x] ARU read address register */
966 /*! @{ */
967 
968 #define GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR0_MASK (0x1FFU)
969 #define GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR0_SHIFT (0U)
970 #define GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR0_WIDTH (9U)
971 #define GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR0_MASK)
972 
973 #define GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR1_MASK (0x1FF0000U)
974 #define GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR1_SHIFT (16U)
975 #define GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR1_WIDTH (9U)
976 #define GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_RDADDR_RDADDR1_MASK)
977 /*! @} */
978 
979 /*! @name ATOM3_CH1_CTRL - ATOM[i] channel [x] control register */
980 /*! @{ */
981 
982 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_MODE_MASK    (0x3U)
983 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_MODE_SHIFT   (0U)
984 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_MODE_WIDTH   (2U)
985 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_MODE_MASK)
986 
987 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TB12_SEL_MASK (0x4U)
988 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TB12_SEL_SHIFT (2U)
989 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TB12_SEL_WIDTH (1U)
990 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TB12_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_TB12_SEL_MASK)
991 
992 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ARU_EN_MASK  (0x8U)
993 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ARU_EN_SHIFT (3U)
994 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ARU_EN_WIDTH (1U)
995 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ARU_EN(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_ARU_EN_MASK)
996 
997 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ACB_MASK     (0x1F0U)
998 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ACB_SHIFT    (4U)
999 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ACB_WIDTH    (5U)
1000 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ACB(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_ACB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_ACB_MASK)
1001 
1002 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_CMP_CTRL_MASK (0x200U)
1003 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_CMP_CTRL_SHIFT (9U)
1004 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_CMP_CTRL_WIDTH (1U)
1005 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_CMP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_CMP_CTRL_MASK)
1006 
1007 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EUPM_MASK    (0x400U)
1008 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EUPM_SHIFT   (10U)
1009 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EUPM_WIDTH   (1U)
1010 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EUPM(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_EUPM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_EUPM_MASK)
1011 
1012 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SL_MASK      (0x800U)
1013 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SL_SHIFT     (11U)
1014 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SL_WIDTH     (1U)
1015 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_SL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_SL_MASK)
1016 
1017 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_CLK_SRC_MASK (0xF000U)
1018 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_CLK_SRC_SHIFT (12U)
1019 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_CLK_SRC_WIDTH (4U)
1020 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_CLK_SRC_MASK)
1021 
1022 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_WR_REQ_MASK  (0x10000U)
1023 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_WR_REQ_SHIFT (16U)
1024 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_WR_REQ_WIDTH (1U)
1025 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_WR_REQ(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_WR_REQ_MASK)
1026 
1027 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIG_PULSE_MASK (0x20000U)
1028 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIG_PULSE_SHIFT (17U)
1029 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIG_PULSE_WIDTH (1U)
1030 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIG_PULSE_MASK)
1031 
1032 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_UDMODE_MASK  (0xC0000U)
1033 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_UDMODE_SHIFT (18U)
1034 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_UDMODE_WIDTH (2U)
1035 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_UDMODE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_UDMODE_MASK)
1036 
1037 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_RST_CCU0_MASK (0x100000U)
1038 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_RST_CCU0_SHIFT (20U)
1039 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_RST_CCU0_WIDTH (1U)
1040 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_RST_CCU0(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_RST_CCU0_MASK)
1041 
1042 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_TRIG_MASK (0x200000U)
1043 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_TRIG_SHIFT (21U)
1044 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_TRIG_WIDTH (1U)
1045 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_TRIG_MASK)
1046 
1047 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_TRIG_MASK (0x400000U)
1048 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_TRIG_SHIFT (22U)
1049 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_TRIG_WIDTH (1U)
1050 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_TRIG_MASK)
1051 
1052 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXTTRIGOUT_MASK (0x800000U)
1053 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXTTRIGOUT_SHIFT (23U)
1054 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXTTRIGOUT_WIDTH (1U)
1055 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_EXTTRIGOUT_MASK)
1056 
1057 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIGOUT_MASK (0x1000000U)
1058 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIGOUT_SHIFT (24U)
1059 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIGOUT_WIDTH (1U)
1060 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIGOUT(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_TRIGOUT_MASK)
1061 
1062 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SLA_MASK     (0x2000000U)
1063 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SLA_SHIFT    (25U)
1064 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SLA_WIDTH    (1U)
1065 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SLA(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_SLA_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_SLA_MASK)
1066 
1067 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_MASK     (0x4000000U)
1068 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_SHIFT    (26U)
1069 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_WIDTH    (1U)
1070 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_OSM_MASK)
1071 
1072 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ABM_MASK     (0x8000000U)
1073 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ABM_SHIFT    (27U)
1074 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ABM_WIDTH    (1U)
1075 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_ABM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_ABM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_ABM_MASK)
1076 
1077 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_FUPD_MASK (0x20000000U)
1078 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_FUPD_SHIFT (29U)
1079 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_FUPD_WIDTH (1U)
1080 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_FUPD(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_EXT_FUPD_MASK)
1081 
1082 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SOMB_MASK    (0x40000000U)
1083 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SOMB_SHIFT   (30U)
1084 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SOMB_WIDTH   (1U)
1085 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SOMB(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_SOMB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_SOMB_MASK)
1086 
1087 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_FREEZE_MASK  (0x80000000U)
1088 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_FREEZE_SHIFT (31U)
1089 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_FREEZE_WIDTH (1U)
1090 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_FREEZE_MASK)
1091 /*! @} */
1092 
1093 /*! @name ATOM3_CH1_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */
1094 /*! @{ */
1095 
1096 #define GTM_gtm_cls3_ATOM3_CH1_SR0_SR0_MASK      (0xFFFFFFU)
1097 #define GTM_gtm_cls3_ATOM3_CH1_SR0_SR0_SHIFT     (0U)
1098 #define GTM_gtm_cls3_ATOM3_CH1_SR0_SR0_WIDTH     (24U)
1099 #define GTM_gtm_cls3_ATOM3_CH1_SR0_SR0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_SR0_SR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_SR0_SR0_MASK)
1100 /*! @} */
1101 
1102 /*! @name ATOM3_CH1_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */
1103 /*! @{ */
1104 
1105 #define GTM_gtm_cls3_ATOM3_CH1_SR1_SR1_MASK      (0xFFFFFFU)
1106 #define GTM_gtm_cls3_ATOM3_CH1_SR1_SR1_SHIFT     (0U)
1107 #define GTM_gtm_cls3_ATOM3_CH1_SR1_SR1_WIDTH     (24U)
1108 #define GTM_gtm_cls3_ATOM3_CH1_SR1_SR1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_SR1_SR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_SR1_SR1_MASK)
1109 /*! @} */
1110 
1111 /*! @name ATOM3_CH1_CM0 - ATOM[i] channel [x] CCU0 compare register */
1112 /*! @{ */
1113 
1114 #define GTM_gtm_cls3_ATOM3_CH1_CM0_CM0_MASK      (0xFFFFFFU)
1115 #define GTM_gtm_cls3_ATOM3_CH1_CM0_CM0_SHIFT     (0U)
1116 #define GTM_gtm_cls3_ATOM3_CH1_CM0_CM0_WIDTH     (24U)
1117 #define GTM_gtm_cls3_ATOM3_CH1_CM0_CM0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CM0_CM0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CM0_CM0_MASK)
1118 /*! @} */
1119 
1120 /*! @name ATOM3_CH1_CM1 - ATOM[i] channel [x] CCU0 compare register */
1121 /*! @{ */
1122 
1123 #define GTM_gtm_cls3_ATOM3_CH1_CM1_CM1_MASK      (0xFFFFFFU)
1124 #define GTM_gtm_cls3_ATOM3_CH1_CM1_CM1_SHIFT     (0U)
1125 #define GTM_gtm_cls3_ATOM3_CH1_CM1_CM1_WIDTH     (24U)
1126 #define GTM_gtm_cls3_ATOM3_CH1_CM1_CM1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CM1_CM1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CM1_CM1_MASK)
1127 /*! @} */
1128 
1129 /*! @name ATOM3_CH1_CN0 - ATOM[i] channel [x] CCU0 counter register */
1130 /*! @{ */
1131 
1132 #define GTM_gtm_cls3_ATOM3_CH1_CN0_CN0_MASK      (0xFFFFFFU)
1133 #define GTM_gtm_cls3_ATOM3_CH1_CN0_CN0_SHIFT     (0U)
1134 #define GTM_gtm_cls3_ATOM3_CH1_CN0_CN0_WIDTH     (24U)
1135 #define GTM_gtm_cls3_ATOM3_CH1_CN0_CN0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CN0_CN0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CN0_CN0_MASK)
1136 /*! @} */
1137 
1138 /*! @name ATOM3_CH1_STAT - ATOM[i] channel [x] status register */
1139 /*! @{ */
1140 
1141 #define GTM_gtm_cls3_ATOM3_CH1_STAT_OL_MASK      (0x1U)
1142 #define GTM_gtm_cls3_ATOM3_CH1_STAT_OL_SHIFT     (0U)
1143 #define GTM_gtm_cls3_ATOM3_CH1_STAT_OL_WIDTH     (1U)
1144 #define GTM_gtm_cls3_ATOM3_CH1_STAT_OL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_STAT_OL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_STAT_OL_MASK)
1145 
1146 #define GTM_gtm_cls3_ATOM3_CH1_STAT_ACBI_MASK    (0x1F0000U)
1147 #define GTM_gtm_cls3_ATOM3_CH1_STAT_ACBI_SHIFT   (16U)
1148 #define GTM_gtm_cls3_ATOM3_CH1_STAT_ACBI_WIDTH   (5U)
1149 #define GTM_gtm_cls3_ATOM3_CH1_STAT_ACBI(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_STAT_ACBI_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_STAT_ACBI_MASK)
1150 
1151 #define GTM_gtm_cls3_ATOM3_CH1_STAT_DV_MASK      (0x200000U)
1152 #define GTM_gtm_cls3_ATOM3_CH1_STAT_DV_SHIFT     (21U)
1153 #define GTM_gtm_cls3_ATOM3_CH1_STAT_DV_WIDTH     (1U)
1154 #define GTM_gtm_cls3_ATOM3_CH1_STAT_DV(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_STAT_DV_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_STAT_DV_MASK)
1155 
1156 #define GTM_gtm_cls3_ATOM3_CH1_STAT_WRF_MASK     (0x400000U)
1157 #define GTM_gtm_cls3_ATOM3_CH1_STAT_WRF_SHIFT    (22U)
1158 #define GTM_gtm_cls3_ATOM3_CH1_STAT_WRF_WIDTH    (1U)
1159 #define GTM_gtm_cls3_ATOM3_CH1_STAT_WRF(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_STAT_WRF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_STAT_WRF_MASK)
1160 
1161 #define GTM_gtm_cls3_ATOM3_CH1_STAT_DR_MASK      (0x800000U)
1162 #define GTM_gtm_cls3_ATOM3_CH1_STAT_DR_SHIFT     (23U)
1163 #define GTM_gtm_cls3_ATOM3_CH1_STAT_DR_WIDTH     (1U)
1164 #define GTM_gtm_cls3_ATOM3_CH1_STAT_DR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_STAT_DR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_STAT_DR_MASK)
1165 
1166 #define GTM_gtm_cls3_ATOM3_CH1_STAT_ACBO_MASK    (0x1F000000U)
1167 #define GTM_gtm_cls3_ATOM3_CH1_STAT_ACBO_SHIFT   (24U)
1168 #define GTM_gtm_cls3_ATOM3_CH1_STAT_ACBO_WIDTH   (5U)
1169 #define GTM_gtm_cls3_ATOM3_CH1_STAT_ACBO(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_STAT_ACBO_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_STAT_ACBO_MASK)
1170 
1171 #define GTM_gtm_cls3_ATOM3_CH1_STAT_OSM_RTF_MASK (0x20000000U)
1172 #define GTM_gtm_cls3_ATOM3_CH1_STAT_OSM_RTF_SHIFT (29U)
1173 #define GTM_gtm_cls3_ATOM3_CH1_STAT_OSM_RTF_WIDTH (1U)
1174 #define GTM_gtm_cls3_ATOM3_CH1_STAT_OSM_RTF(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_STAT_OSM_RTF_MASK)
1175 /*! @} */
1176 
1177 /*! @name ATOM3_CH1_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */
1178 /*! @{ */
1179 
1180 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU0TC_MASK (0x1U)
1181 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU0TC_SHIFT (0U)
1182 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU0TC_WIDTH (1U)
1183 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU0TC_MASK)
1184 
1185 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU1TC_MASK (0x2U)
1186 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU1TC_SHIFT (1U)
1187 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU1TC_WIDTH (1U)
1188 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_IRQ_NOTIFY_CCU1TC_MASK)
1189 /*! @} */
1190 
1191 /*! @name ATOM3_CH1_IRQ_EN - ATOM[i] channel [x] interrupt enable register */
1192 /*! @{ */
1193 
1194 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U)
1195 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U)
1196 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U)
1197 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU0TC_IRQ_EN_MASK)
1198 
1199 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U)
1200 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U)
1201 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U)
1202 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_IRQ_EN_CCU1TC_IRQ_EN_MASK)
1203 /*! @} */
1204 
1205 /*! @name ATOM3_CH1_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */
1206 /*! @{ */
1207 
1208 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U)
1209 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U)
1210 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U)
1211 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU0TC_MASK)
1212 
1213 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U)
1214 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U)
1215 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U)
1216 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_IRQ_FORCINT_TRG_CCU1TC_MASK)
1217 /*! @} */
1218 
1219 /*! @name ATOM3_CH1_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */
1220 /*! @{ */
1221 
1222 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U)
1223 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U)
1224 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U)
1225 #define GTM_gtm_cls3_ATOM3_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_IRQ_MODE_IRQ_MODE_MASK)
1226 /*! @} */
1227 
1228 /*! @name ATOM3_CH1_CTRL_SR - ATOM[i] channel [x] control shadow register */
1229 /*! @{ */
1230 
1231 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_SL_SR_MASK (0x800U)
1232 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_SL_SR_SHIFT (11U)
1233 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_SL_SR_WIDTH (1U)
1234 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_SL_SR(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_SL_SR_MASK)
1235 
1236 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_CLK_SRC_SR_MASK (0xF000U)
1237 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_CLK_SRC_SR_SHIFT (12U)
1238 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_CLK_SRC_SR_WIDTH (4U)
1239 #define GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH1_CTRL_SR_CLK_SRC_SR_MASK)
1240 /*! @} */
1241 
1242 /*! @name ATOM3_CH2_RDADDR - ATOM[i] channel[x] ARU read address register */
1243 /*! @{ */
1244 
1245 #define GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR0_MASK (0x1FFU)
1246 #define GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR0_SHIFT (0U)
1247 #define GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR0_WIDTH (9U)
1248 #define GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR0_MASK)
1249 
1250 #define GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR1_MASK (0x1FF0000U)
1251 #define GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR1_SHIFT (16U)
1252 #define GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR1_WIDTH (9U)
1253 #define GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_RDADDR_RDADDR1_MASK)
1254 /*! @} */
1255 
1256 /*! @name ATOM3_CH2_CTRL - ATOM[i] channel [x] control register */
1257 /*! @{ */
1258 
1259 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_MODE_MASK    (0x3U)
1260 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_MODE_SHIFT   (0U)
1261 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_MODE_WIDTH   (2U)
1262 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_MODE_MASK)
1263 
1264 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TB12_SEL_MASK (0x4U)
1265 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TB12_SEL_SHIFT (2U)
1266 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TB12_SEL_WIDTH (1U)
1267 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TB12_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_TB12_SEL_MASK)
1268 
1269 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ARU_EN_MASK  (0x8U)
1270 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ARU_EN_SHIFT (3U)
1271 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ARU_EN_WIDTH (1U)
1272 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ARU_EN(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_ARU_EN_MASK)
1273 
1274 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ACB_MASK     (0x1F0U)
1275 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ACB_SHIFT    (4U)
1276 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ACB_WIDTH    (5U)
1277 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ACB(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_ACB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_ACB_MASK)
1278 
1279 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_CMP_CTRL_MASK (0x200U)
1280 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_CMP_CTRL_SHIFT (9U)
1281 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_CMP_CTRL_WIDTH (1U)
1282 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_CMP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_CMP_CTRL_MASK)
1283 
1284 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EUPM_MASK    (0x400U)
1285 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EUPM_SHIFT   (10U)
1286 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EUPM_WIDTH   (1U)
1287 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EUPM(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_EUPM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_EUPM_MASK)
1288 
1289 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SL_MASK      (0x800U)
1290 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SL_SHIFT     (11U)
1291 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SL_WIDTH     (1U)
1292 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_SL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_SL_MASK)
1293 
1294 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_CLK_SRC_MASK (0xF000U)
1295 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_CLK_SRC_SHIFT (12U)
1296 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_CLK_SRC_WIDTH (4U)
1297 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_CLK_SRC_MASK)
1298 
1299 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_WR_REQ_MASK  (0x10000U)
1300 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_WR_REQ_SHIFT (16U)
1301 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_WR_REQ_WIDTH (1U)
1302 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_WR_REQ(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_WR_REQ_MASK)
1303 
1304 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIG_PULSE_MASK (0x20000U)
1305 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIG_PULSE_SHIFT (17U)
1306 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIG_PULSE_WIDTH (1U)
1307 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIG_PULSE_MASK)
1308 
1309 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_UDMODE_MASK  (0xC0000U)
1310 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_UDMODE_SHIFT (18U)
1311 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_UDMODE_WIDTH (2U)
1312 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_UDMODE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_UDMODE_MASK)
1313 
1314 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_RST_CCU0_MASK (0x100000U)
1315 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_RST_CCU0_SHIFT (20U)
1316 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_RST_CCU0_WIDTH (1U)
1317 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_RST_CCU0(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_RST_CCU0_MASK)
1318 
1319 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_TRIG_MASK (0x200000U)
1320 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_TRIG_SHIFT (21U)
1321 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_TRIG_WIDTH (1U)
1322 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_TRIG_MASK)
1323 
1324 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_TRIG_MASK (0x400000U)
1325 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_TRIG_SHIFT (22U)
1326 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_TRIG_WIDTH (1U)
1327 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_TRIG_MASK)
1328 
1329 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXTTRIGOUT_MASK (0x800000U)
1330 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXTTRIGOUT_SHIFT (23U)
1331 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXTTRIGOUT_WIDTH (1U)
1332 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_EXTTRIGOUT_MASK)
1333 
1334 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIGOUT_MASK (0x1000000U)
1335 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIGOUT_SHIFT (24U)
1336 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIGOUT_WIDTH (1U)
1337 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIGOUT(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_TRIGOUT_MASK)
1338 
1339 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SLA_MASK     (0x2000000U)
1340 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SLA_SHIFT    (25U)
1341 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SLA_WIDTH    (1U)
1342 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SLA(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_SLA_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_SLA_MASK)
1343 
1344 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_MASK     (0x4000000U)
1345 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_SHIFT    (26U)
1346 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_WIDTH    (1U)
1347 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_OSM_MASK)
1348 
1349 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ABM_MASK     (0x8000000U)
1350 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ABM_SHIFT    (27U)
1351 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ABM_WIDTH    (1U)
1352 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_ABM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_ABM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_ABM_MASK)
1353 
1354 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_FUPD_MASK (0x20000000U)
1355 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_FUPD_SHIFT (29U)
1356 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_FUPD_WIDTH (1U)
1357 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_FUPD(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_EXT_FUPD_MASK)
1358 
1359 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SOMB_MASK    (0x40000000U)
1360 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SOMB_SHIFT   (30U)
1361 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SOMB_WIDTH   (1U)
1362 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SOMB(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_SOMB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_SOMB_MASK)
1363 
1364 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_FREEZE_MASK  (0x80000000U)
1365 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_FREEZE_SHIFT (31U)
1366 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_FREEZE_WIDTH (1U)
1367 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_FREEZE_MASK)
1368 /*! @} */
1369 
1370 /*! @name ATOM3_CH2_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */
1371 /*! @{ */
1372 
1373 #define GTM_gtm_cls3_ATOM3_CH2_SR0_SR0_MASK      (0xFFFFFFU)
1374 #define GTM_gtm_cls3_ATOM3_CH2_SR0_SR0_SHIFT     (0U)
1375 #define GTM_gtm_cls3_ATOM3_CH2_SR0_SR0_WIDTH     (24U)
1376 #define GTM_gtm_cls3_ATOM3_CH2_SR0_SR0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_SR0_SR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_SR0_SR0_MASK)
1377 /*! @} */
1378 
1379 /*! @name ATOM3_CH2_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */
1380 /*! @{ */
1381 
1382 #define GTM_gtm_cls3_ATOM3_CH2_SR1_SR1_MASK      (0xFFFFFFU)
1383 #define GTM_gtm_cls3_ATOM3_CH2_SR1_SR1_SHIFT     (0U)
1384 #define GTM_gtm_cls3_ATOM3_CH2_SR1_SR1_WIDTH     (24U)
1385 #define GTM_gtm_cls3_ATOM3_CH2_SR1_SR1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_SR1_SR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_SR1_SR1_MASK)
1386 /*! @} */
1387 
1388 /*! @name ATOM3_CH2_CM0 - ATOM[i] channel [x] CCU0 compare register */
1389 /*! @{ */
1390 
1391 #define GTM_gtm_cls3_ATOM3_CH2_CM0_CM0_MASK      (0xFFFFFFU)
1392 #define GTM_gtm_cls3_ATOM3_CH2_CM0_CM0_SHIFT     (0U)
1393 #define GTM_gtm_cls3_ATOM3_CH2_CM0_CM0_WIDTH     (24U)
1394 #define GTM_gtm_cls3_ATOM3_CH2_CM0_CM0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CM0_CM0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CM0_CM0_MASK)
1395 /*! @} */
1396 
1397 /*! @name ATOM3_CH2_CM1 - ATOM[i] channel [x] CCU0 compare register */
1398 /*! @{ */
1399 
1400 #define GTM_gtm_cls3_ATOM3_CH2_CM1_CM1_MASK      (0xFFFFFFU)
1401 #define GTM_gtm_cls3_ATOM3_CH2_CM1_CM1_SHIFT     (0U)
1402 #define GTM_gtm_cls3_ATOM3_CH2_CM1_CM1_WIDTH     (24U)
1403 #define GTM_gtm_cls3_ATOM3_CH2_CM1_CM1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CM1_CM1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CM1_CM1_MASK)
1404 /*! @} */
1405 
1406 /*! @name ATOM3_CH2_CN0 - ATOM[i] channel [x] CCU0 counter register */
1407 /*! @{ */
1408 
1409 #define GTM_gtm_cls3_ATOM3_CH2_CN0_CN0_MASK      (0xFFFFFFU)
1410 #define GTM_gtm_cls3_ATOM3_CH2_CN0_CN0_SHIFT     (0U)
1411 #define GTM_gtm_cls3_ATOM3_CH2_CN0_CN0_WIDTH     (24U)
1412 #define GTM_gtm_cls3_ATOM3_CH2_CN0_CN0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CN0_CN0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CN0_CN0_MASK)
1413 /*! @} */
1414 
1415 /*! @name ATOM3_CH2_STAT - ATOM[i] channel [x] status register */
1416 /*! @{ */
1417 
1418 #define GTM_gtm_cls3_ATOM3_CH2_STAT_OL_MASK      (0x1U)
1419 #define GTM_gtm_cls3_ATOM3_CH2_STAT_OL_SHIFT     (0U)
1420 #define GTM_gtm_cls3_ATOM3_CH2_STAT_OL_WIDTH     (1U)
1421 #define GTM_gtm_cls3_ATOM3_CH2_STAT_OL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_STAT_OL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_STAT_OL_MASK)
1422 
1423 #define GTM_gtm_cls3_ATOM3_CH2_STAT_ACBI_MASK    (0x1F0000U)
1424 #define GTM_gtm_cls3_ATOM3_CH2_STAT_ACBI_SHIFT   (16U)
1425 #define GTM_gtm_cls3_ATOM3_CH2_STAT_ACBI_WIDTH   (5U)
1426 #define GTM_gtm_cls3_ATOM3_CH2_STAT_ACBI(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_STAT_ACBI_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_STAT_ACBI_MASK)
1427 
1428 #define GTM_gtm_cls3_ATOM3_CH2_STAT_DV_MASK      (0x200000U)
1429 #define GTM_gtm_cls3_ATOM3_CH2_STAT_DV_SHIFT     (21U)
1430 #define GTM_gtm_cls3_ATOM3_CH2_STAT_DV_WIDTH     (1U)
1431 #define GTM_gtm_cls3_ATOM3_CH2_STAT_DV(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_STAT_DV_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_STAT_DV_MASK)
1432 
1433 #define GTM_gtm_cls3_ATOM3_CH2_STAT_WRF_MASK     (0x400000U)
1434 #define GTM_gtm_cls3_ATOM3_CH2_STAT_WRF_SHIFT    (22U)
1435 #define GTM_gtm_cls3_ATOM3_CH2_STAT_WRF_WIDTH    (1U)
1436 #define GTM_gtm_cls3_ATOM3_CH2_STAT_WRF(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_STAT_WRF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_STAT_WRF_MASK)
1437 
1438 #define GTM_gtm_cls3_ATOM3_CH2_STAT_DR_MASK      (0x800000U)
1439 #define GTM_gtm_cls3_ATOM3_CH2_STAT_DR_SHIFT     (23U)
1440 #define GTM_gtm_cls3_ATOM3_CH2_STAT_DR_WIDTH     (1U)
1441 #define GTM_gtm_cls3_ATOM3_CH2_STAT_DR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_STAT_DR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_STAT_DR_MASK)
1442 
1443 #define GTM_gtm_cls3_ATOM3_CH2_STAT_ACBO_MASK    (0x1F000000U)
1444 #define GTM_gtm_cls3_ATOM3_CH2_STAT_ACBO_SHIFT   (24U)
1445 #define GTM_gtm_cls3_ATOM3_CH2_STAT_ACBO_WIDTH   (5U)
1446 #define GTM_gtm_cls3_ATOM3_CH2_STAT_ACBO(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_STAT_ACBO_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_STAT_ACBO_MASK)
1447 
1448 #define GTM_gtm_cls3_ATOM3_CH2_STAT_OSM_RTF_MASK (0x20000000U)
1449 #define GTM_gtm_cls3_ATOM3_CH2_STAT_OSM_RTF_SHIFT (29U)
1450 #define GTM_gtm_cls3_ATOM3_CH2_STAT_OSM_RTF_WIDTH (1U)
1451 #define GTM_gtm_cls3_ATOM3_CH2_STAT_OSM_RTF(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_STAT_OSM_RTF_MASK)
1452 /*! @} */
1453 
1454 /*! @name ATOM3_CH2_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */
1455 /*! @{ */
1456 
1457 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU0TC_MASK (0x1U)
1458 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU0TC_SHIFT (0U)
1459 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU0TC_WIDTH (1U)
1460 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU0TC_MASK)
1461 
1462 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU1TC_MASK (0x2U)
1463 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU1TC_SHIFT (1U)
1464 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU1TC_WIDTH (1U)
1465 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_IRQ_NOTIFY_CCU1TC_MASK)
1466 /*! @} */
1467 
1468 /*! @name ATOM3_CH2_IRQ_EN - ATOM[i] channel [x] interrupt enable register */
1469 /*! @{ */
1470 
1471 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U)
1472 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U)
1473 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U)
1474 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU0TC_IRQ_EN_MASK)
1475 
1476 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U)
1477 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U)
1478 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U)
1479 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_IRQ_EN_CCU1TC_IRQ_EN_MASK)
1480 /*! @} */
1481 
1482 /*! @name ATOM3_CH2_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */
1483 /*! @{ */
1484 
1485 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U)
1486 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U)
1487 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U)
1488 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU0TC_MASK)
1489 
1490 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U)
1491 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U)
1492 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U)
1493 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_IRQ_FORCINT_TRG_CCU1TC_MASK)
1494 /*! @} */
1495 
1496 /*! @name ATOM3_CH2_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */
1497 /*! @{ */
1498 
1499 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U)
1500 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U)
1501 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U)
1502 #define GTM_gtm_cls3_ATOM3_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_IRQ_MODE_IRQ_MODE_MASK)
1503 /*! @} */
1504 
1505 /*! @name ATOM3_CH2_CTRL_SR - ATOM[i] channel [x] control shadow register */
1506 /*! @{ */
1507 
1508 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_SL_SR_MASK (0x800U)
1509 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_SL_SR_SHIFT (11U)
1510 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_SL_SR_WIDTH (1U)
1511 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_SL_SR(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_SL_SR_MASK)
1512 
1513 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_CLK_SRC_SR_MASK (0xF000U)
1514 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_CLK_SRC_SR_SHIFT (12U)
1515 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_CLK_SRC_SR_WIDTH (4U)
1516 #define GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH2_CTRL_SR_CLK_SRC_SR_MASK)
1517 /*! @} */
1518 
1519 /*! @name ATOM3_CH3_RDADDR - ATOM[i] channel[x] ARU read address register */
1520 /*! @{ */
1521 
1522 #define GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR0_MASK (0x1FFU)
1523 #define GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR0_SHIFT (0U)
1524 #define GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR0_WIDTH (9U)
1525 #define GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR0_MASK)
1526 
1527 #define GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR1_MASK (0x1FF0000U)
1528 #define GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR1_SHIFT (16U)
1529 #define GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR1_WIDTH (9U)
1530 #define GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_RDADDR_RDADDR1_MASK)
1531 /*! @} */
1532 
1533 /*! @name ATOM3_CH3_CTRL - ATOM[i] channel [x] control register */
1534 /*! @{ */
1535 
1536 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_MODE_MASK    (0x3U)
1537 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_MODE_SHIFT   (0U)
1538 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_MODE_WIDTH   (2U)
1539 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_MODE_MASK)
1540 
1541 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TB12_SEL_MASK (0x4U)
1542 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TB12_SEL_SHIFT (2U)
1543 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TB12_SEL_WIDTH (1U)
1544 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TB12_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_TB12_SEL_MASK)
1545 
1546 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ARU_EN_MASK  (0x8U)
1547 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ARU_EN_SHIFT (3U)
1548 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ARU_EN_WIDTH (1U)
1549 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ARU_EN(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_ARU_EN_MASK)
1550 
1551 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ACB_MASK     (0x1F0U)
1552 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ACB_SHIFT    (4U)
1553 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ACB_WIDTH    (5U)
1554 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ACB(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_ACB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_ACB_MASK)
1555 
1556 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_CMP_CTRL_MASK (0x200U)
1557 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_CMP_CTRL_SHIFT (9U)
1558 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_CMP_CTRL_WIDTH (1U)
1559 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_CMP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_CMP_CTRL_MASK)
1560 
1561 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EUPM_MASK    (0x400U)
1562 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EUPM_SHIFT   (10U)
1563 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EUPM_WIDTH   (1U)
1564 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EUPM(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_EUPM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_EUPM_MASK)
1565 
1566 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SL_MASK      (0x800U)
1567 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SL_SHIFT     (11U)
1568 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SL_WIDTH     (1U)
1569 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_SL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_SL_MASK)
1570 
1571 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_CLK_SRC_MASK (0xF000U)
1572 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_CLK_SRC_SHIFT (12U)
1573 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_CLK_SRC_WIDTH (4U)
1574 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_CLK_SRC_MASK)
1575 
1576 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_WR_REQ_MASK  (0x10000U)
1577 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_WR_REQ_SHIFT (16U)
1578 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_WR_REQ_WIDTH (1U)
1579 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_WR_REQ(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_WR_REQ_MASK)
1580 
1581 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIG_PULSE_MASK (0x20000U)
1582 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIG_PULSE_SHIFT (17U)
1583 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIG_PULSE_WIDTH (1U)
1584 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIG_PULSE_MASK)
1585 
1586 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_UDMODE_MASK  (0xC0000U)
1587 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_UDMODE_SHIFT (18U)
1588 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_UDMODE_WIDTH (2U)
1589 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_UDMODE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_UDMODE_MASK)
1590 
1591 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_RST_CCU0_MASK (0x100000U)
1592 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_RST_CCU0_SHIFT (20U)
1593 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_RST_CCU0_WIDTH (1U)
1594 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_RST_CCU0(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_RST_CCU0_MASK)
1595 
1596 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_TRIG_MASK (0x200000U)
1597 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_TRIG_SHIFT (21U)
1598 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_TRIG_WIDTH (1U)
1599 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_TRIG_MASK)
1600 
1601 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_TRIG_MASK (0x400000U)
1602 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_TRIG_SHIFT (22U)
1603 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_TRIG_WIDTH (1U)
1604 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_TRIG_MASK)
1605 
1606 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXTTRIGOUT_MASK (0x800000U)
1607 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXTTRIGOUT_SHIFT (23U)
1608 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXTTRIGOUT_WIDTH (1U)
1609 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_EXTTRIGOUT_MASK)
1610 
1611 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIGOUT_MASK (0x1000000U)
1612 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIGOUT_SHIFT (24U)
1613 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIGOUT_WIDTH (1U)
1614 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIGOUT(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_TRIGOUT_MASK)
1615 
1616 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SLA_MASK     (0x2000000U)
1617 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SLA_SHIFT    (25U)
1618 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SLA_WIDTH    (1U)
1619 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SLA(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_SLA_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_SLA_MASK)
1620 
1621 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_MASK     (0x4000000U)
1622 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_SHIFT    (26U)
1623 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_WIDTH    (1U)
1624 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_OSM_MASK)
1625 
1626 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ABM_MASK     (0x8000000U)
1627 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ABM_SHIFT    (27U)
1628 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ABM_WIDTH    (1U)
1629 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_ABM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_ABM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_ABM_MASK)
1630 
1631 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_FUPD_MASK (0x20000000U)
1632 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_FUPD_SHIFT (29U)
1633 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_FUPD_WIDTH (1U)
1634 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_FUPD(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_EXT_FUPD_MASK)
1635 
1636 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SOMB_MASK    (0x40000000U)
1637 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SOMB_SHIFT   (30U)
1638 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SOMB_WIDTH   (1U)
1639 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SOMB(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_SOMB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_SOMB_MASK)
1640 
1641 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_FREEZE_MASK  (0x80000000U)
1642 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_FREEZE_SHIFT (31U)
1643 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_FREEZE_WIDTH (1U)
1644 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_FREEZE_MASK)
1645 /*! @} */
1646 
1647 /*! @name ATOM3_CH3_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */
1648 /*! @{ */
1649 
1650 #define GTM_gtm_cls3_ATOM3_CH3_SR0_SR0_MASK      (0xFFFFFFU)
1651 #define GTM_gtm_cls3_ATOM3_CH3_SR0_SR0_SHIFT     (0U)
1652 #define GTM_gtm_cls3_ATOM3_CH3_SR0_SR0_WIDTH     (24U)
1653 #define GTM_gtm_cls3_ATOM3_CH3_SR0_SR0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_SR0_SR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_SR0_SR0_MASK)
1654 /*! @} */
1655 
1656 /*! @name ATOM3_CH3_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */
1657 /*! @{ */
1658 
1659 #define GTM_gtm_cls3_ATOM3_CH3_SR1_SR1_MASK      (0xFFFFFFU)
1660 #define GTM_gtm_cls3_ATOM3_CH3_SR1_SR1_SHIFT     (0U)
1661 #define GTM_gtm_cls3_ATOM3_CH3_SR1_SR1_WIDTH     (24U)
1662 #define GTM_gtm_cls3_ATOM3_CH3_SR1_SR1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_SR1_SR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_SR1_SR1_MASK)
1663 /*! @} */
1664 
1665 /*! @name ATOM3_CH3_CM0 - ATOM[i] channel [x] CCU0 compare register */
1666 /*! @{ */
1667 
1668 #define GTM_gtm_cls3_ATOM3_CH3_CM0_CM0_MASK      (0xFFFFFFU)
1669 #define GTM_gtm_cls3_ATOM3_CH3_CM0_CM0_SHIFT     (0U)
1670 #define GTM_gtm_cls3_ATOM3_CH3_CM0_CM0_WIDTH     (24U)
1671 #define GTM_gtm_cls3_ATOM3_CH3_CM0_CM0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CM0_CM0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CM0_CM0_MASK)
1672 /*! @} */
1673 
1674 /*! @name ATOM3_CH3_CM1 - ATOM[i] channel [x] CCU0 compare register */
1675 /*! @{ */
1676 
1677 #define GTM_gtm_cls3_ATOM3_CH3_CM1_CM1_MASK      (0xFFFFFFU)
1678 #define GTM_gtm_cls3_ATOM3_CH3_CM1_CM1_SHIFT     (0U)
1679 #define GTM_gtm_cls3_ATOM3_CH3_CM1_CM1_WIDTH     (24U)
1680 #define GTM_gtm_cls3_ATOM3_CH3_CM1_CM1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CM1_CM1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CM1_CM1_MASK)
1681 /*! @} */
1682 
1683 /*! @name ATOM3_CH3_CN0 - ATOM[i] channel [x] CCU0 counter register */
1684 /*! @{ */
1685 
1686 #define GTM_gtm_cls3_ATOM3_CH3_CN0_CN0_MASK      (0xFFFFFFU)
1687 #define GTM_gtm_cls3_ATOM3_CH3_CN0_CN0_SHIFT     (0U)
1688 #define GTM_gtm_cls3_ATOM3_CH3_CN0_CN0_WIDTH     (24U)
1689 #define GTM_gtm_cls3_ATOM3_CH3_CN0_CN0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CN0_CN0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CN0_CN0_MASK)
1690 /*! @} */
1691 
1692 /*! @name ATOM3_CH3_STAT - ATOM[i] channel [x] status register */
1693 /*! @{ */
1694 
1695 #define GTM_gtm_cls3_ATOM3_CH3_STAT_OL_MASK      (0x1U)
1696 #define GTM_gtm_cls3_ATOM3_CH3_STAT_OL_SHIFT     (0U)
1697 #define GTM_gtm_cls3_ATOM3_CH3_STAT_OL_WIDTH     (1U)
1698 #define GTM_gtm_cls3_ATOM3_CH3_STAT_OL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_STAT_OL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_STAT_OL_MASK)
1699 
1700 #define GTM_gtm_cls3_ATOM3_CH3_STAT_ACBI_MASK    (0x1F0000U)
1701 #define GTM_gtm_cls3_ATOM3_CH3_STAT_ACBI_SHIFT   (16U)
1702 #define GTM_gtm_cls3_ATOM3_CH3_STAT_ACBI_WIDTH   (5U)
1703 #define GTM_gtm_cls3_ATOM3_CH3_STAT_ACBI(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_STAT_ACBI_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_STAT_ACBI_MASK)
1704 
1705 #define GTM_gtm_cls3_ATOM3_CH3_STAT_DV_MASK      (0x200000U)
1706 #define GTM_gtm_cls3_ATOM3_CH3_STAT_DV_SHIFT     (21U)
1707 #define GTM_gtm_cls3_ATOM3_CH3_STAT_DV_WIDTH     (1U)
1708 #define GTM_gtm_cls3_ATOM3_CH3_STAT_DV(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_STAT_DV_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_STAT_DV_MASK)
1709 
1710 #define GTM_gtm_cls3_ATOM3_CH3_STAT_WRF_MASK     (0x400000U)
1711 #define GTM_gtm_cls3_ATOM3_CH3_STAT_WRF_SHIFT    (22U)
1712 #define GTM_gtm_cls3_ATOM3_CH3_STAT_WRF_WIDTH    (1U)
1713 #define GTM_gtm_cls3_ATOM3_CH3_STAT_WRF(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_STAT_WRF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_STAT_WRF_MASK)
1714 
1715 #define GTM_gtm_cls3_ATOM3_CH3_STAT_DR_MASK      (0x800000U)
1716 #define GTM_gtm_cls3_ATOM3_CH3_STAT_DR_SHIFT     (23U)
1717 #define GTM_gtm_cls3_ATOM3_CH3_STAT_DR_WIDTH     (1U)
1718 #define GTM_gtm_cls3_ATOM3_CH3_STAT_DR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_STAT_DR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_STAT_DR_MASK)
1719 
1720 #define GTM_gtm_cls3_ATOM3_CH3_STAT_ACBO_MASK    (0x1F000000U)
1721 #define GTM_gtm_cls3_ATOM3_CH3_STAT_ACBO_SHIFT   (24U)
1722 #define GTM_gtm_cls3_ATOM3_CH3_STAT_ACBO_WIDTH   (5U)
1723 #define GTM_gtm_cls3_ATOM3_CH3_STAT_ACBO(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_STAT_ACBO_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_STAT_ACBO_MASK)
1724 
1725 #define GTM_gtm_cls3_ATOM3_CH3_STAT_OSM_RTF_MASK (0x20000000U)
1726 #define GTM_gtm_cls3_ATOM3_CH3_STAT_OSM_RTF_SHIFT (29U)
1727 #define GTM_gtm_cls3_ATOM3_CH3_STAT_OSM_RTF_WIDTH (1U)
1728 #define GTM_gtm_cls3_ATOM3_CH3_STAT_OSM_RTF(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_STAT_OSM_RTF_MASK)
1729 /*! @} */
1730 
1731 /*! @name ATOM3_CH3_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */
1732 /*! @{ */
1733 
1734 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU0TC_MASK (0x1U)
1735 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU0TC_SHIFT (0U)
1736 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU0TC_WIDTH (1U)
1737 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU0TC_MASK)
1738 
1739 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU1TC_MASK (0x2U)
1740 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU1TC_SHIFT (1U)
1741 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU1TC_WIDTH (1U)
1742 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_IRQ_NOTIFY_CCU1TC_MASK)
1743 /*! @} */
1744 
1745 /*! @name ATOM3_CH3_IRQ_EN - ATOM[i] channel [x] interrupt enable register */
1746 /*! @{ */
1747 
1748 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U)
1749 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U)
1750 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U)
1751 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU0TC_IRQ_EN_MASK)
1752 
1753 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U)
1754 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U)
1755 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U)
1756 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_IRQ_EN_CCU1TC_IRQ_EN_MASK)
1757 /*! @} */
1758 
1759 /*! @name ATOM3_CH3_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */
1760 /*! @{ */
1761 
1762 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U)
1763 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U)
1764 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U)
1765 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU0TC_MASK)
1766 
1767 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U)
1768 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U)
1769 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U)
1770 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_IRQ_FORCINT_TRG_CCU1TC_MASK)
1771 /*! @} */
1772 
1773 /*! @name ATOM3_CH3_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */
1774 /*! @{ */
1775 
1776 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U)
1777 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U)
1778 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U)
1779 #define GTM_gtm_cls3_ATOM3_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_IRQ_MODE_IRQ_MODE_MASK)
1780 /*! @} */
1781 
1782 /*! @name ATOM3_CH3_CTRL_SR - ATOM[i] channel [x] control shadow register */
1783 /*! @{ */
1784 
1785 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_SL_SR_MASK (0x800U)
1786 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_SL_SR_SHIFT (11U)
1787 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_SL_SR_WIDTH (1U)
1788 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_SL_SR(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_SL_SR_MASK)
1789 
1790 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_CLK_SRC_SR_MASK (0xF000U)
1791 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_CLK_SRC_SR_SHIFT (12U)
1792 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_CLK_SRC_SR_WIDTH (4U)
1793 #define GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH3_CTRL_SR_CLK_SRC_SR_MASK)
1794 /*! @} */
1795 
1796 /*! @name ATOM3_CH4_RDADDR - ATOM[i] channel[x] ARU read address register */
1797 /*! @{ */
1798 
1799 #define GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR0_MASK (0x1FFU)
1800 #define GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR0_SHIFT (0U)
1801 #define GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR0_WIDTH (9U)
1802 #define GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR0_MASK)
1803 
1804 #define GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR1_MASK (0x1FF0000U)
1805 #define GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR1_SHIFT (16U)
1806 #define GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR1_WIDTH (9U)
1807 #define GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_RDADDR_RDADDR1_MASK)
1808 /*! @} */
1809 
1810 /*! @name ATOM3_CH4_CTRL - ATOM[i] channel [x] control register */
1811 /*! @{ */
1812 
1813 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_MODE_MASK    (0x3U)
1814 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_MODE_SHIFT   (0U)
1815 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_MODE_WIDTH   (2U)
1816 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_MODE_MASK)
1817 
1818 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TB12_SEL_MASK (0x4U)
1819 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TB12_SEL_SHIFT (2U)
1820 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TB12_SEL_WIDTH (1U)
1821 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TB12_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_TB12_SEL_MASK)
1822 
1823 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ARU_EN_MASK  (0x8U)
1824 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ARU_EN_SHIFT (3U)
1825 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ARU_EN_WIDTH (1U)
1826 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ARU_EN(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_ARU_EN_MASK)
1827 
1828 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ACB_MASK     (0x1F0U)
1829 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ACB_SHIFT    (4U)
1830 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ACB_WIDTH    (5U)
1831 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ACB(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_ACB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_ACB_MASK)
1832 
1833 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_CMP_CTRL_MASK (0x200U)
1834 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_CMP_CTRL_SHIFT (9U)
1835 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_CMP_CTRL_WIDTH (1U)
1836 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_CMP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_CMP_CTRL_MASK)
1837 
1838 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EUPM_MASK    (0x400U)
1839 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EUPM_SHIFT   (10U)
1840 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EUPM_WIDTH   (1U)
1841 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EUPM(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_EUPM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_EUPM_MASK)
1842 
1843 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SL_MASK      (0x800U)
1844 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SL_SHIFT     (11U)
1845 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SL_WIDTH     (1U)
1846 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_SL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_SL_MASK)
1847 
1848 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_CLK_SRC_MASK (0xF000U)
1849 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_CLK_SRC_SHIFT (12U)
1850 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_CLK_SRC_WIDTH (4U)
1851 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_CLK_SRC_MASK)
1852 
1853 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_WR_REQ_MASK  (0x10000U)
1854 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_WR_REQ_SHIFT (16U)
1855 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_WR_REQ_WIDTH (1U)
1856 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_WR_REQ(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_WR_REQ_MASK)
1857 
1858 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIG_PULSE_MASK (0x20000U)
1859 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIG_PULSE_SHIFT (17U)
1860 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIG_PULSE_WIDTH (1U)
1861 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIG_PULSE_MASK)
1862 
1863 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_UDMODE_MASK  (0xC0000U)
1864 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_UDMODE_SHIFT (18U)
1865 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_UDMODE_WIDTH (2U)
1866 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_UDMODE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_UDMODE_MASK)
1867 
1868 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_RST_CCU0_MASK (0x100000U)
1869 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_RST_CCU0_SHIFT (20U)
1870 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_RST_CCU0_WIDTH (1U)
1871 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_RST_CCU0(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_RST_CCU0_MASK)
1872 
1873 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_TRIG_MASK (0x200000U)
1874 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_TRIG_SHIFT (21U)
1875 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_TRIG_WIDTH (1U)
1876 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_TRIG_MASK)
1877 
1878 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_TRIG_MASK (0x400000U)
1879 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_TRIG_SHIFT (22U)
1880 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_TRIG_WIDTH (1U)
1881 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_TRIG_MASK)
1882 
1883 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXTTRIGOUT_MASK (0x800000U)
1884 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXTTRIGOUT_SHIFT (23U)
1885 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXTTRIGOUT_WIDTH (1U)
1886 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_EXTTRIGOUT_MASK)
1887 
1888 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIGOUT_MASK (0x1000000U)
1889 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIGOUT_SHIFT (24U)
1890 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIGOUT_WIDTH (1U)
1891 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIGOUT(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_TRIGOUT_MASK)
1892 
1893 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SLA_MASK     (0x2000000U)
1894 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SLA_SHIFT    (25U)
1895 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SLA_WIDTH    (1U)
1896 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SLA(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_SLA_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_SLA_MASK)
1897 
1898 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_MASK     (0x4000000U)
1899 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_SHIFT    (26U)
1900 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_WIDTH    (1U)
1901 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_OSM_MASK)
1902 
1903 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ABM_MASK     (0x8000000U)
1904 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ABM_SHIFT    (27U)
1905 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ABM_WIDTH    (1U)
1906 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_ABM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_ABM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_ABM_MASK)
1907 
1908 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_FUPD_MASK (0x20000000U)
1909 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_FUPD_SHIFT (29U)
1910 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_FUPD_WIDTH (1U)
1911 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_FUPD(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_EXT_FUPD_MASK)
1912 
1913 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SOMB_MASK    (0x40000000U)
1914 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SOMB_SHIFT   (30U)
1915 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SOMB_WIDTH   (1U)
1916 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SOMB(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_SOMB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_SOMB_MASK)
1917 
1918 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_FREEZE_MASK  (0x80000000U)
1919 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_FREEZE_SHIFT (31U)
1920 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_FREEZE_WIDTH (1U)
1921 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_FREEZE_MASK)
1922 /*! @} */
1923 
1924 /*! @name ATOM3_CH4_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */
1925 /*! @{ */
1926 
1927 #define GTM_gtm_cls3_ATOM3_CH4_SR0_SR0_MASK      (0xFFFFFFU)
1928 #define GTM_gtm_cls3_ATOM3_CH4_SR0_SR0_SHIFT     (0U)
1929 #define GTM_gtm_cls3_ATOM3_CH4_SR0_SR0_WIDTH     (24U)
1930 #define GTM_gtm_cls3_ATOM3_CH4_SR0_SR0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_SR0_SR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_SR0_SR0_MASK)
1931 /*! @} */
1932 
1933 /*! @name ATOM3_CH4_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */
1934 /*! @{ */
1935 
1936 #define GTM_gtm_cls3_ATOM3_CH4_SR1_SR1_MASK      (0xFFFFFFU)
1937 #define GTM_gtm_cls3_ATOM3_CH4_SR1_SR1_SHIFT     (0U)
1938 #define GTM_gtm_cls3_ATOM3_CH4_SR1_SR1_WIDTH     (24U)
1939 #define GTM_gtm_cls3_ATOM3_CH4_SR1_SR1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_SR1_SR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_SR1_SR1_MASK)
1940 /*! @} */
1941 
1942 /*! @name ATOM3_CH4_CM0 - ATOM[i] channel [x] CCU0 compare register */
1943 /*! @{ */
1944 
1945 #define GTM_gtm_cls3_ATOM3_CH4_CM0_CM0_MASK      (0xFFFFFFU)
1946 #define GTM_gtm_cls3_ATOM3_CH4_CM0_CM0_SHIFT     (0U)
1947 #define GTM_gtm_cls3_ATOM3_CH4_CM0_CM0_WIDTH     (24U)
1948 #define GTM_gtm_cls3_ATOM3_CH4_CM0_CM0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CM0_CM0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CM0_CM0_MASK)
1949 /*! @} */
1950 
1951 /*! @name ATOM3_CH4_CM1 - ATOM[i] channel [x] CCU0 compare register */
1952 /*! @{ */
1953 
1954 #define GTM_gtm_cls3_ATOM3_CH4_CM1_CM1_MASK      (0xFFFFFFU)
1955 #define GTM_gtm_cls3_ATOM3_CH4_CM1_CM1_SHIFT     (0U)
1956 #define GTM_gtm_cls3_ATOM3_CH4_CM1_CM1_WIDTH     (24U)
1957 #define GTM_gtm_cls3_ATOM3_CH4_CM1_CM1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CM1_CM1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CM1_CM1_MASK)
1958 /*! @} */
1959 
1960 /*! @name ATOM3_CH4_CN0 - ATOM[i] channel [x] CCU0 counter register */
1961 /*! @{ */
1962 
1963 #define GTM_gtm_cls3_ATOM3_CH4_CN0_CN0_MASK      (0xFFFFFFU)
1964 #define GTM_gtm_cls3_ATOM3_CH4_CN0_CN0_SHIFT     (0U)
1965 #define GTM_gtm_cls3_ATOM3_CH4_CN0_CN0_WIDTH     (24U)
1966 #define GTM_gtm_cls3_ATOM3_CH4_CN0_CN0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CN0_CN0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CN0_CN0_MASK)
1967 /*! @} */
1968 
1969 /*! @name ATOM3_CH4_STAT - ATOM[i] channel [x] status register */
1970 /*! @{ */
1971 
1972 #define GTM_gtm_cls3_ATOM3_CH4_STAT_OL_MASK      (0x1U)
1973 #define GTM_gtm_cls3_ATOM3_CH4_STAT_OL_SHIFT     (0U)
1974 #define GTM_gtm_cls3_ATOM3_CH4_STAT_OL_WIDTH     (1U)
1975 #define GTM_gtm_cls3_ATOM3_CH4_STAT_OL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_STAT_OL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_STAT_OL_MASK)
1976 
1977 #define GTM_gtm_cls3_ATOM3_CH4_STAT_ACBI_MASK    (0x1F0000U)
1978 #define GTM_gtm_cls3_ATOM3_CH4_STAT_ACBI_SHIFT   (16U)
1979 #define GTM_gtm_cls3_ATOM3_CH4_STAT_ACBI_WIDTH   (5U)
1980 #define GTM_gtm_cls3_ATOM3_CH4_STAT_ACBI(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_STAT_ACBI_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_STAT_ACBI_MASK)
1981 
1982 #define GTM_gtm_cls3_ATOM3_CH4_STAT_DV_MASK      (0x200000U)
1983 #define GTM_gtm_cls3_ATOM3_CH4_STAT_DV_SHIFT     (21U)
1984 #define GTM_gtm_cls3_ATOM3_CH4_STAT_DV_WIDTH     (1U)
1985 #define GTM_gtm_cls3_ATOM3_CH4_STAT_DV(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_STAT_DV_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_STAT_DV_MASK)
1986 
1987 #define GTM_gtm_cls3_ATOM3_CH4_STAT_WRF_MASK     (0x400000U)
1988 #define GTM_gtm_cls3_ATOM3_CH4_STAT_WRF_SHIFT    (22U)
1989 #define GTM_gtm_cls3_ATOM3_CH4_STAT_WRF_WIDTH    (1U)
1990 #define GTM_gtm_cls3_ATOM3_CH4_STAT_WRF(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_STAT_WRF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_STAT_WRF_MASK)
1991 
1992 #define GTM_gtm_cls3_ATOM3_CH4_STAT_DR_MASK      (0x800000U)
1993 #define GTM_gtm_cls3_ATOM3_CH4_STAT_DR_SHIFT     (23U)
1994 #define GTM_gtm_cls3_ATOM3_CH4_STAT_DR_WIDTH     (1U)
1995 #define GTM_gtm_cls3_ATOM3_CH4_STAT_DR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_STAT_DR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_STAT_DR_MASK)
1996 
1997 #define GTM_gtm_cls3_ATOM3_CH4_STAT_ACBO_MASK    (0x1F000000U)
1998 #define GTM_gtm_cls3_ATOM3_CH4_STAT_ACBO_SHIFT   (24U)
1999 #define GTM_gtm_cls3_ATOM3_CH4_STAT_ACBO_WIDTH   (5U)
2000 #define GTM_gtm_cls3_ATOM3_CH4_STAT_ACBO(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_STAT_ACBO_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_STAT_ACBO_MASK)
2001 
2002 #define GTM_gtm_cls3_ATOM3_CH4_STAT_OSM_RTF_MASK (0x20000000U)
2003 #define GTM_gtm_cls3_ATOM3_CH4_STAT_OSM_RTF_SHIFT (29U)
2004 #define GTM_gtm_cls3_ATOM3_CH4_STAT_OSM_RTF_WIDTH (1U)
2005 #define GTM_gtm_cls3_ATOM3_CH4_STAT_OSM_RTF(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_STAT_OSM_RTF_MASK)
2006 /*! @} */
2007 
2008 /*! @name ATOM3_CH4_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */
2009 /*! @{ */
2010 
2011 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU0TC_MASK (0x1U)
2012 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU0TC_SHIFT (0U)
2013 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU0TC_WIDTH (1U)
2014 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU0TC_MASK)
2015 
2016 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU1TC_MASK (0x2U)
2017 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU1TC_SHIFT (1U)
2018 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU1TC_WIDTH (1U)
2019 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_IRQ_NOTIFY_CCU1TC_MASK)
2020 /*! @} */
2021 
2022 /*! @name ATOM3_CH4_IRQ_EN - ATOM[i] channel [x] interrupt enable register */
2023 /*! @{ */
2024 
2025 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U)
2026 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U)
2027 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U)
2028 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU0TC_IRQ_EN_MASK)
2029 
2030 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U)
2031 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U)
2032 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U)
2033 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_IRQ_EN_CCU1TC_IRQ_EN_MASK)
2034 /*! @} */
2035 
2036 /*! @name ATOM3_CH4_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */
2037 /*! @{ */
2038 
2039 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U)
2040 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U)
2041 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U)
2042 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU0TC_MASK)
2043 
2044 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U)
2045 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U)
2046 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U)
2047 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_IRQ_FORCINT_TRG_CCU1TC_MASK)
2048 /*! @} */
2049 
2050 /*! @name ATOM3_CH4_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */
2051 /*! @{ */
2052 
2053 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U)
2054 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U)
2055 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U)
2056 #define GTM_gtm_cls3_ATOM3_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_IRQ_MODE_IRQ_MODE_MASK)
2057 /*! @} */
2058 
2059 /*! @name ATOM3_CH4_CTRL_SR - ATOM[i] channel [x] control shadow register */
2060 /*! @{ */
2061 
2062 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_SL_SR_MASK (0x800U)
2063 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_SL_SR_SHIFT (11U)
2064 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_SL_SR_WIDTH (1U)
2065 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_SL_SR(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_SL_SR_MASK)
2066 
2067 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_CLK_SRC_SR_MASK (0xF000U)
2068 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_CLK_SRC_SR_SHIFT (12U)
2069 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_CLK_SRC_SR_WIDTH (4U)
2070 #define GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH4_CTRL_SR_CLK_SRC_SR_MASK)
2071 /*! @} */
2072 
2073 /*! @name ATOM3_CH5_RDADDR - ATOM[i] channel[x] ARU read address register */
2074 /*! @{ */
2075 
2076 #define GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR0_MASK (0x1FFU)
2077 #define GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR0_SHIFT (0U)
2078 #define GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR0_WIDTH (9U)
2079 #define GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR0_MASK)
2080 
2081 #define GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR1_MASK (0x1FF0000U)
2082 #define GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR1_SHIFT (16U)
2083 #define GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR1_WIDTH (9U)
2084 #define GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_RDADDR_RDADDR1_MASK)
2085 /*! @} */
2086 
2087 /*! @name ATOM3_CH5_CTRL - ATOM[i] channel [x] control register */
2088 /*! @{ */
2089 
2090 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_MODE_MASK    (0x3U)
2091 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_MODE_SHIFT   (0U)
2092 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_MODE_WIDTH   (2U)
2093 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_MODE_MASK)
2094 
2095 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TB12_SEL_MASK (0x4U)
2096 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TB12_SEL_SHIFT (2U)
2097 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TB12_SEL_WIDTH (1U)
2098 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TB12_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_TB12_SEL_MASK)
2099 
2100 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ARU_EN_MASK  (0x8U)
2101 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ARU_EN_SHIFT (3U)
2102 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ARU_EN_WIDTH (1U)
2103 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ARU_EN(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_ARU_EN_MASK)
2104 
2105 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ACB_MASK     (0x1F0U)
2106 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ACB_SHIFT    (4U)
2107 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ACB_WIDTH    (5U)
2108 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ACB(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_ACB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_ACB_MASK)
2109 
2110 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_CMP_CTRL_MASK (0x200U)
2111 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_CMP_CTRL_SHIFT (9U)
2112 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_CMP_CTRL_WIDTH (1U)
2113 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_CMP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_CMP_CTRL_MASK)
2114 
2115 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EUPM_MASK    (0x400U)
2116 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EUPM_SHIFT   (10U)
2117 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EUPM_WIDTH   (1U)
2118 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EUPM(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_EUPM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_EUPM_MASK)
2119 
2120 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SL_MASK      (0x800U)
2121 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SL_SHIFT     (11U)
2122 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SL_WIDTH     (1U)
2123 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_SL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_SL_MASK)
2124 
2125 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_CLK_SRC_MASK (0xF000U)
2126 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_CLK_SRC_SHIFT (12U)
2127 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_CLK_SRC_WIDTH (4U)
2128 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_CLK_SRC_MASK)
2129 
2130 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_WR_REQ_MASK  (0x10000U)
2131 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_WR_REQ_SHIFT (16U)
2132 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_WR_REQ_WIDTH (1U)
2133 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_WR_REQ(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_WR_REQ_MASK)
2134 
2135 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIG_PULSE_MASK (0x20000U)
2136 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIG_PULSE_SHIFT (17U)
2137 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIG_PULSE_WIDTH (1U)
2138 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIG_PULSE_MASK)
2139 
2140 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_UDMODE_MASK  (0xC0000U)
2141 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_UDMODE_SHIFT (18U)
2142 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_UDMODE_WIDTH (2U)
2143 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_UDMODE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_UDMODE_MASK)
2144 
2145 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_RST_CCU0_MASK (0x100000U)
2146 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_RST_CCU0_SHIFT (20U)
2147 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_RST_CCU0_WIDTH (1U)
2148 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_RST_CCU0(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_RST_CCU0_MASK)
2149 
2150 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_TRIG_MASK (0x200000U)
2151 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_TRIG_SHIFT (21U)
2152 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_TRIG_WIDTH (1U)
2153 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_TRIG_MASK)
2154 
2155 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_TRIG_MASK (0x400000U)
2156 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_TRIG_SHIFT (22U)
2157 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_TRIG_WIDTH (1U)
2158 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_TRIG_MASK)
2159 
2160 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXTTRIGOUT_MASK (0x800000U)
2161 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXTTRIGOUT_SHIFT (23U)
2162 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXTTRIGOUT_WIDTH (1U)
2163 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_EXTTRIGOUT_MASK)
2164 
2165 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIGOUT_MASK (0x1000000U)
2166 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIGOUT_SHIFT (24U)
2167 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIGOUT_WIDTH (1U)
2168 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIGOUT(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_TRIGOUT_MASK)
2169 
2170 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SLA_MASK     (0x2000000U)
2171 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SLA_SHIFT    (25U)
2172 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SLA_WIDTH    (1U)
2173 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SLA(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_SLA_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_SLA_MASK)
2174 
2175 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_MASK     (0x4000000U)
2176 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_SHIFT    (26U)
2177 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_WIDTH    (1U)
2178 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_OSM_MASK)
2179 
2180 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ABM_MASK     (0x8000000U)
2181 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ABM_SHIFT    (27U)
2182 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ABM_WIDTH    (1U)
2183 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_ABM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_ABM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_ABM_MASK)
2184 
2185 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_FUPD_MASK (0x20000000U)
2186 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_FUPD_SHIFT (29U)
2187 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_FUPD_WIDTH (1U)
2188 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_FUPD(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_EXT_FUPD_MASK)
2189 
2190 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SOMB_MASK    (0x40000000U)
2191 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SOMB_SHIFT   (30U)
2192 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SOMB_WIDTH   (1U)
2193 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SOMB(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_SOMB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_SOMB_MASK)
2194 
2195 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_FREEZE_MASK  (0x80000000U)
2196 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_FREEZE_SHIFT (31U)
2197 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_FREEZE_WIDTH (1U)
2198 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_FREEZE_MASK)
2199 /*! @} */
2200 
2201 /*! @name ATOM3_CH5_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */
2202 /*! @{ */
2203 
2204 #define GTM_gtm_cls3_ATOM3_CH5_SR0_SR0_MASK      (0xFFFFFFU)
2205 #define GTM_gtm_cls3_ATOM3_CH5_SR0_SR0_SHIFT     (0U)
2206 #define GTM_gtm_cls3_ATOM3_CH5_SR0_SR0_WIDTH     (24U)
2207 #define GTM_gtm_cls3_ATOM3_CH5_SR0_SR0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_SR0_SR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_SR0_SR0_MASK)
2208 /*! @} */
2209 
2210 /*! @name ATOM3_CH5_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */
2211 /*! @{ */
2212 
2213 #define GTM_gtm_cls3_ATOM3_CH5_SR1_SR1_MASK      (0xFFFFFFU)
2214 #define GTM_gtm_cls3_ATOM3_CH5_SR1_SR1_SHIFT     (0U)
2215 #define GTM_gtm_cls3_ATOM3_CH5_SR1_SR1_WIDTH     (24U)
2216 #define GTM_gtm_cls3_ATOM3_CH5_SR1_SR1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_SR1_SR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_SR1_SR1_MASK)
2217 /*! @} */
2218 
2219 /*! @name ATOM3_CH5_CM0 - ATOM[i] channel [x] CCU0 compare register */
2220 /*! @{ */
2221 
2222 #define GTM_gtm_cls3_ATOM3_CH5_CM0_CM0_MASK      (0xFFFFFFU)
2223 #define GTM_gtm_cls3_ATOM3_CH5_CM0_CM0_SHIFT     (0U)
2224 #define GTM_gtm_cls3_ATOM3_CH5_CM0_CM0_WIDTH     (24U)
2225 #define GTM_gtm_cls3_ATOM3_CH5_CM0_CM0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CM0_CM0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CM0_CM0_MASK)
2226 /*! @} */
2227 
2228 /*! @name ATOM3_CH5_CM1 - ATOM[i] channel [x] CCU0 compare register */
2229 /*! @{ */
2230 
2231 #define GTM_gtm_cls3_ATOM3_CH5_CM1_CM1_MASK      (0xFFFFFFU)
2232 #define GTM_gtm_cls3_ATOM3_CH5_CM1_CM1_SHIFT     (0U)
2233 #define GTM_gtm_cls3_ATOM3_CH5_CM1_CM1_WIDTH     (24U)
2234 #define GTM_gtm_cls3_ATOM3_CH5_CM1_CM1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CM1_CM1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CM1_CM1_MASK)
2235 /*! @} */
2236 
2237 /*! @name ATOM3_CH5_CN0 - ATOM[i] channel [x] CCU0 counter register */
2238 /*! @{ */
2239 
2240 #define GTM_gtm_cls3_ATOM3_CH5_CN0_CN0_MASK      (0xFFFFFFU)
2241 #define GTM_gtm_cls3_ATOM3_CH5_CN0_CN0_SHIFT     (0U)
2242 #define GTM_gtm_cls3_ATOM3_CH5_CN0_CN0_WIDTH     (24U)
2243 #define GTM_gtm_cls3_ATOM3_CH5_CN0_CN0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CN0_CN0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CN0_CN0_MASK)
2244 /*! @} */
2245 
2246 /*! @name ATOM3_CH5_STAT - ATOM[i] channel [x] status register */
2247 /*! @{ */
2248 
2249 #define GTM_gtm_cls3_ATOM3_CH5_STAT_OL_MASK      (0x1U)
2250 #define GTM_gtm_cls3_ATOM3_CH5_STAT_OL_SHIFT     (0U)
2251 #define GTM_gtm_cls3_ATOM3_CH5_STAT_OL_WIDTH     (1U)
2252 #define GTM_gtm_cls3_ATOM3_CH5_STAT_OL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_STAT_OL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_STAT_OL_MASK)
2253 
2254 #define GTM_gtm_cls3_ATOM3_CH5_STAT_ACBI_MASK    (0x1F0000U)
2255 #define GTM_gtm_cls3_ATOM3_CH5_STAT_ACBI_SHIFT   (16U)
2256 #define GTM_gtm_cls3_ATOM3_CH5_STAT_ACBI_WIDTH   (5U)
2257 #define GTM_gtm_cls3_ATOM3_CH5_STAT_ACBI(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_STAT_ACBI_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_STAT_ACBI_MASK)
2258 
2259 #define GTM_gtm_cls3_ATOM3_CH5_STAT_DV_MASK      (0x200000U)
2260 #define GTM_gtm_cls3_ATOM3_CH5_STAT_DV_SHIFT     (21U)
2261 #define GTM_gtm_cls3_ATOM3_CH5_STAT_DV_WIDTH     (1U)
2262 #define GTM_gtm_cls3_ATOM3_CH5_STAT_DV(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_STAT_DV_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_STAT_DV_MASK)
2263 
2264 #define GTM_gtm_cls3_ATOM3_CH5_STAT_WRF_MASK     (0x400000U)
2265 #define GTM_gtm_cls3_ATOM3_CH5_STAT_WRF_SHIFT    (22U)
2266 #define GTM_gtm_cls3_ATOM3_CH5_STAT_WRF_WIDTH    (1U)
2267 #define GTM_gtm_cls3_ATOM3_CH5_STAT_WRF(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_STAT_WRF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_STAT_WRF_MASK)
2268 
2269 #define GTM_gtm_cls3_ATOM3_CH5_STAT_DR_MASK      (0x800000U)
2270 #define GTM_gtm_cls3_ATOM3_CH5_STAT_DR_SHIFT     (23U)
2271 #define GTM_gtm_cls3_ATOM3_CH5_STAT_DR_WIDTH     (1U)
2272 #define GTM_gtm_cls3_ATOM3_CH5_STAT_DR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_STAT_DR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_STAT_DR_MASK)
2273 
2274 #define GTM_gtm_cls3_ATOM3_CH5_STAT_ACBO_MASK    (0x1F000000U)
2275 #define GTM_gtm_cls3_ATOM3_CH5_STAT_ACBO_SHIFT   (24U)
2276 #define GTM_gtm_cls3_ATOM3_CH5_STAT_ACBO_WIDTH   (5U)
2277 #define GTM_gtm_cls3_ATOM3_CH5_STAT_ACBO(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_STAT_ACBO_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_STAT_ACBO_MASK)
2278 
2279 #define GTM_gtm_cls3_ATOM3_CH5_STAT_OSM_RTF_MASK (0x20000000U)
2280 #define GTM_gtm_cls3_ATOM3_CH5_STAT_OSM_RTF_SHIFT (29U)
2281 #define GTM_gtm_cls3_ATOM3_CH5_STAT_OSM_RTF_WIDTH (1U)
2282 #define GTM_gtm_cls3_ATOM3_CH5_STAT_OSM_RTF(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_STAT_OSM_RTF_MASK)
2283 /*! @} */
2284 
2285 /*! @name ATOM3_CH5_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */
2286 /*! @{ */
2287 
2288 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU0TC_MASK (0x1U)
2289 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU0TC_SHIFT (0U)
2290 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU0TC_WIDTH (1U)
2291 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU0TC_MASK)
2292 
2293 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU1TC_MASK (0x2U)
2294 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU1TC_SHIFT (1U)
2295 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU1TC_WIDTH (1U)
2296 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_IRQ_NOTIFY_CCU1TC_MASK)
2297 /*! @} */
2298 
2299 /*! @name ATOM3_CH5_IRQ_EN - ATOM[i] channel [x] interrupt enable register */
2300 /*! @{ */
2301 
2302 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U)
2303 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U)
2304 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U)
2305 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU0TC_IRQ_EN_MASK)
2306 
2307 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U)
2308 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U)
2309 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U)
2310 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_IRQ_EN_CCU1TC_IRQ_EN_MASK)
2311 /*! @} */
2312 
2313 /*! @name ATOM3_CH5_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */
2314 /*! @{ */
2315 
2316 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U)
2317 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U)
2318 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U)
2319 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU0TC_MASK)
2320 
2321 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U)
2322 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U)
2323 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U)
2324 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_IRQ_FORCINT_TRG_CCU1TC_MASK)
2325 /*! @} */
2326 
2327 /*! @name ATOM3_CH5_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */
2328 /*! @{ */
2329 
2330 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U)
2331 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U)
2332 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U)
2333 #define GTM_gtm_cls3_ATOM3_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_IRQ_MODE_IRQ_MODE_MASK)
2334 /*! @} */
2335 
2336 /*! @name ATOM3_CH5_CTRL_SR - ATOM[i] channel [x] control shadow register */
2337 /*! @{ */
2338 
2339 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_SL_SR_MASK (0x800U)
2340 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_SL_SR_SHIFT (11U)
2341 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_SL_SR_WIDTH (1U)
2342 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_SL_SR(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_SL_SR_MASK)
2343 
2344 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_CLK_SRC_SR_MASK (0xF000U)
2345 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_CLK_SRC_SR_SHIFT (12U)
2346 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_CLK_SRC_SR_WIDTH (4U)
2347 #define GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH5_CTRL_SR_CLK_SRC_SR_MASK)
2348 /*! @} */
2349 
2350 /*! @name ATOM3_CH6_RDADDR - ATOM[i] channel[x] ARU read address register */
2351 /*! @{ */
2352 
2353 #define GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR0_MASK (0x1FFU)
2354 #define GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR0_SHIFT (0U)
2355 #define GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR0_WIDTH (9U)
2356 #define GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR0_MASK)
2357 
2358 #define GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR1_MASK (0x1FF0000U)
2359 #define GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR1_SHIFT (16U)
2360 #define GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR1_WIDTH (9U)
2361 #define GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_RDADDR_RDADDR1_MASK)
2362 /*! @} */
2363 
2364 /*! @name ATOM3_CH6_CTRL - ATOM[i] channel [x] control register */
2365 /*! @{ */
2366 
2367 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_MODE_MASK    (0x3U)
2368 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_MODE_SHIFT   (0U)
2369 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_MODE_WIDTH   (2U)
2370 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_MODE_MASK)
2371 
2372 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TB12_SEL_MASK (0x4U)
2373 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TB12_SEL_SHIFT (2U)
2374 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TB12_SEL_WIDTH (1U)
2375 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TB12_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_TB12_SEL_MASK)
2376 
2377 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ARU_EN_MASK  (0x8U)
2378 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ARU_EN_SHIFT (3U)
2379 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ARU_EN_WIDTH (1U)
2380 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ARU_EN(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_ARU_EN_MASK)
2381 
2382 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ACB_MASK     (0x1F0U)
2383 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ACB_SHIFT    (4U)
2384 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ACB_WIDTH    (5U)
2385 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ACB(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_ACB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_ACB_MASK)
2386 
2387 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_CMP_CTRL_MASK (0x200U)
2388 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_CMP_CTRL_SHIFT (9U)
2389 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_CMP_CTRL_WIDTH (1U)
2390 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_CMP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_CMP_CTRL_MASK)
2391 
2392 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EUPM_MASK    (0x400U)
2393 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EUPM_SHIFT   (10U)
2394 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EUPM_WIDTH   (1U)
2395 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EUPM(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_EUPM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_EUPM_MASK)
2396 
2397 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SL_MASK      (0x800U)
2398 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SL_SHIFT     (11U)
2399 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SL_WIDTH     (1U)
2400 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_SL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_SL_MASK)
2401 
2402 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_CLK_SRC_MASK (0xF000U)
2403 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_CLK_SRC_SHIFT (12U)
2404 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_CLK_SRC_WIDTH (4U)
2405 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_CLK_SRC_MASK)
2406 
2407 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_WR_REQ_MASK  (0x10000U)
2408 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_WR_REQ_SHIFT (16U)
2409 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_WR_REQ_WIDTH (1U)
2410 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_WR_REQ(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_WR_REQ_MASK)
2411 
2412 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIG_PULSE_MASK (0x20000U)
2413 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIG_PULSE_SHIFT (17U)
2414 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIG_PULSE_WIDTH (1U)
2415 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIG_PULSE_MASK)
2416 
2417 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_UDMODE_MASK  (0xC0000U)
2418 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_UDMODE_SHIFT (18U)
2419 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_UDMODE_WIDTH (2U)
2420 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_UDMODE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_UDMODE_MASK)
2421 
2422 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_RST_CCU0_MASK (0x100000U)
2423 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_RST_CCU0_SHIFT (20U)
2424 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_RST_CCU0_WIDTH (1U)
2425 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_RST_CCU0(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_RST_CCU0_MASK)
2426 
2427 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_TRIG_MASK (0x200000U)
2428 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_TRIG_SHIFT (21U)
2429 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_TRIG_WIDTH (1U)
2430 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_TRIG_MASK)
2431 
2432 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_TRIG_MASK (0x400000U)
2433 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_TRIG_SHIFT (22U)
2434 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_TRIG_WIDTH (1U)
2435 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_TRIG_MASK)
2436 
2437 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXTTRIGOUT_MASK (0x800000U)
2438 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXTTRIGOUT_SHIFT (23U)
2439 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXTTRIGOUT_WIDTH (1U)
2440 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_EXTTRIGOUT_MASK)
2441 
2442 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIGOUT_MASK (0x1000000U)
2443 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIGOUT_SHIFT (24U)
2444 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIGOUT_WIDTH (1U)
2445 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIGOUT(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_TRIGOUT_MASK)
2446 
2447 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SLA_MASK     (0x2000000U)
2448 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SLA_SHIFT    (25U)
2449 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SLA_WIDTH    (1U)
2450 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SLA(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_SLA_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_SLA_MASK)
2451 
2452 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_MASK     (0x4000000U)
2453 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_SHIFT    (26U)
2454 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_WIDTH    (1U)
2455 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_OSM_MASK)
2456 
2457 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ABM_MASK     (0x8000000U)
2458 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ABM_SHIFT    (27U)
2459 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ABM_WIDTH    (1U)
2460 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_ABM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_ABM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_ABM_MASK)
2461 
2462 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_FUPD_MASK (0x20000000U)
2463 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_FUPD_SHIFT (29U)
2464 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_FUPD_WIDTH (1U)
2465 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_FUPD(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_EXT_FUPD_MASK)
2466 
2467 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SOMB_MASK    (0x40000000U)
2468 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SOMB_SHIFT   (30U)
2469 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SOMB_WIDTH   (1U)
2470 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SOMB(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_SOMB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_SOMB_MASK)
2471 
2472 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_FREEZE_MASK  (0x80000000U)
2473 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_FREEZE_SHIFT (31U)
2474 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_FREEZE_WIDTH (1U)
2475 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_FREEZE_MASK)
2476 /*! @} */
2477 
2478 /*! @name ATOM3_CH6_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */
2479 /*! @{ */
2480 
2481 #define GTM_gtm_cls3_ATOM3_CH6_SR0_SR0_MASK      (0xFFFFFFU)
2482 #define GTM_gtm_cls3_ATOM3_CH6_SR0_SR0_SHIFT     (0U)
2483 #define GTM_gtm_cls3_ATOM3_CH6_SR0_SR0_WIDTH     (24U)
2484 #define GTM_gtm_cls3_ATOM3_CH6_SR0_SR0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_SR0_SR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_SR0_SR0_MASK)
2485 /*! @} */
2486 
2487 /*! @name ATOM3_CH6_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */
2488 /*! @{ */
2489 
2490 #define GTM_gtm_cls3_ATOM3_CH6_SR1_SR1_MASK      (0xFFFFFFU)
2491 #define GTM_gtm_cls3_ATOM3_CH6_SR1_SR1_SHIFT     (0U)
2492 #define GTM_gtm_cls3_ATOM3_CH6_SR1_SR1_WIDTH     (24U)
2493 #define GTM_gtm_cls3_ATOM3_CH6_SR1_SR1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_SR1_SR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_SR1_SR1_MASK)
2494 /*! @} */
2495 
2496 /*! @name ATOM3_CH6_CM0 - ATOM[i] channel [x] CCU0 compare register */
2497 /*! @{ */
2498 
2499 #define GTM_gtm_cls3_ATOM3_CH6_CM0_CM0_MASK      (0xFFFFFFU)
2500 #define GTM_gtm_cls3_ATOM3_CH6_CM0_CM0_SHIFT     (0U)
2501 #define GTM_gtm_cls3_ATOM3_CH6_CM0_CM0_WIDTH     (24U)
2502 #define GTM_gtm_cls3_ATOM3_CH6_CM0_CM0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CM0_CM0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CM0_CM0_MASK)
2503 /*! @} */
2504 
2505 /*! @name ATOM3_CH6_CM1 - ATOM[i] channel [x] CCU0 compare register */
2506 /*! @{ */
2507 
2508 #define GTM_gtm_cls3_ATOM3_CH6_CM1_CM1_MASK      (0xFFFFFFU)
2509 #define GTM_gtm_cls3_ATOM3_CH6_CM1_CM1_SHIFT     (0U)
2510 #define GTM_gtm_cls3_ATOM3_CH6_CM1_CM1_WIDTH     (24U)
2511 #define GTM_gtm_cls3_ATOM3_CH6_CM1_CM1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CM1_CM1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CM1_CM1_MASK)
2512 /*! @} */
2513 
2514 /*! @name ATOM3_CH6_CN0 - ATOM[i] channel [x] CCU0 counter register */
2515 /*! @{ */
2516 
2517 #define GTM_gtm_cls3_ATOM3_CH6_CN0_CN0_MASK      (0xFFFFFFU)
2518 #define GTM_gtm_cls3_ATOM3_CH6_CN0_CN0_SHIFT     (0U)
2519 #define GTM_gtm_cls3_ATOM3_CH6_CN0_CN0_WIDTH     (24U)
2520 #define GTM_gtm_cls3_ATOM3_CH6_CN0_CN0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CN0_CN0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CN0_CN0_MASK)
2521 /*! @} */
2522 
2523 /*! @name ATOM3_CH6_STAT - ATOM[i] channel [x] status register */
2524 /*! @{ */
2525 
2526 #define GTM_gtm_cls3_ATOM3_CH6_STAT_OL_MASK      (0x1U)
2527 #define GTM_gtm_cls3_ATOM3_CH6_STAT_OL_SHIFT     (0U)
2528 #define GTM_gtm_cls3_ATOM3_CH6_STAT_OL_WIDTH     (1U)
2529 #define GTM_gtm_cls3_ATOM3_CH6_STAT_OL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_STAT_OL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_STAT_OL_MASK)
2530 
2531 #define GTM_gtm_cls3_ATOM3_CH6_STAT_ACBI_MASK    (0x1F0000U)
2532 #define GTM_gtm_cls3_ATOM3_CH6_STAT_ACBI_SHIFT   (16U)
2533 #define GTM_gtm_cls3_ATOM3_CH6_STAT_ACBI_WIDTH   (5U)
2534 #define GTM_gtm_cls3_ATOM3_CH6_STAT_ACBI(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_STAT_ACBI_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_STAT_ACBI_MASK)
2535 
2536 #define GTM_gtm_cls3_ATOM3_CH6_STAT_DV_MASK      (0x200000U)
2537 #define GTM_gtm_cls3_ATOM3_CH6_STAT_DV_SHIFT     (21U)
2538 #define GTM_gtm_cls3_ATOM3_CH6_STAT_DV_WIDTH     (1U)
2539 #define GTM_gtm_cls3_ATOM3_CH6_STAT_DV(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_STAT_DV_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_STAT_DV_MASK)
2540 
2541 #define GTM_gtm_cls3_ATOM3_CH6_STAT_WRF_MASK     (0x400000U)
2542 #define GTM_gtm_cls3_ATOM3_CH6_STAT_WRF_SHIFT    (22U)
2543 #define GTM_gtm_cls3_ATOM3_CH6_STAT_WRF_WIDTH    (1U)
2544 #define GTM_gtm_cls3_ATOM3_CH6_STAT_WRF(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_STAT_WRF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_STAT_WRF_MASK)
2545 
2546 #define GTM_gtm_cls3_ATOM3_CH6_STAT_DR_MASK      (0x800000U)
2547 #define GTM_gtm_cls3_ATOM3_CH6_STAT_DR_SHIFT     (23U)
2548 #define GTM_gtm_cls3_ATOM3_CH6_STAT_DR_WIDTH     (1U)
2549 #define GTM_gtm_cls3_ATOM3_CH6_STAT_DR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_STAT_DR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_STAT_DR_MASK)
2550 
2551 #define GTM_gtm_cls3_ATOM3_CH6_STAT_ACBO_MASK    (0x1F000000U)
2552 #define GTM_gtm_cls3_ATOM3_CH6_STAT_ACBO_SHIFT   (24U)
2553 #define GTM_gtm_cls3_ATOM3_CH6_STAT_ACBO_WIDTH   (5U)
2554 #define GTM_gtm_cls3_ATOM3_CH6_STAT_ACBO(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_STAT_ACBO_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_STAT_ACBO_MASK)
2555 
2556 #define GTM_gtm_cls3_ATOM3_CH6_STAT_OSM_RTF_MASK (0x20000000U)
2557 #define GTM_gtm_cls3_ATOM3_CH6_STAT_OSM_RTF_SHIFT (29U)
2558 #define GTM_gtm_cls3_ATOM3_CH6_STAT_OSM_RTF_WIDTH (1U)
2559 #define GTM_gtm_cls3_ATOM3_CH6_STAT_OSM_RTF(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_STAT_OSM_RTF_MASK)
2560 /*! @} */
2561 
2562 /*! @name ATOM3_CH6_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */
2563 /*! @{ */
2564 
2565 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU0TC_MASK (0x1U)
2566 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU0TC_SHIFT (0U)
2567 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU0TC_WIDTH (1U)
2568 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU0TC_MASK)
2569 
2570 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU1TC_MASK (0x2U)
2571 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU1TC_SHIFT (1U)
2572 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU1TC_WIDTH (1U)
2573 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_IRQ_NOTIFY_CCU1TC_MASK)
2574 /*! @} */
2575 
2576 /*! @name ATOM3_CH6_IRQ_EN - ATOM[i] channel [x] interrupt enable register */
2577 /*! @{ */
2578 
2579 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U)
2580 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U)
2581 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U)
2582 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU0TC_IRQ_EN_MASK)
2583 
2584 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U)
2585 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U)
2586 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U)
2587 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_IRQ_EN_CCU1TC_IRQ_EN_MASK)
2588 /*! @} */
2589 
2590 /*! @name ATOM3_CH6_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */
2591 /*! @{ */
2592 
2593 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U)
2594 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U)
2595 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U)
2596 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU0TC_MASK)
2597 
2598 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U)
2599 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U)
2600 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U)
2601 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_IRQ_FORCINT_TRG_CCU1TC_MASK)
2602 /*! @} */
2603 
2604 /*! @name ATOM3_CH6_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */
2605 /*! @{ */
2606 
2607 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U)
2608 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U)
2609 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U)
2610 #define GTM_gtm_cls3_ATOM3_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_IRQ_MODE_IRQ_MODE_MASK)
2611 /*! @} */
2612 
2613 /*! @name ATOM3_CH6_CTRL_SR - ATOM[i] channel [x] control shadow register */
2614 /*! @{ */
2615 
2616 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_SL_SR_MASK (0x800U)
2617 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_SL_SR_SHIFT (11U)
2618 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_SL_SR_WIDTH (1U)
2619 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_SL_SR(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_SL_SR_MASK)
2620 
2621 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_CLK_SRC_SR_MASK (0xF000U)
2622 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_CLK_SRC_SR_SHIFT (12U)
2623 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_CLK_SRC_SR_WIDTH (4U)
2624 #define GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH6_CTRL_SR_CLK_SRC_SR_MASK)
2625 /*! @} */
2626 
2627 /*! @name ATOM3_CH7_RDADDR - ATOM[i] channel[x] ARU read address register */
2628 /*! @{ */
2629 
2630 #define GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR0_MASK (0x1FFU)
2631 #define GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR0_SHIFT (0U)
2632 #define GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR0_WIDTH (9U)
2633 #define GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR0_MASK)
2634 
2635 #define GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR1_MASK (0x1FF0000U)
2636 #define GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR1_SHIFT (16U)
2637 #define GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR1_WIDTH (9U)
2638 #define GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_RDADDR_RDADDR1_MASK)
2639 /*! @} */
2640 
2641 /*! @name ATOM3_CH7_CTRL - ATOM[i] channel [x] control register */
2642 /*! @{ */
2643 
2644 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_MODE_MASK    (0x3U)
2645 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_MODE_SHIFT   (0U)
2646 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_MODE_WIDTH   (2U)
2647 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_MODE_MASK)
2648 
2649 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TB12_SEL_MASK (0x4U)
2650 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TB12_SEL_SHIFT (2U)
2651 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TB12_SEL_WIDTH (1U)
2652 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TB12_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_TB12_SEL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_TB12_SEL_MASK)
2653 
2654 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ARU_EN_MASK  (0x8U)
2655 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ARU_EN_SHIFT (3U)
2656 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ARU_EN_WIDTH (1U)
2657 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ARU_EN(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_ARU_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_ARU_EN_MASK)
2658 
2659 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ACB_MASK     (0x1F0U)
2660 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ACB_SHIFT    (4U)
2661 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ACB_WIDTH    (5U)
2662 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ACB(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_ACB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_ACB_MASK)
2663 
2664 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_CMP_CTRL_MASK (0x200U)
2665 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_CMP_CTRL_SHIFT (9U)
2666 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_CMP_CTRL_WIDTH (1U)
2667 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_CMP_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_CMP_CTRL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_CMP_CTRL_MASK)
2668 
2669 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EUPM_MASK    (0x400U)
2670 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EUPM_SHIFT   (10U)
2671 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EUPM_WIDTH   (1U)
2672 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EUPM(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_EUPM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_EUPM_MASK)
2673 
2674 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SL_MASK      (0x800U)
2675 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SL_SHIFT     (11U)
2676 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SL_WIDTH     (1U)
2677 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_SL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_SL_MASK)
2678 
2679 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_CLK_SRC_MASK (0xF000U)
2680 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_CLK_SRC_SHIFT (12U)
2681 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_CLK_SRC_WIDTH (4U)
2682 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_CLK_SRC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_CLK_SRC_MASK)
2683 
2684 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_WR_REQ_MASK  (0x10000U)
2685 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_WR_REQ_SHIFT (16U)
2686 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_WR_REQ_WIDTH (1U)
2687 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_WR_REQ(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_WR_REQ_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_WR_REQ_MASK)
2688 
2689 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIG_PULSE_MASK (0x20000U)
2690 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIG_PULSE_SHIFT (17U)
2691 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIG_PULSE_WIDTH (1U)
2692 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIG_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIG_PULSE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIG_PULSE_MASK)
2693 
2694 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_UDMODE_MASK  (0xC0000U)
2695 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_UDMODE_SHIFT (18U)
2696 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_UDMODE_WIDTH (2U)
2697 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_UDMODE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_UDMODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_UDMODE_MASK)
2698 
2699 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_RST_CCU0_MASK (0x100000U)
2700 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_RST_CCU0_SHIFT (20U)
2701 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_RST_CCU0_WIDTH (1U)
2702 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_RST_CCU0(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_RST_CCU0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_RST_CCU0_MASK)
2703 
2704 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_TRIG_MASK (0x200000U)
2705 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_TRIG_SHIFT (21U)
2706 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_TRIG_WIDTH (1U)
2707 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_TRIG_MASK)
2708 
2709 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_TRIG_MASK (0x400000U)
2710 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_TRIG_SHIFT (22U)
2711 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_TRIG_WIDTH (1U)
2712 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_TRIG(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_TRIG_MASK)
2713 
2714 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXTTRIGOUT_MASK (0x800000U)
2715 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXTTRIGOUT_SHIFT (23U)
2716 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXTTRIGOUT_WIDTH (1U)
2717 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXTTRIGOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_EXTTRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_EXTTRIGOUT_MASK)
2718 
2719 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIGOUT_MASK (0x1000000U)
2720 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIGOUT_SHIFT (24U)
2721 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIGOUT_WIDTH (1U)
2722 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIGOUT(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIGOUT_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_TRIGOUT_MASK)
2723 
2724 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SLA_MASK     (0x2000000U)
2725 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SLA_SHIFT    (25U)
2726 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SLA_WIDTH    (1U)
2727 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SLA(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_SLA_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_SLA_MASK)
2728 
2729 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_MASK     (0x4000000U)
2730 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_SHIFT    (26U)
2731 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_WIDTH    (1U)
2732 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_OSM_MASK)
2733 
2734 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ABM_MASK     (0x8000000U)
2735 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ABM_SHIFT    (27U)
2736 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ABM_WIDTH    (1U)
2737 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_ABM(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_ABM_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_ABM_MASK)
2738 
2739 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_FUPD_MASK (0x20000000U)
2740 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_FUPD_SHIFT (29U)
2741 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_FUPD_WIDTH (1U)
2742 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_FUPD(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_FUPD_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_EXT_FUPD_MASK)
2743 
2744 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SOMB_MASK    (0x40000000U)
2745 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SOMB_SHIFT   (30U)
2746 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SOMB_WIDTH   (1U)
2747 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SOMB(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_SOMB_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_SOMB_MASK)
2748 
2749 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_FREEZE_MASK  (0x80000000U)
2750 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_FREEZE_SHIFT (31U)
2751 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_FREEZE_WIDTH (1U)
2752 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_FREEZE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_FREEZE_MASK)
2753 /*! @} */
2754 
2755 /*! @name ATOM3_CH7_SR0 - ATOM[i] channel [x] CCU0 compare shadow register */
2756 /*! @{ */
2757 
2758 #define GTM_gtm_cls3_ATOM3_CH7_SR0_SR0_MASK      (0xFFFFFFU)
2759 #define GTM_gtm_cls3_ATOM3_CH7_SR0_SR0_SHIFT     (0U)
2760 #define GTM_gtm_cls3_ATOM3_CH7_SR0_SR0_WIDTH     (24U)
2761 #define GTM_gtm_cls3_ATOM3_CH7_SR0_SR0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_SR0_SR0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_SR0_SR0_MASK)
2762 /*! @} */
2763 
2764 /*! @name ATOM3_CH7_SR1 - ATOM[i] channel [x] CCU0 compare shadow register */
2765 /*! @{ */
2766 
2767 #define GTM_gtm_cls3_ATOM3_CH7_SR1_SR1_MASK      (0xFFFFFFU)
2768 #define GTM_gtm_cls3_ATOM3_CH7_SR1_SR1_SHIFT     (0U)
2769 #define GTM_gtm_cls3_ATOM3_CH7_SR1_SR1_WIDTH     (24U)
2770 #define GTM_gtm_cls3_ATOM3_CH7_SR1_SR1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_SR1_SR1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_SR1_SR1_MASK)
2771 /*! @} */
2772 
2773 /*! @name ATOM3_CH7_CM0 - ATOM[i] channel [x] CCU0 compare register */
2774 /*! @{ */
2775 
2776 #define GTM_gtm_cls3_ATOM3_CH7_CM0_CM0_MASK      (0xFFFFFFU)
2777 #define GTM_gtm_cls3_ATOM3_CH7_CM0_CM0_SHIFT     (0U)
2778 #define GTM_gtm_cls3_ATOM3_CH7_CM0_CM0_WIDTH     (24U)
2779 #define GTM_gtm_cls3_ATOM3_CH7_CM0_CM0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CM0_CM0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CM0_CM0_MASK)
2780 /*! @} */
2781 
2782 /*! @name ATOM3_CH7_CM1 - ATOM[i] channel [x] CCU0 compare register */
2783 /*! @{ */
2784 
2785 #define GTM_gtm_cls3_ATOM3_CH7_CM1_CM1_MASK      (0xFFFFFFU)
2786 #define GTM_gtm_cls3_ATOM3_CH7_CM1_CM1_SHIFT     (0U)
2787 #define GTM_gtm_cls3_ATOM3_CH7_CM1_CM1_WIDTH     (24U)
2788 #define GTM_gtm_cls3_ATOM3_CH7_CM1_CM1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CM1_CM1_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CM1_CM1_MASK)
2789 /*! @} */
2790 
2791 /*! @name ATOM3_CH7_CN0 - ATOM[i] channel [x] CCU0 counter register */
2792 /*! @{ */
2793 
2794 #define GTM_gtm_cls3_ATOM3_CH7_CN0_CN0_MASK      (0xFFFFFFU)
2795 #define GTM_gtm_cls3_ATOM3_CH7_CN0_CN0_SHIFT     (0U)
2796 #define GTM_gtm_cls3_ATOM3_CH7_CN0_CN0_WIDTH     (24U)
2797 #define GTM_gtm_cls3_ATOM3_CH7_CN0_CN0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CN0_CN0_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CN0_CN0_MASK)
2798 /*! @} */
2799 
2800 /*! @name ATOM3_CH7_STAT - ATOM[i] channel [x] status register */
2801 /*! @{ */
2802 
2803 #define GTM_gtm_cls3_ATOM3_CH7_STAT_OL_MASK      (0x1U)
2804 #define GTM_gtm_cls3_ATOM3_CH7_STAT_OL_SHIFT     (0U)
2805 #define GTM_gtm_cls3_ATOM3_CH7_STAT_OL_WIDTH     (1U)
2806 #define GTM_gtm_cls3_ATOM3_CH7_STAT_OL(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_STAT_OL_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_STAT_OL_MASK)
2807 
2808 #define GTM_gtm_cls3_ATOM3_CH7_STAT_ACBI_MASK    (0x1F0000U)
2809 #define GTM_gtm_cls3_ATOM3_CH7_STAT_ACBI_SHIFT   (16U)
2810 #define GTM_gtm_cls3_ATOM3_CH7_STAT_ACBI_WIDTH   (5U)
2811 #define GTM_gtm_cls3_ATOM3_CH7_STAT_ACBI(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_STAT_ACBI_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_STAT_ACBI_MASK)
2812 
2813 #define GTM_gtm_cls3_ATOM3_CH7_STAT_DV_MASK      (0x200000U)
2814 #define GTM_gtm_cls3_ATOM3_CH7_STAT_DV_SHIFT     (21U)
2815 #define GTM_gtm_cls3_ATOM3_CH7_STAT_DV_WIDTH     (1U)
2816 #define GTM_gtm_cls3_ATOM3_CH7_STAT_DV(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_STAT_DV_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_STAT_DV_MASK)
2817 
2818 #define GTM_gtm_cls3_ATOM3_CH7_STAT_WRF_MASK     (0x400000U)
2819 #define GTM_gtm_cls3_ATOM3_CH7_STAT_WRF_SHIFT    (22U)
2820 #define GTM_gtm_cls3_ATOM3_CH7_STAT_WRF_WIDTH    (1U)
2821 #define GTM_gtm_cls3_ATOM3_CH7_STAT_WRF(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_STAT_WRF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_STAT_WRF_MASK)
2822 
2823 #define GTM_gtm_cls3_ATOM3_CH7_STAT_DR_MASK      (0x800000U)
2824 #define GTM_gtm_cls3_ATOM3_CH7_STAT_DR_SHIFT     (23U)
2825 #define GTM_gtm_cls3_ATOM3_CH7_STAT_DR_WIDTH     (1U)
2826 #define GTM_gtm_cls3_ATOM3_CH7_STAT_DR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_STAT_DR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_STAT_DR_MASK)
2827 
2828 #define GTM_gtm_cls3_ATOM3_CH7_STAT_ACBO_MASK    (0x1F000000U)
2829 #define GTM_gtm_cls3_ATOM3_CH7_STAT_ACBO_SHIFT   (24U)
2830 #define GTM_gtm_cls3_ATOM3_CH7_STAT_ACBO_WIDTH   (5U)
2831 #define GTM_gtm_cls3_ATOM3_CH7_STAT_ACBO(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_STAT_ACBO_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_STAT_ACBO_MASK)
2832 
2833 #define GTM_gtm_cls3_ATOM3_CH7_STAT_OSM_RTF_MASK (0x20000000U)
2834 #define GTM_gtm_cls3_ATOM3_CH7_STAT_OSM_RTF_SHIFT (29U)
2835 #define GTM_gtm_cls3_ATOM3_CH7_STAT_OSM_RTF_WIDTH (1U)
2836 #define GTM_gtm_cls3_ATOM3_CH7_STAT_OSM_RTF(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_STAT_OSM_RTF_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_STAT_OSM_RTF_MASK)
2837 /*! @} */
2838 
2839 /*! @name ATOM3_CH7_IRQ_NOTIFY - ATOM[i] channel [x] interrupt notification register */
2840 /*! @{ */
2841 
2842 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU0TC_MASK (0x1U)
2843 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU0TC_SHIFT (0U)
2844 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU0TC_WIDTH (1U)
2845 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU0TC_MASK)
2846 
2847 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU1TC_MASK (0x2U)
2848 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU1TC_SHIFT (1U)
2849 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU1TC_WIDTH (1U)
2850 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_IRQ_NOTIFY_CCU1TC_MASK)
2851 /*! @} */
2852 
2853 /*! @name ATOM3_CH7_IRQ_EN - ATOM[i] channel [x] interrupt enable register */
2854 /*! @{ */
2855 
2856 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU0TC_IRQ_EN_MASK (0x1U)
2857 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU0TC_IRQ_EN_SHIFT (0U)
2858 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU0TC_IRQ_EN_WIDTH (1U)
2859 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU0TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU0TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU0TC_IRQ_EN_MASK)
2860 
2861 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU1TC_IRQ_EN_MASK (0x2U)
2862 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU1TC_IRQ_EN_SHIFT (1U)
2863 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU1TC_IRQ_EN_WIDTH (1U)
2864 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU1TC_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU1TC_IRQ_EN_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_IRQ_EN_CCU1TC_IRQ_EN_MASK)
2865 /*! @} */
2866 
2867 /*! @name ATOM3_CH7_IRQ_FORCINT - ATOM[i] channel [x] software interrupt generation */
2868 /*! @{ */
2869 
2870 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU0TC_MASK (0x1U)
2871 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU0TC_SHIFT (0U)
2872 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU0TC_WIDTH (1U)
2873 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU0TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU0TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU0TC_MASK)
2874 
2875 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU1TC_MASK (0x2U)
2876 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU1TC_SHIFT (1U)
2877 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU1TC_WIDTH (1U)
2878 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU1TC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU1TC_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_IRQ_FORCINT_TRG_CCU1TC_MASK)
2879 /*! @} */
2880 
2881 /*! @name ATOM3_CH7_IRQ_MODE - ATOM[i] channel [x] interrupt mode configuration register */
2882 /*! @{ */
2883 
2884 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U)
2885 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U)
2886 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U)
2887 #define GTM_gtm_cls3_ATOM3_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_IRQ_MODE_IRQ_MODE_MASK)
2888 /*! @} */
2889 
2890 /*! @name ATOM3_CH7_CTRL_SR - ATOM[i] channel [x] control shadow register */
2891 /*! @{ */
2892 
2893 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_SL_SR_MASK (0x800U)
2894 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_SL_SR_SHIFT (11U)
2895 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_SL_SR_WIDTH (1U)
2896 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_SL_SR(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_SL_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_SL_SR_MASK)
2897 
2898 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_CLK_SRC_SR_MASK (0xF000U)
2899 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_CLK_SRC_SR_SHIFT (12U)
2900 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_CLK_SRC_SR_WIDTH (4U)
2901 #define GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_CLK_SRC_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_CLK_SRC_SR_SHIFT)) & GTM_gtm_cls3_ATOM3_CH7_CTRL_SR_CLK_SRC_SR_MASK)
2902 /*! @} */
2903 
2904 /*! @name ATOM3_AGC_GLB_CTRL - ATOM[i] AGC global control register */
2905 /*! @{ */
2906 
2907 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_HOST_TRIG_MASK (0x1U)
2908 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_HOST_TRIG_SHIFT (0U)
2909 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_HOST_TRIG_WIDTH (1U)
2910 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_HOST_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_HOST_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_HOST_TRIG_MASK)
2911 
2912 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH0_MASK (0x100U)
2913 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH0_SHIFT (8U)
2914 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH0_WIDTH (1U)
2915 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH0_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH0_MASK)
2916 
2917 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH1_MASK (0x200U)
2918 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH1_SHIFT (9U)
2919 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH1_WIDTH (1U)
2920 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH1_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH1_MASK)
2921 
2922 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH2_MASK (0x400U)
2923 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH2_SHIFT (10U)
2924 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH2_WIDTH (1U)
2925 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH2_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH2_MASK)
2926 
2927 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH3_MASK (0x800U)
2928 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH3_SHIFT (11U)
2929 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH3_WIDTH (1U)
2930 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH3_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH3_MASK)
2931 
2932 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH4_MASK (0x1000U)
2933 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH4_SHIFT (12U)
2934 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH4_WIDTH (1U)
2935 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH4_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH4_MASK)
2936 
2937 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH5_MASK (0x2000U)
2938 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH5_SHIFT (13U)
2939 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH5_WIDTH (1U)
2940 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH5_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH5_MASK)
2941 
2942 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH6_MASK (0x4000U)
2943 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH6_SHIFT (14U)
2944 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH6_WIDTH (1U)
2945 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH6_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH6_MASK)
2946 
2947 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH7_MASK (0x8000U)
2948 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH7_SHIFT (15U)
2949 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH7_WIDTH (1U)
2950 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH7_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_RST_CH7_MASK)
2951 
2952 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL0_MASK (0x30000U)
2953 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL0_SHIFT (16U)
2954 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL0_WIDTH (2U)
2955 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL0_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL0_MASK)
2956 
2957 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL1_MASK (0xC0000U)
2958 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL1_SHIFT (18U)
2959 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL1_WIDTH (2U)
2960 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL1_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL1_MASK)
2961 
2962 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL2_MASK (0x300000U)
2963 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL2_SHIFT (20U)
2964 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL2_WIDTH (2U)
2965 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL2_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL2_MASK)
2966 
2967 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL3_MASK (0xC00000U)
2968 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL3_SHIFT (22U)
2969 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL3_WIDTH (2U)
2970 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL3_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL3_MASK)
2971 
2972 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL4_MASK (0x3000000U)
2973 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL4_SHIFT (24U)
2974 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL4_WIDTH (2U)
2975 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL4_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL4_MASK)
2976 
2977 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL5_MASK (0xC000000U)
2978 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL5_SHIFT (26U)
2979 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL5_WIDTH (2U)
2980 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL5_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL5_MASK)
2981 
2982 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL6_MASK (0x30000000U)
2983 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL6_SHIFT (28U)
2984 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL6_WIDTH (2U)
2985 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL6_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL6_MASK)
2986 
2987 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL7_MASK (0xC0000000U)
2988 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL7_SHIFT (30U)
2989 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL7_WIDTH (2U)
2990 #define GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL7_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_GLB_CTRL_UPEN_CTRL7_MASK)
2991 /*! @} */
2992 
2993 /*! @name ATOM3_AGC_ENDIS_CTRL - ATOM[i] AGC enable/disable control register */
2994 /*! @{ */
2995 
2996 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL0_MASK (0x3U)
2997 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL0_SHIFT (0U)
2998 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL0_WIDTH (2U)
2999 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL0_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL0_MASK)
3000 
3001 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL1_MASK (0xCU)
3002 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL1_SHIFT (2U)
3003 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL1_WIDTH (2U)
3004 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL1_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL1_MASK)
3005 
3006 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL2_MASK (0x30U)
3007 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL2_SHIFT (4U)
3008 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL2_WIDTH (2U)
3009 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL2_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL2_MASK)
3010 
3011 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL3_MASK (0xC0U)
3012 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL3_SHIFT (6U)
3013 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL3_WIDTH (2U)
3014 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL3_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL3_MASK)
3015 
3016 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL4_MASK (0x300U)
3017 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL4_SHIFT (8U)
3018 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL4_WIDTH (2U)
3019 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL4_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL4_MASK)
3020 
3021 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL5_MASK (0xC00U)
3022 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL5_SHIFT (10U)
3023 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL5_WIDTH (2U)
3024 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL5_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL5_MASK)
3025 
3026 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL6_MASK (0x3000U)
3027 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL6_SHIFT (12U)
3028 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL6_WIDTH (2U)
3029 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL6_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL6_MASK)
3030 
3031 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL7_MASK (0xC000U)
3032 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL7_SHIFT (14U)
3033 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL7_WIDTH (2U)
3034 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL7_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_CTRL_ENDIS_CTRL7_MASK)
3035 /*! @} */
3036 
3037 /*! @name ATOM3_AGC_ENDIS_STAT - ATOM[i] AGC enable/disable status register */
3038 /*! @{ */
3039 
3040 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT0_MASK (0x3U)
3041 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT0_SHIFT (0U)
3042 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT0_WIDTH (2U)
3043 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT0_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT0_MASK)
3044 
3045 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT1_MASK (0xCU)
3046 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT1_SHIFT (2U)
3047 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT1_WIDTH (2U)
3048 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT1_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT1_MASK)
3049 
3050 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT2_MASK (0x30U)
3051 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT2_SHIFT (4U)
3052 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT2_WIDTH (2U)
3053 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT2_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT2_MASK)
3054 
3055 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT3_MASK (0xC0U)
3056 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT3_SHIFT (6U)
3057 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT3_WIDTH (2U)
3058 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT3_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT3_MASK)
3059 
3060 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT4_MASK (0x300U)
3061 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT4_SHIFT (8U)
3062 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT4_WIDTH (2U)
3063 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT4_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT4_MASK)
3064 
3065 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT5_MASK (0xC00U)
3066 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT5_SHIFT (10U)
3067 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT5_WIDTH (2U)
3068 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT5_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT5_MASK)
3069 
3070 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT6_MASK (0x3000U)
3071 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT6_SHIFT (12U)
3072 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT6_WIDTH (2U)
3073 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT6_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT6_MASK)
3074 
3075 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT7_MASK (0xC000U)
3076 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT7_SHIFT (14U)
3077 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT7_WIDTH (2U)
3078 #define GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT7_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ENDIS_STAT_ENDIS_STAT7_MASK)
3079 /*! @} */
3080 
3081 /*! @name ATOM3_AGC_ACT_TB - ATOM[i] AGC action time base register */
3082 /*! @{ */
3083 
3084 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_ACT_TB_MASK (0xFFFFFFU)
3085 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_ACT_TB_SHIFT (0U)
3086 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_ACT_TB_WIDTH (24U)
3087 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_ACT_TB(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ACT_TB_ACT_TB_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ACT_TB_ACT_TB_MASK)
3088 
3089 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TB_TRIG_MASK (0x1000000U)
3090 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TB_TRIG_SHIFT (24U)
3091 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TB_TRIG_WIDTH (1U)
3092 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TB_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TB_TRIG_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TB_TRIG_MASK)
3093 
3094 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TBU_SEL_MASK (0x6000000U)
3095 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TBU_SEL_SHIFT (25U)
3096 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TBU_SEL_WIDTH (2U)
3097 #define GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TBU_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TBU_SEL_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_ACT_TB_TBU_SEL_MASK)
3098 /*! @} */
3099 
3100 /*! @name ATOM3_AGC_OUTEN_CTRL - ATOM[i] AGC output enable control register */
3101 /*! @{ */
3102 
3103 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL0_MASK (0x3U)
3104 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL0_SHIFT (0U)
3105 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL0_WIDTH (2U)
3106 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL0_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL0_MASK)
3107 
3108 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL1_MASK (0xCU)
3109 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL1_SHIFT (2U)
3110 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL1_WIDTH (2U)
3111 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL1_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL1_MASK)
3112 
3113 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL2_MASK (0x30U)
3114 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL2_SHIFT (4U)
3115 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL2_WIDTH (2U)
3116 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL2_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL2_MASK)
3117 
3118 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL3_MASK (0xC0U)
3119 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL3_SHIFT (6U)
3120 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL3_WIDTH (2U)
3121 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL3_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL3_MASK)
3122 
3123 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL4_MASK (0x300U)
3124 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL4_SHIFT (8U)
3125 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL4_WIDTH (2U)
3126 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL4_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL4_MASK)
3127 
3128 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL5_MASK (0xC00U)
3129 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL5_SHIFT (10U)
3130 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL5_WIDTH (2U)
3131 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL5_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL5_MASK)
3132 
3133 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL6_MASK (0x3000U)
3134 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL6_SHIFT (12U)
3135 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL6_WIDTH (2U)
3136 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL6_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL6_MASK)
3137 
3138 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL7_MASK (0xC000U)
3139 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL7_SHIFT (14U)
3140 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL7_WIDTH (2U)
3141 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL7_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_CTRL_OUTEN_CTRL7_MASK)
3142 /*! @} */
3143 
3144 /*! @name ATOM3_AGC_OUTEN_STAT - ATOM[i] AGC output enable status register */
3145 /*! @{ */
3146 
3147 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT0_MASK (0x3U)
3148 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT0_SHIFT (0U)
3149 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT0_WIDTH (2U)
3150 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT0_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT0_MASK)
3151 
3152 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT1_MASK (0xCU)
3153 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT1_SHIFT (2U)
3154 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT1_WIDTH (2U)
3155 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT1_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT1_MASK)
3156 
3157 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT2_MASK (0x30U)
3158 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT2_SHIFT (4U)
3159 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT2_WIDTH (2U)
3160 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT2_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT2_MASK)
3161 
3162 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT3_MASK (0xC0U)
3163 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT3_SHIFT (6U)
3164 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT3_WIDTH (2U)
3165 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT3_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT3_MASK)
3166 
3167 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT4_MASK (0x300U)
3168 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT4_SHIFT (8U)
3169 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT4_WIDTH (2U)
3170 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT4_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT4_MASK)
3171 
3172 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT5_MASK (0xC00U)
3173 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT5_SHIFT (10U)
3174 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT5_WIDTH (2U)
3175 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT5_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT5_MASK)
3176 
3177 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT6_MASK (0x3000U)
3178 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT6_SHIFT (12U)
3179 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT6_WIDTH (2U)
3180 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT6_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT6_MASK)
3181 
3182 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT7_MASK (0xC000U)
3183 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT7_SHIFT (14U)
3184 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT7_WIDTH (2U)
3185 #define GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT7_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_OUTEN_STAT_OUTEN_STAT7_MASK)
3186 /*! @} */
3187 
3188 /*! @name ATOM3_AGC_FUPD_CTRL - ATOM[i] AGC force update control register */
3189 /*! @{ */
3190 
3191 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL0_MASK (0x3U)
3192 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL0_SHIFT (0U)
3193 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL0_WIDTH (2U)
3194 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL0_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL0_MASK)
3195 
3196 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL1_MASK (0xCU)
3197 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL1_SHIFT (2U)
3198 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL1_WIDTH (2U)
3199 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL1_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL1_MASK)
3200 
3201 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL2_MASK (0x30U)
3202 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL2_SHIFT (4U)
3203 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL2_WIDTH (2U)
3204 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL2_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL2_MASK)
3205 
3206 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL3_MASK (0xC0U)
3207 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL3_SHIFT (6U)
3208 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL3_WIDTH (2U)
3209 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL3_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL3_MASK)
3210 
3211 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL4_MASK (0x300U)
3212 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL4_SHIFT (8U)
3213 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL4_WIDTH (2U)
3214 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL4_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL4_MASK)
3215 
3216 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL5_MASK (0xC00U)
3217 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL5_SHIFT (10U)
3218 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL5_WIDTH (2U)
3219 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL5_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL5_MASK)
3220 
3221 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL6_MASK (0x3000U)
3222 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL6_SHIFT (12U)
3223 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL6_WIDTH (2U)
3224 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL6_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL6_MASK)
3225 
3226 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL7_MASK (0xC000U)
3227 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL7_SHIFT (14U)
3228 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL7_WIDTH (2U)
3229 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL7_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_FUPD_CTRL7_MASK)
3230 
3231 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH0_MASK (0x30000U)
3232 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH0_SHIFT (16U)
3233 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH0_WIDTH (2U)
3234 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH0_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH0_MASK)
3235 
3236 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH1_MASK (0xC0000U)
3237 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH1_SHIFT (18U)
3238 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH1_WIDTH (2U)
3239 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH1_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH1_MASK)
3240 
3241 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH2_MASK (0x300000U)
3242 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH2_SHIFT (20U)
3243 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH2_WIDTH (2U)
3244 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH2_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH2_MASK)
3245 
3246 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH3_MASK (0xC00000U)
3247 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH3_SHIFT (22U)
3248 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH3_WIDTH (2U)
3249 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH3_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH3_MASK)
3250 
3251 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH4_MASK (0x3000000U)
3252 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH4_SHIFT (24U)
3253 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH4_WIDTH (2U)
3254 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH4_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH4_MASK)
3255 
3256 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH5_MASK (0xC000000U)
3257 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH5_SHIFT (26U)
3258 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH5_WIDTH (2U)
3259 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH5_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH5_MASK)
3260 
3261 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH6_MASK (0x30000000U)
3262 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH6_SHIFT (28U)
3263 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH6_WIDTH (2U)
3264 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH6_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH6_MASK)
3265 
3266 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH7_MASK (0xC0000000U)
3267 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH7_SHIFT (30U)
3268 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH7_WIDTH (2U)
3269 #define GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH7_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_FUPD_CTRL_RSTCN0_CH7_MASK)
3270 /*! @} */
3271 
3272 /*! @name ATOM3_AGC_INT_TRIG - ATOM[i] AGC internal trigger control register */
3273 /*! @{ */
3274 
3275 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG0_MASK (0x3U)
3276 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG0_SHIFT (0U)
3277 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG0_WIDTH (2U)
3278 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG0_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG0_MASK)
3279 
3280 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG1_MASK (0xCU)
3281 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG1_SHIFT (2U)
3282 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG1_WIDTH (2U)
3283 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG1_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG1_MASK)
3284 
3285 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG2_MASK (0x30U)
3286 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG2_SHIFT (4U)
3287 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG2_WIDTH (2U)
3288 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG2_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG2_MASK)
3289 
3290 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG3_MASK (0xC0U)
3291 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG3_SHIFT (6U)
3292 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG3_WIDTH (2U)
3293 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG3_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG3_MASK)
3294 
3295 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG4_MASK (0x300U)
3296 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG4_SHIFT (8U)
3297 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG4_WIDTH (2U)
3298 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG4_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG4_MASK)
3299 
3300 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG5_MASK (0xC00U)
3301 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG5_SHIFT (10U)
3302 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG5_WIDTH (2U)
3303 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG5_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG5_MASK)
3304 
3305 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG6_MASK (0x3000U)
3306 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG6_SHIFT (12U)
3307 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG6_WIDTH (2U)
3308 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG6_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG6_MASK)
3309 
3310 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG7_MASK (0xC000U)
3311 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG7_SHIFT (14U)
3312 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG7_WIDTH (2U)
3313 #define GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG7_SHIFT)) & GTM_gtm_cls3_ATOM3_AGC_INT_TRIG_INT_TRIG7_MASK)
3314 /*! @} */
3315 
3316 /*! @name MCS3_CH0_R0 - MCS[i] channel x general purpose register [y] */
3317 /*! @{ */
3318 
3319 #define GTM_gtm_cls3_MCS3_CH0_R0_DATA_MASK       (0xFFFFFFU)
3320 #define GTM_gtm_cls3_MCS3_CH0_R0_DATA_SHIFT      (0U)
3321 #define GTM_gtm_cls3_MCS3_CH0_R0_DATA_WIDTH      (24U)
3322 #define GTM_gtm_cls3_MCS3_CH0_R0_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_R0_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_R0_DATA_MASK)
3323 /*! @} */
3324 
3325 /*! @name MCS3_CH0_R1 - MCS[i] channel x general purpose register [y] */
3326 /*! @{ */
3327 
3328 #define GTM_gtm_cls3_MCS3_CH0_R1_DATA_MASK       (0xFFFFFFU)
3329 #define GTM_gtm_cls3_MCS3_CH0_R1_DATA_SHIFT      (0U)
3330 #define GTM_gtm_cls3_MCS3_CH0_R1_DATA_WIDTH      (24U)
3331 #define GTM_gtm_cls3_MCS3_CH0_R1_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_R1_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_R1_DATA_MASK)
3332 /*! @} */
3333 
3334 /*! @name MCS3_CH0_R2 - MCS[i] channel x general purpose register [y] */
3335 /*! @{ */
3336 
3337 #define GTM_gtm_cls3_MCS3_CH0_R2_DATA_MASK       (0xFFFFFFU)
3338 #define GTM_gtm_cls3_MCS3_CH0_R2_DATA_SHIFT      (0U)
3339 #define GTM_gtm_cls3_MCS3_CH0_R2_DATA_WIDTH      (24U)
3340 #define GTM_gtm_cls3_MCS3_CH0_R2_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_R2_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_R2_DATA_MASK)
3341 /*! @} */
3342 
3343 /*! @name MCS3_CH0_R3 - MCS[i] channel x general purpose register [y] */
3344 /*! @{ */
3345 
3346 #define GTM_gtm_cls3_MCS3_CH0_R3_DATA_MASK       (0xFFFFFFU)
3347 #define GTM_gtm_cls3_MCS3_CH0_R3_DATA_SHIFT      (0U)
3348 #define GTM_gtm_cls3_MCS3_CH0_R3_DATA_WIDTH      (24U)
3349 #define GTM_gtm_cls3_MCS3_CH0_R3_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_R3_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_R3_DATA_MASK)
3350 /*! @} */
3351 
3352 /*! @name MCS3_CH0_R4 - MCS[i] channel x general purpose register [y] */
3353 /*! @{ */
3354 
3355 #define GTM_gtm_cls3_MCS3_CH0_R4_DATA_MASK       (0xFFFFFFU)
3356 #define GTM_gtm_cls3_MCS3_CH0_R4_DATA_SHIFT      (0U)
3357 #define GTM_gtm_cls3_MCS3_CH0_R4_DATA_WIDTH      (24U)
3358 #define GTM_gtm_cls3_MCS3_CH0_R4_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_R4_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_R4_DATA_MASK)
3359 /*! @} */
3360 
3361 /*! @name MCS3_CH0_R5 - MCS[i] channel x general purpose register [y] */
3362 /*! @{ */
3363 
3364 #define GTM_gtm_cls3_MCS3_CH0_R5_DATA_MASK       (0xFFFFFFU)
3365 #define GTM_gtm_cls3_MCS3_CH0_R5_DATA_SHIFT      (0U)
3366 #define GTM_gtm_cls3_MCS3_CH0_R5_DATA_WIDTH      (24U)
3367 #define GTM_gtm_cls3_MCS3_CH0_R5_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_R5_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_R5_DATA_MASK)
3368 /*! @} */
3369 
3370 /*! @name MCS3_CH0_R6 - MCS[i] channel x general purpose register [y] */
3371 /*! @{ */
3372 
3373 #define GTM_gtm_cls3_MCS3_CH0_R6_DATA_MASK       (0xFFFFFFU)
3374 #define GTM_gtm_cls3_MCS3_CH0_R6_DATA_SHIFT      (0U)
3375 #define GTM_gtm_cls3_MCS3_CH0_R6_DATA_WIDTH      (24U)
3376 #define GTM_gtm_cls3_MCS3_CH0_R6_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_R6_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_R6_DATA_MASK)
3377 /*! @} */
3378 
3379 /*! @name MCS3_CH0_R7 - MCS[i] channel x general purpose register [y] */
3380 /*! @{ */
3381 
3382 #define GTM_gtm_cls3_MCS3_CH0_R7_DATA_MASK       (0xFFFFFFU)
3383 #define GTM_gtm_cls3_MCS3_CH0_R7_DATA_SHIFT      (0U)
3384 #define GTM_gtm_cls3_MCS3_CH0_R7_DATA_WIDTH      (24U)
3385 #define GTM_gtm_cls3_MCS3_CH0_R7_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_R7_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_R7_DATA_MASK)
3386 /*! @} */
3387 
3388 /*! @name MCS3_CH0_CTRL - MCS[i] channel x control register */
3389 /*! @{ */
3390 
3391 #define GTM_gtm_cls3_MCS3_CH0_CTRL_EN_MASK       (0x1U)
3392 #define GTM_gtm_cls3_MCS3_CH0_CTRL_EN_SHIFT      (0U)
3393 #define GTM_gtm_cls3_MCS3_CH0_CTRL_EN_WIDTH      (1U)
3394 #define GTM_gtm_cls3_MCS3_CH0_CTRL_EN(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_CTRL_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_CTRL_EN_MASK)
3395 
3396 #define GTM_gtm_cls3_MCS3_CH0_CTRL_IRQ_MASK      (0x2U)
3397 #define GTM_gtm_cls3_MCS3_CH0_CTRL_IRQ_SHIFT     (1U)
3398 #define GTM_gtm_cls3_MCS3_CH0_CTRL_IRQ_WIDTH     (1U)
3399 #define GTM_gtm_cls3_MCS3_CH0_CTRL_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_CTRL_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_CTRL_IRQ_MASK)
3400 
3401 #define GTM_gtm_cls3_MCS3_CH0_CTRL_ERR_MASK      (0x4U)
3402 #define GTM_gtm_cls3_MCS3_CH0_CTRL_ERR_SHIFT     (2U)
3403 #define GTM_gtm_cls3_MCS3_CH0_CTRL_ERR_WIDTH     (1U)
3404 #define GTM_gtm_cls3_MCS3_CH0_CTRL_ERR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_CTRL_ERR_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_CTRL_ERR_MASK)
3405 
3406 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CY_MASK       (0x10U)
3407 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CY_SHIFT      (4U)
3408 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CY_WIDTH      (1U)
3409 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CY(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_CTRL_CY_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_CTRL_CY_MASK)
3410 
3411 #define GTM_gtm_cls3_MCS3_CH0_CTRL_Z_MASK        (0x20U)
3412 #define GTM_gtm_cls3_MCS3_CH0_CTRL_Z_SHIFT       (5U)
3413 #define GTM_gtm_cls3_MCS3_CH0_CTRL_Z_WIDTH       (1U)
3414 #define GTM_gtm_cls3_MCS3_CH0_CTRL_Z(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_CTRL_Z_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_CTRL_Z_MASK)
3415 
3416 #define GTM_gtm_cls3_MCS3_CH0_CTRL_V_MASK        (0x40U)
3417 #define GTM_gtm_cls3_MCS3_CH0_CTRL_V_SHIFT       (6U)
3418 #define GTM_gtm_cls3_MCS3_CH0_CTRL_V_WIDTH       (1U)
3419 #define GTM_gtm_cls3_MCS3_CH0_CTRL_V(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_CTRL_V_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_CTRL_V_MASK)
3420 
3421 #define GTM_gtm_cls3_MCS3_CH0_CTRL_N_MASK        (0x80U)
3422 #define GTM_gtm_cls3_MCS3_CH0_CTRL_N_SHIFT       (7U)
3423 #define GTM_gtm_cls3_MCS3_CH0_CTRL_N_WIDTH       (1U)
3424 #define GTM_gtm_cls3_MCS3_CH0_CTRL_N(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_CTRL_N_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_CTRL_N_MASK)
3425 
3426 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CAT_MASK      (0x100U)
3427 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CAT_SHIFT     (8U)
3428 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CAT_WIDTH     (1U)
3429 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_CTRL_CAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_CTRL_CAT_MASK)
3430 
3431 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CWT_MASK      (0x200U)
3432 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CWT_SHIFT     (9U)
3433 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CWT_WIDTH     (1U)
3434 #define GTM_gtm_cls3_MCS3_CH0_CTRL_CWT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_CTRL_CWT_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_CTRL_CWT_MASK)
3435 
3436 #define GTM_gtm_cls3_MCS3_CH0_CTRL_SAT_MASK      (0x400U)
3437 #define GTM_gtm_cls3_MCS3_CH0_CTRL_SAT_SHIFT     (10U)
3438 #define GTM_gtm_cls3_MCS3_CH0_CTRL_SAT_WIDTH     (1U)
3439 #define GTM_gtm_cls3_MCS3_CH0_CTRL_SAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_CTRL_SAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_CTRL_SAT_MASK)
3440 /*! @} */
3441 
3442 /*! @name MCS3_CH0_ACB - MCS[i] channel x ARU control Bit register */
3443 /*! @{ */
3444 
3445 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB0_MASK      (0x1U)
3446 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB0_SHIFT     (0U)
3447 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB0_WIDTH     (1U)
3448 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_ACB_ACB0_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_ACB_ACB0_MASK)
3449 
3450 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB1_MASK      (0x2U)
3451 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB1_SHIFT     (1U)
3452 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB1_WIDTH     (1U)
3453 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_ACB_ACB1_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_ACB_ACB1_MASK)
3454 
3455 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB2_MASK      (0x4U)
3456 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB2_SHIFT     (2U)
3457 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB2_WIDTH     (1U)
3458 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB2(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_ACB_ACB2_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_ACB_ACB2_MASK)
3459 
3460 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB3_MASK      (0x8U)
3461 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB3_SHIFT     (3U)
3462 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB3_WIDTH     (1U)
3463 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB3(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_ACB_ACB3_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_ACB_ACB3_MASK)
3464 
3465 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB4_MASK      (0x10U)
3466 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB4_SHIFT     (4U)
3467 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB4_WIDTH     (1U)
3468 #define GTM_gtm_cls3_MCS3_CH0_ACB_ACB4(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_ACB_ACB4_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_ACB_ACB4_MASK)
3469 /*! @} */
3470 
3471 /*! @name MCS3_CH0_MHB - MCS[i] channel x memory high byte register */
3472 /*! @{ */
3473 
3474 #define GTM_gtm_cls3_MCS3_CH0_MHB_DATA_MASK      (0xFFU)
3475 #define GTM_gtm_cls3_MCS3_CH0_MHB_DATA_SHIFT     (0U)
3476 #define GTM_gtm_cls3_MCS3_CH0_MHB_DATA_WIDTH     (8U)
3477 #define GTM_gtm_cls3_MCS3_CH0_MHB_DATA(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_MHB_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_MHB_DATA_MASK)
3478 /*! @} */
3479 
3480 /*! @name MCS3_CH0_PC - MCS[i] channel x program counter register */
3481 /*! @{ */
3482 
3483 #define GTM_gtm_cls3_MCS3_CH0_PC_PC_MASK         (0xFFFFU)
3484 #define GTM_gtm_cls3_MCS3_CH0_PC_PC_SHIFT        (0U)
3485 #define GTM_gtm_cls3_MCS3_CH0_PC_PC_WIDTH        (16U)
3486 #define GTM_gtm_cls3_MCS3_CH0_PC_PC(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_PC_PC_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_PC_PC_MASK)
3487 /*! @} */
3488 
3489 /*! @name MCS3_CH0_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */
3490 /*! @{ */
3491 
3492 #define GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U)
3493 #define GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U)
3494 #define GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U)
3495 #define GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_MCS_IRQ_MASK)
3496 
3497 #define GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U)
3498 #define GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U)
3499 #define GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U)
3500 #define GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_IRQ_NOTIFY_ERR_IRQ_MASK)
3501 /*! @} */
3502 
3503 /*! @name MCS3_CH0_IRQ_EN - MCS[i] channel x interrupt enable register */
3504 /*! @{ */
3505 
3506 #define GTM_gtm_cls3_MCS3_CH0_IRQ_EN_MCS_IRQ_EN_MASK (0x1U)
3507 #define GTM_gtm_cls3_MCS3_CH0_IRQ_EN_MCS_IRQ_EN_SHIFT (0U)
3508 #define GTM_gtm_cls3_MCS3_CH0_IRQ_EN_MCS_IRQ_EN_WIDTH (1U)
3509 #define GTM_gtm_cls3_MCS3_CH0_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_IRQ_EN_MCS_IRQ_EN_MASK)
3510 
3511 #define GTM_gtm_cls3_MCS3_CH0_IRQ_EN_ERR_IRQ_EN_MASK (0x4U)
3512 #define GTM_gtm_cls3_MCS3_CH0_IRQ_EN_ERR_IRQ_EN_SHIFT (2U)
3513 #define GTM_gtm_cls3_MCS3_CH0_IRQ_EN_ERR_IRQ_EN_WIDTH (1U)
3514 #define GTM_gtm_cls3_MCS3_CH0_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_IRQ_EN_ERR_IRQ_EN_MASK)
3515 /*! @} */
3516 
3517 /*! @name MCS3_CH0_IRQ_FORCINT - MCS[i] channel x force interrupt register */
3518 /*! @{ */
3519 
3520 #define GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U)
3521 #define GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U)
3522 #define GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U)
3523 #define GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_MCS_IRQ_MASK)
3524 
3525 #define GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U)
3526 #define GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U)
3527 #define GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U)
3528 #define GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_IRQ_FORCINT_TRG_ERR_IRQ_MASK)
3529 /*! @} */
3530 
3531 /*! @name MCS3_CH0_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */
3532 /*! @{ */
3533 
3534 #define GTM_gtm_cls3_MCS3_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U)
3535 #define GTM_gtm_cls3_MCS3_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U)
3536 #define GTM_gtm_cls3_MCS3_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U)
3537 #define GTM_gtm_cls3_MCS3_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_IRQ_MODE_IRQ_MODE_MASK)
3538 /*! @} */
3539 
3540 /*! @name MCS3_CH0_EIRQ_EN - MCS[i] channel x error interrupt enable register */
3541 /*! @{ */
3542 
3543 #define GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U)
3544 #define GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U)
3545 #define GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U)
3546 #define GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_MCS_EIRQ_EN_MASK)
3547 
3548 #define GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U)
3549 #define GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U)
3550 #define GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U)
3551 #define GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH0_EIRQ_EN_ERR_EIRQ_EN_MASK)
3552 /*! @} */
3553 
3554 /*! @name MCS3_CH1_R0 - MCS[i] channel x general purpose register [y] */
3555 /*! @{ */
3556 
3557 #define GTM_gtm_cls3_MCS3_CH1_R0_DATA_MASK       (0xFFFFFFU)
3558 #define GTM_gtm_cls3_MCS3_CH1_R0_DATA_SHIFT      (0U)
3559 #define GTM_gtm_cls3_MCS3_CH1_R0_DATA_WIDTH      (24U)
3560 #define GTM_gtm_cls3_MCS3_CH1_R0_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_R0_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_R0_DATA_MASK)
3561 /*! @} */
3562 
3563 /*! @name MCS3_CH1_R1 - MCS[i] channel x general purpose register [y] */
3564 /*! @{ */
3565 
3566 #define GTM_gtm_cls3_MCS3_CH1_R1_DATA_MASK       (0xFFFFFFU)
3567 #define GTM_gtm_cls3_MCS3_CH1_R1_DATA_SHIFT      (0U)
3568 #define GTM_gtm_cls3_MCS3_CH1_R1_DATA_WIDTH      (24U)
3569 #define GTM_gtm_cls3_MCS3_CH1_R1_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_R1_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_R1_DATA_MASK)
3570 /*! @} */
3571 
3572 /*! @name MCS3_CH1_R2 - MCS[i] channel x general purpose register [y] */
3573 /*! @{ */
3574 
3575 #define GTM_gtm_cls3_MCS3_CH1_R2_DATA_MASK       (0xFFFFFFU)
3576 #define GTM_gtm_cls3_MCS3_CH1_R2_DATA_SHIFT      (0U)
3577 #define GTM_gtm_cls3_MCS3_CH1_R2_DATA_WIDTH      (24U)
3578 #define GTM_gtm_cls3_MCS3_CH1_R2_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_R2_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_R2_DATA_MASK)
3579 /*! @} */
3580 
3581 /*! @name MCS3_CH1_R3 - MCS[i] channel x general purpose register [y] */
3582 /*! @{ */
3583 
3584 #define GTM_gtm_cls3_MCS3_CH1_R3_DATA_MASK       (0xFFFFFFU)
3585 #define GTM_gtm_cls3_MCS3_CH1_R3_DATA_SHIFT      (0U)
3586 #define GTM_gtm_cls3_MCS3_CH1_R3_DATA_WIDTH      (24U)
3587 #define GTM_gtm_cls3_MCS3_CH1_R3_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_R3_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_R3_DATA_MASK)
3588 /*! @} */
3589 
3590 /*! @name MCS3_CH1_R4 - MCS[i] channel x general purpose register [y] */
3591 /*! @{ */
3592 
3593 #define GTM_gtm_cls3_MCS3_CH1_R4_DATA_MASK       (0xFFFFFFU)
3594 #define GTM_gtm_cls3_MCS3_CH1_R4_DATA_SHIFT      (0U)
3595 #define GTM_gtm_cls3_MCS3_CH1_R4_DATA_WIDTH      (24U)
3596 #define GTM_gtm_cls3_MCS3_CH1_R4_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_R4_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_R4_DATA_MASK)
3597 /*! @} */
3598 
3599 /*! @name MCS3_CH1_R5 - MCS[i] channel x general purpose register [y] */
3600 /*! @{ */
3601 
3602 #define GTM_gtm_cls3_MCS3_CH1_R5_DATA_MASK       (0xFFFFFFU)
3603 #define GTM_gtm_cls3_MCS3_CH1_R5_DATA_SHIFT      (0U)
3604 #define GTM_gtm_cls3_MCS3_CH1_R5_DATA_WIDTH      (24U)
3605 #define GTM_gtm_cls3_MCS3_CH1_R5_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_R5_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_R5_DATA_MASK)
3606 /*! @} */
3607 
3608 /*! @name MCS3_CH1_R6 - MCS[i] channel x general purpose register [y] */
3609 /*! @{ */
3610 
3611 #define GTM_gtm_cls3_MCS3_CH1_R6_DATA_MASK       (0xFFFFFFU)
3612 #define GTM_gtm_cls3_MCS3_CH1_R6_DATA_SHIFT      (0U)
3613 #define GTM_gtm_cls3_MCS3_CH1_R6_DATA_WIDTH      (24U)
3614 #define GTM_gtm_cls3_MCS3_CH1_R6_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_R6_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_R6_DATA_MASK)
3615 /*! @} */
3616 
3617 /*! @name MCS3_CH1_R7 - MCS[i] channel x general purpose register [y] */
3618 /*! @{ */
3619 
3620 #define GTM_gtm_cls3_MCS3_CH1_R7_DATA_MASK       (0xFFFFFFU)
3621 #define GTM_gtm_cls3_MCS3_CH1_R7_DATA_SHIFT      (0U)
3622 #define GTM_gtm_cls3_MCS3_CH1_R7_DATA_WIDTH      (24U)
3623 #define GTM_gtm_cls3_MCS3_CH1_R7_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_R7_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_R7_DATA_MASK)
3624 /*! @} */
3625 
3626 /*! @name MCS3_CH1_CTRL - MCS[i] channel x control register */
3627 /*! @{ */
3628 
3629 #define GTM_gtm_cls3_MCS3_CH1_CTRL_EN_MASK       (0x1U)
3630 #define GTM_gtm_cls3_MCS3_CH1_CTRL_EN_SHIFT      (0U)
3631 #define GTM_gtm_cls3_MCS3_CH1_CTRL_EN_WIDTH      (1U)
3632 #define GTM_gtm_cls3_MCS3_CH1_CTRL_EN(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_CTRL_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_CTRL_EN_MASK)
3633 
3634 #define GTM_gtm_cls3_MCS3_CH1_CTRL_IRQ_MASK      (0x2U)
3635 #define GTM_gtm_cls3_MCS3_CH1_CTRL_IRQ_SHIFT     (1U)
3636 #define GTM_gtm_cls3_MCS3_CH1_CTRL_IRQ_WIDTH     (1U)
3637 #define GTM_gtm_cls3_MCS3_CH1_CTRL_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_CTRL_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_CTRL_IRQ_MASK)
3638 
3639 #define GTM_gtm_cls3_MCS3_CH1_CTRL_ERR_MASK      (0x4U)
3640 #define GTM_gtm_cls3_MCS3_CH1_CTRL_ERR_SHIFT     (2U)
3641 #define GTM_gtm_cls3_MCS3_CH1_CTRL_ERR_WIDTH     (1U)
3642 #define GTM_gtm_cls3_MCS3_CH1_CTRL_ERR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_CTRL_ERR_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_CTRL_ERR_MASK)
3643 
3644 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CY_MASK       (0x10U)
3645 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CY_SHIFT      (4U)
3646 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CY_WIDTH      (1U)
3647 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CY(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_CTRL_CY_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_CTRL_CY_MASK)
3648 
3649 #define GTM_gtm_cls3_MCS3_CH1_CTRL_Z_MASK        (0x20U)
3650 #define GTM_gtm_cls3_MCS3_CH1_CTRL_Z_SHIFT       (5U)
3651 #define GTM_gtm_cls3_MCS3_CH1_CTRL_Z_WIDTH       (1U)
3652 #define GTM_gtm_cls3_MCS3_CH1_CTRL_Z(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_CTRL_Z_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_CTRL_Z_MASK)
3653 
3654 #define GTM_gtm_cls3_MCS3_CH1_CTRL_V_MASK        (0x40U)
3655 #define GTM_gtm_cls3_MCS3_CH1_CTRL_V_SHIFT       (6U)
3656 #define GTM_gtm_cls3_MCS3_CH1_CTRL_V_WIDTH       (1U)
3657 #define GTM_gtm_cls3_MCS3_CH1_CTRL_V(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_CTRL_V_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_CTRL_V_MASK)
3658 
3659 #define GTM_gtm_cls3_MCS3_CH1_CTRL_N_MASK        (0x80U)
3660 #define GTM_gtm_cls3_MCS3_CH1_CTRL_N_SHIFT       (7U)
3661 #define GTM_gtm_cls3_MCS3_CH1_CTRL_N_WIDTH       (1U)
3662 #define GTM_gtm_cls3_MCS3_CH1_CTRL_N(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_CTRL_N_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_CTRL_N_MASK)
3663 
3664 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CAT_MASK      (0x100U)
3665 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CAT_SHIFT     (8U)
3666 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CAT_WIDTH     (1U)
3667 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_CTRL_CAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_CTRL_CAT_MASK)
3668 
3669 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CWT_MASK      (0x200U)
3670 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CWT_SHIFT     (9U)
3671 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CWT_WIDTH     (1U)
3672 #define GTM_gtm_cls3_MCS3_CH1_CTRL_CWT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_CTRL_CWT_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_CTRL_CWT_MASK)
3673 
3674 #define GTM_gtm_cls3_MCS3_CH1_CTRL_SAT_MASK      (0x400U)
3675 #define GTM_gtm_cls3_MCS3_CH1_CTRL_SAT_SHIFT     (10U)
3676 #define GTM_gtm_cls3_MCS3_CH1_CTRL_SAT_WIDTH     (1U)
3677 #define GTM_gtm_cls3_MCS3_CH1_CTRL_SAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_CTRL_SAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_CTRL_SAT_MASK)
3678 /*! @} */
3679 
3680 /*! @name MCS3_CH1_ACB - MCS[i] channel x ARU control Bit register */
3681 /*! @{ */
3682 
3683 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB0_MASK      (0x1U)
3684 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB0_SHIFT     (0U)
3685 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB0_WIDTH     (1U)
3686 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_ACB_ACB0_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_ACB_ACB0_MASK)
3687 
3688 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB1_MASK      (0x2U)
3689 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB1_SHIFT     (1U)
3690 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB1_WIDTH     (1U)
3691 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_ACB_ACB1_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_ACB_ACB1_MASK)
3692 
3693 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB2_MASK      (0x4U)
3694 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB2_SHIFT     (2U)
3695 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB2_WIDTH     (1U)
3696 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB2(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_ACB_ACB2_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_ACB_ACB2_MASK)
3697 
3698 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB3_MASK      (0x8U)
3699 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB3_SHIFT     (3U)
3700 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB3_WIDTH     (1U)
3701 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB3(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_ACB_ACB3_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_ACB_ACB3_MASK)
3702 
3703 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB4_MASK      (0x10U)
3704 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB4_SHIFT     (4U)
3705 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB4_WIDTH     (1U)
3706 #define GTM_gtm_cls3_MCS3_CH1_ACB_ACB4(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_ACB_ACB4_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_ACB_ACB4_MASK)
3707 /*! @} */
3708 
3709 /*! @name MCS3_CH1_MHB - MCS[i] channel x memory high byte register */
3710 /*! @{ */
3711 
3712 #define GTM_gtm_cls3_MCS3_CH1_MHB_DATA_MASK      (0xFFU)
3713 #define GTM_gtm_cls3_MCS3_CH1_MHB_DATA_SHIFT     (0U)
3714 #define GTM_gtm_cls3_MCS3_CH1_MHB_DATA_WIDTH     (8U)
3715 #define GTM_gtm_cls3_MCS3_CH1_MHB_DATA(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_MHB_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_MHB_DATA_MASK)
3716 /*! @} */
3717 
3718 /*! @name MCS3_CH1_PC - MCS[i] channel x program counter register */
3719 /*! @{ */
3720 
3721 #define GTM_gtm_cls3_MCS3_CH1_PC_PC_MASK         (0xFFFFU)
3722 #define GTM_gtm_cls3_MCS3_CH1_PC_PC_SHIFT        (0U)
3723 #define GTM_gtm_cls3_MCS3_CH1_PC_PC_WIDTH        (16U)
3724 #define GTM_gtm_cls3_MCS3_CH1_PC_PC(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_PC_PC_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_PC_PC_MASK)
3725 /*! @} */
3726 
3727 /*! @name MCS3_CH1_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */
3728 /*! @{ */
3729 
3730 #define GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U)
3731 #define GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U)
3732 #define GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U)
3733 #define GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_MCS_IRQ_MASK)
3734 
3735 #define GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U)
3736 #define GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U)
3737 #define GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U)
3738 #define GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_IRQ_NOTIFY_ERR_IRQ_MASK)
3739 /*! @} */
3740 
3741 /*! @name MCS3_CH1_IRQ_EN - MCS[i] channel x interrupt enable register */
3742 /*! @{ */
3743 
3744 #define GTM_gtm_cls3_MCS3_CH1_IRQ_EN_MCS_IRQ_EN_MASK (0x1U)
3745 #define GTM_gtm_cls3_MCS3_CH1_IRQ_EN_MCS_IRQ_EN_SHIFT (0U)
3746 #define GTM_gtm_cls3_MCS3_CH1_IRQ_EN_MCS_IRQ_EN_WIDTH (1U)
3747 #define GTM_gtm_cls3_MCS3_CH1_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_IRQ_EN_MCS_IRQ_EN_MASK)
3748 
3749 #define GTM_gtm_cls3_MCS3_CH1_IRQ_EN_ERR_IRQ_EN_MASK (0x4U)
3750 #define GTM_gtm_cls3_MCS3_CH1_IRQ_EN_ERR_IRQ_EN_SHIFT (2U)
3751 #define GTM_gtm_cls3_MCS3_CH1_IRQ_EN_ERR_IRQ_EN_WIDTH (1U)
3752 #define GTM_gtm_cls3_MCS3_CH1_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_IRQ_EN_ERR_IRQ_EN_MASK)
3753 /*! @} */
3754 
3755 /*! @name MCS3_CH1_IRQ_FORCINT - MCS[i] channel x force interrupt register */
3756 /*! @{ */
3757 
3758 #define GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U)
3759 #define GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U)
3760 #define GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U)
3761 #define GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_MCS_IRQ_MASK)
3762 
3763 #define GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U)
3764 #define GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U)
3765 #define GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U)
3766 #define GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_IRQ_FORCINT_TRG_ERR_IRQ_MASK)
3767 /*! @} */
3768 
3769 /*! @name MCS3_CH1_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */
3770 /*! @{ */
3771 
3772 #define GTM_gtm_cls3_MCS3_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U)
3773 #define GTM_gtm_cls3_MCS3_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U)
3774 #define GTM_gtm_cls3_MCS3_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U)
3775 #define GTM_gtm_cls3_MCS3_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_IRQ_MODE_IRQ_MODE_MASK)
3776 /*! @} */
3777 
3778 /*! @name MCS3_CH1_EIRQ_EN - MCS[i] channel x error interrupt enable register */
3779 /*! @{ */
3780 
3781 #define GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U)
3782 #define GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U)
3783 #define GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U)
3784 #define GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_MCS_EIRQ_EN_MASK)
3785 
3786 #define GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U)
3787 #define GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U)
3788 #define GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U)
3789 #define GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH1_EIRQ_EN_ERR_EIRQ_EN_MASK)
3790 /*! @} */
3791 
3792 /*! @name MCS3_CH2_R0 - MCS[i] channel x general purpose register [y] */
3793 /*! @{ */
3794 
3795 #define GTM_gtm_cls3_MCS3_CH2_R0_DATA_MASK       (0xFFFFFFU)
3796 #define GTM_gtm_cls3_MCS3_CH2_R0_DATA_SHIFT      (0U)
3797 #define GTM_gtm_cls3_MCS3_CH2_R0_DATA_WIDTH      (24U)
3798 #define GTM_gtm_cls3_MCS3_CH2_R0_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_R0_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_R0_DATA_MASK)
3799 /*! @} */
3800 
3801 /*! @name MCS3_CH2_R1 - MCS[i] channel x general purpose register [y] */
3802 /*! @{ */
3803 
3804 #define GTM_gtm_cls3_MCS3_CH2_R1_DATA_MASK       (0xFFFFFFU)
3805 #define GTM_gtm_cls3_MCS3_CH2_R1_DATA_SHIFT      (0U)
3806 #define GTM_gtm_cls3_MCS3_CH2_R1_DATA_WIDTH      (24U)
3807 #define GTM_gtm_cls3_MCS3_CH2_R1_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_R1_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_R1_DATA_MASK)
3808 /*! @} */
3809 
3810 /*! @name MCS3_CH2_R2 - MCS[i] channel x general purpose register [y] */
3811 /*! @{ */
3812 
3813 #define GTM_gtm_cls3_MCS3_CH2_R2_DATA_MASK       (0xFFFFFFU)
3814 #define GTM_gtm_cls3_MCS3_CH2_R2_DATA_SHIFT      (0U)
3815 #define GTM_gtm_cls3_MCS3_CH2_R2_DATA_WIDTH      (24U)
3816 #define GTM_gtm_cls3_MCS3_CH2_R2_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_R2_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_R2_DATA_MASK)
3817 /*! @} */
3818 
3819 /*! @name MCS3_CH2_R3 - MCS[i] channel x general purpose register [y] */
3820 /*! @{ */
3821 
3822 #define GTM_gtm_cls3_MCS3_CH2_R3_DATA_MASK       (0xFFFFFFU)
3823 #define GTM_gtm_cls3_MCS3_CH2_R3_DATA_SHIFT      (0U)
3824 #define GTM_gtm_cls3_MCS3_CH2_R3_DATA_WIDTH      (24U)
3825 #define GTM_gtm_cls3_MCS3_CH2_R3_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_R3_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_R3_DATA_MASK)
3826 /*! @} */
3827 
3828 /*! @name MCS3_CH2_R4 - MCS[i] channel x general purpose register [y] */
3829 /*! @{ */
3830 
3831 #define GTM_gtm_cls3_MCS3_CH2_R4_DATA_MASK       (0xFFFFFFU)
3832 #define GTM_gtm_cls3_MCS3_CH2_R4_DATA_SHIFT      (0U)
3833 #define GTM_gtm_cls3_MCS3_CH2_R4_DATA_WIDTH      (24U)
3834 #define GTM_gtm_cls3_MCS3_CH2_R4_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_R4_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_R4_DATA_MASK)
3835 /*! @} */
3836 
3837 /*! @name MCS3_CH2_R5 - MCS[i] channel x general purpose register [y] */
3838 /*! @{ */
3839 
3840 #define GTM_gtm_cls3_MCS3_CH2_R5_DATA_MASK       (0xFFFFFFU)
3841 #define GTM_gtm_cls3_MCS3_CH2_R5_DATA_SHIFT      (0U)
3842 #define GTM_gtm_cls3_MCS3_CH2_R5_DATA_WIDTH      (24U)
3843 #define GTM_gtm_cls3_MCS3_CH2_R5_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_R5_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_R5_DATA_MASK)
3844 /*! @} */
3845 
3846 /*! @name MCS3_CH2_R6 - MCS[i] channel x general purpose register [y] */
3847 /*! @{ */
3848 
3849 #define GTM_gtm_cls3_MCS3_CH2_R6_DATA_MASK       (0xFFFFFFU)
3850 #define GTM_gtm_cls3_MCS3_CH2_R6_DATA_SHIFT      (0U)
3851 #define GTM_gtm_cls3_MCS3_CH2_R6_DATA_WIDTH      (24U)
3852 #define GTM_gtm_cls3_MCS3_CH2_R6_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_R6_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_R6_DATA_MASK)
3853 /*! @} */
3854 
3855 /*! @name MCS3_CH2_R7 - MCS[i] channel x general purpose register [y] */
3856 /*! @{ */
3857 
3858 #define GTM_gtm_cls3_MCS3_CH2_R7_DATA_MASK       (0xFFFFFFU)
3859 #define GTM_gtm_cls3_MCS3_CH2_R7_DATA_SHIFT      (0U)
3860 #define GTM_gtm_cls3_MCS3_CH2_R7_DATA_WIDTH      (24U)
3861 #define GTM_gtm_cls3_MCS3_CH2_R7_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_R7_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_R7_DATA_MASK)
3862 /*! @} */
3863 
3864 /*! @name MCS3_CH2_CTRL - MCS[i] channel x control register */
3865 /*! @{ */
3866 
3867 #define GTM_gtm_cls3_MCS3_CH2_CTRL_EN_MASK       (0x1U)
3868 #define GTM_gtm_cls3_MCS3_CH2_CTRL_EN_SHIFT      (0U)
3869 #define GTM_gtm_cls3_MCS3_CH2_CTRL_EN_WIDTH      (1U)
3870 #define GTM_gtm_cls3_MCS3_CH2_CTRL_EN(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_CTRL_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_CTRL_EN_MASK)
3871 
3872 #define GTM_gtm_cls3_MCS3_CH2_CTRL_IRQ_MASK      (0x2U)
3873 #define GTM_gtm_cls3_MCS3_CH2_CTRL_IRQ_SHIFT     (1U)
3874 #define GTM_gtm_cls3_MCS3_CH2_CTRL_IRQ_WIDTH     (1U)
3875 #define GTM_gtm_cls3_MCS3_CH2_CTRL_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_CTRL_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_CTRL_IRQ_MASK)
3876 
3877 #define GTM_gtm_cls3_MCS3_CH2_CTRL_ERR_MASK      (0x4U)
3878 #define GTM_gtm_cls3_MCS3_CH2_CTRL_ERR_SHIFT     (2U)
3879 #define GTM_gtm_cls3_MCS3_CH2_CTRL_ERR_WIDTH     (1U)
3880 #define GTM_gtm_cls3_MCS3_CH2_CTRL_ERR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_CTRL_ERR_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_CTRL_ERR_MASK)
3881 
3882 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CY_MASK       (0x10U)
3883 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CY_SHIFT      (4U)
3884 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CY_WIDTH      (1U)
3885 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CY(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_CTRL_CY_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_CTRL_CY_MASK)
3886 
3887 #define GTM_gtm_cls3_MCS3_CH2_CTRL_Z_MASK        (0x20U)
3888 #define GTM_gtm_cls3_MCS3_CH2_CTRL_Z_SHIFT       (5U)
3889 #define GTM_gtm_cls3_MCS3_CH2_CTRL_Z_WIDTH       (1U)
3890 #define GTM_gtm_cls3_MCS3_CH2_CTRL_Z(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_CTRL_Z_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_CTRL_Z_MASK)
3891 
3892 #define GTM_gtm_cls3_MCS3_CH2_CTRL_V_MASK        (0x40U)
3893 #define GTM_gtm_cls3_MCS3_CH2_CTRL_V_SHIFT       (6U)
3894 #define GTM_gtm_cls3_MCS3_CH2_CTRL_V_WIDTH       (1U)
3895 #define GTM_gtm_cls3_MCS3_CH2_CTRL_V(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_CTRL_V_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_CTRL_V_MASK)
3896 
3897 #define GTM_gtm_cls3_MCS3_CH2_CTRL_N_MASK        (0x80U)
3898 #define GTM_gtm_cls3_MCS3_CH2_CTRL_N_SHIFT       (7U)
3899 #define GTM_gtm_cls3_MCS3_CH2_CTRL_N_WIDTH       (1U)
3900 #define GTM_gtm_cls3_MCS3_CH2_CTRL_N(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_CTRL_N_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_CTRL_N_MASK)
3901 
3902 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CAT_MASK      (0x100U)
3903 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CAT_SHIFT     (8U)
3904 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CAT_WIDTH     (1U)
3905 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_CTRL_CAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_CTRL_CAT_MASK)
3906 
3907 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CWT_MASK      (0x200U)
3908 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CWT_SHIFT     (9U)
3909 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CWT_WIDTH     (1U)
3910 #define GTM_gtm_cls3_MCS3_CH2_CTRL_CWT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_CTRL_CWT_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_CTRL_CWT_MASK)
3911 
3912 #define GTM_gtm_cls3_MCS3_CH2_CTRL_SAT_MASK      (0x400U)
3913 #define GTM_gtm_cls3_MCS3_CH2_CTRL_SAT_SHIFT     (10U)
3914 #define GTM_gtm_cls3_MCS3_CH2_CTRL_SAT_WIDTH     (1U)
3915 #define GTM_gtm_cls3_MCS3_CH2_CTRL_SAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_CTRL_SAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_CTRL_SAT_MASK)
3916 /*! @} */
3917 
3918 /*! @name MCS3_CH2_ACB - MCS[i] channel x ARU control Bit register */
3919 /*! @{ */
3920 
3921 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB0_MASK      (0x1U)
3922 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB0_SHIFT     (0U)
3923 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB0_WIDTH     (1U)
3924 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_ACB_ACB0_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_ACB_ACB0_MASK)
3925 
3926 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB1_MASK      (0x2U)
3927 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB1_SHIFT     (1U)
3928 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB1_WIDTH     (1U)
3929 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_ACB_ACB1_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_ACB_ACB1_MASK)
3930 
3931 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB2_MASK      (0x4U)
3932 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB2_SHIFT     (2U)
3933 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB2_WIDTH     (1U)
3934 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB2(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_ACB_ACB2_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_ACB_ACB2_MASK)
3935 
3936 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB3_MASK      (0x8U)
3937 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB3_SHIFT     (3U)
3938 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB3_WIDTH     (1U)
3939 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB3(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_ACB_ACB3_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_ACB_ACB3_MASK)
3940 
3941 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB4_MASK      (0x10U)
3942 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB4_SHIFT     (4U)
3943 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB4_WIDTH     (1U)
3944 #define GTM_gtm_cls3_MCS3_CH2_ACB_ACB4(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_ACB_ACB4_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_ACB_ACB4_MASK)
3945 /*! @} */
3946 
3947 /*! @name MCS3_CH2_MHB - MCS[i] channel x memory high byte register */
3948 /*! @{ */
3949 
3950 #define GTM_gtm_cls3_MCS3_CH2_MHB_DATA_MASK      (0xFFU)
3951 #define GTM_gtm_cls3_MCS3_CH2_MHB_DATA_SHIFT     (0U)
3952 #define GTM_gtm_cls3_MCS3_CH2_MHB_DATA_WIDTH     (8U)
3953 #define GTM_gtm_cls3_MCS3_CH2_MHB_DATA(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_MHB_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_MHB_DATA_MASK)
3954 /*! @} */
3955 
3956 /*! @name MCS3_CH2_PC - MCS[i] channel x program counter register */
3957 /*! @{ */
3958 
3959 #define GTM_gtm_cls3_MCS3_CH2_PC_PC_MASK         (0xFFFFU)
3960 #define GTM_gtm_cls3_MCS3_CH2_PC_PC_SHIFT        (0U)
3961 #define GTM_gtm_cls3_MCS3_CH2_PC_PC_WIDTH        (16U)
3962 #define GTM_gtm_cls3_MCS3_CH2_PC_PC(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_PC_PC_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_PC_PC_MASK)
3963 /*! @} */
3964 
3965 /*! @name MCS3_CH2_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */
3966 /*! @{ */
3967 
3968 #define GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U)
3969 #define GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U)
3970 #define GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U)
3971 #define GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_MCS_IRQ_MASK)
3972 
3973 #define GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U)
3974 #define GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U)
3975 #define GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U)
3976 #define GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_IRQ_NOTIFY_ERR_IRQ_MASK)
3977 /*! @} */
3978 
3979 /*! @name MCS3_CH2_IRQ_EN - MCS[i] channel x interrupt enable register */
3980 /*! @{ */
3981 
3982 #define GTM_gtm_cls3_MCS3_CH2_IRQ_EN_MCS_IRQ_EN_MASK (0x1U)
3983 #define GTM_gtm_cls3_MCS3_CH2_IRQ_EN_MCS_IRQ_EN_SHIFT (0U)
3984 #define GTM_gtm_cls3_MCS3_CH2_IRQ_EN_MCS_IRQ_EN_WIDTH (1U)
3985 #define GTM_gtm_cls3_MCS3_CH2_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_IRQ_EN_MCS_IRQ_EN_MASK)
3986 
3987 #define GTM_gtm_cls3_MCS3_CH2_IRQ_EN_ERR_IRQ_EN_MASK (0x4U)
3988 #define GTM_gtm_cls3_MCS3_CH2_IRQ_EN_ERR_IRQ_EN_SHIFT (2U)
3989 #define GTM_gtm_cls3_MCS3_CH2_IRQ_EN_ERR_IRQ_EN_WIDTH (1U)
3990 #define GTM_gtm_cls3_MCS3_CH2_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_IRQ_EN_ERR_IRQ_EN_MASK)
3991 /*! @} */
3992 
3993 /*! @name MCS3_CH2_IRQ_FORCINT - MCS[i] channel x force interrupt register */
3994 /*! @{ */
3995 
3996 #define GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U)
3997 #define GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U)
3998 #define GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U)
3999 #define GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_MCS_IRQ_MASK)
4000 
4001 #define GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U)
4002 #define GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U)
4003 #define GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U)
4004 #define GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_IRQ_FORCINT_TRG_ERR_IRQ_MASK)
4005 /*! @} */
4006 
4007 /*! @name MCS3_CH2_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */
4008 /*! @{ */
4009 
4010 #define GTM_gtm_cls3_MCS3_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U)
4011 #define GTM_gtm_cls3_MCS3_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U)
4012 #define GTM_gtm_cls3_MCS3_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U)
4013 #define GTM_gtm_cls3_MCS3_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_IRQ_MODE_IRQ_MODE_MASK)
4014 /*! @} */
4015 
4016 /*! @name MCS3_CH2_EIRQ_EN - MCS[i] channel x error interrupt enable register */
4017 /*! @{ */
4018 
4019 #define GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U)
4020 #define GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U)
4021 #define GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U)
4022 #define GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_MCS_EIRQ_EN_MASK)
4023 
4024 #define GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U)
4025 #define GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U)
4026 #define GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U)
4027 #define GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH2_EIRQ_EN_ERR_EIRQ_EN_MASK)
4028 /*! @} */
4029 
4030 /*! @name MCS3_CH3_R0 - MCS[i] channel x general purpose register [y] */
4031 /*! @{ */
4032 
4033 #define GTM_gtm_cls3_MCS3_CH3_R0_DATA_MASK       (0xFFFFFFU)
4034 #define GTM_gtm_cls3_MCS3_CH3_R0_DATA_SHIFT      (0U)
4035 #define GTM_gtm_cls3_MCS3_CH3_R0_DATA_WIDTH      (24U)
4036 #define GTM_gtm_cls3_MCS3_CH3_R0_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_R0_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_R0_DATA_MASK)
4037 /*! @} */
4038 
4039 /*! @name MCS3_CH3_R1 - MCS[i] channel x general purpose register [y] */
4040 /*! @{ */
4041 
4042 #define GTM_gtm_cls3_MCS3_CH3_R1_DATA_MASK       (0xFFFFFFU)
4043 #define GTM_gtm_cls3_MCS3_CH3_R1_DATA_SHIFT      (0U)
4044 #define GTM_gtm_cls3_MCS3_CH3_R1_DATA_WIDTH      (24U)
4045 #define GTM_gtm_cls3_MCS3_CH3_R1_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_R1_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_R1_DATA_MASK)
4046 /*! @} */
4047 
4048 /*! @name MCS3_CH3_R2 - MCS[i] channel x general purpose register [y] */
4049 /*! @{ */
4050 
4051 #define GTM_gtm_cls3_MCS3_CH3_R2_DATA_MASK       (0xFFFFFFU)
4052 #define GTM_gtm_cls3_MCS3_CH3_R2_DATA_SHIFT      (0U)
4053 #define GTM_gtm_cls3_MCS3_CH3_R2_DATA_WIDTH      (24U)
4054 #define GTM_gtm_cls3_MCS3_CH3_R2_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_R2_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_R2_DATA_MASK)
4055 /*! @} */
4056 
4057 /*! @name MCS3_CH3_R3 - MCS[i] channel x general purpose register [y] */
4058 /*! @{ */
4059 
4060 #define GTM_gtm_cls3_MCS3_CH3_R3_DATA_MASK       (0xFFFFFFU)
4061 #define GTM_gtm_cls3_MCS3_CH3_R3_DATA_SHIFT      (0U)
4062 #define GTM_gtm_cls3_MCS3_CH3_R3_DATA_WIDTH      (24U)
4063 #define GTM_gtm_cls3_MCS3_CH3_R3_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_R3_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_R3_DATA_MASK)
4064 /*! @} */
4065 
4066 /*! @name MCS3_CH3_R4 - MCS[i] channel x general purpose register [y] */
4067 /*! @{ */
4068 
4069 #define GTM_gtm_cls3_MCS3_CH3_R4_DATA_MASK       (0xFFFFFFU)
4070 #define GTM_gtm_cls3_MCS3_CH3_R4_DATA_SHIFT      (0U)
4071 #define GTM_gtm_cls3_MCS3_CH3_R4_DATA_WIDTH      (24U)
4072 #define GTM_gtm_cls3_MCS3_CH3_R4_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_R4_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_R4_DATA_MASK)
4073 /*! @} */
4074 
4075 /*! @name MCS3_CH3_R5 - MCS[i] channel x general purpose register [y] */
4076 /*! @{ */
4077 
4078 #define GTM_gtm_cls3_MCS3_CH3_R5_DATA_MASK       (0xFFFFFFU)
4079 #define GTM_gtm_cls3_MCS3_CH3_R5_DATA_SHIFT      (0U)
4080 #define GTM_gtm_cls3_MCS3_CH3_R5_DATA_WIDTH      (24U)
4081 #define GTM_gtm_cls3_MCS3_CH3_R5_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_R5_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_R5_DATA_MASK)
4082 /*! @} */
4083 
4084 /*! @name MCS3_CH3_R6 - MCS[i] channel x general purpose register [y] */
4085 /*! @{ */
4086 
4087 #define GTM_gtm_cls3_MCS3_CH3_R6_DATA_MASK       (0xFFFFFFU)
4088 #define GTM_gtm_cls3_MCS3_CH3_R6_DATA_SHIFT      (0U)
4089 #define GTM_gtm_cls3_MCS3_CH3_R6_DATA_WIDTH      (24U)
4090 #define GTM_gtm_cls3_MCS3_CH3_R6_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_R6_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_R6_DATA_MASK)
4091 /*! @} */
4092 
4093 /*! @name MCS3_CH3_R7 - MCS[i] channel x general purpose register [y] */
4094 /*! @{ */
4095 
4096 #define GTM_gtm_cls3_MCS3_CH3_R7_DATA_MASK       (0xFFFFFFU)
4097 #define GTM_gtm_cls3_MCS3_CH3_R7_DATA_SHIFT      (0U)
4098 #define GTM_gtm_cls3_MCS3_CH3_R7_DATA_WIDTH      (24U)
4099 #define GTM_gtm_cls3_MCS3_CH3_R7_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_R7_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_R7_DATA_MASK)
4100 /*! @} */
4101 
4102 /*! @name MCS3_CH3_CTRL - MCS[i] channel x control register */
4103 /*! @{ */
4104 
4105 #define GTM_gtm_cls3_MCS3_CH3_CTRL_EN_MASK       (0x1U)
4106 #define GTM_gtm_cls3_MCS3_CH3_CTRL_EN_SHIFT      (0U)
4107 #define GTM_gtm_cls3_MCS3_CH3_CTRL_EN_WIDTH      (1U)
4108 #define GTM_gtm_cls3_MCS3_CH3_CTRL_EN(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_CTRL_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_CTRL_EN_MASK)
4109 
4110 #define GTM_gtm_cls3_MCS3_CH3_CTRL_IRQ_MASK      (0x2U)
4111 #define GTM_gtm_cls3_MCS3_CH3_CTRL_IRQ_SHIFT     (1U)
4112 #define GTM_gtm_cls3_MCS3_CH3_CTRL_IRQ_WIDTH     (1U)
4113 #define GTM_gtm_cls3_MCS3_CH3_CTRL_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_CTRL_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_CTRL_IRQ_MASK)
4114 
4115 #define GTM_gtm_cls3_MCS3_CH3_CTRL_ERR_MASK      (0x4U)
4116 #define GTM_gtm_cls3_MCS3_CH3_CTRL_ERR_SHIFT     (2U)
4117 #define GTM_gtm_cls3_MCS3_CH3_CTRL_ERR_WIDTH     (1U)
4118 #define GTM_gtm_cls3_MCS3_CH3_CTRL_ERR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_CTRL_ERR_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_CTRL_ERR_MASK)
4119 
4120 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CY_MASK       (0x10U)
4121 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CY_SHIFT      (4U)
4122 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CY_WIDTH      (1U)
4123 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CY(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_CTRL_CY_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_CTRL_CY_MASK)
4124 
4125 #define GTM_gtm_cls3_MCS3_CH3_CTRL_Z_MASK        (0x20U)
4126 #define GTM_gtm_cls3_MCS3_CH3_CTRL_Z_SHIFT       (5U)
4127 #define GTM_gtm_cls3_MCS3_CH3_CTRL_Z_WIDTH       (1U)
4128 #define GTM_gtm_cls3_MCS3_CH3_CTRL_Z(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_CTRL_Z_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_CTRL_Z_MASK)
4129 
4130 #define GTM_gtm_cls3_MCS3_CH3_CTRL_V_MASK        (0x40U)
4131 #define GTM_gtm_cls3_MCS3_CH3_CTRL_V_SHIFT       (6U)
4132 #define GTM_gtm_cls3_MCS3_CH3_CTRL_V_WIDTH       (1U)
4133 #define GTM_gtm_cls3_MCS3_CH3_CTRL_V(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_CTRL_V_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_CTRL_V_MASK)
4134 
4135 #define GTM_gtm_cls3_MCS3_CH3_CTRL_N_MASK        (0x80U)
4136 #define GTM_gtm_cls3_MCS3_CH3_CTRL_N_SHIFT       (7U)
4137 #define GTM_gtm_cls3_MCS3_CH3_CTRL_N_WIDTH       (1U)
4138 #define GTM_gtm_cls3_MCS3_CH3_CTRL_N(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_CTRL_N_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_CTRL_N_MASK)
4139 
4140 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CAT_MASK      (0x100U)
4141 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CAT_SHIFT     (8U)
4142 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CAT_WIDTH     (1U)
4143 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_CTRL_CAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_CTRL_CAT_MASK)
4144 
4145 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CWT_MASK      (0x200U)
4146 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CWT_SHIFT     (9U)
4147 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CWT_WIDTH     (1U)
4148 #define GTM_gtm_cls3_MCS3_CH3_CTRL_CWT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_CTRL_CWT_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_CTRL_CWT_MASK)
4149 
4150 #define GTM_gtm_cls3_MCS3_CH3_CTRL_SAT_MASK      (0x400U)
4151 #define GTM_gtm_cls3_MCS3_CH3_CTRL_SAT_SHIFT     (10U)
4152 #define GTM_gtm_cls3_MCS3_CH3_CTRL_SAT_WIDTH     (1U)
4153 #define GTM_gtm_cls3_MCS3_CH3_CTRL_SAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_CTRL_SAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_CTRL_SAT_MASK)
4154 /*! @} */
4155 
4156 /*! @name MCS3_CH3_ACB - MCS[i] channel x ARU control Bit register */
4157 /*! @{ */
4158 
4159 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB0_MASK      (0x1U)
4160 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB0_SHIFT     (0U)
4161 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB0_WIDTH     (1U)
4162 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_ACB_ACB0_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_ACB_ACB0_MASK)
4163 
4164 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB1_MASK      (0x2U)
4165 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB1_SHIFT     (1U)
4166 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB1_WIDTH     (1U)
4167 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_ACB_ACB1_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_ACB_ACB1_MASK)
4168 
4169 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB2_MASK      (0x4U)
4170 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB2_SHIFT     (2U)
4171 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB2_WIDTH     (1U)
4172 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB2(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_ACB_ACB2_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_ACB_ACB2_MASK)
4173 
4174 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB3_MASK      (0x8U)
4175 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB3_SHIFT     (3U)
4176 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB3_WIDTH     (1U)
4177 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB3(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_ACB_ACB3_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_ACB_ACB3_MASK)
4178 
4179 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB4_MASK      (0x10U)
4180 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB4_SHIFT     (4U)
4181 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB4_WIDTH     (1U)
4182 #define GTM_gtm_cls3_MCS3_CH3_ACB_ACB4(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_ACB_ACB4_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_ACB_ACB4_MASK)
4183 /*! @} */
4184 
4185 /*! @name MCS3_CH3_MHB - MCS[i] channel x memory high byte register */
4186 /*! @{ */
4187 
4188 #define GTM_gtm_cls3_MCS3_CH3_MHB_DATA_MASK      (0xFFU)
4189 #define GTM_gtm_cls3_MCS3_CH3_MHB_DATA_SHIFT     (0U)
4190 #define GTM_gtm_cls3_MCS3_CH3_MHB_DATA_WIDTH     (8U)
4191 #define GTM_gtm_cls3_MCS3_CH3_MHB_DATA(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_MHB_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_MHB_DATA_MASK)
4192 /*! @} */
4193 
4194 /*! @name MCS3_CH3_PC - MCS[i] channel x program counter register */
4195 /*! @{ */
4196 
4197 #define GTM_gtm_cls3_MCS3_CH3_PC_PC_MASK         (0xFFFFU)
4198 #define GTM_gtm_cls3_MCS3_CH3_PC_PC_SHIFT        (0U)
4199 #define GTM_gtm_cls3_MCS3_CH3_PC_PC_WIDTH        (16U)
4200 #define GTM_gtm_cls3_MCS3_CH3_PC_PC(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_PC_PC_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_PC_PC_MASK)
4201 /*! @} */
4202 
4203 /*! @name MCS3_CH3_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */
4204 /*! @{ */
4205 
4206 #define GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U)
4207 #define GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U)
4208 #define GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U)
4209 #define GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_MCS_IRQ_MASK)
4210 
4211 #define GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U)
4212 #define GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U)
4213 #define GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U)
4214 #define GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_IRQ_NOTIFY_ERR_IRQ_MASK)
4215 /*! @} */
4216 
4217 /*! @name MCS3_CH3_IRQ_EN - MCS[i] channel x interrupt enable register */
4218 /*! @{ */
4219 
4220 #define GTM_gtm_cls3_MCS3_CH3_IRQ_EN_MCS_IRQ_EN_MASK (0x1U)
4221 #define GTM_gtm_cls3_MCS3_CH3_IRQ_EN_MCS_IRQ_EN_SHIFT (0U)
4222 #define GTM_gtm_cls3_MCS3_CH3_IRQ_EN_MCS_IRQ_EN_WIDTH (1U)
4223 #define GTM_gtm_cls3_MCS3_CH3_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_IRQ_EN_MCS_IRQ_EN_MASK)
4224 
4225 #define GTM_gtm_cls3_MCS3_CH3_IRQ_EN_ERR_IRQ_EN_MASK (0x4U)
4226 #define GTM_gtm_cls3_MCS3_CH3_IRQ_EN_ERR_IRQ_EN_SHIFT (2U)
4227 #define GTM_gtm_cls3_MCS3_CH3_IRQ_EN_ERR_IRQ_EN_WIDTH (1U)
4228 #define GTM_gtm_cls3_MCS3_CH3_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_IRQ_EN_ERR_IRQ_EN_MASK)
4229 /*! @} */
4230 
4231 /*! @name MCS3_CH3_IRQ_FORCINT - MCS[i] channel x force interrupt register */
4232 /*! @{ */
4233 
4234 #define GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U)
4235 #define GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U)
4236 #define GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U)
4237 #define GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_MCS_IRQ_MASK)
4238 
4239 #define GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U)
4240 #define GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U)
4241 #define GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U)
4242 #define GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_IRQ_FORCINT_TRG_ERR_IRQ_MASK)
4243 /*! @} */
4244 
4245 /*! @name MCS3_CH3_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */
4246 /*! @{ */
4247 
4248 #define GTM_gtm_cls3_MCS3_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U)
4249 #define GTM_gtm_cls3_MCS3_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U)
4250 #define GTM_gtm_cls3_MCS3_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U)
4251 #define GTM_gtm_cls3_MCS3_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_IRQ_MODE_IRQ_MODE_MASK)
4252 /*! @} */
4253 
4254 /*! @name MCS3_CH3_EIRQ_EN - MCS[i] channel x error interrupt enable register */
4255 /*! @{ */
4256 
4257 #define GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U)
4258 #define GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U)
4259 #define GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U)
4260 #define GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_MCS_EIRQ_EN_MASK)
4261 
4262 #define GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U)
4263 #define GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U)
4264 #define GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U)
4265 #define GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH3_EIRQ_EN_ERR_EIRQ_EN_MASK)
4266 /*! @} */
4267 
4268 /*! @name MCS3_CH4_R0 - MCS[i] channel x general purpose register [y] */
4269 /*! @{ */
4270 
4271 #define GTM_gtm_cls3_MCS3_CH4_R0_DATA_MASK       (0xFFFFFFU)
4272 #define GTM_gtm_cls3_MCS3_CH4_R0_DATA_SHIFT      (0U)
4273 #define GTM_gtm_cls3_MCS3_CH4_R0_DATA_WIDTH      (24U)
4274 #define GTM_gtm_cls3_MCS3_CH4_R0_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_R0_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_R0_DATA_MASK)
4275 /*! @} */
4276 
4277 /*! @name MCS3_CH4_R1 - MCS[i] channel x general purpose register [y] */
4278 /*! @{ */
4279 
4280 #define GTM_gtm_cls3_MCS3_CH4_R1_DATA_MASK       (0xFFFFFFU)
4281 #define GTM_gtm_cls3_MCS3_CH4_R1_DATA_SHIFT      (0U)
4282 #define GTM_gtm_cls3_MCS3_CH4_R1_DATA_WIDTH      (24U)
4283 #define GTM_gtm_cls3_MCS3_CH4_R1_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_R1_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_R1_DATA_MASK)
4284 /*! @} */
4285 
4286 /*! @name MCS3_CH4_R2 - MCS[i] channel x general purpose register [y] */
4287 /*! @{ */
4288 
4289 #define GTM_gtm_cls3_MCS3_CH4_R2_DATA_MASK       (0xFFFFFFU)
4290 #define GTM_gtm_cls3_MCS3_CH4_R2_DATA_SHIFT      (0U)
4291 #define GTM_gtm_cls3_MCS3_CH4_R2_DATA_WIDTH      (24U)
4292 #define GTM_gtm_cls3_MCS3_CH4_R2_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_R2_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_R2_DATA_MASK)
4293 /*! @} */
4294 
4295 /*! @name MCS3_CH4_R3 - MCS[i] channel x general purpose register [y] */
4296 /*! @{ */
4297 
4298 #define GTM_gtm_cls3_MCS3_CH4_R3_DATA_MASK       (0xFFFFFFU)
4299 #define GTM_gtm_cls3_MCS3_CH4_R3_DATA_SHIFT      (0U)
4300 #define GTM_gtm_cls3_MCS3_CH4_R3_DATA_WIDTH      (24U)
4301 #define GTM_gtm_cls3_MCS3_CH4_R3_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_R3_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_R3_DATA_MASK)
4302 /*! @} */
4303 
4304 /*! @name MCS3_CH4_R4 - MCS[i] channel x general purpose register [y] */
4305 /*! @{ */
4306 
4307 #define GTM_gtm_cls3_MCS3_CH4_R4_DATA_MASK       (0xFFFFFFU)
4308 #define GTM_gtm_cls3_MCS3_CH4_R4_DATA_SHIFT      (0U)
4309 #define GTM_gtm_cls3_MCS3_CH4_R4_DATA_WIDTH      (24U)
4310 #define GTM_gtm_cls3_MCS3_CH4_R4_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_R4_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_R4_DATA_MASK)
4311 /*! @} */
4312 
4313 /*! @name MCS3_CH4_R5 - MCS[i] channel x general purpose register [y] */
4314 /*! @{ */
4315 
4316 #define GTM_gtm_cls3_MCS3_CH4_R5_DATA_MASK       (0xFFFFFFU)
4317 #define GTM_gtm_cls3_MCS3_CH4_R5_DATA_SHIFT      (0U)
4318 #define GTM_gtm_cls3_MCS3_CH4_R5_DATA_WIDTH      (24U)
4319 #define GTM_gtm_cls3_MCS3_CH4_R5_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_R5_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_R5_DATA_MASK)
4320 /*! @} */
4321 
4322 /*! @name MCS3_CH4_R6 - MCS[i] channel x general purpose register [y] */
4323 /*! @{ */
4324 
4325 #define GTM_gtm_cls3_MCS3_CH4_R6_DATA_MASK       (0xFFFFFFU)
4326 #define GTM_gtm_cls3_MCS3_CH4_R6_DATA_SHIFT      (0U)
4327 #define GTM_gtm_cls3_MCS3_CH4_R6_DATA_WIDTH      (24U)
4328 #define GTM_gtm_cls3_MCS3_CH4_R6_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_R6_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_R6_DATA_MASK)
4329 /*! @} */
4330 
4331 /*! @name MCS3_CH4_R7 - MCS[i] channel x general purpose register [y] */
4332 /*! @{ */
4333 
4334 #define GTM_gtm_cls3_MCS3_CH4_R7_DATA_MASK       (0xFFFFFFU)
4335 #define GTM_gtm_cls3_MCS3_CH4_R7_DATA_SHIFT      (0U)
4336 #define GTM_gtm_cls3_MCS3_CH4_R7_DATA_WIDTH      (24U)
4337 #define GTM_gtm_cls3_MCS3_CH4_R7_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_R7_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_R7_DATA_MASK)
4338 /*! @} */
4339 
4340 /*! @name MCS3_CH4_CTRL - MCS[i] channel x control register */
4341 /*! @{ */
4342 
4343 #define GTM_gtm_cls3_MCS3_CH4_CTRL_EN_MASK       (0x1U)
4344 #define GTM_gtm_cls3_MCS3_CH4_CTRL_EN_SHIFT      (0U)
4345 #define GTM_gtm_cls3_MCS3_CH4_CTRL_EN_WIDTH      (1U)
4346 #define GTM_gtm_cls3_MCS3_CH4_CTRL_EN(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_CTRL_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_CTRL_EN_MASK)
4347 
4348 #define GTM_gtm_cls3_MCS3_CH4_CTRL_IRQ_MASK      (0x2U)
4349 #define GTM_gtm_cls3_MCS3_CH4_CTRL_IRQ_SHIFT     (1U)
4350 #define GTM_gtm_cls3_MCS3_CH4_CTRL_IRQ_WIDTH     (1U)
4351 #define GTM_gtm_cls3_MCS3_CH4_CTRL_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_CTRL_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_CTRL_IRQ_MASK)
4352 
4353 #define GTM_gtm_cls3_MCS3_CH4_CTRL_ERR_MASK      (0x4U)
4354 #define GTM_gtm_cls3_MCS3_CH4_CTRL_ERR_SHIFT     (2U)
4355 #define GTM_gtm_cls3_MCS3_CH4_CTRL_ERR_WIDTH     (1U)
4356 #define GTM_gtm_cls3_MCS3_CH4_CTRL_ERR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_CTRL_ERR_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_CTRL_ERR_MASK)
4357 
4358 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CY_MASK       (0x10U)
4359 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CY_SHIFT      (4U)
4360 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CY_WIDTH      (1U)
4361 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CY(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_CTRL_CY_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_CTRL_CY_MASK)
4362 
4363 #define GTM_gtm_cls3_MCS3_CH4_CTRL_Z_MASK        (0x20U)
4364 #define GTM_gtm_cls3_MCS3_CH4_CTRL_Z_SHIFT       (5U)
4365 #define GTM_gtm_cls3_MCS3_CH4_CTRL_Z_WIDTH       (1U)
4366 #define GTM_gtm_cls3_MCS3_CH4_CTRL_Z(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_CTRL_Z_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_CTRL_Z_MASK)
4367 
4368 #define GTM_gtm_cls3_MCS3_CH4_CTRL_V_MASK        (0x40U)
4369 #define GTM_gtm_cls3_MCS3_CH4_CTRL_V_SHIFT       (6U)
4370 #define GTM_gtm_cls3_MCS3_CH4_CTRL_V_WIDTH       (1U)
4371 #define GTM_gtm_cls3_MCS3_CH4_CTRL_V(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_CTRL_V_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_CTRL_V_MASK)
4372 
4373 #define GTM_gtm_cls3_MCS3_CH4_CTRL_N_MASK        (0x80U)
4374 #define GTM_gtm_cls3_MCS3_CH4_CTRL_N_SHIFT       (7U)
4375 #define GTM_gtm_cls3_MCS3_CH4_CTRL_N_WIDTH       (1U)
4376 #define GTM_gtm_cls3_MCS3_CH4_CTRL_N(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_CTRL_N_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_CTRL_N_MASK)
4377 
4378 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CAT_MASK      (0x100U)
4379 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CAT_SHIFT     (8U)
4380 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CAT_WIDTH     (1U)
4381 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_CTRL_CAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_CTRL_CAT_MASK)
4382 
4383 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CWT_MASK      (0x200U)
4384 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CWT_SHIFT     (9U)
4385 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CWT_WIDTH     (1U)
4386 #define GTM_gtm_cls3_MCS3_CH4_CTRL_CWT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_CTRL_CWT_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_CTRL_CWT_MASK)
4387 
4388 #define GTM_gtm_cls3_MCS3_CH4_CTRL_SAT_MASK      (0x400U)
4389 #define GTM_gtm_cls3_MCS3_CH4_CTRL_SAT_SHIFT     (10U)
4390 #define GTM_gtm_cls3_MCS3_CH4_CTRL_SAT_WIDTH     (1U)
4391 #define GTM_gtm_cls3_MCS3_CH4_CTRL_SAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_CTRL_SAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_CTRL_SAT_MASK)
4392 /*! @} */
4393 
4394 /*! @name MCS3_CH4_ACB - MCS[i] channel x ARU control Bit register */
4395 /*! @{ */
4396 
4397 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB0_MASK      (0x1U)
4398 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB0_SHIFT     (0U)
4399 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB0_WIDTH     (1U)
4400 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_ACB_ACB0_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_ACB_ACB0_MASK)
4401 
4402 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB1_MASK      (0x2U)
4403 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB1_SHIFT     (1U)
4404 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB1_WIDTH     (1U)
4405 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_ACB_ACB1_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_ACB_ACB1_MASK)
4406 
4407 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB2_MASK      (0x4U)
4408 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB2_SHIFT     (2U)
4409 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB2_WIDTH     (1U)
4410 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB2(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_ACB_ACB2_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_ACB_ACB2_MASK)
4411 
4412 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB3_MASK      (0x8U)
4413 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB3_SHIFT     (3U)
4414 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB3_WIDTH     (1U)
4415 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB3(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_ACB_ACB3_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_ACB_ACB3_MASK)
4416 
4417 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB4_MASK      (0x10U)
4418 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB4_SHIFT     (4U)
4419 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB4_WIDTH     (1U)
4420 #define GTM_gtm_cls3_MCS3_CH4_ACB_ACB4(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_ACB_ACB4_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_ACB_ACB4_MASK)
4421 /*! @} */
4422 
4423 /*! @name MCS3_CH4_MHB - MCS[i] channel x memory high byte register */
4424 /*! @{ */
4425 
4426 #define GTM_gtm_cls3_MCS3_CH4_MHB_DATA_MASK      (0xFFU)
4427 #define GTM_gtm_cls3_MCS3_CH4_MHB_DATA_SHIFT     (0U)
4428 #define GTM_gtm_cls3_MCS3_CH4_MHB_DATA_WIDTH     (8U)
4429 #define GTM_gtm_cls3_MCS3_CH4_MHB_DATA(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_MHB_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_MHB_DATA_MASK)
4430 /*! @} */
4431 
4432 /*! @name MCS3_CH4_PC - MCS[i] channel x program counter register */
4433 /*! @{ */
4434 
4435 #define GTM_gtm_cls3_MCS3_CH4_PC_PC_MASK         (0xFFFFU)
4436 #define GTM_gtm_cls3_MCS3_CH4_PC_PC_SHIFT        (0U)
4437 #define GTM_gtm_cls3_MCS3_CH4_PC_PC_WIDTH        (16U)
4438 #define GTM_gtm_cls3_MCS3_CH4_PC_PC(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_PC_PC_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_PC_PC_MASK)
4439 /*! @} */
4440 
4441 /*! @name MCS3_CH4_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */
4442 /*! @{ */
4443 
4444 #define GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U)
4445 #define GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U)
4446 #define GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U)
4447 #define GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_MCS_IRQ_MASK)
4448 
4449 #define GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U)
4450 #define GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U)
4451 #define GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U)
4452 #define GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_IRQ_NOTIFY_ERR_IRQ_MASK)
4453 /*! @} */
4454 
4455 /*! @name MCS3_CH4_IRQ_EN - MCS[i] channel x interrupt enable register */
4456 /*! @{ */
4457 
4458 #define GTM_gtm_cls3_MCS3_CH4_IRQ_EN_MCS_IRQ_EN_MASK (0x1U)
4459 #define GTM_gtm_cls3_MCS3_CH4_IRQ_EN_MCS_IRQ_EN_SHIFT (0U)
4460 #define GTM_gtm_cls3_MCS3_CH4_IRQ_EN_MCS_IRQ_EN_WIDTH (1U)
4461 #define GTM_gtm_cls3_MCS3_CH4_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_IRQ_EN_MCS_IRQ_EN_MASK)
4462 
4463 #define GTM_gtm_cls3_MCS3_CH4_IRQ_EN_ERR_IRQ_EN_MASK (0x4U)
4464 #define GTM_gtm_cls3_MCS3_CH4_IRQ_EN_ERR_IRQ_EN_SHIFT (2U)
4465 #define GTM_gtm_cls3_MCS3_CH4_IRQ_EN_ERR_IRQ_EN_WIDTH (1U)
4466 #define GTM_gtm_cls3_MCS3_CH4_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_IRQ_EN_ERR_IRQ_EN_MASK)
4467 /*! @} */
4468 
4469 /*! @name MCS3_CH4_IRQ_FORCINT - MCS[i] channel x force interrupt register */
4470 /*! @{ */
4471 
4472 #define GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U)
4473 #define GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U)
4474 #define GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U)
4475 #define GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_MCS_IRQ_MASK)
4476 
4477 #define GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U)
4478 #define GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U)
4479 #define GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U)
4480 #define GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_IRQ_FORCINT_TRG_ERR_IRQ_MASK)
4481 /*! @} */
4482 
4483 /*! @name MCS3_CH4_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */
4484 /*! @{ */
4485 
4486 #define GTM_gtm_cls3_MCS3_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U)
4487 #define GTM_gtm_cls3_MCS3_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U)
4488 #define GTM_gtm_cls3_MCS3_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U)
4489 #define GTM_gtm_cls3_MCS3_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_IRQ_MODE_IRQ_MODE_MASK)
4490 /*! @} */
4491 
4492 /*! @name MCS3_CH4_EIRQ_EN - MCS[i] channel x error interrupt enable register */
4493 /*! @{ */
4494 
4495 #define GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U)
4496 #define GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U)
4497 #define GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U)
4498 #define GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_MCS_EIRQ_EN_MASK)
4499 
4500 #define GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U)
4501 #define GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U)
4502 #define GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U)
4503 #define GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH4_EIRQ_EN_ERR_EIRQ_EN_MASK)
4504 /*! @} */
4505 
4506 /*! @name MCS3_CH5_R0 - MCS[i] channel x general purpose register [y] */
4507 /*! @{ */
4508 
4509 #define GTM_gtm_cls3_MCS3_CH5_R0_DATA_MASK       (0xFFFFFFU)
4510 #define GTM_gtm_cls3_MCS3_CH5_R0_DATA_SHIFT      (0U)
4511 #define GTM_gtm_cls3_MCS3_CH5_R0_DATA_WIDTH      (24U)
4512 #define GTM_gtm_cls3_MCS3_CH5_R0_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_R0_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_R0_DATA_MASK)
4513 /*! @} */
4514 
4515 /*! @name MCS3_CH5_R1 - MCS[i] channel x general purpose register [y] */
4516 /*! @{ */
4517 
4518 #define GTM_gtm_cls3_MCS3_CH5_R1_DATA_MASK       (0xFFFFFFU)
4519 #define GTM_gtm_cls3_MCS3_CH5_R1_DATA_SHIFT      (0U)
4520 #define GTM_gtm_cls3_MCS3_CH5_R1_DATA_WIDTH      (24U)
4521 #define GTM_gtm_cls3_MCS3_CH5_R1_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_R1_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_R1_DATA_MASK)
4522 /*! @} */
4523 
4524 /*! @name MCS3_CH5_R2 - MCS[i] channel x general purpose register [y] */
4525 /*! @{ */
4526 
4527 #define GTM_gtm_cls3_MCS3_CH5_R2_DATA_MASK       (0xFFFFFFU)
4528 #define GTM_gtm_cls3_MCS3_CH5_R2_DATA_SHIFT      (0U)
4529 #define GTM_gtm_cls3_MCS3_CH5_R2_DATA_WIDTH      (24U)
4530 #define GTM_gtm_cls3_MCS3_CH5_R2_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_R2_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_R2_DATA_MASK)
4531 /*! @} */
4532 
4533 /*! @name MCS3_CH5_R3 - MCS[i] channel x general purpose register [y] */
4534 /*! @{ */
4535 
4536 #define GTM_gtm_cls3_MCS3_CH5_R3_DATA_MASK       (0xFFFFFFU)
4537 #define GTM_gtm_cls3_MCS3_CH5_R3_DATA_SHIFT      (0U)
4538 #define GTM_gtm_cls3_MCS3_CH5_R3_DATA_WIDTH      (24U)
4539 #define GTM_gtm_cls3_MCS3_CH5_R3_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_R3_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_R3_DATA_MASK)
4540 /*! @} */
4541 
4542 /*! @name MCS3_CH5_R4 - MCS[i] channel x general purpose register [y] */
4543 /*! @{ */
4544 
4545 #define GTM_gtm_cls3_MCS3_CH5_R4_DATA_MASK       (0xFFFFFFU)
4546 #define GTM_gtm_cls3_MCS3_CH5_R4_DATA_SHIFT      (0U)
4547 #define GTM_gtm_cls3_MCS3_CH5_R4_DATA_WIDTH      (24U)
4548 #define GTM_gtm_cls3_MCS3_CH5_R4_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_R4_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_R4_DATA_MASK)
4549 /*! @} */
4550 
4551 /*! @name MCS3_CH5_R5 - MCS[i] channel x general purpose register [y] */
4552 /*! @{ */
4553 
4554 #define GTM_gtm_cls3_MCS3_CH5_R5_DATA_MASK       (0xFFFFFFU)
4555 #define GTM_gtm_cls3_MCS3_CH5_R5_DATA_SHIFT      (0U)
4556 #define GTM_gtm_cls3_MCS3_CH5_R5_DATA_WIDTH      (24U)
4557 #define GTM_gtm_cls3_MCS3_CH5_R5_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_R5_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_R5_DATA_MASK)
4558 /*! @} */
4559 
4560 /*! @name MCS3_CH5_R6 - MCS[i] channel x general purpose register [y] */
4561 /*! @{ */
4562 
4563 #define GTM_gtm_cls3_MCS3_CH5_R6_DATA_MASK       (0xFFFFFFU)
4564 #define GTM_gtm_cls3_MCS3_CH5_R6_DATA_SHIFT      (0U)
4565 #define GTM_gtm_cls3_MCS3_CH5_R6_DATA_WIDTH      (24U)
4566 #define GTM_gtm_cls3_MCS3_CH5_R6_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_R6_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_R6_DATA_MASK)
4567 /*! @} */
4568 
4569 /*! @name MCS3_CH5_R7 - MCS[i] channel x general purpose register [y] */
4570 /*! @{ */
4571 
4572 #define GTM_gtm_cls3_MCS3_CH5_R7_DATA_MASK       (0xFFFFFFU)
4573 #define GTM_gtm_cls3_MCS3_CH5_R7_DATA_SHIFT      (0U)
4574 #define GTM_gtm_cls3_MCS3_CH5_R7_DATA_WIDTH      (24U)
4575 #define GTM_gtm_cls3_MCS3_CH5_R7_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_R7_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_R7_DATA_MASK)
4576 /*! @} */
4577 
4578 /*! @name MCS3_CH5_CTRL - MCS[i] channel x control register */
4579 /*! @{ */
4580 
4581 #define GTM_gtm_cls3_MCS3_CH5_CTRL_EN_MASK       (0x1U)
4582 #define GTM_gtm_cls3_MCS3_CH5_CTRL_EN_SHIFT      (0U)
4583 #define GTM_gtm_cls3_MCS3_CH5_CTRL_EN_WIDTH      (1U)
4584 #define GTM_gtm_cls3_MCS3_CH5_CTRL_EN(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_CTRL_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_CTRL_EN_MASK)
4585 
4586 #define GTM_gtm_cls3_MCS3_CH5_CTRL_IRQ_MASK      (0x2U)
4587 #define GTM_gtm_cls3_MCS3_CH5_CTRL_IRQ_SHIFT     (1U)
4588 #define GTM_gtm_cls3_MCS3_CH5_CTRL_IRQ_WIDTH     (1U)
4589 #define GTM_gtm_cls3_MCS3_CH5_CTRL_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_CTRL_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_CTRL_IRQ_MASK)
4590 
4591 #define GTM_gtm_cls3_MCS3_CH5_CTRL_ERR_MASK      (0x4U)
4592 #define GTM_gtm_cls3_MCS3_CH5_CTRL_ERR_SHIFT     (2U)
4593 #define GTM_gtm_cls3_MCS3_CH5_CTRL_ERR_WIDTH     (1U)
4594 #define GTM_gtm_cls3_MCS3_CH5_CTRL_ERR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_CTRL_ERR_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_CTRL_ERR_MASK)
4595 
4596 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CY_MASK       (0x10U)
4597 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CY_SHIFT      (4U)
4598 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CY_WIDTH      (1U)
4599 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CY(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_CTRL_CY_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_CTRL_CY_MASK)
4600 
4601 #define GTM_gtm_cls3_MCS3_CH5_CTRL_Z_MASK        (0x20U)
4602 #define GTM_gtm_cls3_MCS3_CH5_CTRL_Z_SHIFT       (5U)
4603 #define GTM_gtm_cls3_MCS3_CH5_CTRL_Z_WIDTH       (1U)
4604 #define GTM_gtm_cls3_MCS3_CH5_CTRL_Z(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_CTRL_Z_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_CTRL_Z_MASK)
4605 
4606 #define GTM_gtm_cls3_MCS3_CH5_CTRL_V_MASK        (0x40U)
4607 #define GTM_gtm_cls3_MCS3_CH5_CTRL_V_SHIFT       (6U)
4608 #define GTM_gtm_cls3_MCS3_CH5_CTRL_V_WIDTH       (1U)
4609 #define GTM_gtm_cls3_MCS3_CH5_CTRL_V(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_CTRL_V_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_CTRL_V_MASK)
4610 
4611 #define GTM_gtm_cls3_MCS3_CH5_CTRL_N_MASK        (0x80U)
4612 #define GTM_gtm_cls3_MCS3_CH5_CTRL_N_SHIFT       (7U)
4613 #define GTM_gtm_cls3_MCS3_CH5_CTRL_N_WIDTH       (1U)
4614 #define GTM_gtm_cls3_MCS3_CH5_CTRL_N(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_CTRL_N_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_CTRL_N_MASK)
4615 
4616 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CAT_MASK      (0x100U)
4617 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CAT_SHIFT     (8U)
4618 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CAT_WIDTH     (1U)
4619 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_CTRL_CAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_CTRL_CAT_MASK)
4620 
4621 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CWT_MASK      (0x200U)
4622 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CWT_SHIFT     (9U)
4623 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CWT_WIDTH     (1U)
4624 #define GTM_gtm_cls3_MCS3_CH5_CTRL_CWT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_CTRL_CWT_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_CTRL_CWT_MASK)
4625 
4626 #define GTM_gtm_cls3_MCS3_CH5_CTRL_SAT_MASK      (0x400U)
4627 #define GTM_gtm_cls3_MCS3_CH5_CTRL_SAT_SHIFT     (10U)
4628 #define GTM_gtm_cls3_MCS3_CH5_CTRL_SAT_WIDTH     (1U)
4629 #define GTM_gtm_cls3_MCS3_CH5_CTRL_SAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_CTRL_SAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_CTRL_SAT_MASK)
4630 /*! @} */
4631 
4632 /*! @name MCS3_CH5_ACB - MCS[i] channel x ARU control Bit register */
4633 /*! @{ */
4634 
4635 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB0_MASK      (0x1U)
4636 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB0_SHIFT     (0U)
4637 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB0_WIDTH     (1U)
4638 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_ACB_ACB0_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_ACB_ACB0_MASK)
4639 
4640 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB1_MASK      (0x2U)
4641 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB1_SHIFT     (1U)
4642 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB1_WIDTH     (1U)
4643 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_ACB_ACB1_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_ACB_ACB1_MASK)
4644 
4645 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB2_MASK      (0x4U)
4646 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB2_SHIFT     (2U)
4647 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB2_WIDTH     (1U)
4648 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB2(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_ACB_ACB2_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_ACB_ACB2_MASK)
4649 
4650 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB3_MASK      (0x8U)
4651 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB3_SHIFT     (3U)
4652 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB3_WIDTH     (1U)
4653 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB3(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_ACB_ACB3_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_ACB_ACB3_MASK)
4654 
4655 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB4_MASK      (0x10U)
4656 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB4_SHIFT     (4U)
4657 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB4_WIDTH     (1U)
4658 #define GTM_gtm_cls3_MCS3_CH5_ACB_ACB4(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_ACB_ACB4_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_ACB_ACB4_MASK)
4659 /*! @} */
4660 
4661 /*! @name MCS3_CH5_MHB - MCS[i] channel x memory high byte register */
4662 /*! @{ */
4663 
4664 #define GTM_gtm_cls3_MCS3_CH5_MHB_DATA_MASK      (0xFFU)
4665 #define GTM_gtm_cls3_MCS3_CH5_MHB_DATA_SHIFT     (0U)
4666 #define GTM_gtm_cls3_MCS3_CH5_MHB_DATA_WIDTH     (8U)
4667 #define GTM_gtm_cls3_MCS3_CH5_MHB_DATA(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_MHB_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_MHB_DATA_MASK)
4668 /*! @} */
4669 
4670 /*! @name MCS3_CH5_PC - MCS[i] channel x program counter register */
4671 /*! @{ */
4672 
4673 #define GTM_gtm_cls3_MCS3_CH5_PC_PC_MASK         (0xFFFFU)
4674 #define GTM_gtm_cls3_MCS3_CH5_PC_PC_SHIFT        (0U)
4675 #define GTM_gtm_cls3_MCS3_CH5_PC_PC_WIDTH        (16U)
4676 #define GTM_gtm_cls3_MCS3_CH5_PC_PC(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_PC_PC_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_PC_PC_MASK)
4677 /*! @} */
4678 
4679 /*! @name MCS3_CH5_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */
4680 /*! @{ */
4681 
4682 #define GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U)
4683 #define GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U)
4684 #define GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U)
4685 #define GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_MCS_IRQ_MASK)
4686 
4687 #define GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U)
4688 #define GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U)
4689 #define GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U)
4690 #define GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_IRQ_NOTIFY_ERR_IRQ_MASK)
4691 /*! @} */
4692 
4693 /*! @name MCS3_CH5_IRQ_EN - MCS[i] channel x interrupt enable register */
4694 /*! @{ */
4695 
4696 #define GTM_gtm_cls3_MCS3_CH5_IRQ_EN_MCS_IRQ_EN_MASK (0x1U)
4697 #define GTM_gtm_cls3_MCS3_CH5_IRQ_EN_MCS_IRQ_EN_SHIFT (0U)
4698 #define GTM_gtm_cls3_MCS3_CH5_IRQ_EN_MCS_IRQ_EN_WIDTH (1U)
4699 #define GTM_gtm_cls3_MCS3_CH5_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_IRQ_EN_MCS_IRQ_EN_MASK)
4700 
4701 #define GTM_gtm_cls3_MCS3_CH5_IRQ_EN_ERR_IRQ_EN_MASK (0x4U)
4702 #define GTM_gtm_cls3_MCS3_CH5_IRQ_EN_ERR_IRQ_EN_SHIFT (2U)
4703 #define GTM_gtm_cls3_MCS3_CH5_IRQ_EN_ERR_IRQ_EN_WIDTH (1U)
4704 #define GTM_gtm_cls3_MCS3_CH5_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_IRQ_EN_ERR_IRQ_EN_MASK)
4705 /*! @} */
4706 
4707 /*! @name MCS3_CH5_IRQ_FORCINT - MCS[i] channel x force interrupt register */
4708 /*! @{ */
4709 
4710 #define GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U)
4711 #define GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U)
4712 #define GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U)
4713 #define GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_MCS_IRQ_MASK)
4714 
4715 #define GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U)
4716 #define GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U)
4717 #define GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U)
4718 #define GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_IRQ_FORCINT_TRG_ERR_IRQ_MASK)
4719 /*! @} */
4720 
4721 /*! @name MCS3_CH5_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */
4722 /*! @{ */
4723 
4724 #define GTM_gtm_cls3_MCS3_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U)
4725 #define GTM_gtm_cls3_MCS3_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U)
4726 #define GTM_gtm_cls3_MCS3_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U)
4727 #define GTM_gtm_cls3_MCS3_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_IRQ_MODE_IRQ_MODE_MASK)
4728 /*! @} */
4729 
4730 /*! @name MCS3_CH5_EIRQ_EN - MCS[i] channel x error interrupt enable register */
4731 /*! @{ */
4732 
4733 #define GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U)
4734 #define GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U)
4735 #define GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U)
4736 #define GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_MCS_EIRQ_EN_MASK)
4737 
4738 #define GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U)
4739 #define GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U)
4740 #define GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U)
4741 #define GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH5_EIRQ_EN_ERR_EIRQ_EN_MASK)
4742 /*! @} */
4743 
4744 /*! @name MCS3_CH6_R0 - MCS[i] channel x general purpose register [y] */
4745 /*! @{ */
4746 
4747 #define GTM_gtm_cls3_MCS3_CH6_R0_DATA_MASK       (0xFFFFFFU)
4748 #define GTM_gtm_cls3_MCS3_CH6_R0_DATA_SHIFT      (0U)
4749 #define GTM_gtm_cls3_MCS3_CH6_R0_DATA_WIDTH      (24U)
4750 #define GTM_gtm_cls3_MCS3_CH6_R0_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_R0_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_R0_DATA_MASK)
4751 /*! @} */
4752 
4753 /*! @name MCS3_CH6_R1 - MCS[i] channel x general purpose register [y] */
4754 /*! @{ */
4755 
4756 #define GTM_gtm_cls3_MCS3_CH6_R1_DATA_MASK       (0xFFFFFFU)
4757 #define GTM_gtm_cls3_MCS3_CH6_R1_DATA_SHIFT      (0U)
4758 #define GTM_gtm_cls3_MCS3_CH6_R1_DATA_WIDTH      (24U)
4759 #define GTM_gtm_cls3_MCS3_CH6_R1_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_R1_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_R1_DATA_MASK)
4760 /*! @} */
4761 
4762 /*! @name MCS3_CH6_R2 - MCS[i] channel x general purpose register [y] */
4763 /*! @{ */
4764 
4765 #define GTM_gtm_cls3_MCS3_CH6_R2_DATA_MASK       (0xFFFFFFU)
4766 #define GTM_gtm_cls3_MCS3_CH6_R2_DATA_SHIFT      (0U)
4767 #define GTM_gtm_cls3_MCS3_CH6_R2_DATA_WIDTH      (24U)
4768 #define GTM_gtm_cls3_MCS3_CH6_R2_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_R2_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_R2_DATA_MASK)
4769 /*! @} */
4770 
4771 /*! @name MCS3_CH6_R3 - MCS[i] channel x general purpose register [y] */
4772 /*! @{ */
4773 
4774 #define GTM_gtm_cls3_MCS3_CH6_R3_DATA_MASK       (0xFFFFFFU)
4775 #define GTM_gtm_cls3_MCS3_CH6_R3_DATA_SHIFT      (0U)
4776 #define GTM_gtm_cls3_MCS3_CH6_R3_DATA_WIDTH      (24U)
4777 #define GTM_gtm_cls3_MCS3_CH6_R3_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_R3_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_R3_DATA_MASK)
4778 /*! @} */
4779 
4780 /*! @name MCS3_CH6_R4 - MCS[i] channel x general purpose register [y] */
4781 /*! @{ */
4782 
4783 #define GTM_gtm_cls3_MCS3_CH6_R4_DATA_MASK       (0xFFFFFFU)
4784 #define GTM_gtm_cls3_MCS3_CH6_R4_DATA_SHIFT      (0U)
4785 #define GTM_gtm_cls3_MCS3_CH6_R4_DATA_WIDTH      (24U)
4786 #define GTM_gtm_cls3_MCS3_CH6_R4_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_R4_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_R4_DATA_MASK)
4787 /*! @} */
4788 
4789 /*! @name MCS3_CH6_R5 - MCS[i] channel x general purpose register [y] */
4790 /*! @{ */
4791 
4792 #define GTM_gtm_cls3_MCS3_CH6_R5_DATA_MASK       (0xFFFFFFU)
4793 #define GTM_gtm_cls3_MCS3_CH6_R5_DATA_SHIFT      (0U)
4794 #define GTM_gtm_cls3_MCS3_CH6_R5_DATA_WIDTH      (24U)
4795 #define GTM_gtm_cls3_MCS3_CH6_R5_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_R5_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_R5_DATA_MASK)
4796 /*! @} */
4797 
4798 /*! @name MCS3_CH6_R6 - MCS[i] channel x general purpose register [y] */
4799 /*! @{ */
4800 
4801 #define GTM_gtm_cls3_MCS3_CH6_R6_DATA_MASK       (0xFFFFFFU)
4802 #define GTM_gtm_cls3_MCS3_CH6_R6_DATA_SHIFT      (0U)
4803 #define GTM_gtm_cls3_MCS3_CH6_R6_DATA_WIDTH      (24U)
4804 #define GTM_gtm_cls3_MCS3_CH6_R6_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_R6_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_R6_DATA_MASK)
4805 /*! @} */
4806 
4807 /*! @name MCS3_CH6_R7 - MCS[i] channel x general purpose register [y] */
4808 /*! @{ */
4809 
4810 #define GTM_gtm_cls3_MCS3_CH6_R7_DATA_MASK       (0xFFFFFFU)
4811 #define GTM_gtm_cls3_MCS3_CH6_R7_DATA_SHIFT      (0U)
4812 #define GTM_gtm_cls3_MCS3_CH6_R7_DATA_WIDTH      (24U)
4813 #define GTM_gtm_cls3_MCS3_CH6_R7_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_R7_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_R7_DATA_MASK)
4814 /*! @} */
4815 
4816 /*! @name MCS3_CH6_CTRL - MCS[i] channel x control register */
4817 /*! @{ */
4818 
4819 #define GTM_gtm_cls3_MCS3_CH6_CTRL_EN_MASK       (0x1U)
4820 #define GTM_gtm_cls3_MCS3_CH6_CTRL_EN_SHIFT      (0U)
4821 #define GTM_gtm_cls3_MCS3_CH6_CTRL_EN_WIDTH      (1U)
4822 #define GTM_gtm_cls3_MCS3_CH6_CTRL_EN(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_CTRL_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_CTRL_EN_MASK)
4823 
4824 #define GTM_gtm_cls3_MCS3_CH6_CTRL_IRQ_MASK      (0x2U)
4825 #define GTM_gtm_cls3_MCS3_CH6_CTRL_IRQ_SHIFT     (1U)
4826 #define GTM_gtm_cls3_MCS3_CH6_CTRL_IRQ_WIDTH     (1U)
4827 #define GTM_gtm_cls3_MCS3_CH6_CTRL_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_CTRL_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_CTRL_IRQ_MASK)
4828 
4829 #define GTM_gtm_cls3_MCS3_CH6_CTRL_ERR_MASK      (0x4U)
4830 #define GTM_gtm_cls3_MCS3_CH6_CTRL_ERR_SHIFT     (2U)
4831 #define GTM_gtm_cls3_MCS3_CH6_CTRL_ERR_WIDTH     (1U)
4832 #define GTM_gtm_cls3_MCS3_CH6_CTRL_ERR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_CTRL_ERR_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_CTRL_ERR_MASK)
4833 
4834 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CY_MASK       (0x10U)
4835 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CY_SHIFT      (4U)
4836 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CY_WIDTH      (1U)
4837 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CY(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_CTRL_CY_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_CTRL_CY_MASK)
4838 
4839 #define GTM_gtm_cls3_MCS3_CH6_CTRL_Z_MASK        (0x20U)
4840 #define GTM_gtm_cls3_MCS3_CH6_CTRL_Z_SHIFT       (5U)
4841 #define GTM_gtm_cls3_MCS3_CH6_CTRL_Z_WIDTH       (1U)
4842 #define GTM_gtm_cls3_MCS3_CH6_CTRL_Z(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_CTRL_Z_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_CTRL_Z_MASK)
4843 
4844 #define GTM_gtm_cls3_MCS3_CH6_CTRL_V_MASK        (0x40U)
4845 #define GTM_gtm_cls3_MCS3_CH6_CTRL_V_SHIFT       (6U)
4846 #define GTM_gtm_cls3_MCS3_CH6_CTRL_V_WIDTH       (1U)
4847 #define GTM_gtm_cls3_MCS3_CH6_CTRL_V(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_CTRL_V_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_CTRL_V_MASK)
4848 
4849 #define GTM_gtm_cls3_MCS3_CH6_CTRL_N_MASK        (0x80U)
4850 #define GTM_gtm_cls3_MCS3_CH6_CTRL_N_SHIFT       (7U)
4851 #define GTM_gtm_cls3_MCS3_CH6_CTRL_N_WIDTH       (1U)
4852 #define GTM_gtm_cls3_MCS3_CH6_CTRL_N(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_CTRL_N_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_CTRL_N_MASK)
4853 
4854 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CAT_MASK      (0x100U)
4855 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CAT_SHIFT     (8U)
4856 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CAT_WIDTH     (1U)
4857 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_CTRL_CAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_CTRL_CAT_MASK)
4858 
4859 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CWT_MASK      (0x200U)
4860 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CWT_SHIFT     (9U)
4861 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CWT_WIDTH     (1U)
4862 #define GTM_gtm_cls3_MCS3_CH6_CTRL_CWT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_CTRL_CWT_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_CTRL_CWT_MASK)
4863 
4864 #define GTM_gtm_cls3_MCS3_CH6_CTRL_SAT_MASK      (0x400U)
4865 #define GTM_gtm_cls3_MCS3_CH6_CTRL_SAT_SHIFT     (10U)
4866 #define GTM_gtm_cls3_MCS3_CH6_CTRL_SAT_WIDTH     (1U)
4867 #define GTM_gtm_cls3_MCS3_CH6_CTRL_SAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_CTRL_SAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_CTRL_SAT_MASK)
4868 /*! @} */
4869 
4870 /*! @name MCS3_CH6_ACB - MCS[i] channel x ARU control Bit register */
4871 /*! @{ */
4872 
4873 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB0_MASK      (0x1U)
4874 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB0_SHIFT     (0U)
4875 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB0_WIDTH     (1U)
4876 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_ACB_ACB0_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_ACB_ACB0_MASK)
4877 
4878 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB1_MASK      (0x2U)
4879 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB1_SHIFT     (1U)
4880 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB1_WIDTH     (1U)
4881 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_ACB_ACB1_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_ACB_ACB1_MASK)
4882 
4883 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB2_MASK      (0x4U)
4884 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB2_SHIFT     (2U)
4885 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB2_WIDTH     (1U)
4886 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB2(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_ACB_ACB2_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_ACB_ACB2_MASK)
4887 
4888 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB3_MASK      (0x8U)
4889 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB3_SHIFT     (3U)
4890 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB3_WIDTH     (1U)
4891 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB3(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_ACB_ACB3_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_ACB_ACB3_MASK)
4892 
4893 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB4_MASK      (0x10U)
4894 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB4_SHIFT     (4U)
4895 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB4_WIDTH     (1U)
4896 #define GTM_gtm_cls3_MCS3_CH6_ACB_ACB4(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_ACB_ACB4_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_ACB_ACB4_MASK)
4897 /*! @} */
4898 
4899 /*! @name MCS3_CH6_MHB - MCS[i] channel x memory high byte register */
4900 /*! @{ */
4901 
4902 #define GTM_gtm_cls3_MCS3_CH6_MHB_DATA_MASK      (0xFFU)
4903 #define GTM_gtm_cls3_MCS3_CH6_MHB_DATA_SHIFT     (0U)
4904 #define GTM_gtm_cls3_MCS3_CH6_MHB_DATA_WIDTH     (8U)
4905 #define GTM_gtm_cls3_MCS3_CH6_MHB_DATA(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_MHB_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_MHB_DATA_MASK)
4906 /*! @} */
4907 
4908 /*! @name MCS3_CH6_PC - MCS[i] channel x program counter register */
4909 /*! @{ */
4910 
4911 #define GTM_gtm_cls3_MCS3_CH6_PC_PC_MASK         (0xFFFFU)
4912 #define GTM_gtm_cls3_MCS3_CH6_PC_PC_SHIFT        (0U)
4913 #define GTM_gtm_cls3_MCS3_CH6_PC_PC_WIDTH        (16U)
4914 #define GTM_gtm_cls3_MCS3_CH6_PC_PC(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_PC_PC_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_PC_PC_MASK)
4915 /*! @} */
4916 
4917 /*! @name MCS3_CH6_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */
4918 /*! @{ */
4919 
4920 #define GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U)
4921 #define GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U)
4922 #define GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U)
4923 #define GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_MCS_IRQ_MASK)
4924 
4925 #define GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U)
4926 #define GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U)
4927 #define GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U)
4928 #define GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_IRQ_NOTIFY_ERR_IRQ_MASK)
4929 /*! @} */
4930 
4931 /*! @name MCS3_CH6_IRQ_EN - MCS[i] channel x interrupt enable register */
4932 /*! @{ */
4933 
4934 #define GTM_gtm_cls3_MCS3_CH6_IRQ_EN_MCS_IRQ_EN_MASK (0x1U)
4935 #define GTM_gtm_cls3_MCS3_CH6_IRQ_EN_MCS_IRQ_EN_SHIFT (0U)
4936 #define GTM_gtm_cls3_MCS3_CH6_IRQ_EN_MCS_IRQ_EN_WIDTH (1U)
4937 #define GTM_gtm_cls3_MCS3_CH6_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_IRQ_EN_MCS_IRQ_EN_MASK)
4938 
4939 #define GTM_gtm_cls3_MCS3_CH6_IRQ_EN_ERR_IRQ_EN_MASK (0x4U)
4940 #define GTM_gtm_cls3_MCS3_CH6_IRQ_EN_ERR_IRQ_EN_SHIFT (2U)
4941 #define GTM_gtm_cls3_MCS3_CH6_IRQ_EN_ERR_IRQ_EN_WIDTH (1U)
4942 #define GTM_gtm_cls3_MCS3_CH6_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_IRQ_EN_ERR_IRQ_EN_MASK)
4943 /*! @} */
4944 
4945 /*! @name MCS3_CH6_IRQ_FORCINT - MCS[i] channel x force interrupt register */
4946 /*! @{ */
4947 
4948 #define GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U)
4949 #define GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U)
4950 #define GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U)
4951 #define GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_MCS_IRQ_MASK)
4952 
4953 #define GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U)
4954 #define GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U)
4955 #define GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U)
4956 #define GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_IRQ_FORCINT_TRG_ERR_IRQ_MASK)
4957 /*! @} */
4958 
4959 /*! @name MCS3_CH6_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */
4960 /*! @{ */
4961 
4962 #define GTM_gtm_cls3_MCS3_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U)
4963 #define GTM_gtm_cls3_MCS3_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U)
4964 #define GTM_gtm_cls3_MCS3_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U)
4965 #define GTM_gtm_cls3_MCS3_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_IRQ_MODE_IRQ_MODE_MASK)
4966 /*! @} */
4967 
4968 /*! @name MCS3_CH6_EIRQ_EN - MCS[i] channel x error interrupt enable register */
4969 /*! @{ */
4970 
4971 #define GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U)
4972 #define GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U)
4973 #define GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U)
4974 #define GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_MCS_EIRQ_EN_MASK)
4975 
4976 #define GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U)
4977 #define GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U)
4978 #define GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U)
4979 #define GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH6_EIRQ_EN_ERR_EIRQ_EN_MASK)
4980 /*! @} */
4981 
4982 /*! @name MCS3_CH7_R0 - MCS[i] channel x general purpose register [y] */
4983 /*! @{ */
4984 
4985 #define GTM_gtm_cls3_MCS3_CH7_R0_DATA_MASK       (0xFFFFFFU)
4986 #define GTM_gtm_cls3_MCS3_CH7_R0_DATA_SHIFT      (0U)
4987 #define GTM_gtm_cls3_MCS3_CH7_R0_DATA_WIDTH      (24U)
4988 #define GTM_gtm_cls3_MCS3_CH7_R0_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_R0_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_R0_DATA_MASK)
4989 /*! @} */
4990 
4991 /*! @name MCS3_CH7_R1 - MCS[i] channel x general purpose register [y] */
4992 /*! @{ */
4993 
4994 #define GTM_gtm_cls3_MCS3_CH7_R1_DATA_MASK       (0xFFFFFFU)
4995 #define GTM_gtm_cls3_MCS3_CH7_R1_DATA_SHIFT      (0U)
4996 #define GTM_gtm_cls3_MCS3_CH7_R1_DATA_WIDTH      (24U)
4997 #define GTM_gtm_cls3_MCS3_CH7_R1_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_R1_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_R1_DATA_MASK)
4998 /*! @} */
4999 
5000 /*! @name MCS3_CH7_R2 - MCS[i] channel x general purpose register [y] */
5001 /*! @{ */
5002 
5003 #define GTM_gtm_cls3_MCS3_CH7_R2_DATA_MASK       (0xFFFFFFU)
5004 #define GTM_gtm_cls3_MCS3_CH7_R2_DATA_SHIFT      (0U)
5005 #define GTM_gtm_cls3_MCS3_CH7_R2_DATA_WIDTH      (24U)
5006 #define GTM_gtm_cls3_MCS3_CH7_R2_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_R2_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_R2_DATA_MASK)
5007 /*! @} */
5008 
5009 /*! @name MCS3_CH7_R3 - MCS[i] channel x general purpose register [y] */
5010 /*! @{ */
5011 
5012 #define GTM_gtm_cls3_MCS3_CH7_R3_DATA_MASK       (0xFFFFFFU)
5013 #define GTM_gtm_cls3_MCS3_CH7_R3_DATA_SHIFT      (0U)
5014 #define GTM_gtm_cls3_MCS3_CH7_R3_DATA_WIDTH      (24U)
5015 #define GTM_gtm_cls3_MCS3_CH7_R3_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_R3_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_R3_DATA_MASK)
5016 /*! @} */
5017 
5018 /*! @name MCS3_CH7_R4 - MCS[i] channel x general purpose register [y] */
5019 /*! @{ */
5020 
5021 #define GTM_gtm_cls3_MCS3_CH7_R4_DATA_MASK       (0xFFFFFFU)
5022 #define GTM_gtm_cls3_MCS3_CH7_R4_DATA_SHIFT      (0U)
5023 #define GTM_gtm_cls3_MCS3_CH7_R4_DATA_WIDTH      (24U)
5024 #define GTM_gtm_cls3_MCS3_CH7_R4_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_R4_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_R4_DATA_MASK)
5025 /*! @} */
5026 
5027 /*! @name MCS3_CH7_R5 - MCS[i] channel x general purpose register [y] */
5028 /*! @{ */
5029 
5030 #define GTM_gtm_cls3_MCS3_CH7_R5_DATA_MASK       (0xFFFFFFU)
5031 #define GTM_gtm_cls3_MCS3_CH7_R5_DATA_SHIFT      (0U)
5032 #define GTM_gtm_cls3_MCS3_CH7_R5_DATA_WIDTH      (24U)
5033 #define GTM_gtm_cls3_MCS3_CH7_R5_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_R5_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_R5_DATA_MASK)
5034 /*! @} */
5035 
5036 /*! @name MCS3_CH7_R6 - MCS[i] channel x general purpose register [y] */
5037 /*! @{ */
5038 
5039 #define GTM_gtm_cls3_MCS3_CH7_R6_DATA_MASK       (0xFFFFFFU)
5040 #define GTM_gtm_cls3_MCS3_CH7_R6_DATA_SHIFT      (0U)
5041 #define GTM_gtm_cls3_MCS3_CH7_R6_DATA_WIDTH      (24U)
5042 #define GTM_gtm_cls3_MCS3_CH7_R6_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_R6_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_R6_DATA_MASK)
5043 /*! @} */
5044 
5045 /*! @name MCS3_CH7_R7 - MCS[i] channel x general purpose register [y] */
5046 /*! @{ */
5047 
5048 #define GTM_gtm_cls3_MCS3_CH7_R7_DATA_MASK       (0xFFFFFFU)
5049 #define GTM_gtm_cls3_MCS3_CH7_R7_DATA_SHIFT      (0U)
5050 #define GTM_gtm_cls3_MCS3_CH7_R7_DATA_WIDTH      (24U)
5051 #define GTM_gtm_cls3_MCS3_CH7_R7_DATA(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_R7_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_R7_DATA_MASK)
5052 /*! @} */
5053 
5054 /*! @name MCS3_CH7_CTRL - MCS[i] channel x control register */
5055 /*! @{ */
5056 
5057 #define GTM_gtm_cls3_MCS3_CH7_CTRL_EN_MASK       (0x1U)
5058 #define GTM_gtm_cls3_MCS3_CH7_CTRL_EN_SHIFT      (0U)
5059 #define GTM_gtm_cls3_MCS3_CH7_CTRL_EN_WIDTH      (1U)
5060 #define GTM_gtm_cls3_MCS3_CH7_CTRL_EN(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_CTRL_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_CTRL_EN_MASK)
5061 
5062 #define GTM_gtm_cls3_MCS3_CH7_CTRL_IRQ_MASK      (0x2U)
5063 #define GTM_gtm_cls3_MCS3_CH7_CTRL_IRQ_SHIFT     (1U)
5064 #define GTM_gtm_cls3_MCS3_CH7_CTRL_IRQ_WIDTH     (1U)
5065 #define GTM_gtm_cls3_MCS3_CH7_CTRL_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_CTRL_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_CTRL_IRQ_MASK)
5066 
5067 #define GTM_gtm_cls3_MCS3_CH7_CTRL_ERR_MASK      (0x4U)
5068 #define GTM_gtm_cls3_MCS3_CH7_CTRL_ERR_SHIFT     (2U)
5069 #define GTM_gtm_cls3_MCS3_CH7_CTRL_ERR_WIDTH     (1U)
5070 #define GTM_gtm_cls3_MCS3_CH7_CTRL_ERR(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_CTRL_ERR_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_CTRL_ERR_MASK)
5071 
5072 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CY_MASK       (0x10U)
5073 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CY_SHIFT      (4U)
5074 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CY_WIDTH      (1U)
5075 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CY(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_CTRL_CY_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_CTRL_CY_MASK)
5076 
5077 #define GTM_gtm_cls3_MCS3_CH7_CTRL_Z_MASK        (0x20U)
5078 #define GTM_gtm_cls3_MCS3_CH7_CTRL_Z_SHIFT       (5U)
5079 #define GTM_gtm_cls3_MCS3_CH7_CTRL_Z_WIDTH       (1U)
5080 #define GTM_gtm_cls3_MCS3_CH7_CTRL_Z(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_CTRL_Z_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_CTRL_Z_MASK)
5081 
5082 #define GTM_gtm_cls3_MCS3_CH7_CTRL_V_MASK        (0x40U)
5083 #define GTM_gtm_cls3_MCS3_CH7_CTRL_V_SHIFT       (6U)
5084 #define GTM_gtm_cls3_MCS3_CH7_CTRL_V_WIDTH       (1U)
5085 #define GTM_gtm_cls3_MCS3_CH7_CTRL_V(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_CTRL_V_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_CTRL_V_MASK)
5086 
5087 #define GTM_gtm_cls3_MCS3_CH7_CTRL_N_MASK        (0x80U)
5088 #define GTM_gtm_cls3_MCS3_CH7_CTRL_N_SHIFT       (7U)
5089 #define GTM_gtm_cls3_MCS3_CH7_CTRL_N_WIDTH       (1U)
5090 #define GTM_gtm_cls3_MCS3_CH7_CTRL_N(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_CTRL_N_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_CTRL_N_MASK)
5091 
5092 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CAT_MASK      (0x100U)
5093 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CAT_SHIFT     (8U)
5094 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CAT_WIDTH     (1U)
5095 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_CTRL_CAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_CTRL_CAT_MASK)
5096 
5097 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CWT_MASK      (0x200U)
5098 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CWT_SHIFT     (9U)
5099 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CWT_WIDTH     (1U)
5100 #define GTM_gtm_cls3_MCS3_CH7_CTRL_CWT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_CTRL_CWT_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_CTRL_CWT_MASK)
5101 
5102 #define GTM_gtm_cls3_MCS3_CH7_CTRL_SAT_MASK      (0x400U)
5103 #define GTM_gtm_cls3_MCS3_CH7_CTRL_SAT_SHIFT     (10U)
5104 #define GTM_gtm_cls3_MCS3_CH7_CTRL_SAT_WIDTH     (1U)
5105 #define GTM_gtm_cls3_MCS3_CH7_CTRL_SAT(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_CTRL_SAT_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_CTRL_SAT_MASK)
5106 /*! @} */
5107 
5108 /*! @name MCS3_CH7_ACB - MCS[i] channel x ARU control Bit register */
5109 /*! @{ */
5110 
5111 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB0_MASK      (0x1U)
5112 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB0_SHIFT     (0U)
5113 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB0_WIDTH     (1U)
5114 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_ACB_ACB0_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_ACB_ACB0_MASK)
5115 
5116 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB1_MASK      (0x2U)
5117 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB1_SHIFT     (1U)
5118 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB1_WIDTH     (1U)
5119 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_ACB_ACB1_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_ACB_ACB1_MASK)
5120 
5121 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB2_MASK      (0x4U)
5122 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB2_SHIFT     (2U)
5123 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB2_WIDTH     (1U)
5124 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB2(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_ACB_ACB2_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_ACB_ACB2_MASK)
5125 
5126 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB3_MASK      (0x8U)
5127 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB3_SHIFT     (3U)
5128 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB3_WIDTH     (1U)
5129 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB3(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_ACB_ACB3_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_ACB_ACB3_MASK)
5130 
5131 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB4_MASK      (0x10U)
5132 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB4_SHIFT     (4U)
5133 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB4_WIDTH     (1U)
5134 #define GTM_gtm_cls3_MCS3_CH7_ACB_ACB4(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_ACB_ACB4_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_ACB_ACB4_MASK)
5135 /*! @} */
5136 
5137 /*! @name MCS3_CH7_MHB - MCS[i] channel x memory high byte register */
5138 /*! @{ */
5139 
5140 #define GTM_gtm_cls3_MCS3_CH7_MHB_DATA_MASK      (0xFFU)
5141 #define GTM_gtm_cls3_MCS3_CH7_MHB_DATA_SHIFT     (0U)
5142 #define GTM_gtm_cls3_MCS3_CH7_MHB_DATA_WIDTH     (8U)
5143 #define GTM_gtm_cls3_MCS3_CH7_MHB_DATA(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_MHB_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_MHB_DATA_MASK)
5144 /*! @} */
5145 
5146 /*! @name MCS3_CH7_PC - MCS[i] channel x program counter register */
5147 /*! @{ */
5148 
5149 #define GTM_gtm_cls3_MCS3_CH7_PC_PC_MASK         (0xFFFFU)
5150 #define GTM_gtm_cls3_MCS3_CH7_PC_PC_SHIFT        (0U)
5151 #define GTM_gtm_cls3_MCS3_CH7_PC_PC_WIDTH        (16U)
5152 #define GTM_gtm_cls3_MCS3_CH7_PC_PC(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_PC_PC_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_PC_PC_MASK)
5153 /*! @} */
5154 
5155 /*! @name MCS3_CH7_IRQ_NOTIFY - MCS[i] channel x interrupt notification register */
5156 /*! @{ */
5157 
5158 #define GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_MCS_IRQ_MASK (0x1U)
5159 #define GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_MCS_IRQ_SHIFT (0U)
5160 #define GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_MCS_IRQ_WIDTH (1U)
5161 #define GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_MCS_IRQ_MASK)
5162 
5163 #define GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_ERR_IRQ_MASK (0x4U)
5164 #define GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_ERR_IRQ_SHIFT (2U)
5165 #define GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_ERR_IRQ_WIDTH (1U)
5166 #define GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_IRQ_NOTIFY_ERR_IRQ_MASK)
5167 /*! @} */
5168 
5169 /*! @name MCS3_CH7_IRQ_EN - MCS[i] channel x interrupt enable register */
5170 /*! @{ */
5171 
5172 #define GTM_gtm_cls3_MCS3_CH7_IRQ_EN_MCS_IRQ_EN_MASK (0x1U)
5173 #define GTM_gtm_cls3_MCS3_CH7_IRQ_EN_MCS_IRQ_EN_SHIFT (0U)
5174 #define GTM_gtm_cls3_MCS3_CH7_IRQ_EN_MCS_IRQ_EN_WIDTH (1U)
5175 #define GTM_gtm_cls3_MCS3_CH7_IRQ_EN_MCS_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_IRQ_EN_MCS_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_IRQ_EN_MCS_IRQ_EN_MASK)
5176 
5177 #define GTM_gtm_cls3_MCS3_CH7_IRQ_EN_ERR_IRQ_EN_MASK (0x4U)
5178 #define GTM_gtm_cls3_MCS3_CH7_IRQ_EN_ERR_IRQ_EN_SHIFT (2U)
5179 #define GTM_gtm_cls3_MCS3_CH7_IRQ_EN_ERR_IRQ_EN_WIDTH (1U)
5180 #define GTM_gtm_cls3_MCS3_CH7_IRQ_EN_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_IRQ_EN_ERR_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_IRQ_EN_ERR_IRQ_EN_MASK)
5181 /*! @} */
5182 
5183 /*! @name MCS3_CH7_IRQ_FORCINT - MCS[i] channel x force interrupt register */
5184 /*! @{ */
5185 
5186 #define GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_MCS_IRQ_MASK (0x1U)
5187 #define GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT (0U)
5188 #define GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_MCS_IRQ_WIDTH (1U)
5189 #define GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_MCS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_MCS_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_MCS_IRQ_MASK)
5190 
5191 #define GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_ERR_IRQ_MASK (0x4U)
5192 #define GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT (2U)
5193 #define GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_ERR_IRQ_WIDTH (1U)
5194 #define GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_ERR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_ERR_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_IRQ_FORCINT_TRG_ERR_IRQ_MASK)
5195 /*! @} */
5196 
5197 /*! @name MCS3_CH7_IRQ_MODE - MCS[i] channel x IRQ mode configuration register */
5198 /*! @{ */
5199 
5200 #define GTM_gtm_cls3_MCS3_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U)
5201 #define GTM_gtm_cls3_MCS3_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U)
5202 #define GTM_gtm_cls3_MCS3_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U)
5203 #define GTM_gtm_cls3_MCS3_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_IRQ_MODE_IRQ_MODE_MASK)
5204 /*! @} */
5205 
5206 /*! @name MCS3_CH7_EIRQ_EN - MCS[i] channel x error interrupt enable register */
5207 /*! @{ */
5208 
5209 #define GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_MCS_EIRQ_EN_MASK (0x1U)
5210 #define GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_MCS_EIRQ_EN_SHIFT (0U)
5211 #define GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_MCS_EIRQ_EN_WIDTH (1U)
5212 #define GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_MCS_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_MCS_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_MCS_EIRQ_EN_MASK)
5213 
5214 #define GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_ERR_EIRQ_EN_MASK (0x4U)
5215 #define GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_ERR_EIRQ_EN_SHIFT (2U)
5216 #define GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_ERR_EIRQ_EN_WIDTH (1U)
5217 #define GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_ERR_EIRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_ERR_EIRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_CH7_EIRQ_EN_ERR_EIRQ_EN_MASK)
5218 /*! @} */
5219 
5220 /*! @name MCS3_CTRG - MCS[i] clear trigger control register */
5221 /*! @{ */
5222 
5223 #define GTM_gtm_cls3_MCS3_CTRG_TRG0_MASK         (0x1U)
5224 #define GTM_gtm_cls3_MCS3_CTRG_TRG0_SHIFT        (0U)
5225 #define GTM_gtm_cls3_MCS3_CTRG_TRG0_WIDTH        (1U)
5226 #define GTM_gtm_cls3_MCS3_CTRG_TRG0(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG0_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG0_MASK)
5227 
5228 #define GTM_gtm_cls3_MCS3_CTRG_TRG1_MASK         (0x2U)
5229 #define GTM_gtm_cls3_MCS3_CTRG_TRG1_SHIFT        (1U)
5230 #define GTM_gtm_cls3_MCS3_CTRG_TRG1_WIDTH        (1U)
5231 #define GTM_gtm_cls3_MCS3_CTRG_TRG1(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG1_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG1_MASK)
5232 
5233 #define GTM_gtm_cls3_MCS3_CTRG_TRG2_MASK         (0x4U)
5234 #define GTM_gtm_cls3_MCS3_CTRG_TRG2_SHIFT        (2U)
5235 #define GTM_gtm_cls3_MCS3_CTRG_TRG2_WIDTH        (1U)
5236 #define GTM_gtm_cls3_MCS3_CTRG_TRG2(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG2_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG2_MASK)
5237 
5238 #define GTM_gtm_cls3_MCS3_CTRG_TRG3_MASK         (0x8U)
5239 #define GTM_gtm_cls3_MCS3_CTRG_TRG3_SHIFT        (3U)
5240 #define GTM_gtm_cls3_MCS3_CTRG_TRG3_WIDTH        (1U)
5241 #define GTM_gtm_cls3_MCS3_CTRG_TRG3(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG3_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG3_MASK)
5242 
5243 #define GTM_gtm_cls3_MCS3_CTRG_TRG4_MASK         (0x10U)
5244 #define GTM_gtm_cls3_MCS3_CTRG_TRG4_SHIFT        (4U)
5245 #define GTM_gtm_cls3_MCS3_CTRG_TRG4_WIDTH        (1U)
5246 #define GTM_gtm_cls3_MCS3_CTRG_TRG4(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG4_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG4_MASK)
5247 
5248 #define GTM_gtm_cls3_MCS3_CTRG_TRG5_MASK         (0x20U)
5249 #define GTM_gtm_cls3_MCS3_CTRG_TRG5_SHIFT        (5U)
5250 #define GTM_gtm_cls3_MCS3_CTRG_TRG5_WIDTH        (1U)
5251 #define GTM_gtm_cls3_MCS3_CTRG_TRG5(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG5_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG5_MASK)
5252 
5253 #define GTM_gtm_cls3_MCS3_CTRG_TRG6_MASK         (0x40U)
5254 #define GTM_gtm_cls3_MCS3_CTRG_TRG6_SHIFT        (6U)
5255 #define GTM_gtm_cls3_MCS3_CTRG_TRG6_WIDTH        (1U)
5256 #define GTM_gtm_cls3_MCS3_CTRG_TRG6(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG6_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG6_MASK)
5257 
5258 #define GTM_gtm_cls3_MCS3_CTRG_TRG7_MASK         (0x80U)
5259 #define GTM_gtm_cls3_MCS3_CTRG_TRG7_SHIFT        (7U)
5260 #define GTM_gtm_cls3_MCS3_CTRG_TRG7_WIDTH        (1U)
5261 #define GTM_gtm_cls3_MCS3_CTRG_TRG7(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG7_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG7_MASK)
5262 
5263 #define GTM_gtm_cls3_MCS3_CTRG_TRG8_MASK         (0x100U)
5264 #define GTM_gtm_cls3_MCS3_CTRG_TRG8_SHIFT        (8U)
5265 #define GTM_gtm_cls3_MCS3_CTRG_TRG8_WIDTH        (1U)
5266 #define GTM_gtm_cls3_MCS3_CTRG_TRG8(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG8_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG8_MASK)
5267 
5268 #define GTM_gtm_cls3_MCS3_CTRG_TRG9_MASK         (0x200U)
5269 #define GTM_gtm_cls3_MCS3_CTRG_TRG9_SHIFT        (9U)
5270 #define GTM_gtm_cls3_MCS3_CTRG_TRG9_WIDTH        (1U)
5271 #define GTM_gtm_cls3_MCS3_CTRG_TRG9(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG9_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG9_MASK)
5272 
5273 #define GTM_gtm_cls3_MCS3_CTRG_TRG10_MASK        (0x400U)
5274 #define GTM_gtm_cls3_MCS3_CTRG_TRG10_SHIFT       (10U)
5275 #define GTM_gtm_cls3_MCS3_CTRG_TRG10_WIDTH       (1U)
5276 #define GTM_gtm_cls3_MCS3_CTRG_TRG10(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG10_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG10_MASK)
5277 
5278 #define GTM_gtm_cls3_MCS3_CTRG_TRG11_MASK        (0x800U)
5279 #define GTM_gtm_cls3_MCS3_CTRG_TRG11_SHIFT       (11U)
5280 #define GTM_gtm_cls3_MCS3_CTRG_TRG11_WIDTH       (1U)
5281 #define GTM_gtm_cls3_MCS3_CTRG_TRG11(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG11_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG11_MASK)
5282 
5283 #define GTM_gtm_cls3_MCS3_CTRG_TRG12_MASK        (0x1000U)
5284 #define GTM_gtm_cls3_MCS3_CTRG_TRG12_SHIFT       (12U)
5285 #define GTM_gtm_cls3_MCS3_CTRG_TRG12_WIDTH       (1U)
5286 #define GTM_gtm_cls3_MCS3_CTRG_TRG12(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG12_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG12_MASK)
5287 
5288 #define GTM_gtm_cls3_MCS3_CTRG_TRG13_MASK        (0x2000U)
5289 #define GTM_gtm_cls3_MCS3_CTRG_TRG13_SHIFT       (13U)
5290 #define GTM_gtm_cls3_MCS3_CTRG_TRG13_WIDTH       (1U)
5291 #define GTM_gtm_cls3_MCS3_CTRG_TRG13(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG13_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG13_MASK)
5292 
5293 #define GTM_gtm_cls3_MCS3_CTRG_TRG14_MASK        (0x4000U)
5294 #define GTM_gtm_cls3_MCS3_CTRG_TRG14_SHIFT       (14U)
5295 #define GTM_gtm_cls3_MCS3_CTRG_TRG14_WIDTH       (1U)
5296 #define GTM_gtm_cls3_MCS3_CTRG_TRG14(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG14_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG14_MASK)
5297 
5298 #define GTM_gtm_cls3_MCS3_CTRG_TRG15_MASK        (0x8000U)
5299 #define GTM_gtm_cls3_MCS3_CTRG_TRG15_SHIFT       (15U)
5300 #define GTM_gtm_cls3_MCS3_CTRG_TRG15_WIDTH       (1U)
5301 #define GTM_gtm_cls3_MCS3_CTRG_TRG15(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG15_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG15_MASK)
5302 
5303 #define GTM_gtm_cls3_MCS3_CTRG_TRG16_MASK        (0x10000U)
5304 #define GTM_gtm_cls3_MCS3_CTRG_TRG16_SHIFT       (16U)
5305 #define GTM_gtm_cls3_MCS3_CTRG_TRG16_WIDTH       (1U)
5306 #define GTM_gtm_cls3_MCS3_CTRG_TRG16(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG16_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG16_MASK)
5307 
5308 #define GTM_gtm_cls3_MCS3_CTRG_TRG17_MASK        (0x20000U)
5309 #define GTM_gtm_cls3_MCS3_CTRG_TRG17_SHIFT       (17U)
5310 #define GTM_gtm_cls3_MCS3_CTRG_TRG17_WIDTH       (1U)
5311 #define GTM_gtm_cls3_MCS3_CTRG_TRG17(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG17_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG17_MASK)
5312 
5313 #define GTM_gtm_cls3_MCS3_CTRG_TRG18_MASK        (0x40000U)
5314 #define GTM_gtm_cls3_MCS3_CTRG_TRG18_SHIFT       (18U)
5315 #define GTM_gtm_cls3_MCS3_CTRG_TRG18_WIDTH       (1U)
5316 #define GTM_gtm_cls3_MCS3_CTRG_TRG18(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG18_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG18_MASK)
5317 
5318 #define GTM_gtm_cls3_MCS3_CTRG_TRG19_MASK        (0x80000U)
5319 #define GTM_gtm_cls3_MCS3_CTRG_TRG19_SHIFT       (19U)
5320 #define GTM_gtm_cls3_MCS3_CTRG_TRG19_WIDTH       (1U)
5321 #define GTM_gtm_cls3_MCS3_CTRG_TRG19(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG19_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG19_MASK)
5322 
5323 #define GTM_gtm_cls3_MCS3_CTRG_TRG20_MASK        (0x100000U)
5324 #define GTM_gtm_cls3_MCS3_CTRG_TRG20_SHIFT       (20U)
5325 #define GTM_gtm_cls3_MCS3_CTRG_TRG20_WIDTH       (1U)
5326 #define GTM_gtm_cls3_MCS3_CTRG_TRG20(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG20_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG20_MASK)
5327 
5328 #define GTM_gtm_cls3_MCS3_CTRG_TRG21_MASK        (0x200000U)
5329 #define GTM_gtm_cls3_MCS3_CTRG_TRG21_SHIFT       (21U)
5330 #define GTM_gtm_cls3_MCS3_CTRG_TRG21_WIDTH       (1U)
5331 #define GTM_gtm_cls3_MCS3_CTRG_TRG21(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG21_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG21_MASK)
5332 
5333 #define GTM_gtm_cls3_MCS3_CTRG_TRG22_MASK        (0x400000U)
5334 #define GTM_gtm_cls3_MCS3_CTRG_TRG22_SHIFT       (22U)
5335 #define GTM_gtm_cls3_MCS3_CTRG_TRG22_WIDTH       (1U)
5336 #define GTM_gtm_cls3_MCS3_CTRG_TRG22(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG22_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG22_MASK)
5337 
5338 #define GTM_gtm_cls3_MCS3_CTRG_TRG23_MASK        (0x800000U)
5339 #define GTM_gtm_cls3_MCS3_CTRG_TRG23_SHIFT       (23U)
5340 #define GTM_gtm_cls3_MCS3_CTRG_TRG23_WIDTH       (1U)
5341 #define GTM_gtm_cls3_MCS3_CTRG_TRG23(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRG_TRG23_SHIFT)) & GTM_gtm_cls3_MCS3_CTRG_TRG23_MASK)
5342 /*! @} */
5343 
5344 /*! @name MCS3_STRG - MCS[i] set trigger control register */
5345 /*! @{ */
5346 
5347 #define GTM_gtm_cls3_MCS3_STRG_TRG0_MASK         (0x1U)
5348 #define GTM_gtm_cls3_MCS3_STRG_TRG0_SHIFT        (0U)
5349 #define GTM_gtm_cls3_MCS3_STRG_TRG0_WIDTH        (1U)
5350 #define GTM_gtm_cls3_MCS3_STRG_TRG0(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG0_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG0_MASK)
5351 
5352 #define GTM_gtm_cls3_MCS3_STRG_TRG1_MASK         (0x2U)
5353 #define GTM_gtm_cls3_MCS3_STRG_TRG1_SHIFT        (1U)
5354 #define GTM_gtm_cls3_MCS3_STRG_TRG1_WIDTH        (1U)
5355 #define GTM_gtm_cls3_MCS3_STRG_TRG1(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG1_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG1_MASK)
5356 
5357 #define GTM_gtm_cls3_MCS3_STRG_TRG2_MASK         (0x4U)
5358 #define GTM_gtm_cls3_MCS3_STRG_TRG2_SHIFT        (2U)
5359 #define GTM_gtm_cls3_MCS3_STRG_TRG2_WIDTH        (1U)
5360 #define GTM_gtm_cls3_MCS3_STRG_TRG2(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG2_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG2_MASK)
5361 
5362 #define GTM_gtm_cls3_MCS3_STRG_TRG3_MASK         (0x8U)
5363 #define GTM_gtm_cls3_MCS3_STRG_TRG3_SHIFT        (3U)
5364 #define GTM_gtm_cls3_MCS3_STRG_TRG3_WIDTH        (1U)
5365 #define GTM_gtm_cls3_MCS3_STRG_TRG3(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG3_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG3_MASK)
5366 
5367 #define GTM_gtm_cls3_MCS3_STRG_TRG4_MASK         (0x10U)
5368 #define GTM_gtm_cls3_MCS3_STRG_TRG4_SHIFT        (4U)
5369 #define GTM_gtm_cls3_MCS3_STRG_TRG4_WIDTH        (1U)
5370 #define GTM_gtm_cls3_MCS3_STRG_TRG4(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG4_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG4_MASK)
5371 
5372 #define GTM_gtm_cls3_MCS3_STRG_TRG5_MASK         (0x20U)
5373 #define GTM_gtm_cls3_MCS3_STRG_TRG5_SHIFT        (5U)
5374 #define GTM_gtm_cls3_MCS3_STRG_TRG5_WIDTH        (1U)
5375 #define GTM_gtm_cls3_MCS3_STRG_TRG5(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG5_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG5_MASK)
5376 
5377 #define GTM_gtm_cls3_MCS3_STRG_TRG6_MASK         (0x40U)
5378 #define GTM_gtm_cls3_MCS3_STRG_TRG6_SHIFT        (6U)
5379 #define GTM_gtm_cls3_MCS3_STRG_TRG6_WIDTH        (1U)
5380 #define GTM_gtm_cls3_MCS3_STRG_TRG6(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG6_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG6_MASK)
5381 
5382 #define GTM_gtm_cls3_MCS3_STRG_TRG7_MASK         (0x80U)
5383 #define GTM_gtm_cls3_MCS3_STRG_TRG7_SHIFT        (7U)
5384 #define GTM_gtm_cls3_MCS3_STRG_TRG7_WIDTH        (1U)
5385 #define GTM_gtm_cls3_MCS3_STRG_TRG7(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG7_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG7_MASK)
5386 
5387 #define GTM_gtm_cls3_MCS3_STRG_TRG8_MASK         (0x100U)
5388 #define GTM_gtm_cls3_MCS3_STRG_TRG8_SHIFT        (8U)
5389 #define GTM_gtm_cls3_MCS3_STRG_TRG8_WIDTH        (1U)
5390 #define GTM_gtm_cls3_MCS3_STRG_TRG8(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG8_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG8_MASK)
5391 
5392 #define GTM_gtm_cls3_MCS3_STRG_TRG9_MASK         (0x200U)
5393 #define GTM_gtm_cls3_MCS3_STRG_TRG9_SHIFT        (9U)
5394 #define GTM_gtm_cls3_MCS3_STRG_TRG9_WIDTH        (1U)
5395 #define GTM_gtm_cls3_MCS3_STRG_TRG9(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG9_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG9_MASK)
5396 
5397 #define GTM_gtm_cls3_MCS3_STRG_TRG10_MASK        (0x400U)
5398 #define GTM_gtm_cls3_MCS3_STRG_TRG10_SHIFT       (10U)
5399 #define GTM_gtm_cls3_MCS3_STRG_TRG10_WIDTH       (1U)
5400 #define GTM_gtm_cls3_MCS3_STRG_TRG10(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG10_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG10_MASK)
5401 
5402 #define GTM_gtm_cls3_MCS3_STRG_TRG11_MASK        (0x800U)
5403 #define GTM_gtm_cls3_MCS3_STRG_TRG11_SHIFT       (11U)
5404 #define GTM_gtm_cls3_MCS3_STRG_TRG11_WIDTH       (1U)
5405 #define GTM_gtm_cls3_MCS3_STRG_TRG11(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG11_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG11_MASK)
5406 
5407 #define GTM_gtm_cls3_MCS3_STRG_TRG12_MASK        (0x1000U)
5408 #define GTM_gtm_cls3_MCS3_STRG_TRG12_SHIFT       (12U)
5409 #define GTM_gtm_cls3_MCS3_STRG_TRG12_WIDTH       (1U)
5410 #define GTM_gtm_cls3_MCS3_STRG_TRG12(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG12_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG12_MASK)
5411 
5412 #define GTM_gtm_cls3_MCS3_STRG_TRG13_MASK        (0x2000U)
5413 #define GTM_gtm_cls3_MCS3_STRG_TRG13_SHIFT       (13U)
5414 #define GTM_gtm_cls3_MCS3_STRG_TRG13_WIDTH       (1U)
5415 #define GTM_gtm_cls3_MCS3_STRG_TRG13(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG13_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG13_MASK)
5416 
5417 #define GTM_gtm_cls3_MCS3_STRG_TRG14_MASK        (0x4000U)
5418 #define GTM_gtm_cls3_MCS3_STRG_TRG14_SHIFT       (14U)
5419 #define GTM_gtm_cls3_MCS3_STRG_TRG14_WIDTH       (1U)
5420 #define GTM_gtm_cls3_MCS3_STRG_TRG14(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG14_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG14_MASK)
5421 
5422 #define GTM_gtm_cls3_MCS3_STRG_TRG15_MASK        (0x8000U)
5423 #define GTM_gtm_cls3_MCS3_STRG_TRG15_SHIFT       (15U)
5424 #define GTM_gtm_cls3_MCS3_STRG_TRG15_WIDTH       (1U)
5425 #define GTM_gtm_cls3_MCS3_STRG_TRG15(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG15_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG15_MASK)
5426 
5427 #define GTM_gtm_cls3_MCS3_STRG_TRG16_MASK        (0x10000U)
5428 #define GTM_gtm_cls3_MCS3_STRG_TRG16_SHIFT       (16U)
5429 #define GTM_gtm_cls3_MCS3_STRG_TRG16_WIDTH       (1U)
5430 #define GTM_gtm_cls3_MCS3_STRG_TRG16(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG16_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG16_MASK)
5431 
5432 #define GTM_gtm_cls3_MCS3_STRG_TRG17_MASK        (0x20000U)
5433 #define GTM_gtm_cls3_MCS3_STRG_TRG17_SHIFT       (17U)
5434 #define GTM_gtm_cls3_MCS3_STRG_TRG17_WIDTH       (1U)
5435 #define GTM_gtm_cls3_MCS3_STRG_TRG17(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG17_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG17_MASK)
5436 
5437 #define GTM_gtm_cls3_MCS3_STRG_TRG18_MASK        (0x40000U)
5438 #define GTM_gtm_cls3_MCS3_STRG_TRG18_SHIFT       (18U)
5439 #define GTM_gtm_cls3_MCS3_STRG_TRG18_WIDTH       (1U)
5440 #define GTM_gtm_cls3_MCS3_STRG_TRG18(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG18_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG18_MASK)
5441 
5442 #define GTM_gtm_cls3_MCS3_STRG_TRG19_MASK        (0x80000U)
5443 #define GTM_gtm_cls3_MCS3_STRG_TRG19_SHIFT       (19U)
5444 #define GTM_gtm_cls3_MCS3_STRG_TRG19_WIDTH       (1U)
5445 #define GTM_gtm_cls3_MCS3_STRG_TRG19(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG19_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG19_MASK)
5446 
5447 #define GTM_gtm_cls3_MCS3_STRG_TRG20_MASK        (0x100000U)
5448 #define GTM_gtm_cls3_MCS3_STRG_TRG20_SHIFT       (20U)
5449 #define GTM_gtm_cls3_MCS3_STRG_TRG20_WIDTH       (1U)
5450 #define GTM_gtm_cls3_MCS3_STRG_TRG20(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG20_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG20_MASK)
5451 
5452 #define GTM_gtm_cls3_MCS3_STRG_TRG21_MASK        (0x200000U)
5453 #define GTM_gtm_cls3_MCS3_STRG_TRG21_SHIFT       (21U)
5454 #define GTM_gtm_cls3_MCS3_STRG_TRG21_WIDTH       (1U)
5455 #define GTM_gtm_cls3_MCS3_STRG_TRG21(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG21_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG21_MASK)
5456 
5457 #define GTM_gtm_cls3_MCS3_STRG_TRG22_MASK        (0x400000U)
5458 #define GTM_gtm_cls3_MCS3_STRG_TRG22_SHIFT       (22U)
5459 #define GTM_gtm_cls3_MCS3_STRG_TRG22_WIDTH       (1U)
5460 #define GTM_gtm_cls3_MCS3_STRG_TRG22(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG22_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG22_MASK)
5461 
5462 #define GTM_gtm_cls3_MCS3_STRG_TRG23_MASK        (0x800000U)
5463 #define GTM_gtm_cls3_MCS3_STRG_TRG23_SHIFT       (23U)
5464 #define GTM_gtm_cls3_MCS3_STRG_TRG23_WIDTH       (1U)
5465 #define GTM_gtm_cls3_MCS3_STRG_TRG23(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_STRG_TRG23_SHIFT)) & GTM_gtm_cls3_MCS3_STRG_TRG23_MASK)
5466 /*! @} */
5467 
5468 /*! @name MCS3_CTRL_STAT - MCS[i] control and status register */
5469 /*! @{ */
5470 
5471 #define GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_MODE_MASK (0x3U)
5472 #define GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_MODE_SHIFT (0U)
5473 #define GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_MODE_WIDTH (2U)
5474 #define GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_MODE(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_MODE_MASK)
5475 
5476 #define GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_CH_MASK  (0xF00U)
5477 #define GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_CH_SHIFT (8U)
5478 #define GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_CH_WIDTH (4U)
5479 #define GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_CH(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_CH_SHIFT)) & GTM_gtm_cls3_MCS3_CTRL_STAT_SCD_CH_MASK)
5480 
5481 #define GTM_gtm_cls3_MCS3_CTRL_STAT_RAM_RST_MASK (0x10000U)
5482 #define GTM_gtm_cls3_MCS3_CTRL_STAT_RAM_RST_SHIFT (16U)
5483 #define GTM_gtm_cls3_MCS3_CTRL_STAT_RAM_RST_WIDTH (1U)
5484 #define GTM_gtm_cls3_MCS3_CTRL_STAT_RAM_RST(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRL_STAT_RAM_RST_SHIFT)) & GTM_gtm_cls3_MCS3_CTRL_STAT_RAM_RST_MASK)
5485 
5486 #define GTM_gtm_cls3_MCS3_CTRL_STAT_ERR_SRC_ID_MASK (0x700000U)
5487 #define GTM_gtm_cls3_MCS3_CTRL_STAT_ERR_SRC_ID_SHIFT (20U)
5488 #define GTM_gtm_cls3_MCS3_CTRL_STAT_ERR_SRC_ID_WIDTH (3U)
5489 #define GTM_gtm_cls3_MCS3_CTRL_STAT_ERR_SRC_ID(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRL_STAT_ERR_SRC_ID_SHIFT)) & GTM_gtm_cls3_MCS3_CTRL_STAT_ERR_SRC_ID_MASK)
5490 
5491 #define GTM_gtm_cls3_MCS3_CTRL_STAT_EN_TIM_FOUT_MASK (0x1000000U)
5492 #define GTM_gtm_cls3_MCS3_CTRL_STAT_EN_TIM_FOUT_SHIFT (24U)
5493 #define GTM_gtm_cls3_MCS3_CTRL_STAT_EN_TIM_FOUT_WIDTH (1U)
5494 #define GTM_gtm_cls3_MCS3_CTRL_STAT_EN_TIM_FOUT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRL_STAT_EN_TIM_FOUT_SHIFT)) & GTM_gtm_cls3_MCS3_CTRL_STAT_EN_TIM_FOUT_MASK)
5495 
5496 #define GTM_gtm_cls3_MCS3_CTRL_STAT_EN_HVD_MASK  (0x2000000U)
5497 #define GTM_gtm_cls3_MCS3_CTRL_STAT_EN_HVD_SHIFT (25U)
5498 #define GTM_gtm_cls3_MCS3_CTRL_STAT_EN_HVD_WIDTH (1U)
5499 #define GTM_gtm_cls3_MCS3_CTRL_STAT_EN_HVD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRL_STAT_EN_HVD_SHIFT)) & GTM_gtm_cls3_MCS3_CTRL_STAT_EN_HVD_MASK)
5500 
5501 #define GTM_gtm_cls3_MCS3_CTRL_STAT_HLT_AEIM_ERR_MASK (0x4000000U)
5502 #define GTM_gtm_cls3_MCS3_CTRL_STAT_HLT_AEIM_ERR_SHIFT (26U)
5503 #define GTM_gtm_cls3_MCS3_CTRL_STAT_HLT_AEIM_ERR_WIDTH (1U)
5504 #define GTM_gtm_cls3_MCS3_CTRL_STAT_HLT_AEIM_ERR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CTRL_STAT_HLT_AEIM_ERR_SHIFT)) & GTM_gtm_cls3_MCS3_CTRL_STAT_HLT_AEIM_ERR_MASK)
5505 /*! @} */
5506 
5507 /*! @name MCS3_RESET - MCS[i] reset register */
5508 /*! @{ */
5509 
5510 #define GTM_gtm_cls3_MCS3_RESET_RST0_MASK        (0x1U)
5511 #define GTM_gtm_cls3_MCS3_RESET_RST0_SHIFT       (0U)
5512 #define GTM_gtm_cls3_MCS3_RESET_RST0_WIDTH       (1U)
5513 #define GTM_gtm_cls3_MCS3_RESET_RST0(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_RESET_RST0_SHIFT)) & GTM_gtm_cls3_MCS3_RESET_RST0_MASK)
5514 
5515 #define GTM_gtm_cls3_MCS3_RESET_RST1_MASK        (0x2U)
5516 #define GTM_gtm_cls3_MCS3_RESET_RST1_SHIFT       (1U)
5517 #define GTM_gtm_cls3_MCS3_RESET_RST1_WIDTH       (1U)
5518 #define GTM_gtm_cls3_MCS3_RESET_RST1(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_RESET_RST1_SHIFT)) & GTM_gtm_cls3_MCS3_RESET_RST1_MASK)
5519 
5520 #define GTM_gtm_cls3_MCS3_RESET_RST2_MASK        (0x4U)
5521 #define GTM_gtm_cls3_MCS3_RESET_RST2_SHIFT       (2U)
5522 #define GTM_gtm_cls3_MCS3_RESET_RST2_WIDTH       (1U)
5523 #define GTM_gtm_cls3_MCS3_RESET_RST2(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_RESET_RST2_SHIFT)) & GTM_gtm_cls3_MCS3_RESET_RST2_MASK)
5524 
5525 #define GTM_gtm_cls3_MCS3_RESET_RST3_MASK        (0x8U)
5526 #define GTM_gtm_cls3_MCS3_RESET_RST3_SHIFT       (3U)
5527 #define GTM_gtm_cls3_MCS3_RESET_RST3_WIDTH       (1U)
5528 #define GTM_gtm_cls3_MCS3_RESET_RST3(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_RESET_RST3_SHIFT)) & GTM_gtm_cls3_MCS3_RESET_RST3_MASK)
5529 
5530 #define GTM_gtm_cls3_MCS3_RESET_RST4_MASK        (0x10U)
5531 #define GTM_gtm_cls3_MCS3_RESET_RST4_SHIFT       (4U)
5532 #define GTM_gtm_cls3_MCS3_RESET_RST4_WIDTH       (1U)
5533 #define GTM_gtm_cls3_MCS3_RESET_RST4(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_RESET_RST4_SHIFT)) & GTM_gtm_cls3_MCS3_RESET_RST4_MASK)
5534 
5535 #define GTM_gtm_cls3_MCS3_RESET_RST5_MASK        (0x20U)
5536 #define GTM_gtm_cls3_MCS3_RESET_RST5_SHIFT       (5U)
5537 #define GTM_gtm_cls3_MCS3_RESET_RST5_WIDTH       (1U)
5538 #define GTM_gtm_cls3_MCS3_RESET_RST5(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_RESET_RST5_SHIFT)) & GTM_gtm_cls3_MCS3_RESET_RST5_MASK)
5539 
5540 #define GTM_gtm_cls3_MCS3_RESET_RST6_MASK        (0x40U)
5541 #define GTM_gtm_cls3_MCS3_RESET_RST6_SHIFT       (6U)
5542 #define GTM_gtm_cls3_MCS3_RESET_RST6_WIDTH       (1U)
5543 #define GTM_gtm_cls3_MCS3_RESET_RST6(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_RESET_RST6_SHIFT)) & GTM_gtm_cls3_MCS3_RESET_RST6_MASK)
5544 
5545 #define GTM_gtm_cls3_MCS3_RESET_RST7_MASK        (0x80U)
5546 #define GTM_gtm_cls3_MCS3_RESET_RST7_SHIFT       (7U)
5547 #define GTM_gtm_cls3_MCS3_RESET_RST7_WIDTH       (1U)
5548 #define GTM_gtm_cls3_MCS3_RESET_RST7(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_RESET_RST7_SHIFT)) & GTM_gtm_cls3_MCS3_RESET_RST7_MASK)
5549 /*! @} */
5550 
5551 /*! @name MCS3_CAT - MCS[i] cancel ARU transfer instruction */
5552 /*! @{ */
5553 
5554 #define GTM_gtm_cls3_MCS3_CAT_CAT0_MASK          (0x1U)
5555 #define GTM_gtm_cls3_MCS3_CAT_CAT0_SHIFT         (0U)
5556 #define GTM_gtm_cls3_MCS3_CAT_CAT0_WIDTH         (1U)
5557 #define GTM_gtm_cls3_MCS3_CAT_CAT0(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CAT_CAT0_SHIFT)) & GTM_gtm_cls3_MCS3_CAT_CAT0_MASK)
5558 
5559 #define GTM_gtm_cls3_MCS3_CAT_CAT1_MASK          (0x2U)
5560 #define GTM_gtm_cls3_MCS3_CAT_CAT1_SHIFT         (1U)
5561 #define GTM_gtm_cls3_MCS3_CAT_CAT1_WIDTH         (1U)
5562 #define GTM_gtm_cls3_MCS3_CAT_CAT1(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CAT_CAT1_SHIFT)) & GTM_gtm_cls3_MCS3_CAT_CAT1_MASK)
5563 
5564 #define GTM_gtm_cls3_MCS3_CAT_CAT2_MASK          (0x4U)
5565 #define GTM_gtm_cls3_MCS3_CAT_CAT2_SHIFT         (2U)
5566 #define GTM_gtm_cls3_MCS3_CAT_CAT2_WIDTH         (1U)
5567 #define GTM_gtm_cls3_MCS3_CAT_CAT2(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CAT_CAT2_SHIFT)) & GTM_gtm_cls3_MCS3_CAT_CAT2_MASK)
5568 
5569 #define GTM_gtm_cls3_MCS3_CAT_CAT3_MASK          (0x8U)
5570 #define GTM_gtm_cls3_MCS3_CAT_CAT3_SHIFT         (3U)
5571 #define GTM_gtm_cls3_MCS3_CAT_CAT3_WIDTH         (1U)
5572 #define GTM_gtm_cls3_MCS3_CAT_CAT3(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CAT_CAT3_SHIFT)) & GTM_gtm_cls3_MCS3_CAT_CAT3_MASK)
5573 
5574 #define GTM_gtm_cls3_MCS3_CAT_CAT4_MASK          (0x10U)
5575 #define GTM_gtm_cls3_MCS3_CAT_CAT4_SHIFT         (4U)
5576 #define GTM_gtm_cls3_MCS3_CAT_CAT4_WIDTH         (1U)
5577 #define GTM_gtm_cls3_MCS3_CAT_CAT4(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CAT_CAT4_SHIFT)) & GTM_gtm_cls3_MCS3_CAT_CAT4_MASK)
5578 
5579 #define GTM_gtm_cls3_MCS3_CAT_CAT5_MASK          (0x20U)
5580 #define GTM_gtm_cls3_MCS3_CAT_CAT5_SHIFT         (5U)
5581 #define GTM_gtm_cls3_MCS3_CAT_CAT5_WIDTH         (1U)
5582 #define GTM_gtm_cls3_MCS3_CAT_CAT5(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CAT_CAT5_SHIFT)) & GTM_gtm_cls3_MCS3_CAT_CAT5_MASK)
5583 
5584 #define GTM_gtm_cls3_MCS3_CAT_CAT6_MASK          (0x40U)
5585 #define GTM_gtm_cls3_MCS3_CAT_CAT6_SHIFT         (6U)
5586 #define GTM_gtm_cls3_MCS3_CAT_CAT6_WIDTH         (1U)
5587 #define GTM_gtm_cls3_MCS3_CAT_CAT6(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CAT_CAT6_SHIFT)) & GTM_gtm_cls3_MCS3_CAT_CAT6_MASK)
5588 
5589 #define GTM_gtm_cls3_MCS3_CAT_CAT7_MASK          (0x80U)
5590 #define GTM_gtm_cls3_MCS3_CAT_CAT7_SHIFT         (7U)
5591 #define GTM_gtm_cls3_MCS3_CAT_CAT7_WIDTH         (1U)
5592 #define GTM_gtm_cls3_MCS3_CAT_CAT7(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CAT_CAT7_SHIFT)) & GTM_gtm_cls3_MCS3_CAT_CAT7_MASK)
5593 /*! @} */
5594 
5595 /*! @name MCS3_CWT - MCS[i] cancel waiting instruction */
5596 /*! @{ */
5597 
5598 #define GTM_gtm_cls3_MCS3_CWT_CWT0_MASK          (0x1U)
5599 #define GTM_gtm_cls3_MCS3_CWT_CWT0_SHIFT         (0U)
5600 #define GTM_gtm_cls3_MCS3_CWT_CWT0_WIDTH         (1U)
5601 #define GTM_gtm_cls3_MCS3_CWT_CWT0(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CWT_CWT0_SHIFT)) & GTM_gtm_cls3_MCS3_CWT_CWT0_MASK)
5602 
5603 #define GTM_gtm_cls3_MCS3_CWT_CWT1_MASK          (0x2U)
5604 #define GTM_gtm_cls3_MCS3_CWT_CWT1_SHIFT         (1U)
5605 #define GTM_gtm_cls3_MCS3_CWT_CWT1_WIDTH         (1U)
5606 #define GTM_gtm_cls3_MCS3_CWT_CWT1(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CWT_CWT1_SHIFT)) & GTM_gtm_cls3_MCS3_CWT_CWT1_MASK)
5607 
5608 #define GTM_gtm_cls3_MCS3_CWT_CWT2_MASK          (0x4U)
5609 #define GTM_gtm_cls3_MCS3_CWT_CWT2_SHIFT         (2U)
5610 #define GTM_gtm_cls3_MCS3_CWT_CWT2_WIDTH         (1U)
5611 #define GTM_gtm_cls3_MCS3_CWT_CWT2(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CWT_CWT2_SHIFT)) & GTM_gtm_cls3_MCS3_CWT_CWT2_MASK)
5612 
5613 #define GTM_gtm_cls3_MCS3_CWT_CWT3_MASK          (0x8U)
5614 #define GTM_gtm_cls3_MCS3_CWT_CWT3_SHIFT         (3U)
5615 #define GTM_gtm_cls3_MCS3_CWT_CWT3_WIDTH         (1U)
5616 #define GTM_gtm_cls3_MCS3_CWT_CWT3(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CWT_CWT3_SHIFT)) & GTM_gtm_cls3_MCS3_CWT_CWT3_MASK)
5617 
5618 #define GTM_gtm_cls3_MCS3_CWT_CWT4_MASK          (0x10U)
5619 #define GTM_gtm_cls3_MCS3_CWT_CWT4_SHIFT         (4U)
5620 #define GTM_gtm_cls3_MCS3_CWT_CWT4_WIDTH         (1U)
5621 #define GTM_gtm_cls3_MCS3_CWT_CWT4(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CWT_CWT4_SHIFT)) & GTM_gtm_cls3_MCS3_CWT_CWT4_MASK)
5622 
5623 #define GTM_gtm_cls3_MCS3_CWT_CWT5_MASK          (0x20U)
5624 #define GTM_gtm_cls3_MCS3_CWT_CWT5_SHIFT         (5U)
5625 #define GTM_gtm_cls3_MCS3_CWT_CWT5_WIDTH         (1U)
5626 #define GTM_gtm_cls3_MCS3_CWT_CWT5(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CWT_CWT5_SHIFT)) & GTM_gtm_cls3_MCS3_CWT_CWT5_MASK)
5627 
5628 #define GTM_gtm_cls3_MCS3_CWT_CWT6_MASK          (0x40U)
5629 #define GTM_gtm_cls3_MCS3_CWT_CWT6_SHIFT         (6U)
5630 #define GTM_gtm_cls3_MCS3_CWT_CWT6_WIDTH         (1U)
5631 #define GTM_gtm_cls3_MCS3_CWT_CWT6(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CWT_CWT6_SHIFT)) & GTM_gtm_cls3_MCS3_CWT_CWT6_MASK)
5632 
5633 #define GTM_gtm_cls3_MCS3_CWT_CWT7_MASK          (0x80U)
5634 #define GTM_gtm_cls3_MCS3_CWT_CWT7_SHIFT         (7U)
5635 #define GTM_gtm_cls3_MCS3_CWT_CWT7_WIDTH         (1U)
5636 #define GTM_gtm_cls3_MCS3_CWT_CWT7(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_CWT_CWT7_SHIFT)) & GTM_gtm_cls3_MCS3_CWT_CWT7_MASK)
5637 /*! @} */
5638 
5639 /*! @name MCS3_ERR - MCS[i] error register */
5640 /*! @{ */
5641 
5642 #define GTM_gtm_cls3_MCS3_ERR_ERR0_MASK          (0x1U)
5643 #define GTM_gtm_cls3_MCS3_ERR_ERR0_SHIFT         (0U)
5644 #define GTM_gtm_cls3_MCS3_ERR_ERR0_WIDTH         (1U)
5645 #define GTM_gtm_cls3_MCS3_ERR_ERR0(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_ERR_ERR0_SHIFT)) & GTM_gtm_cls3_MCS3_ERR_ERR0_MASK)
5646 
5647 #define GTM_gtm_cls3_MCS3_ERR_ERR1_MASK          (0x2U)
5648 #define GTM_gtm_cls3_MCS3_ERR_ERR1_SHIFT         (1U)
5649 #define GTM_gtm_cls3_MCS3_ERR_ERR1_WIDTH         (1U)
5650 #define GTM_gtm_cls3_MCS3_ERR_ERR1(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_ERR_ERR1_SHIFT)) & GTM_gtm_cls3_MCS3_ERR_ERR1_MASK)
5651 
5652 #define GTM_gtm_cls3_MCS3_ERR_ERR2_MASK          (0x4U)
5653 #define GTM_gtm_cls3_MCS3_ERR_ERR2_SHIFT         (2U)
5654 #define GTM_gtm_cls3_MCS3_ERR_ERR2_WIDTH         (1U)
5655 #define GTM_gtm_cls3_MCS3_ERR_ERR2(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_ERR_ERR2_SHIFT)) & GTM_gtm_cls3_MCS3_ERR_ERR2_MASK)
5656 
5657 #define GTM_gtm_cls3_MCS3_ERR_ERR3_MASK          (0x8U)
5658 #define GTM_gtm_cls3_MCS3_ERR_ERR3_SHIFT         (3U)
5659 #define GTM_gtm_cls3_MCS3_ERR_ERR3_WIDTH         (1U)
5660 #define GTM_gtm_cls3_MCS3_ERR_ERR3(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_ERR_ERR3_SHIFT)) & GTM_gtm_cls3_MCS3_ERR_ERR3_MASK)
5661 
5662 #define GTM_gtm_cls3_MCS3_ERR_ERR4_MASK          (0x10U)
5663 #define GTM_gtm_cls3_MCS3_ERR_ERR4_SHIFT         (4U)
5664 #define GTM_gtm_cls3_MCS3_ERR_ERR4_WIDTH         (1U)
5665 #define GTM_gtm_cls3_MCS3_ERR_ERR4(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_ERR_ERR4_SHIFT)) & GTM_gtm_cls3_MCS3_ERR_ERR4_MASK)
5666 
5667 #define GTM_gtm_cls3_MCS3_ERR_ERR5_MASK          (0x20U)
5668 #define GTM_gtm_cls3_MCS3_ERR_ERR5_SHIFT         (5U)
5669 #define GTM_gtm_cls3_MCS3_ERR_ERR5_WIDTH         (1U)
5670 #define GTM_gtm_cls3_MCS3_ERR_ERR5(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_ERR_ERR5_SHIFT)) & GTM_gtm_cls3_MCS3_ERR_ERR5_MASK)
5671 
5672 #define GTM_gtm_cls3_MCS3_ERR_ERR6_MASK          (0x40U)
5673 #define GTM_gtm_cls3_MCS3_ERR_ERR6_SHIFT         (6U)
5674 #define GTM_gtm_cls3_MCS3_ERR_ERR6_WIDTH         (1U)
5675 #define GTM_gtm_cls3_MCS3_ERR_ERR6(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_ERR_ERR6_SHIFT)) & GTM_gtm_cls3_MCS3_ERR_ERR6_MASK)
5676 
5677 #define GTM_gtm_cls3_MCS3_ERR_ERR7_MASK          (0x80U)
5678 #define GTM_gtm_cls3_MCS3_ERR_ERR7_SHIFT         (7U)
5679 #define GTM_gtm_cls3_MCS3_ERR_ERR7_WIDTH         (1U)
5680 #define GTM_gtm_cls3_MCS3_ERR_ERR7(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_ERR_ERR7_SHIFT)) & GTM_gtm_cls3_MCS3_ERR_ERR7_MASK)
5681 /*! @} */
5682 
5683 /*! @name MCS3_REG_PROT - MCS[i] write protection register */
5684 /*! @{ */
5685 
5686 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT0_MASK   (0x3U)
5687 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT0_SHIFT  (0U)
5688 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT0_WIDTH  (2U)
5689 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT0(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_REG_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_MCS3_REG_PROT_WPROT0_MASK)
5690 
5691 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT1_MASK   (0xCU)
5692 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT1_SHIFT  (2U)
5693 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT1_WIDTH  (2U)
5694 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT1(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_REG_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_MCS3_REG_PROT_WPROT1_MASK)
5695 
5696 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT2_MASK   (0x30U)
5697 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT2_SHIFT  (4U)
5698 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT2_WIDTH  (2U)
5699 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT2(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_REG_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_MCS3_REG_PROT_WPROT2_MASK)
5700 
5701 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT3_MASK   (0xC0U)
5702 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT3_SHIFT  (6U)
5703 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT3_WIDTH  (2U)
5704 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT3(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_REG_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_MCS3_REG_PROT_WPROT3_MASK)
5705 
5706 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT4_MASK   (0x300U)
5707 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT4_SHIFT  (8U)
5708 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT4_WIDTH  (2U)
5709 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT4(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_REG_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_MCS3_REG_PROT_WPROT4_MASK)
5710 
5711 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT5_MASK   (0xC00U)
5712 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT5_SHIFT  (10U)
5713 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT5_WIDTH  (2U)
5714 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT5(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_REG_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_MCS3_REG_PROT_WPROT5_MASK)
5715 
5716 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT6_MASK   (0x3000U)
5717 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT6_SHIFT  (12U)
5718 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT6_WIDTH  (2U)
5719 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT6(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_REG_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_MCS3_REG_PROT_WPROT6_MASK)
5720 
5721 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT7_MASK   (0xC000U)
5722 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT7_SHIFT  (14U)
5723 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT7_WIDTH  (2U)
5724 #define GTM_gtm_cls3_MCS3_REG_PROT_WPROT7(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_REG_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_MCS3_REG_PROT_WPROT7_MASK)
5725 /*! @} */
5726 
5727 /*! @name MCS3_SINT_IRQ_NOTIFY - MCS[i] shared interrupt notification register */
5728 /*! @{ */
5729 
5730 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ0_MASK (0x1U)
5731 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ0_SHIFT (0U)
5732 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ0_WIDTH (1U)
5733 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ0_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ0_MASK)
5734 
5735 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ1_MASK (0x2U)
5736 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ1_SHIFT (1U)
5737 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ1_WIDTH (1U)
5738 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ1_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ1_MASK)
5739 
5740 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ2_MASK (0x4U)
5741 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ2_SHIFT (2U)
5742 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ2_WIDTH (1U)
5743 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ2_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ2_MASK)
5744 
5745 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ3_MASK (0x8U)
5746 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ3_SHIFT (3U)
5747 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ3_WIDTH (1U)
5748 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ3_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ3_MASK)
5749 
5750 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ4_MASK (0x10U)
5751 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ4_SHIFT (4U)
5752 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ4_WIDTH (1U)
5753 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ4_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ4_MASK)
5754 
5755 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ5_MASK (0x20U)
5756 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ5_SHIFT (5U)
5757 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ5_WIDTH (1U)
5758 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ5_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ5_MASK)
5759 
5760 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ6_MASK (0x40U)
5761 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ6_SHIFT (6U)
5762 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ6_WIDTH (1U)
5763 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ6_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ6_MASK)
5764 
5765 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ7_MASK (0x80U)
5766 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ7_SHIFT (7U)
5767 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ7_WIDTH (1U)
5768 #define GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ7_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_NOTIFY_S_IRQ7_MASK)
5769 /*! @} */
5770 
5771 /*! @name MCS3_SINT_IRQ_EN - MCS[i] shared interrupt enable register */
5772 /*! @{ */
5773 
5774 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ0_EN_MASK (0x1U)
5775 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ0_EN_SHIFT (0U)
5776 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ0_EN_WIDTH (1U)
5777 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ0_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ0_EN_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ0_EN_MASK)
5778 
5779 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ1_EN_MASK (0x2U)
5780 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ1_EN_SHIFT (1U)
5781 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ1_EN_WIDTH (1U)
5782 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ1_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ1_EN_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ1_EN_MASK)
5783 
5784 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ2_EN_MASK (0x4U)
5785 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ2_EN_SHIFT (2U)
5786 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ2_EN_WIDTH (1U)
5787 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ2_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ2_EN_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ2_EN_MASK)
5788 
5789 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ3_EN_MASK (0x8U)
5790 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ3_EN_SHIFT (3U)
5791 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ3_EN_WIDTH (1U)
5792 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ3_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ3_EN_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ3_EN_MASK)
5793 
5794 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ4_EN_MASK (0x10U)
5795 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ4_EN_SHIFT (4U)
5796 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ4_EN_WIDTH (1U)
5797 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ4_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ4_EN_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ4_EN_MASK)
5798 
5799 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ5_EN_MASK (0x20U)
5800 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ5_EN_SHIFT (5U)
5801 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ5_EN_WIDTH (1U)
5802 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ5_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ5_EN_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ5_EN_MASK)
5803 
5804 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ6_EN_MASK (0x40U)
5805 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ6_EN_SHIFT (6U)
5806 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ6_EN_WIDTH (1U)
5807 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ6_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ6_EN_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ6_EN_MASK)
5808 
5809 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ7_EN_MASK (0x80U)
5810 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ7_EN_SHIFT (7U)
5811 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ7_EN_WIDTH (1U)
5812 #define GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ7_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ7_EN_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_EN_S_IRQ7_EN_MASK)
5813 /*! @} */
5814 
5815 /*! @name MCS3_SINT_IRQ_FORCINT - MCS[i] force shared interrupt register */
5816 /*! @{ */
5817 
5818 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ0_MASK (0x1U)
5819 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ0_SHIFT (0U)
5820 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ0_WIDTH (1U)
5821 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ0_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ0_MASK)
5822 
5823 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ1_MASK (0x2U)
5824 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ1_SHIFT (1U)
5825 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ1_WIDTH (1U)
5826 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ1_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ1_MASK)
5827 
5828 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ2_MASK (0x4U)
5829 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ2_SHIFT (2U)
5830 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ2_WIDTH (1U)
5831 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ2_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ2_MASK)
5832 
5833 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ3_MASK (0x8U)
5834 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ3_SHIFT (3U)
5835 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ3_WIDTH (1U)
5836 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ3_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ3_MASK)
5837 
5838 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ4_MASK (0x10U)
5839 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ4_SHIFT (4U)
5840 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ4_WIDTH (1U)
5841 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ4_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ4_MASK)
5842 
5843 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ5_MASK (0x20U)
5844 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ5_SHIFT (5U)
5845 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ5_WIDTH (1U)
5846 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ5_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ5_MASK)
5847 
5848 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ6_MASK (0x40U)
5849 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ6_SHIFT (6U)
5850 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ6_WIDTH (1U)
5851 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ6_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ6_MASK)
5852 
5853 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ7_MASK (0x80U)
5854 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ7_SHIFT (7U)
5855 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ7_WIDTH (1U)
5856 #define GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ7_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_FORCINT_TRG_S_IRQ7_MASK)
5857 /*! @} */
5858 
5859 /*! @name MCS3_SINT_IRQ_MODE - MCS[i] shared interrupt mode configuration register */
5860 /*! @{ */
5861 
5862 #define GTM_gtm_cls3_MCS3_SINT_IRQ_MODE_IRQ_MODE_MASK (0x3U)
5863 #define GTM_gtm_cls3_MCS3_SINT_IRQ_MODE_IRQ_MODE_SHIFT (0U)
5864 #define GTM_gtm_cls3_MCS3_SINT_IRQ_MODE_IRQ_MODE_WIDTH (2U)
5865 #define GTM_gtm_cls3_MCS3_SINT_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_SINT_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_SINT_IRQ_MODE_IRQ_MODE_MASK)
5866 /*! @} */
5867 
5868 /*! @name MCS3_HBP0_CTRL - MCS[i] hardware break point h control register */
5869 /*! @{ */
5870 
5871 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH0_MASK  (0x1U)
5872 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH0_SHIFT (0U)
5873 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH0_WIDTH (1U)
5874 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH0_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH0_MASK)
5875 
5876 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH1_MASK  (0x2U)
5877 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH1_SHIFT (1U)
5878 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH1_WIDTH (1U)
5879 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH1_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH1_MASK)
5880 
5881 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH2_MASK  (0x4U)
5882 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH2_SHIFT (2U)
5883 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH2_WIDTH (1U)
5884 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH2_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH2_MASK)
5885 
5886 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH3_MASK  (0x8U)
5887 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH3_SHIFT (3U)
5888 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH3_WIDTH (1U)
5889 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH3_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH3_MASK)
5890 
5891 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH4_MASK  (0x10U)
5892 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH4_SHIFT (4U)
5893 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH4_WIDTH (1U)
5894 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH4_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH4_MASK)
5895 
5896 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH5_MASK  (0x20U)
5897 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH5_SHIFT (5U)
5898 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH5_WIDTH (1U)
5899 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH5_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH5_MASK)
5900 
5901 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH6_MASK  (0x40U)
5902 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH6_SHIFT (6U)
5903 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH6_WIDTH (1U)
5904 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH6_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH6_MASK)
5905 
5906 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH7_MASK  (0x80U)
5907 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH7_SHIFT (7U)
5908 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH7_WIDTH (1U)
5909 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH7_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_EN_CH7_MASK)
5910 
5911 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_SCOPE_MASK   (0x300U)
5912 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_SCOPE_SHIFT  (8U)
5913 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_SCOPE_WIDTH  (2U)
5914 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_SCOPE(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_SCOPE_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_SCOPE_MASK)
5915 
5916 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_TYPE_MASK    (0x7000U)
5917 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_TYPE_SHIFT   (12U)
5918 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_TYPE_WIDTH   (3U)
5919 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_TYPE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_TYPE_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_TYPE_MASK)
5920 
5921 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_AND_MASK     (0x10000U)
5922 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_AND_SHIFT    (16U)
5923 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_AND_WIDTH    (1U)
5924 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_AND(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_AND_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_AND_MASK)
5925 
5926 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_NOT_MASK     (0x20000U)
5927 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_NOT_SHIFT    (17U)
5928 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_NOT_WIDTH    (1U)
5929 #define GTM_gtm_cls3_MCS3_HBP0_CTRL_NOT(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_CTRL_NOT_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_CTRL_NOT_MASK)
5930 /*! @} */
5931 
5932 /*! @name MCS3_HBP0_PATTERN - MCS[i] hardware break point pattern register */
5933 /*! @{ */
5934 
5935 #define GTM_gtm_cls3_MCS3_HBP0_PATTERN_DATA_MASK (0xFFFFFFFFU)
5936 #define GTM_gtm_cls3_MCS3_HBP0_PATTERN_DATA_SHIFT (0U)
5937 #define GTM_gtm_cls3_MCS3_HBP0_PATTERN_DATA_WIDTH (32U)
5938 #define GTM_gtm_cls3_MCS3_HBP0_PATTERN_DATA(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_PATTERN_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_PATTERN_DATA_MASK)
5939 /*! @} */
5940 
5941 /*! @name MCS3_HBP0_STATUS - MCS[i] hardware break point status register */
5942 /*! @{ */
5943 
5944 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH0_MASK (0x1U)
5945 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH0_SHIFT (0U)
5946 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH0_WIDTH (1U)
5947 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH0_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH0_MASK)
5948 
5949 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH1_MASK (0x2U)
5950 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH1_SHIFT (1U)
5951 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH1_WIDTH (1U)
5952 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH1_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH1_MASK)
5953 
5954 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH2_MASK (0x4U)
5955 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH2_SHIFT (2U)
5956 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH2_WIDTH (1U)
5957 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH2_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH2_MASK)
5958 
5959 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH3_MASK (0x8U)
5960 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH3_SHIFT (3U)
5961 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH3_WIDTH (1U)
5962 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH3_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH3_MASK)
5963 
5964 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH4_MASK (0x10U)
5965 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH4_SHIFT (4U)
5966 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH4_WIDTH (1U)
5967 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH4_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH4_MASK)
5968 
5969 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH5_MASK (0x20U)
5970 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH5_SHIFT (5U)
5971 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH5_WIDTH (1U)
5972 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH5_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH5_MASK)
5973 
5974 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH6_MASK (0x40U)
5975 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH6_SHIFT (6U)
5976 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH6_WIDTH (1U)
5977 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH6_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH6_MASK)
5978 
5979 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH7_MASK (0x80U)
5980 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH7_SHIFT (7U)
5981 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH7_WIDTH (1U)
5982 #define GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH7_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_STATUS_HALT_CH7_MASK)
5983 /*! @} */
5984 
5985 /*! @name MCS3_HBP0_IRQ_NOTIFY - MCS[i] hardware break point interrupt notification register */
5986 /*! @{ */
5987 
5988 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_NOTIFY_HBP_IRQ_MASK (0x1U)
5989 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_NOTIFY_HBP_IRQ_SHIFT (0U)
5990 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_NOTIFY_HBP_IRQ_WIDTH (1U)
5991 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_NOTIFY_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_IRQ_NOTIFY_HBP_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_IRQ_NOTIFY_HBP_IRQ_MASK)
5992 /*! @} */
5993 
5994 /*! @name MCS3_HBP0_IRQ_EN - MCS[i] hardware break point interrupt enable register */
5995 /*! @{ */
5996 
5997 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_EN_HBP_IRQ_EN_MASK (0x1U)
5998 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_EN_HBP_IRQ_EN_SHIFT (0U)
5999 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_EN_HBP_IRQ_EN_WIDTH (1U)
6000 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_EN_HBP_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_IRQ_EN_HBP_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_IRQ_EN_HBP_IRQ_EN_MASK)
6001 /*! @} */
6002 
6003 /*! @name MCS3_HBP0_IRQ_FORCINT - MCS[i] force hardware break point interrupt register */
6004 /*! @{ */
6005 
6006 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_MASK (0x1U)
6007 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT (0U)
6008 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_WIDTH (1U)
6009 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_FORCINT_TRG_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_IRQ_FORCINT_TRG_HBP_IRQ_MASK)
6010 /*! @} */
6011 
6012 /*! @name MCS3_HBP0_IRQ_MODE - MCS[i] break point h interrupt mode configuration register */
6013 /*! @{ */
6014 
6015 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_MODE_IRQ_MODE_MASK (0x3U)
6016 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_MODE_IRQ_MODE_SHIFT (0U)
6017 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_MODE_IRQ_MODE_WIDTH (2U)
6018 #define GTM_gtm_cls3_MCS3_HBP0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_HBP0_IRQ_MODE_IRQ_MODE_MASK)
6019 /*! @} */
6020 
6021 /*! @name MCS3_HBP1_CTRL - MCS[i] hardware break point h control register */
6022 /*! @{ */
6023 
6024 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH0_MASK  (0x1U)
6025 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH0_SHIFT (0U)
6026 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH0_WIDTH (1U)
6027 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH0_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH0_MASK)
6028 
6029 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH1_MASK  (0x2U)
6030 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH1_SHIFT (1U)
6031 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH1_WIDTH (1U)
6032 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH1_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH1_MASK)
6033 
6034 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH2_MASK  (0x4U)
6035 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH2_SHIFT (2U)
6036 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH2_WIDTH (1U)
6037 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH2_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH2_MASK)
6038 
6039 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH3_MASK  (0x8U)
6040 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH3_SHIFT (3U)
6041 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH3_WIDTH (1U)
6042 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH3_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH3_MASK)
6043 
6044 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH4_MASK  (0x10U)
6045 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH4_SHIFT (4U)
6046 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH4_WIDTH (1U)
6047 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH4_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH4_MASK)
6048 
6049 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH5_MASK  (0x20U)
6050 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH5_SHIFT (5U)
6051 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH5_WIDTH (1U)
6052 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH5_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH5_MASK)
6053 
6054 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH6_MASK  (0x40U)
6055 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH6_SHIFT (6U)
6056 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH6_WIDTH (1U)
6057 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH6_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH6_MASK)
6058 
6059 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH7_MASK  (0x80U)
6060 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH7_SHIFT (7U)
6061 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH7_WIDTH (1U)
6062 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH7_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_EN_CH7_MASK)
6063 
6064 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_SCOPE_MASK   (0x300U)
6065 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_SCOPE_SHIFT  (8U)
6066 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_SCOPE_WIDTH  (2U)
6067 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_SCOPE(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_SCOPE_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_SCOPE_MASK)
6068 
6069 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_TYPE_MASK    (0x7000U)
6070 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_TYPE_SHIFT   (12U)
6071 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_TYPE_WIDTH   (3U)
6072 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_TYPE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_TYPE_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_TYPE_MASK)
6073 
6074 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_AND_MASK     (0x10000U)
6075 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_AND_SHIFT    (16U)
6076 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_AND_WIDTH    (1U)
6077 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_AND(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_AND_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_AND_MASK)
6078 
6079 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_NOT_MASK     (0x20000U)
6080 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_NOT_SHIFT    (17U)
6081 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_NOT_WIDTH    (1U)
6082 #define GTM_gtm_cls3_MCS3_HBP1_CTRL_NOT(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_CTRL_NOT_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_CTRL_NOT_MASK)
6083 /*! @} */
6084 
6085 /*! @name MCS3_HBP1_PATTERN - MCS[i] hardware break point pattern register */
6086 /*! @{ */
6087 
6088 #define GTM_gtm_cls3_MCS3_HBP1_PATTERN_DATA_MASK (0xFFFFFFFFU)
6089 #define GTM_gtm_cls3_MCS3_HBP1_PATTERN_DATA_SHIFT (0U)
6090 #define GTM_gtm_cls3_MCS3_HBP1_PATTERN_DATA_WIDTH (32U)
6091 #define GTM_gtm_cls3_MCS3_HBP1_PATTERN_DATA(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_PATTERN_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_PATTERN_DATA_MASK)
6092 /*! @} */
6093 
6094 /*! @name MCS3_HBP1_STATUS - MCS[i] hardware break point status register */
6095 /*! @{ */
6096 
6097 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH0_MASK (0x1U)
6098 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH0_SHIFT (0U)
6099 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH0_WIDTH (1U)
6100 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH0_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH0_MASK)
6101 
6102 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH1_MASK (0x2U)
6103 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH1_SHIFT (1U)
6104 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH1_WIDTH (1U)
6105 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH1_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH1_MASK)
6106 
6107 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH2_MASK (0x4U)
6108 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH2_SHIFT (2U)
6109 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH2_WIDTH (1U)
6110 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH2_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH2_MASK)
6111 
6112 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH3_MASK (0x8U)
6113 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH3_SHIFT (3U)
6114 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH3_WIDTH (1U)
6115 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH3_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH3_MASK)
6116 
6117 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH4_MASK (0x10U)
6118 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH4_SHIFT (4U)
6119 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH4_WIDTH (1U)
6120 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH4_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH4_MASK)
6121 
6122 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH5_MASK (0x20U)
6123 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH5_SHIFT (5U)
6124 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH5_WIDTH (1U)
6125 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH5_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH5_MASK)
6126 
6127 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH6_MASK (0x40U)
6128 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH6_SHIFT (6U)
6129 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH6_WIDTH (1U)
6130 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH6_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH6_MASK)
6131 
6132 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH7_MASK (0x80U)
6133 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH7_SHIFT (7U)
6134 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH7_WIDTH (1U)
6135 #define GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH7_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_STATUS_HALT_CH7_MASK)
6136 /*! @} */
6137 
6138 /*! @name MCS3_HBP1_IRQ_NOTIFY - MCS[i] hardware break point interrupt notification register */
6139 /*! @{ */
6140 
6141 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_NOTIFY_HBP_IRQ_MASK (0x1U)
6142 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_NOTIFY_HBP_IRQ_SHIFT (0U)
6143 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_NOTIFY_HBP_IRQ_WIDTH (1U)
6144 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_NOTIFY_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_IRQ_NOTIFY_HBP_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_IRQ_NOTIFY_HBP_IRQ_MASK)
6145 /*! @} */
6146 
6147 /*! @name MCS3_HBP1_IRQ_EN - MCS[i] hardware break point interrupt enable register */
6148 /*! @{ */
6149 
6150 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_EN_HBP_IRQ_EN_MASK (0x1U)
6151 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_EN_HBP_IRQ_EN_SHIFT (0U)
6152 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_EN_HBP_IRQ_EN_WIDTH (1U)
6153 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_EN_HBP_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_IRQ_EN_HBP_IRQ_EN_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_IRQ_EN_HBP_IRQ_EN_MASK)
6154 /*! @} */
6155 
6156 /*! @name MCS3_HBP1_IRQ_FORCINT - MCS[i] force hardware break point interrupt register */
6157 /*! @{ */
6158 
6159 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_MASK (0x1U)
6160 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT (0U)
6161 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_WIDTH (1U)
6162 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_FORCINT_TRG_HBP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_IRQ_FORCINT_TRG_HBP_IRQ_MASK)
6163 /*! @} */
6164 
6165 /*! @name MCS3_HBP1_IRQ_MODE - MCS[i] break point h interrupt mode configuration register */
6166 /*! @{ */
6167 
6168 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_MODE_IRQ_MODE_MASK (0x3U)
6169 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_MODE_IRQ_MODE_SHIFT (0U)
6170 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_MODE_IRQ_MODE_WIDTH (2U)
6171 #define GTM_gtm_cls3_MCS3_HBP1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_HBP1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_MCS3_HBP1_IRQ_MODE_IRQ_MODE_MASK)
6172 /*! @} */
6173 
6174 /*! @name TIO3_G0_CH0_CTRL - TIO[i] group [g] channel [c] control register */
6175 /*! @{ */
6176 
6177 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U)
6178 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U)
6179 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U)
6180 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_RE_MASK)
6181 
6182 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U)
6183 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U)
6184 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U)
6185 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_S_FE_MASK)
6186 
6187 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U)
6188 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U)
6189 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U)
6190 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_RE_MASK)
6191 
6192 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U)
6193 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U)
6194 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U)
6195 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_O_FE_MASK)
6196 
6197 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U)
6198 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U)
6199 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
6200 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK)
6201 
6202 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U)
6203 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U)
6204 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
6205 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PL_EVT_MASK)
6206 
6207 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U)
6208 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U)
6209 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
6210 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
6211 
6212 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U)
6213 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U)
6214 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U)
6215 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK)
6216 
6217 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_UPDATE_SRC_MASK (0xF00U)
6218 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_UPDATE_SRC_SHIFT (8U)
6219 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_UPDATE_SRC_WIDTH (4U)
6220 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_UPDATE_SRC_MASK)
6221 
6222 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_MODE_MASK (0x3000U)
6223 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_MODE_SHIFT (12U)
6224 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_MODE_WIDTH (2U)
6225 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_MODE_MASK)
6226 
6227 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_S_EN_MASK (0x4000U)
6228 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_S_EN_SHIFT (14U)
6229 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_S_EN_WIDTH (1U)
6230 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_S_EN_MASK)
6231 
6232 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U)
6233 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_BUFF_SHIFT (15U)
6234 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_BUFF_WIDTH (1U)
6235 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_CYCLIC_BUFF_MASK)
6236 
6237 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_MODE_MASK (0x70000U)
6238 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_MODE_SHIFT (16U)
6239 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_MODE_WIDTH (3U)
6240 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_MODE_MASK)
6241 
6242 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_O_EN_MASK (0x80000U)
6243 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_O_EN_SHIFT (19U)
6244 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_O_EN_WIDTH (1U)
6245 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_FREEZE_O_EN_MASK)
6246 
6247 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_ODIS_MASK (0x100000U)
6248 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_ODIS_SHIFT (20U)
6249 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_ODIS_WIDTH (1U)
6250 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_ODIS_MASK)
6251 
6252 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_SEL_IN_MASK (0x200000U)
6253 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_SEL_IN_SHIFT (21U)
6254 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_SEL_IN_WIDTH (1U)
6255 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_SEL_IN_MASK)
6256 
6257 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U)
6258 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U)
6259 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U)
6260 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_O_TRIG_OUT_EN_MASK)
6261 
6262 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U)
6263 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U)
6264 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U)
6265 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_S_TRIG_OUT_EN_MASK)
6266 
6267 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U)
6268 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U)
6269 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U)
6270 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_RE_MASK)
6271 
6272 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U)
6273 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U)
6274 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U)
6275 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_S_FE_MASK)
6276 
6277 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U)
6278 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U)
6279 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U)
6280 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_RE_MASK)
6281 
6282 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U)
6283 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U)
6284 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U)
6285 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_O_FE_MASK)
6286 
6287 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U)
6288 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U)
6289 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
6290 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK)
6291 
6292 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U)
6293 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U)
6294 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
6295 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK)
6296 
6297 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U)
6298 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U)
6299 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
6300 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
6301 
6302 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U)
6303 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U)
6304 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U)
6305 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL_PL_TRIG_OUT_UPD_EN_MASK)
6306 /*! @} */
6307 
6308 /*! @name TIO3_G0_CH0_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */
6309 /*! @{ */
6310 
6311 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U)
6312 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U)
6313 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U)
6314 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_RE_IRQ_MASK)
6315 
6316 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U)
6317 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U)
6318 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U)
6319 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_S_FE_IRQ_MASK)
6320 
6321 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U)
6322 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U)
6323 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U)
6324 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_RE_IRQ_MASK)
6325 
6326 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U)
6327 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U)
6328 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U)
6329 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_O_FE_IRQ_MASK)
6330 
6331 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U)
6332 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U)
6333 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U)
6334 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_UPDATE_IRQ_MASK)
6335 
6336 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U)
6337 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U)
6338 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U)
6339 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_NOTIFY_PL_EVT_IRQ_MASK)
6340 /*! @} */
6341 
6342 /*! @name TIO3_G0_CH0_IRQ_EN - TIO[i] channel [c] interrupt enable register */
6343 /*! @{ */
6344 
6345 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U)
6346 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U)
6347 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U)
6348 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_RE_IRQ_EN_MASK)
6349 
6350 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U)
6351 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U)
6352 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U)
6353 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_S_FE_IRQ_EN_MASK)
6354 
6355 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U)
6356 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U)
6357 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U)
6358 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_RE_IRQ_EN_MASK)
6359 
6360 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U)
6361 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U)
6362 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U)
6363 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_O_FE_IRQ_EN_MASK)
6364 
6365 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U)
6366 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U)
6367 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U)
6368 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_UPDATE_IRQ_EN_MASK)
6369 
6370 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U)
6371 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U)
6372 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U)
6373 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_EN_PL_EVT_IRQ_EN_MASK)
6374 /*! @} */
6375 
6376 /*! @name TIO3_G0_CH0_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */
6377 /*! @{ */
6378 
6379 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U)
6380 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U)
6381 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U)
6382 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_RE_IRQ_MASK)
6383 
6384 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U)
6385 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U)
6386 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U)
6387 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_S_FE_IRQ_MASK)
6388 
6389 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U)
6390 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U)
6391 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U)
6392 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_RE_IRQ_MASK)
6393 
6394 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U)
6395 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U)
6396 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U)
6397 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_O_FE_IRQ_MASK)
6398 
6399 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U)
6400 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U)
6401 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U)
6402 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK)
6403 
6404 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U)
6405 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U)
6406 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U)
6407 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK)
6408 /*! @} */
6409 
6410 /*! @name TIO3_G0_CH0_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */
6411 /*! @{ */
6412 
6413 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_MODE_IRQ_MODE_MASK (0x3U)
6414 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_MODE_IRQ_MODE_SHIFT (0U)
6415 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_MODE_IRQ_MODE_WIDTH (2U)
6416 #define GTM_gtm_cls3_TIO3_G0_CH0_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_IRQ_MODE_IRQ_MODE_MASK)
6417 /*! @} */
6418 
6419 /*! @name TIO3_G0_CH0_CTRL2 - TIO[i] group [g] channel [c] control register */
6420 /*! @{ */
6421 
6422 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_EN_MASK (0x1U)
6423 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_EN_SHIFT (0U)
6424 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_EN_WIDTH (1U)
6425 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_EN_MASK)
6426 
6427 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U)
6428 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U)
6429 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U)
6430 #define GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_CTRL2_DUAL_CMP_MST_EN_MASK)
6431 /*! @} */
6432 
6433 /*! @name TIO3_G0_CH0_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
6434 /*! @{ */
6435 
6436 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_OP_MASK   (0xFFFFFFU)
6437 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_OP_SHIFT  (0U)
6438 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_OP_WIDTH  (24U)
6439 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_SINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_SINST_OP_MASK)
6440 
6441 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_CMD_MASK  (0x3F000000U)
6442 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_CMD_SHIFT (24U)
6443 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_CMD_WIDTH (6U)
6444 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_SINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_SINST_CMD_MASK)
6445 
6446 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_DATA_PUSH_EN_MASK (0x40000000U)
6447 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_DATA_PUSH_EN_SHIFT (30U)
6448 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_DATA_PUSH_EN_WIDTH (1U)
6449 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_SINST_DATA_PUSH_EN_MASK)
6450 
6451 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_INSTR_PULL_EN_MASK (0x80000000U)
6452 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_INSTR_PULL_EN_SHIFT (31U)
6453 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_INSTR_PULL_EN_WIDTH (1U)
6454 #define GTM_gtm_cls3_TIO3_G0_CH0_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_SINST_INSTR_PULL_EN_MASK)
6455 /*! @} */
6456 
6457 /*! @name TIO3_G0_CH0_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
6458 /*! @{ */
6459 
6460 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_CMD_MASK   (0x3F000000U)
6461 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_CMD_SHIFT  (24U)
6462 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_CMD_WIDTH  (6U)
6463 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_SCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_SCMD_CMD_MASK)
6464 
6465 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_DATA_PUSH_EN_MASK (0x40000000U)
6466 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_DATA_PUSH_EN_SHIFT (30U)
6467 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_DATA_PUSH_EN_WIDTH (1U)
6468 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_SCMD_DATA_PUSH_EN_MASK)
6469 
6470 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_INSTR_PULL_EN_MASK (0x80000000U)
6471 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_INSTR_PULL_EN_SHIFT (31U)
6472 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_INSTR_PULL_EN_WIDTH (1U)
6473 #define GTM_gtm_cls3_TIO3_G0_CH0_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_SCMD_INSTR_PULL_EN_MASK)
6474 /*! @} */
6475 
6476 /*! @name TIO3_G0_CH0_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */
6477 /*! @{ */
6478 
6479 #define GTM_gtm_cls3_TIO3_G0_CH0_SOP_OP_MASK     (0xFFFFFFU)
6480 #define GTM_gtm_cls3_TIO3_G0_CH0_SOP_OP_SHIFT    (0U)
6481 #define GTM_gtm_cls3_TIO3_G0_CH0_SOP_OP_WIDTH    (24U)
6482 #define GTM_gtm_cls3_TIO3_G0_CH0_SOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_SOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_SOP_OP_MASK)
6483 /*! @} */
6484 
6485 /*! @name TIO3_G0_CH0_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */
6486 /*! @{ */
6487 
6488 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_OP_MASK   (0xFFFFFFU)
6489 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_OP_SHIFT  (0U)
6490 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_OP_WIDTH  (24U)
6491 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_OINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_OINST_OP_MASK)
6492 
6493 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_CMD_MASK  (0x3F000000U)
6494 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_CMD_SHIFT (24U)
6495 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_CMD_WIDTH (6U)
6496 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_OINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_OINST_CMD_MASK)
6497 
6498 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_DATA_PUSH_EN_MASK (0x40000000U)
6499 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_DATA_PUSH_EN_SHIFT (30U)
6500 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_DATA_PUSH_EN_WIDTH (1U)
6501 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_OINST_DATA_PUSH_EN_MASK)
6502 
6503 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_INSTR_PULL_EN_MASK (0x80000000U)
6504 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_INSTR_PULL_EN_SHIFT (31U)
6505 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_INSTR_PULL_EN_WIDTH (1U)
6506 #define GTM_gtm_cls3_TIO3_G0_CH0_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_OINST_INSTR_PULL_EN_MASK)
6507 /*! @} */
6508 
6509 /*! @name TIO3_G0_CH0_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */
6510 /*! @{ */
6511 
6512 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_CMD_MASK   (0x3F000000U)
6513 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_CMD_SHIFT  (24U)
6514 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_CMD_WIDTH  (6U)
6515 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_OCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_OCMD_CMD_MASK)
6516 
6517 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_DATA_PUSH_EN_MASK (0x40000000U)
6518 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_DATA_PUSH_EN_SHIFT (30U)
6519 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_DATA_PUSH_EN_WIDTH (1U)
6520 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_OCMD_DATA_PUSH_EN_MASK)
6521 
6522 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_INSTR_PULL_EN_MASK (0x80000000U)
6523 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_INSTR_PULL_EN_SHIFT (31U)
6524 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_INSTR_PULL_EN_WIDTH (1U)
6525 #define GTM_gtm_cls3_TIO3_G0_CH0_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_OCMD_INSTR_PULL_EN_MASK)
6526 /*! @} */
6527 
6528 /*! @name TIO3_G0_CH0_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */
6529 /*! @{ */
6530 
6531 #define GTM_gtm_cls3_TIO3_G0_CH0_OOP_OP_MASK     (0xFFFFFFU)
6532 #define GTM_gtm_cls3_TIO3_G0_CH0_OOP_OP_SHIFT    (0U)
6533 #define GTM_gtm_cls3_TIO3_G0_CH0_OOP_OP_WIDTH    (24U)
6534 #define GTM_gtm_cls3_TIO3_G0_CH0_OOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_OOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_OOP_OP_MASK)
6535 /*! @} */
6536 
6537 /*! @name TIO3_G0_CH0_SHIFTCNT - TIO[i] channel [c] resource shift count register */
6538 /*! @{ */
6539 
6540 #define GTM_gtm_cls3_TIO3_G0_CH0_SHIFTCNT_CNT_MASK (0x1FU)
6541 #define GTM_gtm_cls3_TIO3_G0_CH0_SHIFTCNT_CNT_SHIFT (0U)
6542 #define GTM_gtm_cls3_TIO3_G0_CH0_SHIFTCNT_CNT_WIDTH (5U)
6543 #define GTM_gtm_cls3_TIO3_G0_CH0_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH0_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH0_SHIFTCNT_CNT_MASK)
6544 /*! @} */
6545 
6546 /*! @name TIO3_G0_CH1_CTRL - TIO[i] group [g] channel [c] control register */
6547 /*! @{ */
6548 
6549 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U)
6550 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U)
6551 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U)
6552 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_RE_MASK)
6553 
6554 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U)
6555 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U)
6556 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U)
6557 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_S_FE_MASK)
6558 
6559 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U)
6560 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U)
6561 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U)
6562 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_RE_MASK)
6563 
6564 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U)
6565 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U)
6566 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U)
6567 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_O_FE_MASK)
6568 
6569 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U)
6570 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U)
6571 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
6572 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK)
6573 
6574 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U)
6575 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U)
6576 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
6577 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PL_EVT_MASK)
6578 
6579 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U)
6580 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U)
6581 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
6582 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
6583 
6584 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U)
6585 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U)
6586 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U)
6587 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK)
6588 
6589 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_UPDATE_SRC_MASK (0xF00U)
6590 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_UPDATE_SRC_SHIFT (8U)
6591 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_UPDATE_SRC_WIDTH (4U)
6592 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_UPDATE_SRC_MASK)
6593 
6594 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_MODE_MASK (0x3000U)
6595 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_MODE_SHIFT (12U)
6596 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_MODE_WIDTH (2U)
6597 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_MODE_MASK)
6598 
6599 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_S_EN_MASK (0x4000U)
6600 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_S_EN_SHIFT (14U)
6601 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_S_EN_WIDTH (1U)
6602 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_S_EN_MASK)
6603 
6604 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U)
6605 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_BUFF_SHIFT (15U)
6606 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_BUFF_WIDTH (1U)
6607 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_CYCLIC_BUFF_MASK)
6608 
6609 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_MODE_MASK (0x70000U)
6610 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_MODE_SHIFT (16U)
6611 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_MODE_WIDTH (3U)
6612 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_MODE_MASK)
6613 
6614 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_O_EN_MASK (0x80000U)
6615 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_O_EN_SHIFT (19U)
6616 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_O_EN_WIDTH (1U)
6617 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_FREEZE_O_EN_MASK)
6618 
6619 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_ODIS_MASK (0x100000U)
6620 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_ODIS_SHIFT (20U)
6621 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_ODIS_WIDTH (1U)
6622 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_ODIS_MASK)
6623 
6624 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_SEL_IN_MASK (0x200000U)
6625 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_SEL_IN_SHIFT (21U)
6626 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_SEL_IN_WIDTH (1U)
6627 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_SEL_IN_MASK)
6628 
6629 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U)
6630 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U)
6631 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U)
6632 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_O_TRIG_OUT_EN_MASK)
6633 
6634 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U)
6635 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U)
6636 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U)
6637 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_S_TRIG_OUT_EN_MASK)
6638 
6639 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U)
6640 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U)
6641 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U)
6642 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_RE_MASK)
6643 
6644 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U)
6645 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U)
6646 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U)
6647 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_S_FE_MASK)
6648 
6649 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U)
6650 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U)
6651 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U)
6652 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_RE_MASK)
6653 
6654 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U)
6655 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U)
6656 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U)
6657 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_O_FE_MASK)
6658 
6659 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U)
6660 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U)
6661 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
6662 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK)
6663 
6664 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U)
6665 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U)
6666 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
6667 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK)
6668 
6669 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U)
6670 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U)
6671 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
6672 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
6673 
6674 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U)
6675 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U)
6676 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U)
6677 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL_PL_TRIG_OUT_UPD_EN_MASK)
6678 /*! @} */
6679 
6680 /*! @name TIO3_G0_CH1_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */
6681 /*! @{ */
6682 
6683 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U)
6684 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U)
6685 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U)
6686 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_RE_IRQ_MASK)
6687 
6688 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U)
6689 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U)
6690 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U)
6691 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_S_FE_IRQ_MASK)
6692 
6693 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U)
6694 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U)
6695 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U)
6696 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_RE_IRQ_MASK)
6697 
6698 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U)
6699 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U)
6700 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U)
6701 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_O_FE_IRQ_MASK)
6702 
6703 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U)
6704 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U)
6705 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U)
6706 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_UPDATE_IRQ_MASK)
6707 
6708 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U)
6709 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U)
6710 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U)
6711 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_NOTIFY_PL_EVT_IRQ_MASK)
6712 /*! @} */
6713 
6714 /*! @name TIO3_G0_CH1_IRQ_EN - TIO[i] channel [c] interrupt enable register */
6715 /*! @{ */
6716 
6717 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U)
6718 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U)
6719 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U)
6720 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_RE_IRQ_EN_MASK)
6721 
6722 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U)
6723 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U)
6724 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U)
6725 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_S_FE_IRQ_EN_MASK)
6726 
6727 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U)
6728 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U)
6729 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U)
6730 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_RE_IRQ_EN_MASK)
6731 
6732 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U)
6733 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U)
6734 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U)
6735 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_O_FE_IRQ_EN_MASK)
6736 
6737 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U)
6738 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U)
6739 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U)
6740 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_UPDATE_IRQ_EN_MASK)
6741 
6742 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U)
6743 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U)
6744 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U)
6745 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_EN_PL_EVT_IRQ_EN_MASK)
6746 /*! @} */
6747 
6748 /*! @name TIO3_G0_CH1_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */
6749 /*! @{ */
6750 
6751 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U)
6752 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U)
6753 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U)
6754 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_RE_IRQ_MASK)
6755 
6756 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U)
6757 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U)
6758 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U)
6759 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_S_FE_IRQ_MASK)
6760 
6761 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U)
6762 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U)
6763 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U)
6764 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_RE_IRQ_MASK)
6765 
6766 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U)
6767 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U)
6768 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U)
6769 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_O_FE_IRQ_MASK)
6770 
6771 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U)
6772 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U)
6773 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U)
6774 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK)
6775 
6776 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U)
6777 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U)
6778 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U)
6779 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK)
6780 /*! @} */
6781 
6782 /*! @name TIO3_G0_CH1_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */
6783 /*! @{ */
6784 
6785 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_MODE_IRQ_MODE_MASK (0x3U)
6786 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_MODE_IRQ_MODE_SHIFT (0U)
6787 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_MODE_IRQ_MODE_WIDTH (2U)
6788 #define GTM_gtm_cls3_TIO3_G0_CH1_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_IRQ_MODE_IRQ_MODE_MASK)
6789 /*! @} */
6790 
6791 /*! @name TIO3_G0_CH1_CTRL2 - TIO[i] group [g] channel [c] control register */
6792 /*! @{ */
6793 
6794 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_EN_MASK (0x1U)
6795 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_EN_SHIFT (0U)
6796 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_EN_WIDTH (1U)
6797 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_EN_MASK)
6798 
6799 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U)
6800 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U)
6801 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U)
6802 #define GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_CTRL2_DUAL_CMP_MST_EN_MASK)
6803 /*! @} */
6804 
6805 /*! @name TIO3_G0_CH1_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
6806 /*! @{ */
6807 
6808 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_OP_MASK   (0xFFFFFFU)
6809 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_OP_SHIFT  (0U)
6810 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_OP_WIDTH  (24U)
6811 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_SINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_SINST_OP_MASK)
6812 
6813 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_CMD_MASK  (0x3F000000U)
6814 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_CMD_SHIFT (24U)
6815 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_CMD_WIDTH (6U)
6816 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_SINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_SINST_CMD_MASK)
6817 
6818 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_DATA_PUSH_EN_MASK (0x40000000U)
6819 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_DATA_PUSH_EN_SHIFT (30U)
6820 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_DATA_PUSH_EN_WIDTH (1U)
6821 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_SINST_DATA_PUSH_EN_MASK)
6822 
6823 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_INSTR_PULL_EN_MASK (0x80000000U)
6824 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_INSTR_PULL_EN_SHIFT (31U)
6825 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_INSTR_PULL_EN_WIDTH (1U)
6826 #define GTM_gtm_cls3_TIO3_G0_CH1_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_SINST_INSTR_PULL_EN_MASK)
6827 /*! @} */
6828 
6829 /*! @name TIO3_G0_CH1_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
6830 /*! @{ */
6831 
6832 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_CMD_MASK   (0x3F000000U)
6833 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_CMD_SHIFT  (24U)
6834 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_CMD_WIDTH  (6U)
6835 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_SCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_SCMD_CMD_MASK)
6836 
6837 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_DATA_PUSH_EN_MASK (0x40000000U)
6838 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_DATA_PUSH_EN_SHIFT (30U)
6839 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_DATA_PUSH_EN_WIDTH (1U)
6840 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_SCMD_DATA_PUSH_EN_MASK)
6841 
6842 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_INSTR_PULL_EN_MASK (0x80000000U)
6843 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_INSTR_PULL_EN_SHIFT (31U)
6844 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_INSTR_PULL_EN_WIDTH (1U)
6845 #define GTM_gtm_cls3_TIO3_G0_CH1_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_SCMD_INSTR_PULL_EN_MASK)
6846 /*! @} */
6847 
6848 /*! @name TIO3_G0_CH1_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */
6849 /*! @{ */
6850 
6851 #define GTM_gtm_cls3_TIO3_G0_CH1_SOP_OP_MASK     (0xFFFFFFU)
6852 #define GTM_gtm_cls3_TIO3_G0_CH1_SOP_OP_SHIFT    (0U)
6853 #define GTM_gtm_cls3_TIO3_G0_CH1_SOP_OP_WIDTH    (24U)
6854 #define GTM_gtm_cls3_TIO3_G0_CH1_SOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_SOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_SOP_OP_MASK)
6855 /*! @} */
6856 
6857 /*! @name TIO3_G0_CH1_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */
6858 /*! @{ */
6859 
6860 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_OP_MASK   (0xFFFFFFU)
6861 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_OP_SHIFT  (0U)
6862 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_OP_WIDTH  (24U)
6863 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_OINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_OINST_OP_MASK)
6864 
6865 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_CMD_MASK  (0x3F000000U)
6866 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_CMD_SHIFT (24U)
6867 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_CMD_WIDTH (6U)
6868 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_OINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_OINST_CMD_MASK)
6869 
6870 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_DATA_PUSH_EN_MASK (0x40000000U)
6871 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_DATA_PUSH_EN_SHIFT (30U)
6872 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_DATA_PUSH_EN_WIDTH (1U)
6873 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_OINST_DATA_PUSH_EN_MASK)
6874 
6875 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_INSTR_PULL_EN_MASK (0x80000000U)
6876 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_INSTR_PULL_EN_SHIFT (31U)
6877 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_INSTR_PULL_EN_WIDTH (1U)
6878 #define GTM_gtm_cls3_TIO3_G0_CH1_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_OINST_INSTR_PULL_EN_MASK)
6879 /*! @} */
6880 
6881 /*! @name TIO3_G0_CH1_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */
6882 /*! @{ */
6883 
6884 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_CMD_MASK   (0x3F000000U)
6885 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_CMD_SHIFT  (24U)
6886 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_CMD_WIDTH  (6U)
6887 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_OCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_OCMD_CMD_MASK)
6888 
6889 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_DATA_PUSH_EN_MASK (0x40000000U)
6890 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_DATA_PUSH_EN_SHIFT (30U)
6891 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_DATA_PUSH_EN_WIDTH (1U)
6892 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_OCMD_DATA_PUSH_EN_MASK)
6893 
6894 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_INSTR_PULL_EN_MASK (0x80000000U)
6895 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_INSTR_PULL_EN_SHIFT (31U)
6896 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_INSTR_PULL_EN_WIDTH (1U)
6897 #define GTM_gtm_cls3_TIO3_G0_CH1_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_OCMD_INSTR_PULL_EN_MASK)
6898 /*! @} */
6899 
6900 /*! @name TIO3_G0_CH1_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */
6901 /*! @{ */
6902 
6903 #define GTM_gtm_cls3_TIO3_G0_CH1_OOP_OP_MASK     (0xFFFFFFU)
6904 #define GTM_gtm_cls3_TIO3_G0_CH1_OOP_OP_SHIFT    (0U)
6905 #define GTM_gtm_cls3_TIO3_G0_CH1_OOP_OP_WIDTH    (24U)
6906 #define GTM_gtm_cls3_TIO3_G0_CH1_OOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_OOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_OOP_OP_MASK)
6907 /*! @} */
6908 
6909 /*! @name TIO3_G0_CH1_SHIFTCNT - TIO[i] channel [c] resource shift count register */
6910 /*! @{ */
6911 
6912 #define GTM_gtm_cls3_TIO3_G0_CH1_SHIFTCNT_CNT_MASK (0x1FU)
6913 #define GTM_gtm_cls3_TIO3_G0_CH1_SHIFTCNT_CNT_SHIFT (0U)
6914 #define GTM_gtm_cls3_TIO3_G0_CH1_SHIFTCNT_CNT_WIDTH (5U)
6915 #define GTM_gtm_cls3_TIO3_G0_CH1_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH1_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH1_SHIFTCNT_CNT_MASK)
6916 /*! @} */
6917 
6918 /*! @name TIO3_G0_CH2_CTRL - TIO[i] group [g] channel [c] control register */
6919 /*! @{ */
6920 
6921 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U)
6922 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U)
6923 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U)
6924 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_RE_MASK)
6925 
6926 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U)
6927 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U)
6928 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U)
6929 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_S_FE_MASK)
6930 
6931 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U)
6932 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U)
6933 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U)
6934 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_RE_MASK)
6935 
6936 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U)
6937 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U)
6938 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U)
6939 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_O_FE_MASK)
6940 
6941 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U)
6942 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U)
6943 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
6944 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK)
6945 
6946 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U)
6947 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U)
6948 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
6949 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PL_EVT_MASK)
6950 
6951 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U)
6952 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U)
6953 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
6954 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
6955 
6956 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U)
6957 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U)
6958 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U)
6959 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK)
6960 
6961 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_UPDATE_SRC_MASK (0xF00U)
6962 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_UPDATE_SRC_SHIFT (8U)
6963 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_UPDATE_SRC_WIDTH (4U)
6964 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_UPDATE_SRC_MASK)
6965 
6966 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_MODE_MASK (0x3000U)
6967 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_MODE_SHIFT (12U)
6968 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_MODE_WIDTH (2U)
6969 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_MODE_MASK)
6970 
6971 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_S_EN_MASK (0x4000U)
6972 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_S_EN_SHIFT (14U)
6973 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_S_EN_WIDTH (1U)
6974 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_S_EN_MASK)
6975 
6976 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U)
6977 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_BUFF_SHIFT (15U)
6978 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_BUFF_WIDTH (1U)
6979 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_CYCLIC_BUFF_MASK)
6980 
6981 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_MODE_MASK (0x70000U)
6982 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_MODE_SHIFT (16U)
6983 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_MODE_WIDTH (3U)
6984 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_MODE_MASK)
6985 
6986 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_O_EN_MASK (0x80000U)
6987 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_O_EN_SHIFT (19U)
6988 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_O_EN_WIDTH (1U)
6989 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_FREEZE_O_EN_MASK)
6990 
6991 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_ODIS_MASK (0x100000U)
6992 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_ODIS_SHIFT (20U)
6993 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_ODIS_WIDTH (1U)
6994 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_ODIS_MASK)
6995 
6996 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_SEL_IN_MASK (0x200000U)
6997 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_SEL_IN_SHIFT (21U)
6998 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_SEL_IN_WIDTH (1U)
6999 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_SEL_IN_MASK)
7000 
7001 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U)
7002 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U)
7003 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U)
7004 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_O_TRIG_OUT_EN_MASK)
7005 
7006 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U)
7007 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U)
7008 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U)
7009 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_S_TRIG_OUT_EN_MASK)
7010 
7011 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U)
7012 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U)
7013 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U)
7014 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_RE_MASK)
7015 
7016 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U)
7017 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U)
7018 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U)
7019 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_S_FE_MASK)
7020 
7021 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U)
7022 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U)
7023 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U)
7024 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_RE_MASK)
7025 
7026 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U)
7027 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U)
7028 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U)
7029 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_O_FE_MASK)
7030 
7031 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U)
7032 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U)
7033 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
7034 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK)
7035 
7036 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U)
7037 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U)
7038 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
7039 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK)
7040 
7041 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U)
7042 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U)
7043 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
7044 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
7045 
7046 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U)
7047 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U)
7048 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U)
7049 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL_PL_TRIG_OUT_UPD_EN_MASK)
7050 /*! @} */
7051 
7052 /*! @name TIO3_G0_CH2_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */
7053 /*! @{ */
7054 
7055 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U)
7056 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U)
7057 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U)
7058 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_RE_IRQ_MASK)
7059 
7060 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U)
7061 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U)
7062 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U)
7063 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_S_FE_IRQ_MASK)
7064 
7065 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U)
7066 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U)
7067 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U)
7068 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_RE_IRQ_MASK)
7069 
7070 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U)
7071 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U)
7072 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U)
7073 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_O_FE_IRQ_MASK)
7074 
7075 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U)
7076 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U)
7077 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U)
7078 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_UPDATE_IRQ_MASK)
7079 
7080 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U)
7081 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U)
7082 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U)
7083 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_NOTIFY_PL_EVT_IRQ_MASK)
7084 /*! @} */
7085 
7086 /*! @name TIO3_G0_CH2_IRQ_EN - TIO[i] channel [c] interrupt enable register */
7087 /*! @{ */
7088 
7089 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U)
7090 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U)
7091 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U)
7092 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_RE_IRQ_EN_MASK)
7093 
7094 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U)
7095 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U)
7096 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U)
7097 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_S_FE_IRQ_EN_MASK)
7098 
7099 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U)
7100 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U)
7101 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U)
7102 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_RE_IRQ_EN_MASK)
7103 
7104 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U)
7105 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U)
7106 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U)
7107 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_O_FE_IRQ_EN_MASK)
7108 
7109 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U)
7110 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U)
7111 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U)
7112 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_UPDATE_IRQ_EN_MASK)
7113 
7114 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U)
7115 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U)
7116 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U)
7117 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_EN_PL_EVT_IRQ_EN_MASK)
7118 /*! @} */
7119 
7120 /*! @name TIO3_G0_CH2_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */
7121 /*! @{ */
7122 
7123 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U)
7124 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U)
7125 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U)
7126 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_RE_IRQ_MASK)
7127 
7128 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U)
7129 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U)
7130 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U)
7131 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_S_FE_IRQ_MASK)
7132 
7133 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U)
7134 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U)
7135 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U)
7136 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_RE_IRQ_MASK)
7137 
7138 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U)
7139 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U)
7140 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U)
7141 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_O_FE_IRQ_MASK)
7142 
7143 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U)
7144 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U)
7145 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U)
7146 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK)
7147 
7148 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U)
7149 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U)
7150 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U)
7151 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK)
7152 /*! @} */
7153 
7154 /*! @name TIO3_G0_CH2_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */
7155 /*! @{ */
7156 
7157 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_MODE_IRQ_MODE_MASK (0x3U)
7158 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_MODE_IRQ_MODE_SHIFT (0U)
7159 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_MODE_IRQ_MODE_WIDTH (2U)
7160 #define GTM_gtm_cls3_TIO3_G0_CH2_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_IRQ_MODE_IRQ_MODE_MASK)
7161 /*! @} */
7162 
7163 /*! @name TIO3_G0_CH2_CTRL2 - TIO[i] group [g] channel [c] control register */
7164 /*! @{ */
7165 
7166 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_EN_MASK (0x1U)
7167 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_EN_SHIFT (0U)
7168 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_EN_WIDTH (1U)
7169 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_EN_MASK)
7170 
7171 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U)
7172 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U)
7173 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U)
7174 #define GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_CTRL2_DUAL_CMP_MST_EN_MASK)
7175 /*! @} */
7176 
7177 /*! @name TIO3_G0_CH2_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
7178 /*! @{ */
7179 
7180 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_OP_MASK   (0xFFFFFFU)
7181 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_OP_SHIFT  (0U)
7182 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_OP_WIDTH  (24U)
7183 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_SINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_SINST_OP_MASK)
7184 
7185 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_CMD_MASK  (0x3F000000U)
7186 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_CMD_SHIFT (24U)
7187 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_CMD_WIDTH (6U)
7188 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_SINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_SINST_CMD_MASK)
7189 
7190 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_DATA_PUSH_EN_MASK (0x40000000U)
7191 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_DATA_PUSH_EN_SHIFT (30U)
7192 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_DATA_PUSH_EN_WIDTH (1U)
7193 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_SINST_DATA_PUSH_EN_MASK)
7194 
7195 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_INSTR_PULL_EN_MASK (0x80000000U)
7196 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_INSTR_PULL_EN_SHIFT (31U)
7197 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_INSTR_PULL_EN_WIDTH (1U)
7198 #define GTM_gtm_cls3_TIO3_G0_CH2_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_SINST_INSTR_PULL_EN_MASK)
7199 /*! @} */
7200 
7201 /*! @name TIO3_G0_CH2_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
7202 /*! @{ */
7203 
7204 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_CMD_MASK   (0x3F000000U)
7205 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_CMD_SHIFT  (24U)
7206 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_CMD_WIDTH  (6U)
7207 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_SCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_SCMD_CMD_MASK)
7208 
7209 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_DATA_PUSH_EN_MASK (0x40000000U)
7210 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_DATA_PUSH_EN_SHIFT (30U)
7211 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_DATA_PUSH_EN_WIDTH (1U)
7212 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_SCMD_DATA_PUSH_EN_MASK)
7213 
7214 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_INSTR_PULL_EN_MASK (0x80000000U)
7215 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_INSTR_PULL_EN_SHIFT (31U)
7216 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_INSTR_PULL_EN_WIDTH (1U)
7217 #define GTM_gtm_cls3_TIO3_G0_CH2_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_SCMD_INSTR_PULL_EN_MASK)
7218 /*! @} */
7219 
7220 /*! @name TIO3_G0_CH2_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */
7221 /*! @{ */
7222 
7223 #define GTM_gtm_cls3_TIO3_G0_CH2_SOP_OP_MASK     (0xFFFFFFU)
7224 #define GTM_gtm_cls3_TIO3_G0_CH2_SOP_OP_SHIFT    (0U)
7225 #define GTM_gtm_cls3_TIO3_G0_CH2_SOP_OP_WIDTH    (24U)
7226 #define GTM_gtm_cls3_TIO3_G0_CH2_SOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_SOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_SOP_OP_MASK)
7227 /*! @} */
7228 
7229 /*! @name TIO3_G0_CH2_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */
7230 /*! @{ */
7231 
7232 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_OP_MASK   (0xFFFFFFU)
7233 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_OP_SHIFT  (0U)
7234 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_OP_WIDTH  (24U)
7235 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_OINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_OINST_OP_MASK)
7236 
7237 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_CMD_MASK  (0x3F000000U)
7238 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_CMD_SHIFT (24U)
7239 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_CMD_WIDTH (6U)
7240 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_OINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_OINST_CMD_MASK)
7241 
7242 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_DATA_PUSH_EN_MASK (0x40000000U)
7243 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_DATA_PUSH_EN_SHIFT (30U)
7244 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_DATA_PUSH_EN_WIDTH (1U)
7245 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_OINST_DATA_PUSH_EN_MASK)
7246 
7247 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_INSTR_PULL_EN_MASK (0x80000000U)
7248 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_INSTR_PULL_EN_SHIFT (31U)
7249 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_INSTR_PULL_EN_WIDTH (1U)
7250 #define GTM_gtm_cls3_TIO3_G0_CH2_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_OINST_INSTR_PULL_EN_MASK)
7251 /*! @} */
7252 
7253 /*! @name TIO3_G0_CH2_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */
7254 /*! @{ */
7255 
7256 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_CMD_MASK   (0x3F000000U)
7257 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_CMD_SHIFT  (24U)
7258 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_CMD_WIDTH  (6U)
7259 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_OCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_OCMD_CMD_MASK)
7260 
7261 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_DATA_PUSH_EN_MASK (0x40000000U)
7262 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_DATA_PUSH_EN_SHIFT (30U)
7263 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_DATA_PUSH_EN_WIDTH (1U)
7264 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_OCMD_DATA_PUSH_EN_MASK)
7265 
7266 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_INSTR_PULL_EN_MASK (0x80000000U)
7267 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_INSTR_PULL_EN_SHIFT (31U)
7268 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_INSTR_PULL_EN_WIDTH (1U)
7269 #define GTM_gtm_cls3_TIO3_G0_CH2_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_OCMD_INSTR_PULL_EN_MASK)
7270 /*! @} */
7271 
7272 /*! @name TIO3_G0_CH2_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */
7273 /*! @{ */
7274 
7275 #define GTM_gtm_cls3_TIO3_G0_CH2_OOP_OP_MASK     (0xFFFFFFU)
7276 #define GTM_gtm_cls3_TIO3_G0_CH2_OOP_OP_SHIFT    (0U)
7277 #define GTM_gtm_cls3_TIO3_G0_CH2_OOP_OP_WIDTH    (24U)
7278 #define GTM_gtm_cls3_TIO3_G0_CH2_OOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_OOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_OOP_OP_MASK)
7279 /*! @} */
7280 
7281 /*! @name TIO3_G0_CH2_SHIFTCNT - TIO[i] channel [c] resource shift count register */
7282 /*! @{ */
7283 
7284 #define GTM_gtm_cls3_TIO3_G0_CH2_SHIFTCNT_CNT_MASK (0x1FU)
7285 #define GTM_gtm_cls3_TIO3_G0_CH2_SHIFTCNT_CNT_SHIFT (0U)
7286 #define GTM_gtm_cls3_TIO3_G0_CH2_SHIFTCNT_CNT_WIDTH (5U)
7287 #define GTM_gtm_cls3_TIO3_G0_CH2_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH2_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH2_SHIFTCNT_CNT_MASK)
7288 /*! @} */
7289 
7290 /*! @name TIO3_G0_CH3_CTRL - TIO[i] group [g] channel [c] control register */
7291 /*! @{ */
7292 
7293 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U)
7294 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U)
7295 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U)
7296 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_RE_MASK)
7297 
7298 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U)
7299 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U)
7300 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U)
7301 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_S_FE_MASK)
7302 
7303 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U)
7304 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U)
7305 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U)
7306 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_RE_MASK)
7307 
7308 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U)
7309 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U)
7310 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U)
7311 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_O_FE_MASK)
7312 
7313 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U)
7314 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U)
7315 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
7316 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK)
7317 
7318 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U)
7319 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U)
7320 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
7321 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PL_EVT_MASK)
7322 
7323 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U)
7324 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U)
7325 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
7326 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
7327 
7328 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U)
7329 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U)
7330 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U)
7331 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK)
7332 
7333 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_UPDATE_SRC_MASK (0xF00U)
7334 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_UPDATE_SRC_SHIFT (8U)
7335 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_UPDATE_SRC_WIDTH (4U)
7336 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_UPDATE_SRC_MASK)
7337 
7338 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_MODE_MASK (0x3000U)
7339 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_MODE_SHIFT (12U)
7340 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_MODE_WIDTH (2U)
7341 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_MODE_MASK)
7342 
7343 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_S_EN_MASK (0x4000U)
7344 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_S_EN_SHIFT (14U)
7345 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_S_EN_WIDTH (1U)
7346 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_S_EN_MASK)
7347 
7348 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U)
7349 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_BUFF_SHIFT (15U)
7350 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_BUFF_WIDTH (1U)
7351 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_CYCLIC_BUFF_MASK)
7352 
7353 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_MODE_MASK (0x70000U)
7354 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_MODE_SHIFT (16U)
7355 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_MODE_WIDTH (3U)
7356 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_MODE_MASK)
7357 
7358 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_O_EN_MASK (0x80000U)
7359 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_O_EN_SHIFT (19U)
7360 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_O_EN_WIDTH (1U)
7361 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_FREEZE_O_EN_MASK)
7362 
7363 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_ODIS_MASK (0x100000U)
7364 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_ODIS_SHIFT (20U)
7365 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_ODIS_WIDTH (1U)
7366 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_ODIS_MASK)
7367 
7368 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_SEL_IN_MASK (0x200000U)
7369 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_SEL_IN_SHIFT (21U)
7370 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_SEL_IN_WIDTH (1U)
7371 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_SEL_IN_MASK)
7372 
7373 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U)
7374 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U)
7375 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U)
7376 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_O_TRIG_OUT_EN_MASK)
7377 
7378 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U)
7379 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U)
7380 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U)
7381 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_S_TRIG_OUT_EN_MASK)
7382 
7383 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U)
7384 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U)
7385 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U)
7386 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_RE_MASK)
7387 
7388 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U)
7389 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U)
7390 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U)
7391 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_S_FE_MASK)
7392 
7393 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U)
7394 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U)
7395 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U)
7396 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_RE_MASK)
7397 
7398 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U)
7399 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U)
7400 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U)
7401 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_O_FE_MASK)
7402 
7403 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U)
7404 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U)
7405 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
7406 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK)
7407 
7408 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U)
7409 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U)
7410 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
7411 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK)
7412 
7413 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U)
7414 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U)
7415 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
7416 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
7417 
7418 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U)
7419 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U)
7420 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U)
7421 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL_PL_TRIG_OUT_UPD_EN_MASK)
7422 /*! @} */
7423 
7424 /*! @name TIO3_G0_CH3_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */
7425 /*! @{ */
7426 
7427 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U)
7428 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U)
7429 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U)
7430 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_RE_IRQ_MASK)
7431 
7432 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U)
7433 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U)
7434 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U)
7435 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_S_FE_IRQ_MASK)
7436 
7437 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U)
7438 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U)
7439 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U)
7440 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_RE_IRQ_MASK)
7441 
7442 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U)
7443 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U)
7444 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U)
7445 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_O_FE_IRQ_MASK)
7446 
7447 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U)
7448 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U)
7449 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U)
7450 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_UPDATE_IRQ_MASK)
7451 
7452 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U)
7453 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U)
7454 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U)
7455 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_NOTIFY_PL_EVT_IRQ_MASK)
7456 /*! @} */
7457 
7458 /*! @name TIO3_G0_CH3_IRQ_EN - TIO[i] channel [c] interrupt enable register */
7459 /*! @{ */
7460 
7461 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U)
7462 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U)
7463 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U)
7464 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_RE_IRQ_EN_MASK)
7465 
7466 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U)
7467 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U)
7468 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U)
7469 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_S_FE_IRQ_EN_MASK)
7470 
7471 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U)
7472 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U)
7473 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U)
7474 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_RE_IRQ_EN_MASK)
7475 
7476 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U)
7477 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U)
7478 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U)
7479 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_O_FE_IRQ_EN_MASK)
7480 
7481 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U)
7482 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U)
7483 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U)
7484 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_UPDATE_IRQ_EN_MASK)
7485 
7486 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U)
7487 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U)
7488 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U)
7489 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_EN_PL_EVT_IRQ_EN_MASK)
7490 /*! @} */
7491 
7492 /*! @name TIO3_G0_CH3_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */
7493 /*! @{ */
7494 
7495 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U)
7496 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U)
7497 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U)
7498 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_RE_IRQ_MASK)
7499 
7500 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U)
7501 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U)
7502 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U)
7503 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_S_FE_IRQ_MASK)
7504 
7505 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U)
7506 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U)
7507 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U)
7508 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_RE_IRQ_MASK)
7509 
7510 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U)
7511 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U)
7512 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U)
7513 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_O_FE_IRQ_MASK)
7514 
7515 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U)
7516 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U)
7517 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U)
7518 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK)
7519 
7520 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U)
7521 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U)
7522 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U)
7523 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK)
7524 /*! @} */
7525 
7526 /*! @name TIO3_G0_CH3_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */
7527 /*! @{ */
7528 
7529 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_MODE_IRQ_MODE_MASK (0x3U)
7530 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_MODE_IRQ_MODE_SHIFT (0U)
7531 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_MODE_IRQ_MODE_WIDTH (2U)
7532 #define GTM_gtm_cls3_TIO3_G0_CH3_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_IRQ_MODE_IRQ_MODE_MASK)
7533 /*! @} */
7534 
7535 /*! @name TIO3_G0_CH3_CTRL2 - TIO[i] group [g] channel [c] control register */
7536 /*! @{ */
7537 
7538 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_EN_MASK (0x1U)
7539 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_EN_SHIFT (0U)
7540 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_EN_WIDTH (1U)
7541 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_EN_MASK)
7542 
7543 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U)
7544 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U)
7545 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U)
7546 #define GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_CTRL2_DUAL_CMP_MST_EN_MASK)
7547 /*! @} */
7548 
7549 /*! @name TIO3_G0_CH3_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
7550 /*! @{ */
7551 
7552 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_OP_MASK   (0xFFFFFFU)
7553 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_OP_SHIFT  (0U)
7554 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_OP_WIDTH  (24U)
7555 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_SINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_SINST_OP_MASK)
7556 
7557 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_CMD_MASK  (0x3F000000U)
7558 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_CMD_SHIFT (24U)
7559 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_CMD_WIDTH (6U)
7560 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_SINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_SINST_CMD_MASK)
7561 
7562 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_DATA_PUSH_EN_MASK (0x40000000U)
7563 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_DATA_PUSH_EN_SHIFT (30U)
7564 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_DATA_PUSH_EN_WIDTH (1U)
7565 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_SINST_DATA_PUSH_EN_MASK)
7566 
7567 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_INSTR_PULL_EN_MASK (0x80000000U)
7568 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_INSTR_PULL_EN_SHIFT (31U)
7569 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_INSTR_PULL_EN_WIDTH (1U)
7570 #define GTM_gtm_cls3_TIO3_G0_CH3_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_SINST_INSTR_PULL_EN_MASK)
7571 /*! @} */
7572 
7573 /*! @name TIO3_G0_CH3_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
7574 /*! @{ */
7575 
7576 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_CMD_MASK   (0x3F000000U)
7577 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_CMD_SHIFT  (24U)
7578 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_CMD_WIDTH  (6U)
7579 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_SCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_SCMD_CMD_MASK)
7580 
7581 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_DATA_PUSH_EN_MASK (0x40000000U)
7582 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_DATA_PUSH_EN_SHIFT (30U)
7583 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_DATA_PUSH_EN_WIDTH (1U)
7584 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_SCMD_DATA_PUSH_EN_MASK)
7585 
7586 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_INSTR_PULL_EN_MASK (0x80000000U)
7587 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_INSTR_PULL_EN_SHIFT (31U)
7588 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_INSTR_PULL_EN_WIDTH (1U)
7589 #define GTM_gtm_cls3_TIO3_G0_CH3_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_SCMD_INSTR_PULL_EN_MASK)
7590 /*! @} */
7591 
7592 /*! @name TIO3_G0_CH3_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */
7593 /*! @{ */
7594 
7595 #define GTM_gtm_cls3_TIO3_G0_CH3_SOP_OP_MASK     (0xFFFFFFU)
7596 #define GTM_gtm_cls3_TIO3_G0_CH3_SOP_OP_SHIFT    (0U)
7597 #define GTM_gtm_cls3_TIO3_G0_CH3_SOP_OP_WIDTH    (24U)
7598 #define GTM_gtm_cls3_TIO3_G0_CH3_SOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_SOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_SOP_OP_MASK)
7599 /*! @} */
7600 
7601 /*! @name TIO3_G0_CH3_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */
7602 /*! @{ */
7603 
7604 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_OP_MASK   (0xFFFFFFU)
7605 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_OP_SHIFT  (0U)
7606 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_OP_WIDTH  (24U)
7607 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_OINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_OINST_OP_MASK)
7608 
7609 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_CMD_MASK  (0x3F000000U)
7610 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_CMD_SHIFT (24U)
7611 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_CMD_WIDTH (6U)
7612 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_OINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_OINST_CMD_MASK)
7613 
7614 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_DATA_PUSH_EN_MASK (0x40000000U)
7615 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_DATA_PUSH_EN_SHIFT (30U)
7616 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_DATA_PUSH_EN_WIDTH (1U)
7617 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_OINST_DATA_PUSH_EN_MASK)
7618 
7619 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_INSTR_PULL_EN_MASK (0x80000000U)
7620 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_INSTR_PULL_EN_SHIFT (31U)
7621 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_INSTR_PULL_EN_WIDTH (1U)
7622 #define GTM_gtm_cls3_TIO3_G0_CH3_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_OINST_INSTR_PULL_EN_MASK)
7623 /*! @} */
7624 
7625 /*! @name TIO3_G0_CH3_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */
7626 /*! @{ */
7627 
7628 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_CMD_MASK   (0x3F000000U)
7629 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_CMD_SHIFT  (24U)
7630 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_CMD_WIDTH  (6U)
7631 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_OCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_OCMD_CMD_MASK)
7632 
7633 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_DATA_PUSH_EN_MASK (0x40000000U)
7634 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_DATA_PUSH_EN_SHIFT (30U)
7635 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_DATA_PUSH_EN_WIDTH (1U)
7636 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_OCMD_DATA_PUSH_EN_MASK)
7637 
7638 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_INSTR_PULL_EN_MASK (0x80000000U)
7639 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_INSTR_PULL_EN_SHIFT (31U)
7640 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_INSTR_PULL_EN_WIDTH (1U)
7641 #define GTM_gtm_cls3_TIO3_G0_CH3_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_OCMD_INSTR_PULL_EN_MASK)
7642 /*! @} */
7643 
7644 /*! @name TIO3_G0_CH3_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */
7645 /*! @{ */
7646 
7647 #define GTM_gtm_cls3_TIO3_G0_CH3_OOP_OP_MASK     (0xFFFFFFU)
7648 #define GTM_gtm_cls3_TIO3_G0_CH3_OOP_OP_SHIFT    (0U)
7649 #define GTM_gtm_cls3_TIO3_G0_CH3_OOP_OP_WIDTH    (24U)
7650 #define GTM_gtm_cls3_TIO3_G0_CH3_OOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_OOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_OOP_OP_MASK)
7651 /*! @} */
7652 
7653 /*! @name TIO3_G0_CH3_SHIFTCNT - TIO[i] channel [c] resource shift count register */
7654 /*! @{ */
7655 
7656 #define GTM_gtm_cls3_TIO3_G0_CH3_SHIFTCNT_CNT_MASK (0x1FU)
7657 #define GTM_gtm_cls3_TIO3_G0_CH3_SHIFTCNT_CNT_SHIFT (0U)
7658 #define GTM_gtm_cls3_TIO3_G0_CH3_SHIFTCNT_CNT_WIDTH (5U)
7659 #define GTM_gtm_cls3_TIO3_G0_CH3_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH3_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH3_SHIFTCNT_CNT_MASK)
7660 /*! @} */
7661 
7662 /*! @name TIO3_G0_CH4_CTRL - TIO[i] group [g] channel [c] control register */
7663 /*! @{ */
7664 
7665 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U)
7666 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U)
7667 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U)
7668 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_RE_MASK)
7669 
7670 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U)
7671 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U)
7672 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U)
7673 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_S_FE_MASK)
7674 
7675 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U)
7676 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U)
7677 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U)
7678 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_RE_MASK)
7679 
7680 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U)
7681 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U)
7682 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U)
7683 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_O_FE_MASK)
7684 
7685 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U)
7686 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U)
7687 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
7688 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK)
7689 
7690 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U)
7691 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U)
7692 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
7693 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PL_EVT_MASK)
7694 
7695 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U)
7696 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U)
7697 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
7698 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
7699 
7700 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U)
7701 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U)
7702 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U)
7703 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK)
7704 
7705 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_UPDATE_SRC_MASK (0xF00U)
7706 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_UPDATE_SRC_SHIFT (8U)
7707 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_UPDATE_SRC_WIDTH (4U)
7708 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_UPDATE_SRC_MASK)
7709 
7710 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_MODE_MASK (0x3000U)
7711 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_MODE_SHIFT (12U)
7712 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_MODE_WIDTH (2U)
7713 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_MODE_MASK)
7714 
7715 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_S_EN_MASK (0x4000U)
7716 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_S_EN_SHIFT (14U)
7717 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_S_EN_WIDTH (1U)
7718 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_S_EN_MASK)
7719 
7720 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U)
7721 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_BUFF_SHIFT (15U)
7722 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_BUFF_WIDTH (1U)
7723 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_CYCLIC_BUFF_MASK)
7724 
7725 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_MODE_MASK (0x70000U)
7726 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_MODE_SHIFT (16U)
7727 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_MODE_WIDTH (3U)
7728 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_MODE_MASK)
7729 
7730 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_O_EN_MASK (0x80000U)
7731 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_O_EN_SHIFT (19U)
7732 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_O_EN_WIDTH (1U)
7733 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_FREEZE_O_EN_MASK)
7734 
7735 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_ODIS_MASK (0x100000U)
7736 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_ODIS_SHIFT (20U)
7737 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_ODIS_WIDTH (1U)
7738 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_ODIS_MASK)
7739 
7740 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_SEL_IN_MASK (0x200000U)
7741 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_SEL_IN_SHIFT (21U)
7742 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_SEL_IN_WIDTH (1U)
7743 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_SEL_IN_MASK)
7744 
7745 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U)
7746 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U)
7747 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U)
7748 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_O_TRIG_OUT_EN_MASK)
7749 
7750 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U)
7751 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U)
7752 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U)
7753 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_S_TRIG_OUT_EN_MASK)
7754 
7755 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U)
7756 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U)
7757 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U)
7758 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_RE_MASK)
7759 
7760 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U)
7761 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U)
7762 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U)
7763 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_S_FE_MASK)
7764 
7765 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U)
7766 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U)
7767 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U)
7768 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_RE_MASK)
7769 
7770 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U)
7771 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U)
7772 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U)
7773 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_O_FE_MASK)
7774 
7775 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U)
7776 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U)
7777 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
7778 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK)
7779 
7780 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U)
7781 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U)
7782 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
7783 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK)
7784 
7785 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U)
7786 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U)
7787 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
7788 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
7789 
7790 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U)
7791 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U)
7792 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U)
7793 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL_PL_TRIG_OUT_UPD_EN_MASK)
7794 /*! @} */
7795 
7796 /*! @name TIO3_G0_CH4_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */
7797 /*! @{ */
7798 
7799 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U)
7800 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U)
7801 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U)
7802 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_RE_IRQ_MASK)
7803 
7804 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U)
7805 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U)
7806 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U)
7807 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_S_FE_IRQ_MASK)
7808 
7809 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U)
7810 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U)
7811 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U)
7812 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_RE_IRQ_MASK)
7813 
7814 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U)
7815 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U)
7816 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U)
7817 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_O_FE_IRQ_MASK)
7818 
7819 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U)
7820 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U)
7821 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U)
7822 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_UPDATE_IRQ_MASK)
7823 
7824 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U)
7825 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U)
7826 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U)
7827 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_NOTIFY_PL_EVT_IRQ_MASK)
7828 /*! @} */
7829 
7830 /*! @name TIO3_G0_CH4_IRQ_EN - TIO[i] channel [c] interrupt enable register */
7831 /*! @{ */
7832 
7833 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U)
7834 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U)
7835 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U)
7836 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_RE_IRQ_EN_MASK)
7837 
7838 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U)
7839 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U)
7840 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U)
7841 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_S_FE_IRQ_EN_MASK)
7842 
7843 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U)
7844 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U)
7845 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U)
7846 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_RE_IRQ_EN_MASK)
7847 
7848 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U)
7849 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U)
7850 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U)
7851 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_O_FE_IRQ_EN_MASK)
7852 
7853 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U)
7854 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U)
7855 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U)
7856 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_UPDATE_IRQ_EN_MASK)
7857 
7858 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U)
7859 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U)
7860 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U)
7861 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_EN_PL_EVT_IRQ_EN_MASK)
7862 /*! @} */
7863 
7864 /*! @name TIO3_G0_CH4_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */
7865 /*! @{ */
7866 
7867 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U)
7868 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U)
7869 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U)
7870 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_RE_IRQ_MASK)
7871 
7872 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U)
7873 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U)
7874 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U)
7875 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_S_FE_IRQ_MASK)
7876 
7877 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U)
7878 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U)
7879 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U)
7880 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_RE_IRQ_MASK)
7881 
7882 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U)
7883 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U)
7884 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U)
7885 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_O_FE_IRQ_MASK)
7886 
7887 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U)
7888 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U)
7889 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U)
7890 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK)
7891 
7892 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U)
7893 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U)
7894 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U)
7895 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK)
7896 /*! @} */
7897 
7898 /*! @name TIO3_G0_CH4_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */
7899 /*! @{ */
7900 
7901 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_MODE_IRQ_MODE_MASK (0x3U)
7902 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_MODE_IRQ_MODE_SHIFT (0U)
7903 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_MODE_IRQ_MODE_WIDTH (2U)
7904 #define GTM_gtm_cls3_TIO3_G0_CH4_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_IRQ_MODE_IRQ_MODE_MASK)
7905 /*! @} */
7906 
7907 /*! @name TIO3_G0_CH4_CTRL2 - TIO[i] group [g] channel [c] control register */
7908 /*! @{ */
7909 
7910 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_EN_MASK (0x1U)
7911 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_EN_SHIFT (0U)
7912 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_EN_WIDTH (1U)
7913 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_EN_MASK)
7914 
7915 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U)
7916 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U)
7917 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U)
7918 #define GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_CTRL2_DUAL_CMP_MST_EN_MASK)
7919 /*! @} */
7920 
7921 /*! @name TIO3_G0_CH4_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
7922 /*! @{ */
7923 
7924 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_OP_MASK   (0xFFFFFFU)
7925 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_OP_SHIFT  (0U)
7926 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_OP_WIDTH  (24U)
7927 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_SINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_SINST_OP_MASK)
7928 
7929 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_CMD_MASK  (0x3F000000U)
7930 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_CMD_SHIFT (24U)
7931 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_CMD_WIDTH (6U)
7932 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_SINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_SINST_CMD_MASK)
7933 
7934 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_DATA_PUSH_EN_MASK (0x40000000U)
7935 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_DATA_PUSH_EN_SHIFT (30U)
7936 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_DATA_PUSH_EN_WIDTH (1U)
7937 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_SINST_DATA_PUSH_EN_MASK)
7938 
7939 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_INSTR_PULL_EN_MASK (0x80000000U)
7940 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_INSTR_PULL_EN_SHIFT (31U)
7941 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_INSTR_PULL_EN_WIDTH (1U)
7942 #define GTM_gtm_cls3_TIO3_G0_CH4_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_SINST_INSTR_PULL_EN_MASK)
7943 /*! @} */
7944 
7945 /*! @name TIO3_G0_CH4_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
7946 /*! @{ */
7947 
7948 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_CMD_MASK   (0x3F000000U)
7949 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_CMD_SHIFT  (24U)
7950 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_CMD_WIDTH  (6U)
7951 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_SCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_SCMD_CMD_MASK)
7952 
7953 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_DATA_PUSH_EN_MASK (0x40000000U)
7954 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_DATA_PUSH_EN_SHIFT (30U)
7955 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_DATA_PUSH_EN_WIDTH (1U)
7956 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_SCMD_DATA_PUSH_EN_MASK)
7957 
7958 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_INSTR_PULL_EN_MASK (0x80000000U)
7959 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_INSTR_PULL_EN_SHIFT (31U)
7960 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_INSTR_PULL_EN_WIDTH (1U)
7961 #define GTM_gtm_cls3_TIO3_G0_CH4_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_SCMD_INSTR_PULL_EN_MASK)
7962 /*! @} */
7963 
7964 /*! @name TIO3_G0_CH4_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */
7965 /*! @{ */
7966 
7967 #define GTM_gtm_cls3_TIO3_G0_CH4_SOP_OP_MASK     (0xFFFFFFU)
7968 #define GTM_gtm_cls3_TIO3_G0_CH4_SOP_OP_SHIFT    (0U)
7969 #define GTM_gtm_cls3_TIO3_G0_CH4_SOP_OP_WIDTH    (24U)
7970 #define GTM_gtm_cls3_TIO3_G0_CH4_SOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_SOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_SOP_OP_MASK)
7971 /*! @} */
7972 
7973 /*! @name TIO3_G0_CH4_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */
7974 /*! @{ */
7975 
7976 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_OP_MASK   (0xFFFFFFU)
7977 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_OP_SHIFT  (0U)
7978 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_OP_WIDTH  (24U)
7979 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_OINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_OINST_OP_MASK)
7980 
7981 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_CMD_MASK  (0x3F000000U)
7982 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_CMD_SHIFT (24U)
7983 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_CMD_WIDTH (6U)
7984 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_OINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_OINST_CMD_MASK)
7985 
7986 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_DATA_PUSH_EN_MASK (0x40000000U)
7987 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_DATA_PUSH_EN_SHIFT (30U)
7988 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_DATA_PUSH_EN_WIDTH (1U)
7989 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_OINST_DATA_PUSH_EN_MASK)
7990 
7991 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_INSTR_PULL_EN_MASK (0x80000000U)
7992 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_INSTR_PULL_EN_SHIFT (31U)
7993 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_INSTR_PULL_EN_WIDTH (1U)
7994 #define GTM_gtm_cls3_TIO3_G0_CH4_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_OINST_INSTR_PULL_EN_MASK)
7995 /*! @} */
7996 
7997 /*! @name TIO3_G0_CH4_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */
7998 /*! @{ */
7999 
8000 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_CMD_MASK   (0x3F000000U)
8001 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_CMD_SHIFT  (24U)
8002 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_CMD_WIDTH  (6U)
8003 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_OCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_OCMD_CMD_MASK)
8004 
8005 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_DATA_PUSH_EN_MASK (0x40000000U)
8006 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_DATA_PUSH_EN_SHIFT (30U)
8007 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_DATA_PUSH_EN_WIDTH (1U)
8008 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_OCMD_DATA_PUSH_EN_MASK)
8009 
8010 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_INSTR_PULL_EN_MASK (0x80000000U)
8011 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_INSTR_PULL_EN_SHIFT (31U)
8012 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_INSTR_PULL_EN_WIDTH (1U)
8013 #define GTM_gtm_cls3_TIO3_G0_CH4_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_OCMD_INSTR_PULL_EN_MASK)
8014 /*! @} */
8015 
8016 /*! @name TIO3_G0_CH4_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */
8017 /*! @{ */
8018 
8019 #define GTM_gtm_cls3_TIO3_G0_CH4_OOP_OP_MASK     (0xFFFFFFU)
8020 #define GTM_gtm_cls3_TIO3_G0_CH4_OOP_OP_SHIFT    (0U)
8021 #define GTM_gtm_cls3_TIO3_G0_CH4_OOP_OP_WIDTH    (24U)
8022 #define GTM_gtm_cls3_TIO3_G0_CH4_OOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_OOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_OOP_OP_MASK)
8023 /*! @} */
8024 
8025 /*! @name TIO3_G0_CH4_SHIFTCNT - TIO[i] channel [c] resource shift count register */
8026 /*! @{ */
8027 
8028 #define GTM_gtm_cls3_TIO3_G0_CH4_SHIFTCNT_CNT_MASK (0x1FU)
8029 #define GTM_gtm_cls3_TIO3_G0_CH4_SHIFTCNT_CNT_SHIFT (0U)
8030 #define GTM_gtm_cls3_TIO3_G0_CH4_SHIFTCNT_CNT_WIDTH (5U)
8031 #define GTM_gtm_cls3_TIO3_G0_CH4_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH4_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH4_SHIFTCNT_CNT_MASK)
8032 /*! @} */
8033 
8034 /*! @name TIO3_G0_CH5_CTRL - TIO[i] group [g] channel [c] control register */
8035 /*! @{ */
8036 
8037 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U)
8038 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U)
8039 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U)
8040 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_RE_MASK)
8041 
8042 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U)
8043 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U)
8044 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U)
8045 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_S_FE_MASK)
8046 
8047 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U)
8048 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U)
8049 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U)
8050 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_RE_MASK)
8051 
8052 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U)
8053 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U)
8054 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U)
8055 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_O_FE_MASK)
8056 
8057 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U)
8058 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U)
8059 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
8060 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK)
8061 
8062 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U)
8063 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U)
8064 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
8065 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PL_EVT_MASK)
8066 
8067 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U)
8068 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U)
8069 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
8070 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
8071 
8072 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U)
8073 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U)
8074 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U)
8075 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK)
8076 
8077 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_UPDATE_SRC_MASK (0xF00U)
8078 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_UPDATE_SRC_SHIFT (8U)
8079 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_UPDATE_SRC_WIDTH (4U)
8080 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_UPDATE_SRC_MASK)
8081 
8082 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_MODE_MASK (0x3000U)
8083 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_MODE_SHIFT (12U)
8084 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_MODE_WIDTH (2U)
8085 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_MODE_MASK)
8086 
8087 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_S_EN_MASK (0x4000U)
8088 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_S_EN_SHIFT (14U)
8089 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_S_EN_WIDTH (1U)
8090 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_S_EN_MASK)
8091 
8092 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U)
8093 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_BUFF_SHIFT (15U)
8094 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_BUFF_WIDTH (1U)
8095 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_CYCLIC_BUFF_MASK)
8096 
8097 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_MODE_MASK (0x70000U)
8098 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_MODE_SHIFT (16U)
8099 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_MODE_WIDTH (3U)
8100 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_MODE_MASK)
8101 
8102 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_O_EN_MASK (0x80000U)
8103 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_O_EN_SHIFT (19U)
8104 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_O_EN_WIDTH (1U)
8105 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_FREEZE_O_EN_MASK)
8106 
8107 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_ODIS_MASK (0x100000U)
8108 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_ODIS_SHIFT (20U)
8109 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_ODIS_WIDTH (1U)
8110 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_ODIS_MASK)
8111 
8112 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_SEL_IN_MASK (0x200000U)
8113 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_SEL_IN_SHIFT (21U)
8114 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_SEL_IN_WIDTH (1U)
8115 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_SEL_IN_MASK)
8116 
8117 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U)
8118 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U)
8119 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U)
8120 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_O_TRIG_OUT_EN_MASK)
8121 
8122 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U)
8123 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U)
8124 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U)
8125 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_S_TRIG_OUT_EN_MASK)
8126 
8127 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U)
8128 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U)
8129 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U)
8130 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_RE_MASK)
8131 
8132 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U)
8133 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U)
8134 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U)
8135 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_S_FE_MASK)
8136 
8137 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U)
8138 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U)
8139 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U)
8140 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_RE_MASK)
8141 
8142 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U)
8143 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U)
8144 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U)
8145 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_O_FE_MASK)
8146 
8147 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U)
8148 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U)
8149 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
8150 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK)
8151 
8152 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U)
8153 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U)
8154 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
8155 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK)
8156 
8157 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U)
8158 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U)
8159 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
8160 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
8161 
8162 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U)
8163 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U)
8164 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U)
8165 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL_PL_TRIG_OUT_UPD_EN_MASK)
8166 /*! @} */
8167 
8168 /*! @name TIO3_G0_CH5_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */
8169 /*! @{ */
8170 
8171 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U)
8172 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U)
8173 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U)
8174 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_RE_IRQ_MASK)
8175 
8176 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U)
8177 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U)
8178 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U)
8179 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_S_FE_IRQ_MASK)
8180 
8181 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U)
8182 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U)
8183 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U)
8184 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_RE_IRQ_MASK)
8185 
8186 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U)
8187 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U)
8188 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U)
8189 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_O_FE_IRQ_MASK)
8190 
8191 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U)
8192 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U)
8193 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U)
8194 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_UPDATE_IRQ_MASK)
8195 
8196 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U)
8197 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U)
8198 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U)
8199 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_NOTIFY_PL_EVT_IRQ_MASK)
8200 /*! @} */
8201 
8202 /*! @name TIO3_G0_CH5_IRQ_EN - TIO[i] channel [c] interrupt enable register */
8203 /*! @{ */
8204 
8205 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U)
8206 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U)
8207 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U)
8208 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_RE_IRQ_EN_MASK)
8209 
8210 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U)
8211 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U)
8212 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U)
8213 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_S_FE_IRQ_EN_MASK)
8214 
8215 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U)
8216 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U)
8217 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U)
8218 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_RE_IRQ_EN_MASK)
8219 
8220 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U)
8221 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U)
8222 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U)
8223 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_O_FE_IRQ_EN_MASK)
8224 
8225 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U)
8226 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U)
8227 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U)
8228 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_UPDATE_IRQ_EN_MASK)
8229 
8230 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U)
8231 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U)
8232 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U)
8233 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_EN_PL_EVT_IRQ_EN_MASK)
8234 /*! @} */
8235 
8236 /*! @name TIO3_G0_CH5_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */
8237 /*! @{ */
8238 
8239 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U)
8240 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U)
8241 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U)
8242 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_RE_IRQ_MASK)
8243 
8244 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U)
8245 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U)
8246 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U)
8247 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_S_FE_IRQ_MASK)
8248 
8249 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U)
8250 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U)
8251 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U)
8252 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_RE_IRQ_MASK)
8253 
8254 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U)
8255 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U)
8256 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U)
8257 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_O_FE_IRQ_MASK)
8258 
8259 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U)
8260 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U)
8261 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U)
8262 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK)
8263 
8264 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U)
8265 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U)
8266 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U)
8267 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK)
8268 /*! @} */
8269 
8270 /*! @name TIO3_G0_CH5_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */
8271 /*! @{ */
8272 
8273 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_MODE_IRQ_MODE_MASK (0x3U)
8274 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_MODE_IRQ_MODE_SHIFT (0U)
8275 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_MODE_IRQ_MODE_WIDTH (2U)
8276 #define GTM_gtm_cls3_TIO3_G0_CH5_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_IRQ_MODE_IRQ_MODE_MASK)
8277 /*! @} */
8278 
8279 /*! @name TIO3_G0_CH5_CTRL2 - TIO[i] group [g] channel [c] control register */
8280 /*! @{ */
8281 
8282 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_EN_MASK (0x1U)
8283 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_EN_SHIFT (0U)
8284 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_EN_WIDTH (1U)
8285 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_EN_MASK)
8286 
8287 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U)
8288 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U)
8289 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U)
8290 #define GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_CTRL2_DUAL_CMP_MST_EN_MASK)
8291 /*! @} */
8292 
8293 /*! @name TIO3_G0_CH5_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
8294 /*! @{ */
8295 
8296 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_OP_MASK   (0xFFFFFFU)
8297 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_OP_SHIFT  (0U)
8298 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_OP_WIDTH  (24U)
8299 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_SINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_SINST_OP_MASK)
8300 
8301 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_CMD_MASK  (0x3F000000U)
8302 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_CMD_SHIFT (24U)
8303 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_CMD_WIDTH (6U)
8304 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_SINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_SINST_CMD_MASK)
8305 
8306 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_DATA_PUSH_EN_MASK (0x40000000U)
8307 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_DATA_PUSH_EN_SHIFT (30U)
8308 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_DATA_PUSH_EN_WIDTH (1U)
8309 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_SINST_DATA_PUSH_EN_MASK)
8310 
8311 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_INSTR_PULL_EN_MASK (0x80000000U)
8312 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_INSTR_PULL_EN_SHIFT (31U)
8313 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_INSTR_PULL_EN_WIDTH (1U)
8314 #define GTM_gtm_cls3_TIO3_G0_CH5_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_SINST_INSTR_PULL_EN_MASK)
8315 /*! @} */
8316 
8317 /*! @name TIO3_G0_CH5_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
8318 /*! @{ */
8319 
8320 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_CMD_MASK   (0x3F000000U)
8321 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_CMD_SHIFT  (24U)
8322 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_CMD_WIDTH  (6U)
8323 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_SCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_SCMD_CMD_MASK)
8324 
8325 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_DATA_PUSH_EN_MASK (0x40000000U)
8326 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_DATA_PUSH_EN_SHIFT (30U)
8327 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_DATA_PUSH_EN_WIDTH (1U)
8328 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_SCMD_DATA_PUSH_EN_MASK)
8329 
8330 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_INSTR_PULL_EN_MASK (0x80000000U)
8331 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_INSTR_PULL_EN_SHIFT (31U)
8332 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_INSTR_PULL_EN_WIDTH (1U)
8333 #define GTM_gtm_cls3_TIO3_G0_CH5_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_SCMD_INSTR_PULL_EN_MASK)
8334 /*! @} */
8335 
8336 /*! @name TIO3_G0_CH5_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */
8337 /*! @{ */
8338 
8339 #define GTM_gtm_cls3_TIO3_G0_CH5_SOP_OP_MASK     (0xFFFFFFU)
8340 #define GTM_gtm_cls3_TIO3_G0_CH5_SOP_OP_SHIFT    (0U)
8341 #define GTM_gtm_cls3_TIO3_G0_CH5_SOP_OP_WIDTH    (24U)
8342 #define GTM_gtm_cls3_TIO3_G0_CH5_SOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_SOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_SOP_OP_MASK)
8343 /*! @} */
8344 
8345 /*! @name TIO3_G0_CH5_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */
8346 /*! @{ */
8347 
8348 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_OP_MASK   (0xFFFFFFU)
8349 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_OP_SHIFT  (0U)
8350 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_OP_WIDTH  (24U)
8351 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_OINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_OINST_OP_MASK)
8352 
8353 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_CMD_MASK  (0x3F000000U)
8354 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_CMD_SHIFT (24U)
8355 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_CMD_WIDTH (6U)
8356 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_OINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_OINST_CMD_MASK)
8357 
8358 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_DATA_PUSH_EN_MASK (0x40000000U)
8359 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_DATA_PUSH_EN_SHIFT (30U)
8360 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_DATA_PUSH_EN_WIDTH (1U)
8361 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_OINST_DATA_PUSH_EN_MASK)
8362 
8363 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_INSTR_PULL_EN_MASK (0x80000000U)
8364 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_INSTR_PULL_EN_SHIFT (31U)
8365 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_INSTR_PULL_EN_WIDTH (1U)
8366 #define GTM_gtm_cls3_TIO3_G0_CH5_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_OINST_INSTR_PULL_EN_MASK)
8367 /*! @} */
8368 
8369 /*! @name TIO3_G0_CH5_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */
8370 /*! @{ */
8371 
8372 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_CMD_MASK   (0x3F000000U)
8373 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_CMD_SHIFT  (24U)
8374 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_CMD_WIDTH  (6U)
8375 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_OCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_OCMD_CMD_MASK)
8376 
8377 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_DATA_PUSH_EN_MASK (0x40000000U)
8378 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_DATA_PUSH_EN_SHIFT (30U)
8379 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_DATA_PUSH_EN_WIDTH (1U)
8380 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_OCMD_DATA_PUSH_EN_MASK)
8381 
8382 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_INSTR_PULL_EN_MASK (0x80000000U)
8383 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_INSTR_PULL_EN_SHIFT (31U)
8384 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_INSTR_PULL_EN_WIDTH (1U)
8385 #define GTM_gtm_cls3_TIO3_G0_CH5_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_OCMD_INSTR_PULL_EN_MASK)
8386 /*! @} */
8387 
8388 /*! @name TIO3_G0_CH5_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */
8389 /*! @{ */
8390 
8391 #define GTM_gtm_cls3_TIO3_G0_CH5_OOP_OP_MASK     (0xFFFFFFU)
8392 #define GTM_gtm_cls3_TIO3_G0_CH5_OOP_OP_SHIFT    (0U)
8393 #define GTM_gtm_cls3_TIO3_G0_CH5_OOP_OP_WIDTH    (24U)
8394 #define GTM_gtm_cls3_TIO3_G0_CH5_OOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_OOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_OOP_OP_MASK)
8395 /*! @} */
8396 
8397 /*! @name TIO3_G0_CH5_SHIFTCNT - TIO[i] channel [c] resource shift count register */
8398 /*! @{ */
8399 
8400 #define GTM_gtm_cls3_TIO3_G0_CH5_SHIFTCNT_CNT_MASK (0x1FU)
8401 #define GTM_gtm_cls3_TIO3_G0_CH5_SHIFTCNT_CNT_SHIFT (0U)
8402 #define GTM_gtm_cls3_TIO3_G0_CH5_SHIFTCNT_CNT_WIDTH (5U)
8403 #define GTM_gtm_cls3_TIO3_G0_CH5_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH5_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH5_SHIFTCNT_CNT_MASK)
8404 /*! @} */
8405 
8406 /*! @name TIO3_G0_CH6_CTRL - TIO[i] group [g] channel [c] control register */
8407 /*! @{ */
8408 
8409 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U)
8410 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U)
8411 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U)
8412 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_RE_MASK)
8413 
8414 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U)
8415 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U)
8416 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U)
8417 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_S_FE_MASK)
8418 
8419 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U)
8420 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U)
8421 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U)
8422 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_RE_MASK)
8423 
8424 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U)
8425 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U)
8426 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U)
8427 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_O_FE_MASK)
8428 
8429 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U)
8430 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U)
8431 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
8432 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK)
8433 
8434 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U)
8435 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U)
8436 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
8437 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PL_EVT_MASK)
8438 
8439 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U)
8440 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U)
8441 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
8442 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
8443 
8444 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U)
8445 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U)
8446 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U)
8447 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK)
8448 
8449 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_UPDATE_SRC_MASK (0xF00U)
8450 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_UPDATE_SRC_SHIFT (8U)
8451 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_UPDATE_SRC_WIDTH (4U)
8452 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_UPDATE_SRC_MASK)
8453 
8454 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_MODE_MASK (0x3000U)
8455 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_MODE_SHIFT (12U)
8456 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_MODE_WIDTH (2U)
8457 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_MODE_MASK)
8458 
8459 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_S_EN_MASK (0x4000U)
8460 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_S_EN_SHIFT (14U)
8461 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_S_EN_WIDTH (1U)
8462 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_S_EN_MASK)
8463 
8464 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U)
8465 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_BUFF_SHIFT (15U)
8466 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_BUFF_WIDTH (1U)
8467 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_CYCLIC_BUFF_MASK)
8468 
8469 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_MODE_MASK (0x70000U)
8470 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_MODE_SHIFT (16U)
8471 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_MODE_WIDTH (3U)
8472 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_MODE_MASK)
8473 
8474 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_O_EN_MASK (0x80000U)
8475 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_O_EN_SHIFT (19U)
8476 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_O_EN_WIDTH (1U)
8477 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_FREEZE_O_EN_MASK)
8478 
8479 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_ODIS_MASK (0x100000U)
8480 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_ODIS_SHIFT (20U)
8481 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_ODIS_WIDTH (1U)
8482 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_ODIS_MASK)
8483 
8484 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_SEL_IN_MASK (0x200000U)
8485 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_SEL_IN_SHIFT (21U)
8486 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_SEL_IN_WIDTH (1U)
8487 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_SEL_IN_MASK)
8488 
8489 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U)
8490 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U)
8491 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U)
8492 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_O_TRIG_OUT_EN_MASK)
8493 
8494 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U)
8495 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U)
8496 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U)
8497 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_S_TRIG_OUT_EN_MASK)
8498 
8499 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U)
8500 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U)
8501 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U)
8502 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_RE_MASK)
8503 
8504 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U)
8505 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U)
8506 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U)
8507 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_S_FE_MASK)
8508 
8509 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U)
8510 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U)
8511 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U)
8512 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_RE_MASK)
8513 
8514 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U)
8515 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U)
8516 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U)
8517 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_O_FE_MASK)
8518 
8519 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U)
8520 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U)
8521 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
8522 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK)
8523 
8524 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U)
8525 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U)
8526 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
8527 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK)
8528 
8529 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U)
8530 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U)
8531 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
8532 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
8533 
8534 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U)
8535 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U)
8536 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U)
8537 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL_PL_TRIG_OUT_UPD_EN_MASK)
8538 /*! @} */
8539 
8540 /*! @name TIO3_G0_CH6_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */
8541 /*! @{ */
8542 
8543 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U)
8544 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U)
8545 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U)
8546 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_RE_IRQ_MASK)
8547 
8548 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U)
8549 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U)
8550 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U)
8551 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_S_FE_IRQ_MASK)
8552 
8553 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U)
8554 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U)
8555 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U)
8556 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_RE_IRQ_MASK)
8557 
8558 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U)
8559 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U)
8560 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U)
8561 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_O_FE_IRQ_MASK)
8562 
8563 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U)
8564 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U)
8565 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U)
8566 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_UPDATE_IRQ_MASK)
8567 
8568 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U)
8569 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U)
8570 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U)
8571 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_NOTIFY_PL_EVT_IRQ_MASK)
8572 /*! @} */
8573 
8574 /*! @name TIO3_G0_CH6_IRQ_EN - TIO[i] channel [c] interrupt enable register */
8575 /*! @{ */
8576 
8577 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U)
8578 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U)
8579 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U)
8580 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_RE_IRQ_EN_MASK)
8581 
8582 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U)
8583 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U)
8584 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U)
8585 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_S_FE_IRQ_EN_MASK)
8586 
8587 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U)
8588 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U)
8589 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U)
8590 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_RE_IRQ_EN_MASK)
8591 
8592 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U)
8593 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U)
8594 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U)
8595 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_O_FE_IRQ_EN_MASK)
8596 
8597 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U)
8598 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U)
8599 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U)
8600 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_UPDATE_IRQ_EN_MASK)
8601 
8602 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U)
8603 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U)
8604 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U)
8605 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_EN_PL_EVT_IRQ_EN_MASK)
8606 /*! @} */
8607 
8608 /*! @name TIO3_G0_CH6_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */
8609 /*! @{ */
8610 
8611 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U)
8612 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U)
8613 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U)
8614 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_RE_IRQ_MASK)
8615 
8616 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U)
8617 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U)
8618 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U)
8619 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_S_FE_IRQ_MASK)
8620 
8621 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U)
8622 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U)
8623 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U)
8624 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_RE_IRQ_MASK)
8625 
8626 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U)
8627 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U)
8628 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U)
8629 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_O_FE_IRQ_MASK)
8630 
8631 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U)
8632 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U)
8633 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U)
8634 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK)
8635 
8636 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U)
8637 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U)
8638 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U)
8639 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK)
8640 /*! @} */
8641 
8642 /*! @name TIO3_G0_CH6_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */
8643 /*! @{ */
8644 
8645 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_MODE_IRQ_MODE_MASK (0x3U)
8646 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_MODE_IRQ_MODE_SHIFT (0U)
8647 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_MODE_IRQ_MODE_WIDTH (2U)
8648 #define GTM_gtm_cls3_TIO3_G0_CH6_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_IRQ_MODE_IRQ_MODE_MASK)
8649 /*! @} */
8650 
8651 /*! @name TIO3_G0_CH6_CTRL2 - TIO[i] group [g] channel [c] control register */
8652 /*! @{ */
8653 
8654 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_EN_MASK (0x1U)
8655 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_EN_SHIFT (0U)
8656 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_EN_WIDTH (1U)
8657 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_EN_MASK)
8658 
8659 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U)
8660 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U)
8661 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U)
8662 #define GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_CTRL2_DUAL_CMP_MST_EN_MASK)
8663 /*! @} */
8664 
8665 /*! @name TIO3_G0_CH6_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
8666 /*! @{ */
8667 
8668 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_OP_MASK   (0xFFFFFFU)
8669 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_OP_SHIFT  (0U)
8670 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_OP_WIDTH  (24U)
8671 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_SINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_SINST_OP_MASK)
8672 
8673 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_CMD_MASK  (0x3F000000U)
8674 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_CMD_SHIFT (24U)
8675 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_CMD_WIDTH (6U)
8676 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_SINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_SINST_CMD_MASK)
8677 
8678 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_DATA_PUSH_EN_MASK (0x40000000U)
8679 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_DATA_PUSH_EN_SHIFT (30U)
8680 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_DATA_PUSH_EN_WIDTH (1U)
8681 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_SINST_DATA_PUSH_EN_MASK)
8682 
8683 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_INSTR_PULL_EN_MASK (0x80000000U)
8684 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_INSTR_PULL_EN_SHIFT (31U)
8685 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_INSTR_PULL_EN_WIDTH (1U)
8686 #define GTM_gtm_cls3_TIO3_G0_CH6_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_SINST_INSTR_PULL_EN_MASK)
8687 /*! @} */
8688 
8689 /*! @name TIO3_G0_CH6_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
8690 /*! @{ */
8691 
8692 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_CMD_MASK   (0x3F000000U)
8693 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_CMD_SHIFT  (24U)
8694 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_CMD_WIDTH  (6U)
8695 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_SCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_SCMD_CMD_MASK)
8696 
8697 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_DATA_PUSH_EN_MASK (0x40000000U)
8698 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_DATA_PUSH_EN_SHIFT (30U)
8699 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_DATA_PUSH_EN_WIDTH (1U)
8700 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_SCMD_DATA_PUSH_EN_MASK)
8701 
8702 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_INSTR_PULL_EN_MASK (0x80000000U)
8703 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_INSTR_PULL_EN_SHIFT (31U)
8704 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_INSTR_PULL_EN_WIDTH (1U)
8705 #define GTM_gtm_cls3_TIO3_G0_CH6_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_SCMD_INSTR_PULL_EN_MASK)
8706 /*! @} */
8707 
8708 /*! @name TIO3_G0_CH6_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */
8709 /*! @{ */
8710 
8711 #define GTM_gtm_cls3_TIO3_G0_CH6_SOP_OP_MASK     (0xFFFFFFU)
8712 #define GTM_gtm_cls3_TIO3_G0_CH6_SOP_OP_SHIFT    (0U)
8713 #define GTM_gtm_cls3_TIO3_G0_CH6_SOP_OP_WIDTH    (24U)
8714 #define GTM_gtm_cls3_TIO3_G0_CH6_SOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_SOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_SOP_OP_MASK)
8715 /*! @} */
8716 
8717 /*! @name TIO3_G0_CH6_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */
8718 /*! @{ */
8719 
8720 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_OP_MASK   (0xFFFFFFU)
8721 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_OP_SHIFT  (0U)
8722 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_OP_WIDTH  (24U)
8723 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_OINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_OINST_OP_MASK)
8724 
8725 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_CMD_MASK  (0x3F000000U)
8726 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_CMD_SHIFT (24U)
8727 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_CMD_WIDTH (6U)
8728 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_OINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_OINST_CMD_MASK)
8729 
8730 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_DATA_PUSH_EN_MASK (0x40000000U)
8731 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_DATA_PUSH_EN_SHIFT (30U)
8732 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_DATA_PUSH_EN_WIDTH (1U)
8733 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_OINST_DATA_PUSH_EN_MASK)
8734 
8735 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_INSTR_PULL_EN_MASK (0x80000000U)
8736 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_INSTR_PULL_EN_SHIFT (31U)
8737 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_INSTR_PULL_EN_WIDTH (1U)
8738 #define GTM_gtm_cls3_TIO3_G0_CH6_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_OINST_INSTR_PULL_EN_MASK)
8739 /*! @} */
8740 
8741 /*! @name TIO3_G0_CH6_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */
8742 /*! @{ */
8743 
8744 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_CMD_MASK   (0x3F000000U)
8745 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_CMD_SHIFT  (24U)
8746 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_CMD_WIDTH  (6U)
8747 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_OCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_OCMD_CMD_MASK)
8748 
8749 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_DATA_PUSH_EN_MASK (0x40000000U)
8750 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_DATA_PUSH_EN_SHIFT (30U)
8751 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_DATA_PUSH_EN_WIDTH (1U)
8752 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_OCMD_DATA_PUSH_EN_MASK)
8753 
8754 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_INSTR_PULL_EN_MASK (0x80000000U)
8755 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_INSTR_PULL_EN_SHIFT (31U)
8756 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_INSTR_PULL_EN_WIDTH (1U)
8757 #define GTM_gtm_cls3_TIO3_G0_CH6_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_OCMD_INSTR_PULL_EN_MASK)
8758 /*! @} */
8759 
8760 /*! @name TIO3_G0_CH6_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */
8761 /*! @{ */
8762 
8763 #define GTM_gtm_cls3_TIO3_G0_CH6_OOP_OP_MASK     (0xFFFFFFU)
8764 #define GTM_gtm_cls3_TIO3_G0_CH6_OOP_OP_SHIFT    (0U)
8765 #define GTM_gtm_cls3_TIO3_G0_CH6_OOP_OP_WIDTH    (24U)
8766 #define GTM_gtm_cls3_TIO3_G0_CH6_OOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_OOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_OOP_OP_MASK)
8767 /*! @} */
8768 
8769 /*! @name TIO3_G0_CH6_SHIFTCNT - TIO[i] channel [c] resource shift count register */
8770 /*! @{ */
8771 
8772 #define GTM_gtm_cls3_TIO3_G0_CH6_SHIFTCNT_CNT_MASK (0x1FU)
8773 #define GTM_gtm_cls3_TIO3_G0_CH6_SHIFTCNT_CNT_SHIFT (0U)
8774 #define GTM_gtm_cls3_TIO3_G0_CH6_SHIFTCNT_CNT_WIDTH (5U)
8775 #define GTM_gtm_cls3_TIO3_G0_CH6_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH6_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH6_SHIFTCNT_CNT_MASK)
8776 /*! @} */
8777 
8778 /*! @name TIO3_G0_CH7_CTRL - TIO[i] group [g] channel [c] control register */
8779 /*! @{ */
8780 
8781 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_RE_MASK (0x1U)
8782 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_RE_SHIFT (0U)
8783 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_RE_WIDTH (1U)
8784 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_RE_MASK)
8785 
8786 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_FE_MASK (0x2U)
8787 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_FE_SHIFT (1U)
8788 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_FE_WIDTH (1U)
8789 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_S_FE_MASK)
8790 
8791 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_RE_MASK (0x4U)
8792 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_RE_SHIFT (2U)
8793 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_RE_WIDTH (1U)
8794 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_RE_MASK)
8795 
8796 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_FE_MASK (0x8U)
8797 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_FE_SHIFT (3U)
8798 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_FE_WIDTH (1U)
8799 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_O_FE_MASK)
8800 
8801 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10U)
8802 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT (4U)
8803 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
8804 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_TRIG_MASK)
8805 
8806 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT_MASK (0x20U)
8807 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT (5U)
8808 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
8809 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PL_EVT_MASK)
8810 
8811 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40U)
8812 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (6U)
8813 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
8814 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
8815 
8816 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK (0x80U)
8817 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT (7U)
8818 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN_WIDTH (1U)
8819 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_INIT_TRIG_EN_MASK)
8820 
8821 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_UPDATE_SRC_MASK (0xF00U)
8822 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_UPDATE_SRC_SHIFT (8U)
8823 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_UPDATE_SRC_WIDTH (4U)
8824 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_UPDATE_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_UPDATE_SRC_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_UPDATE_SRC_MASK)
8825 
8826 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_MODE_MASK (0x3000U)
8827 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_MODE_SHIFT (12U)
8828 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_MODE_WIDTH (2U)
8829 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_MODE_MASK)
8830 
8831 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_S_EN_MASK (0x4000U)
8832 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_S_EN_SHIFT (14U)
8833 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_S_EN_WIDTH (1U)
8834 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_S_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_S_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_S_EN_MASK)
8835 
8836 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_BUFF_MASK (0x8000U)
8837 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_BUFF_SHIFT (15U)
8838 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_BUFF_WIDTH (1U)
8839 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_BUFF(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_BUFF_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_CYCLIC_BUFF_MASK)
8840 
8841 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_MODE_MASK (0x70000U)
8842 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_MODE_SHIFT (16U)
8843 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_MODE_WIDTH (3U)
8844 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_MODE_MASK)
8845 
8846 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_O_EN_MASK (0x80000U)
8847 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_O_EN_SHIFT (19U)
8848 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_O_EN_WIDTH (1U)
8849 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_O_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_O_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_FREEZE_O_EN_MASK)
8850 
8851 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_ODIS_MASK (0x100000U)
8852 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_ODIS_SHIFT (20U)
8853 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_ODIS_WIDTH (1U)
8854 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_ODIS(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_ODIS_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_ODIS_MASK)
8855 
8856 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_SEL_IN_MASK (0x200000U)
8857 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_SEL_IN_SHIFT (21U)
8858 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_SEL_IN_WIDTH (1U)
8859 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_SEL_IN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_SEL_IN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_SEL_IN_MASK)
8860 
8861 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_TRIG_OUT_EN_MASK (0x400000U)
8862 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_TRIG_OUT_EN_SHIFT (22U)
8863 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_TRIG_OUT_EN_WIDTH (1U)
8864 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_O_TRIG_OUT_EN_MASK)
8865 
8866 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_TRIG_OUT_EN_MASK (0x800000U)
8867 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_TRIG_OUT_EN_SHIFT (23U)
8868 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_TRIG_OUT_EN_WIDTH (1U)
8869 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_TRIG_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_TRIG_OUT_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_S_TRIG_OUT_EN_MASK)
8870 
8871 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE_MASK (0x1000000U)
8872 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT (24U)
8873 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE_WIDTH (1U)
8874 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_RE_MASK)
8875 
8876 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE_MASK (0x2000000U)
8877 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT (25U)
8878 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE_WIDTH (1U)
8879 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_S_FE_MASK)
8880 
8881 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE_MASK (0x4000000U)
8882 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT (26U)
8883 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE_WIDTH (1U)
8884 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_RE_MASK)
8885 
8886 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE_MASK (0x8000000U)
8887 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT (27U)
8888 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE_WIDTH (1U)
8889 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_O_FE_MASK)
8890 
8891 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK (0x10000000U)
8892 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT (28U)
8893 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_WIDTH (1U)
8894 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_TRIG_MASK)
8895 
8896 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK (0x20000000U)
8897 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT (29U)
8898 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT_WIDTH (1U)
8899 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PL_EVT_MASK)
8900 
8901 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK (0x40000000U)
8902 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT (30U)
8903 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_WIDTH (1U)
8904 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_EN_PREV_PL_TRIG_MASK)
8905 
8906 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN_MASK (0x80000000U)
8907 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT (31U)
8908 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN_WIDTH (1U)
8909 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL_PL_TRIG_OUT_UPD_EN_MASK)
8910 /*! @} */
8911 
8912 /*! @name TIO3_G0_CH7_IRQ_NOTIFY - TIO[i] channel [c] interrupt notification register */
8913 /*! @{ */
8914 
8915 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_RE_IRQ_MASK (0x1U)
8916 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_RE_IRQ_SHIFT (0U)
8917 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_RE_IRQ_WIDTH (1U)
8918 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_RE_IRQ_MASK)
8919 
8920 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_FE_IRQ_MASK (0x2U)
8921 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_FE_IRQ_SHIFT (1U)
8922 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_FE_IRQ_WIDTH (1U)
8923 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_S_FE_IRQ_MASK)
8924 
8925 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_RE_IRQ_MASK (0x4U)
8926 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_RE_IRQ_SHIFT (2U)
8927 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_RE_IRQ_WIDTH (1U)
8928 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_RE_IRQ_MASK)
8929 
8930 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_FE_IRQ_MASK (0x8U)
8931 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_FE_IRQ_SHIFT (3U)
8932 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_FE_IRQ_WIDTH (1U)
8933 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_O_FE_IRQ_MASK)
8934 
8935 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ_MASK (0x10U)
8936 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ_SHIFT (4U)
8937 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ_WIDTH (1U)
8938 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_UPDATE_IRQ_MASK)
8939 
8940 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ_MASK (0x20U)
8941 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT (5U)
8942 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ_WIDTH (1U)
8943 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_NOTIFY_PL_EVT_IRQ_MASK)
8944 /*! @} */
8945 
8946 /*! @name TIO3_G0_CH7_IRQ_EN - TIO[i] channel [c] interrupt enable register */
8947 /*! @{ */
8948 
8949 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_RE_IRQ_EN_MASK (0x1U)
8950 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_RE_IRQ_EN_SHIFT (0U)
8951 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_RE_IRQ_EN_WIDTH (1U)
8952 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_RE_IRQ_EN_MASK)
8953 
8954 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_FE_IRQ_EN_MASK (0x2U)
8955 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_FE_IRQ_EN_SHIFT (1U)
8956 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_FE_IRQ_EN_WIDTH (1U)
8957 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_S_FE_IRQ_EN_MASK)
8958 
8959 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_RE_IRQ_EN_MASK (0x4U)
8960 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_RE_IRQ_EN_SHIFT (2U)
8961 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_RE_IRQ_EN_WIDTH (1U)
8962 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_RE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_RE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_RE_IRQ_EN_MASK)
8963 
8964 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_FE_IRQ_EN_MASK (0x8U)
8965 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_FE_IRQ_EN_SHIFT (3U)
8966 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_FE_IRQ_EN_WIDTH (1U)
8967 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_FE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_FE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_O_FE_IRQ_EN_MASK)
8968 
8969 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_UPDATE_IRQ_EN_MASK (0x10U)
8970 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_UPDATE_IRQ_EN_SHIFT (4U)
8971 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_UPDATE_IRQ_EN_WIDTH (1U)
8972 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_UPDATE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_UPDATE_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_UPDATE_IRQ_EN_MASK)
8973 
8974 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN_MASK (0x20U)
8975 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN_SHIFT (5U)
8976 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN_WIDTH (1U)
8977 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_EN_PL_EVT_IRQ_EN_MASK)
8978 /*! @} */
8979 
8980 /*! @name TIO3_G0_CH7_IRQ_FORCINT - TIO[i] channel [c] force interrupt register */
8981 /*! @{ */
8982 
8983 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ_MASK (0x1U)
8984 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT (0U)
8985 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ_WIDTH (1U)
8986 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_RE_IRQ_MASK)
8987 
8988 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ_MASK (0x2U)
8989 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT (1U)
8990 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ_WIDTH (1U)
8991 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_S_FE_IRQ_MASK)
8992 
8993 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ_MASK (0x4U)
8994 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT (2U)
8995 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ_WIDTH (1U)
8996 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_RE_IRQ_MASK)
8997 
8998 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ_MASK (0x8U)
8999 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT (3U)
9000 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ_WIDTH (1U)
9001 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_O_FE_IRQ_MASK)
9002 
9003 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK (0x10U)
9004 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT (4U)
9005 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ_WIDTH (1U)
9006 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_UPDATE_IRQ_MASK)
9007 
9008 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK (0x20U)
9009 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT (5U)
9010 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ_WIDTH (1U)
9011 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_FORCINT_TRG_PL_EVT_IRQ_MASK)
9012 /*! @} */
9013 
9014 /*! @name TIO3_G0_CH7_IRQ_MODE - TIO[i] channel [c] IRQ mode configuration register */
9015 /*! @{ */
9016 
9017 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_MODE_IRQ_MODE_MASK (0x3U)
9018 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_MODE_IRQ_MODE_SHIFT (0U)
9019 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_MODE_IRQ_MODE_WIDTH (2U)
9020 #define GTM_gtm_cls3_TIO3_G0_CH7_IRQ_MODE_IRQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_IRQ_MODE_IRQ_MODE_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_IRQ_MODE_IRQ_MODE_MASK)
9021 /*! @} */
9022 
9023 /*! @name TIO3_G0_CH7_CTRL2 - TIO[i] group [g] channel [c] control register */
9024 /*! @{ */
9025 
9026 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_EN_MASK (0x1U)
9027 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_EN_SHIFT (0U)
9028 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_EN_WIDTH (1U)
9029 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_EN_MASK)
9030 
9031 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_MST_EN_MASK (0x2U)
9032 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_MST_EN_SHIFT (1U)
9033 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_MST_EN_WIDTH (1U)
9034 #define GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_MST_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_MST_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_CTRL2_DUAL_CMP_MST_EN_MASK)
9035 /*! @} */
9036 
9037 /*! @name TIO3_G0_CH7_SINST - TIO[i] channel [c] resource S instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
9038 /*! @{ */
9039 
9040 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_OP_MASK   (0xFFFFFFU)
9041 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_OP_SHIFT  (0U)
9042 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_OP_WIDTH  (24U)
9043 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_SINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_SINST_OP_MASK)
9044 
9045 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_CMD_MASK  (0x3F000000U)
9046 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_CMD_SHIFT (24U)
9047 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_CMD_WIDTH (6U)
9048 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_SINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_SINST_CMD_MASK)
9049 
9050 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_DATA_PUSH_EN_MASK (0x40000000U)
9051 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_DATA_PUSH_EN_SHIFT (30U)
9052 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_DATA_PUSH_EN_WIDTH (1U)
9053 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_SINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_SINST_DATA_PUSH_EN_MASK)
9054 
9055 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_INSTR_PULL_EN_MASK (0x80000000U)
9056 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_INSTR_PULL_EN_SHIFT (31U)
9057 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_INSTR_PULL_EN_WIDTH (1U)
9058 #define GTM_gtm_cls3_TIO3_G0_CH7_SINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_SINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_SINST_INSTR_PULL_EN_MASK)
9059 /*! @} */
9060 
9061 /*! @name TIO3_G0_CH7_SCMD - TIO[i] channel [c] resource S command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- */
9062 /*! @{ */
9063 
9064 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_CMD_MASK   (0x3F000000U)
9065 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_CMD_SHIFT  (24U)
9066 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_CMD_WIDTH  (6U)
9067 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_SCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_SCMD_CMD_MASK)
9068 
9069 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_DATA_PUSH_EN_MASK (0x40000000U)
9070 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_DATA_PUSH_EN_SHIFT (30U)
9071 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_DATA_PUSH_EN_WIDTH (1U)
9072 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_SCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_SCMD_DATA_PUSH_EN_MASK)
9073 
9074 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_INSTR_PULL_EN_MASK (0x80000000U)
9075 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_INSTR_PULL_EN_SHIFT (31U)
9076 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_INSTR_PULL_EN_WIDTH (1U)
9077 #define GTM_gtm_cls3_TIO3_G0_CH7_SCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_SCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_SCMD_INSTR_PULL_EN_MASK)
9078 /*! @} */
9079 
9080 /*! @name TIO3_G0_CH7_SOP - TIO[i] channel [c] resource S operand register TIO[i]_G[g]_CH[c]_CTRL.PL_S_MODE=0b0- or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b10- or TIO[i]_G[g]_OP_USAGE.MODE[c]=0b1-0 ) */
9081 /*! @{ */
9082 
9083 #define GTM_gtm_cls3_TIO3_G0_CH7_SOP_OP_MASK     (0xFFFFFFU)
9084 #define GTM_gtm_cls3_TIO3_G0_CH7_SOP_OP_SHIFT    (0U)
9085 #define GTM_gtm_cls3_TIO3_G0_CH7_SOP_OP_WIDTH    (24U)
9086 #define GTM_gtm_cls3_TIO3_G0_CH7_SOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_SOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_SOP_OP_MASK)
9087 /*! @} */
9088 
9089 /*! @name TIO3_G0_CH7_OINST - TIO[i] channel [c] resource O instruction register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE =0b00- */
9090 /*! @{ */
9091 
9092 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_OP_MASK   (0xFFFFFFU)
9093 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_OP_SHIFT  (0U)
9094 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_OP_WIDTH  (24U)
9095 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_OP(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_OINST_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_OINST_OP_MASK)
9096 
9097 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_CMD_MASK  (0x3F000000U)
9098 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_CMD_SHIFT (24U)
9099 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_CMD_WIDTH (6U)
9100 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_CMD(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_OINST_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_OINST_CMD_MASK)
9101 
9102 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_DATA_PUSH_EN_MASK (0x40000000U)
9103 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_DATA_PUSH_EN_SHIFT (30U)
9104 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_DATA_PUSH_EN_WIDTH (1U)
9105 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_OINST_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_OINST_DATA_PUSH_EN_MASK)
9106 
9107 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_INSTR_PULL_EN_MASK (0x80000000U)
9108 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_INSTR_PULL_EN_SHIFT (31U)
9109 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_INSTR_PULL_EN_WIDTH (1U)
9110 #define GTM_gtm_cls3_TIO3_G0_CH7_OINST_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_OINST_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_OINST_INSTR_PULL_EN_MASK)
9111 /*! @} */
9112 
9113 /*! @name TIO3_G0_CH7_OCMD - TIO[i] channel [c] resource O command register (buffer operation) TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b00- */
9114 /*! @{ */
9115 
9116 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_CMD_MASK   (0x3F000000U)
9117 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_CMD_SHIFT  (24U)
9118 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_CMD_WIDTH  (6U)
9119 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_CMD(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_OCMD_CMD_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_OCMD_CMD_MASK)
9120 
9121 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_DATA_PUSH_EN_MASK (0x40000000U)
9122 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_DATA_PUSH_EN_SHIFT (30U)
9123 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_DATA_PUSH_EN_WIDTH (1U)
9124 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_DATA_PUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_OCMD_DATA_PUSH_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_OCMD_DATA_PUSH_EN_MASK)
9125 
9126 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_INSTR_PULL_EN_MASK (0x80000000U)
9127 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_INSTR_PULL_EN_SHIFT (31U)
9128 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_INSTR_PULL_EN_WIDTH (1U)
9129 #define GTM_gtm_cls3_TIO3_G0_CH7_OCMD_INSTR_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_OCMD_INSTR_PULL_EN_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_OCMD_INSTR_PULL_EN_MASK)
9130 /*! @} */
9131 
9132 /*! @name TIO3_G0_CH7_OOP - TIO[i] channel [c] resource O operand register !(TIO[i]_G[g]_CH[c]_CTRL.PL_O_MODE=0b1--) or (TIO[i]_G[g]_OP_USAGE.MODE[c]=0b11-) */
9133 /*! @{ */
9134 
9135 #define GTM_gtm_cls3_TIO3_G0_CH7_OOP_OP_MASK     (0xFFFFFFU)
9136 #define GTM_gtm_cls3_TIO3_G0_CH7_OOP_OP_SHIFT    (0U)
9137 #define GTM_gtm_cls3_TIO3_G0_CH7_OOP_OP_WIDTH    (24U)
9138 #define GTM_gtm_cls3_TIO3_G0_CH7_OOP_OP(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_OOP_OP_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_OOP_OP_MASK)
9139 /*! @} */
9140 
9141 /*! @name TIO3_G0_CH7_SHIFTCNT - TIO[i] channel [c] resource shift count register */
9142 /*! @{ */
9143 
9144 #define GTM_gtm_cls3_TIO3_G0_CH7_SHIFTCNT_CNT_MASK (0x1FU)
9145 #define GTM_gtm_cls3_TIO3_G0_CH7_SHIFTCNT_CNT_SHIFT (0U)
9146 #define GTM_gtm_cls3_TIO3_G0_CH7_SHIFTCNT_CNT_WIDTH (5U)
9147 #define GTM_gtm_cls3_TIO3_G0_CH7_SHIFTCNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_CH7_SHIFTCNT_CNT_SHIFT)) & GTM_gtm_cls3_TIO3_G0_CH7_SHIFTCNT_CNT_MASK)
9148 /*! @} */
9149 
9150 /*! @name TIO3_G0_ISEL0_CTRL1 - TIO[i] input selection register 1 */
9151 /*! @{ */
9152 
9153 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_0_MASK (0xFU)
9154 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_0_SHIFT (0U)
9155 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_0_WIDTH (4U)
9156 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_0_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_0_MASK)
9157 
9158 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_1_MASK (0xF0U)
9159 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_1_SHIFT (4U)
9160 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_1_WIDTH (4U)
9161 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_1_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_1_MASK)
9162 
9163 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_2_MASK (0xF00U)
9164 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_2_SHIFT (8U)
9165 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_2_WIDTH (4U)
9166 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_2_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_2_MASK)
9167 
9168 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_3_MASK (0xF000U)
9169 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_3_SHIFT (12U)
9170 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_3_WIDTH (4U)
9171 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_3_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_LUT2_3_MASK)
9172 
9173 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL0_MASK (0x10000U)
9174 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL0_SHIFT (16U)
9175 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL0_WIDTH (1U)
9176 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL0_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL0_MASK)
9177 
9178 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL1_MASK (0x20000U)
9179 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL1_SHIFT (17U)
9180 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL1_WIDTH (1U)
9181 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL1_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL1_MASK)
9182 
9183 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL2_MASK (0x40000U)
9184 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL2_SHIFT (18U)
9185 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL2_WIDTH (1U)
9186 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL2_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL2_MASK)
9187 
9188 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL3_MASK (0x80000U)
9189 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL3_SHIFT (19U)
9190 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL3_WIDTH (1U)
9191 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL3_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_OUT_SEL3_MASK)
9192 
9193 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN0_MASK (0x1000000U)
9194 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN0_SHIFT (24U)
9195 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN0_WIDTH (1U)
9196 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN0_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN0_MASK)
9197 
9198 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN1_MASK (0x2000000U)
9199 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN1_SHIFT (25U)
9200 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN1_WIDTH (1U)
9201 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN1_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN1_MASK)
9202 
9203 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN2_MASK (0x4000000U)
9204 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN2_SHIFT (26U)
9205 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN2_WIDTH (1U)
9206 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN2_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN2_MASK)
9207 
9208 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN3_MASK (0x8000000U)
9209 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN3_SHIFT (27U)
9210 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN3_WIDTH (1U)
9211 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN3_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL1_WRITE_EN3_MASK)
9212 /*! @} */
9213 
9214 /*! @name TIO3_G0_ISEL0_CTRL2 - TIO[i] input selection register 2 */
9215 /*! @{ */
9216 
9217 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3_MASK (0xFFU)
9218 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3_SHIFT (0U)
9219 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3_WIDTH (8U)
9220 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3_MASK)
9221 
9222 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_QOUT_SEL_MASK (0x30000U)
9223 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_QOUT_SEL_SHIFT (16U)
9224 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_QOUT_SEL_WIDTH (2U)
9225 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_QOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_QOUT_SEL_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_QOUT_SEL_MASK)
9226 
9227 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL0_MASK (0x100000U)
9228 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL0_SHIFT (20U)
9229 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL0_WIDTH (1U)
9230 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL0_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL0_MASK)
9231 
9232 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL1_MASK (0x200000U)
9233 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL1_SHIFT (21U)
9234 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL1_WIDTH (1U)
9235 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL1_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL1_MASK)
9236 
9237 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL2_MASK (0x400000U)
9238 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL2_SHIFT (22U)
9239 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL2_WIDTH (1U)
9240 #define GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL2_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL0_CTRL2_LUT3IN_SEL2_MASK)
9241 /*! @} */
9242 
9243 /*! @name TIO3_G0_ISEL1_CTRL1 - TIO[i] input selection register 1 */
9244 /*! @{ */
9245 
9246 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_0_MASK (0xFU)
9247 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_0_SHIFT (0U)
9248 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_0_WIDTH (4U)
9249 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_0_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_0_MASK)
9250 
9251 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_1_MASK (0xF0U)
9252 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_1_SHIFT (4U)
9253 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_1_WIDTH (4U)
9254 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_1_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_1_MASK)
9255 
9256 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_2_MASK (0xF00U)
9257 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_2_SHIFT (8U)
9258 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_2_WIDTH (4U)
9259 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_2_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_2_MASK)
9260 
9261 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_3_MASK (0xF000U)
9262 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_3_SHIFT (12U)
9263 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_3_WIDTH (4U)
9264 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_3_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_LUT2_3_MASK)
9265 
9266 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL0_MASK (0x10000U)
9267 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL0_SHIFT (16U)
9268 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL0_WIDTH (1U)
9269 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL0_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL0_MASK)
9270 
9271 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL1_MASK (0x20000U)
9272 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL1_SHIFT (17U)
9273 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL1_WIDTH (1U)
9274 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL1_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL1_MASK)
9275 
9276 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL2_MASK (0x40000U)
9277 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL2_SHIFT (18U)
9278 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL2_WIDTH (1U)
9279 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL2_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL2_MASK)
9280 
9281 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL3_MASK (0x80000U)
9282 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL3_SHIFT (19U)
9283 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL3_WIDTH (1U)
9284 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL3_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_OUT_SEL3_MASK)
9285 
9286 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN0_MASK (0x1000000U)
9287 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN0_SHIFT (24U)
9288 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN0_WIDTH (1U)
9289 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN0_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN0_MASK)
9290 
9291 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN1_MASK (0x2000000U)
9292 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN1_SHIFT (25U)
9293 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN1_WIDTH (1U)
9294 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN1_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN1_MASK)
9295 
9296 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN2_MASK (0x4000000U)
9297 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN2_SHIFT (26U)
9298 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN2_WIDTH (1U)
9299 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN2_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN2_MASK)
9300 
9301 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN3_MASK (0x8000000U)
9302 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN3_SHIFT (27U)
9303 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN3_WIDTH (1U)
9304 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN3_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL1_WRITE_EN3_MASK)
9305 /*! @} */
9306 
9307 /*! @name TIO3_G0_ISEL1_CTRL2 - TIO[i] input selection register 2 */
9308 /*! @{ */
9309 
9310 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3_MASK (0xFFU)
9311 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3_SHIFT (0U)
9312 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3_WIDTH (8U)
9313 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3_MASK)
9314 
9315 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_QOUT_SEL_MASK (0x30000U)
9316 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_QOUT_SEL_SHIFT (16U)
9317 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_QOUT_SEL_WIDTH (2U)
9318 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_QOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_QOUT_SEL_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_QOUT_SEL_MASK)
9319 
9320 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL0_MASK (0x100000U)
9321 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL0_SHIFT (20U)
9322 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL0_WIDTH (1U)
9323 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL0_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL0_MASK)
9324 
9325 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL1_MASK (0x200000U)
9326 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL1_SHIFT (21U)
9327 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL1_WIDTH (1U)
9328 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL1_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL1_MASK)
9329 
9330 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL2_MASK (0x400000U)
9331 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL2_SHIFT (22U)
9332 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL2_WIDTH (1U)
9333 #define GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL2_SHIFT)) & GTM_gtm_cls3_TIO3_G0_ISEL1_CTRL2_LUT3IN_SEL2_MASK)
9334 /*! @} */
9335 
9336 /*! @name TIO3_G0_OP_USAGE - TIO[i] operand usage selection register */
9337 /*! @{ */
9338 
9339 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE0_MASK (0x7U)
9340 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE0_SHIFT (0U)
9341 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE0_WIDTH (3U)
9342 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE0(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE0_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE0_MASK)
9343 
9344 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE1_MASK (0x38U)
9345 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE1_SHIFT (3U)
9346 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE1_WIDTH (3U)
9347 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE1(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE1_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE1_MASK)
9348 
9349 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE2_MASK (0x1C0U)
9350 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE2_SHIFT (6U)
9351 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE2_WIDTH (3U)
9352 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE2(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE2_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE2_MASK)
9353 
9354 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE3_MASK (0xE00U)
9355 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE3_SHIFT (9U)
9356 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE3_WIDTH (3U)
9357 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE3(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE3_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE3_MASK)
9358 
9359 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE4_MASK (0x7000U)
9360 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE4_SHIFT (12U)
9361 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE4_WIDTH (3U)
9362 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE4(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE4_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE4_MASK)
9363 
9364 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE5_MASK (0x38000U)
9365 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE5_SHIFT (15U)
9366 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE5_WIDTH (3U)
9367 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE5(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE5_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE5_MASK)
9368 
9369 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE6_MASK (0x1C0000U)
9370 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE6_SHIFT (18U)
9371 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE6_WIDTH (3U)
9372 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE6(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE6_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE6_MASK)
9373 
9374 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE7_MASK (0xE00000U)
9375 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE7_SHIFT (21U)
9376 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE7_WIDTH (3U)
9377 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE7(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE7_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_MODE7_MASK)
9378 
9379 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN0_MASK (0x1000000U)
9380 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN0_SHIFT (24U)
9381 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN0_WIDTH (1U)
9382 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN0_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN0_MASK)
9383 
9384 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN1_MASK (0x2000000U)
9385 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN1_SHIFT (25U)
9386 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN1_WIDTH (1U)
9387 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN1_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN1_MASK)
9388 
9389 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN2_MASK (0x4000000U)
9390 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN2_SHIFT (26U)
9391 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN2_WIDTH (1U)
9392 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN2_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN2_MASK)
9393 
9394 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN3_MASK (0x8000000U)
9395 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN3_SHIFT (27U)
9396 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN3_WIDTH (1U)
9397 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN3_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN3_MASK)
9398 
9399 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN4_MASK (0x10000000U)
9400 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN4_SHIFT (28U)
9401 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN4_WIDTH (1U)
9402 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN4_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN4_MASK)
9403 
9404 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN5_MASK (0x20000000U)
9405 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN5_SHIFT (29U)
9406 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN5_WIDTH (1U)
9407 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN5_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN5_MASK)
9408 
9409 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN6_MASK (0x40000000U)
9410 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN6_SHIFT (30U)
9411 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN6_WIDTH (1U)
9412 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN6_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN6_MASK)
9413 
9414 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN7_MASK (0x80000000U)
9415 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN7_SHIFT (31U)
9416 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN7_WIDTH (1U)
9417 #define GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN7_SHIFT)) & GTM_gtm_cls3_TIO3_G0_OP_USAGE_WRITE_EN7_MASK)
9418 /*! @} */
9419 
9420 /*! @name TIO3_S - TIO[i] signal sampling register */
9421 /*! @{ */
9422 
9423 #define GTM_gtm_cls3_TIO3_S_CH0_MASK             (0x1U)
9424 #define GTM_gtm_cls3_TIO3_S_CH0_SHIFT            (0U)
9425 #define GTM_gtm_cls3_TIO3_S_CH0_WIDTH            (1U)
9426 #define GTM_gtm_cls3_TIO3_S_CH0(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_S_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_S_CH0_MASK)
9427 
9428 #define GTM_gtm_cls3_TIO3_S_CH1_MASK             (0x2U)
9429 #define GTM_gtm_cls3_TIO3_S_CH1_SHIFT            (1U)
9430 #define GTM_gtm_cls3_TIO3_S_CH1_WIDTH            (1U)
9431 #define GTM_gtm_cls3_TIO3_S_CH1(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_S_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_S_CH1_MASK)
9432 
9433 #define GTM_gtm_cls3_TIO3_S_CH2_MASK             (0x4U)
9434 #define GTM_gtm_cls3_TIO3_S_CH2_SHIFT            (2U)
9435 #define GTM_gtm_cls3_TIO3_S_CH2_WIDTH            (1U)
9436 #define GTM_gtm_cls3_TIO3_S_CH2(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_S_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_S_CH2_MASK)
9437 
9438 #define GTM_gtm_cls3_TIO3_S_CH3_MASK             (0x8U)
9439 #define GTM_gtm_cls3_TIO3_S_CH3_SHIFT            (3U)
9440 #define GTM_gtm_cls3_TIO3_S_CH3_WIDTH            (1U)
9441 #define GTM_gtm_cls3_TIO3_S_CH3(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_S_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_S_CH3_MASK)
9442 
9443 #define GTM_gtm_cls3_TIO3_S_CH4_MASK             (0x10U)
9444 #define GTM_gtm_cls3_TIO3_S_CH4_SHIFT            (4U)
9445 #define GTM_gtm_cls3_TIO3_S_CH4_WIDTH            (1U)
9446 #define GTM_gtm_cls3_TIO3_S_CH4(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_S_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_S_CH4_MASK)
9447 
9448 #define GTM_gtm_cls3_TIO3_S_CH5_MASK             (0x20U)
9449 #define GTM_gtm_cls3_TIO3_S_CH5_SHIFT            (5U)
9450 #define GTM_gtm_cls3_TIO3_S_CH5_WIDTH            (1U)
9451 #define GTM_gtm_cls3_TIO3_S_CH5(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_S_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_S_CH5_MASK)
9452 
9453 #define GTM_gtm_cls3_TIO3_S_CH6_MASK             (0x40U)
9454 #define GTM_gtm_cls3_TIO3_S_CH6_SHIFT            (6U)
9455 #define GTM_gtm_cls3_TIO3_S_CH6_WIDTH            (1U)
9456 #define GTM_gtm_cls3_TIO3_S_CH6(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_S_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_S_CH6_MASK)
9457 
9458 #define GTM_gtm_cls3_TIO3_S_CH7_MASK             (0x80U)
9459 #define GTM_gtm_cls3_TIO3_S_CH7_SHIFT            (7U)
9460 #define GTM_gtm_cls3_TIO3_S_CH7_WIDTH            (1U)
9461 #define GTM_gtm_cls3_TIO3_S_CH7(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_S_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_S_CH7_MASK)
9462 /*! @} */
9463 
9464 /*! @name TIO3_O - TIO[i] output register */
9465 /*! @{ */
9466 
9467 #define GTM_gtm_cls3_TIO3_O_CH0_MASK             (0x1U)
9468 #define GTM_gtm_cls3_TIO3_O_CH0_SHIFT            (0U)
9469 #define GTM_gtm_cls3_TIO3_O_CH0_WIDTH            (1U)
9470 #define GTM_gtm_cls3_TIO3_O_CH0(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_O_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_O_CH0_MASK)
9471 
9472 #define GTM_gtm_cls3_TIO3_O_CH1_MASK             (0x2U)
9473 #define GTM_gtm_cls3_TIO3_O_CH1_SHIFT            (1U)
9474 #define GTM_gtm_cls3_TIO3_O_CH1_WIDTH            (1U)
9475 #define GTM_gtm_cls3_TIO3_O_CH1(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_O_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_O_CH1_MASK)
9476 
9477 #define GTM_gtm_cls3_TIO3_O_CH2_MASK             (0x4U)
9478 #define GTM_gtm_cls3_TIO3_O_CH2_SHIFT            (2U)
9479 #define GTM_gtm_cls3_TIO3_O_CH2_WIDTH            (1U)
9480 #define GTM_gtm_cls3_TIO3_O_CH2(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_O_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_O_CH2_MASK)
9481 
9482 #define GTM_gtm_cls3_TIO3_O_CH3_MASK             (0x8U)
9483 #define GTM_gtm_cls3_TIO3_O_CH3_SHIFT            (3U)
9484 #define GTM_gtm_cls3_TIO3_O_CH3_WIDTH            (1U)
9485 #define GTM_gtm_cls3_TIO3_O_CH3(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_O_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_O_CH3_MASK)
9486 
9487 #define GTM_gtm_cls3_TIO3_O_CH4_MASK             (0x10U)
9488 #define GTM_gtm_cls3_TIO3_O_CH4_SHIFT            (4U)
9489 #define GTM_gtm_cls3_TIO3_O_CH4_WIDTH            (1U)
9490 #define GTM_gtm_cls3_TIO3_O_CH4(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_O_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_O_CH4_MASK)
9491 
9492 #define GTM_gtm_cls3_TIO3_O_CH5_MASK             (0x20U)
9493 #define GTM_gtm_cls3_TIO3_O_CH5_SHIFT            (5U)
9494 #define GTM_gtm_cls3_TIO3_O_CH5_WIDTH            (1U)
9495 #define GTM_gtm_cls3_TIO3_O_CH5(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_O_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_O_CH5_MASK)
9496 
9497 #define GTM_gtm_cls3_TIO3_O_CH6_MASK             (0x40U)
9498 #define GTM_gtm_cls3_TIO3_O_CH6_SHIFT            (6U)
9499 #define GTM_gtm_cls3_TIO3_O_CH6_WIDTH            (1U)
9500 #define GTM_gtm_cls3_TIO3_O_CH6(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_O_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_O_CH6_MASK)
9501 
9502 #define GTM_gtm_cls3_TIO3_O_CH7_MASK             (0x80U)
9503 #define GTM_gtm_cls3_TIO3_O_CH7_SHIFT            (7U)
9504 #define GTM_gtm_cls3_TIO3_O_CH7_WIDTH            (1U)
9505 #define GTM_gtm_cls3_TIO3_O_CH7(x)               (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_O_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_O_CH7_MASK)
9506 /*! @} */
9507 
9508 /*! @name TIO3_ENDIS - TIO[i] enable/disable register */
9509 /*! @{ */
9510 
9511 #define GTM_gtm_cls3_TIO3_ENDIS_CH0_MASK         (0x1U)
9512 #define GTM_gtm_cls3_TIO3_ENDIS_CH0_SHIFT        (0U)
9513 #define GTM_gtm_cls3_TIO3_ENDIS_CH0_WIDTH        (1U)
9514 #define GTM_gtm_cls3_TIO3_ENDIS_CH0(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ENDIS_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_ENDIS_CH0_MASK)
9515 
9516 #define GTM_gtm_cls3_TIO3_ENDIS_CH1_MASK         (0x2U)
9517 #define GTM_gtm_cls3_TIO3_ENDIS_CH1_SHIFT        (1U)
9518 #define GTM_gtm_cls3_TIO3_ENDIS_CH1_WIDTH        (1U)
9519 #define GTM_gtm_cls3_TIO3_ENDIS_CH1(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ENDIS_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_ENDIS_CH1_MASK)
9520 
9521 #define GTM_gtm_cls3_TIO3_ENDIS_CH2_MASK         (0x4U)
9522 #define GTM_gtm_cls3_TIO3_ENDIS_CH2_SHIFT        (2U)
9523 #define GTM_gtm_cls3_TIO3_ENDIS_CH2_WIDTH        (1U)
9524 #define GTM_gtm_cls3_TIO3_ENDIS_CH2(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ENDIS_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_ENDIS_CH2_MASK)
9525 
9526 #define GTM_gtm_cls3_TIO3_ENDIS_CH3_MASK         (0x8U)
9527 #define GTM_gtm_cls3_TIO3_ENDIS_CH3_SHIFT        (3U)
9528 #define GTM_gtm_cls3_TIO3_ENDIS_CH3_WIDTH        (1U)
9529 #define GTM_gtm_cls3_TIO3_ENDIS_CH3(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ENDIS_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_ENDIS_CH3_MASK)
9530 
9531 #define GTM_gtm_cls3_TIO3_ENDIS_CH4_MASK         (0x10U)
9532 #define GTM_gtm_cls3_TIO3_ENDIS_CH4_SHIFT        (4U)
9533 #define GTM_gtm_cls3_TIO3_ENDIS_CH4_WIDTH        (1U)
9534 #define GTM_gtm_cls3_TIO3_ENDIS_CH4(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ENDIS_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_ENDIS_CH4_MASK)
9535 
9536 #define GTM_gtm_cls3_TIO3_ENDIS_CH5_MASK         (0x20U)
9537 #define GTM_gtm_cls3_TIO3_ENDIS_CH5_SHIFT        (5U)
9538 #define GTM_gtm_cls3_TIO3_ENDIS_CH5_WIDTH        (1U)
9539 #define GTM_gtm_cls3_TIO3_ENDIS_CH5(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ENDIS_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_ENDIS_CH5_MASK)
9540 
9541 #define GTM_gtm_cls3_TIO3_ENDIS_CH6_MASK         (0x40U)
9542 #define GTM_gtm_cls3_TIO3_ENDIS_CH6_SHIFT        (6U)
9543 #define GTM_gtm_cls3_TIO3_ENDIS_CH6_WIDTH        (1U)
9544 #define GTM_gtm_cls3_TIO3_ENDIS_CH6(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ENDIS_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_ENDIS_CH6_MASK)
9545 
9546 #define GTM_gtm_cls3_TIO3_ENDIS_CH7_MASK         (0x80U)
9547 #define GTM_gtm_cls3_TIO3_ENDIS_CH7_SHIFT        (7U)
9548 #define GTM_gtm_cls3_TIO3_ENDIS_CH7_WIDTH        (1U)
9549 #define GTM_gtm_cls3_TIO3_ENDIS_CH7(x)           (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ENDIS_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_ENDIS_CH7_MASK)
9550 /*! @} */
9551 
9552 /*! @name TIO3_INVERT - TIO[i] signal invert register */
9553 /*! @{ */
9554 
9555 #define GTM_gtm_cls3_TIO3_INVERT_CH0_MASK        (0x1U)
9556 #define GTM_gtm_cls3_TIO3_INVERT_CH0_SHIFT       (0U)
9557 #define GTM_gtm_cls3_TIO3_INVERT_CH0_WIDTH       (1U)
9558 #define GTM_gtm_cls3_TIO3_INVERT_CH0(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INVERT_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_INVERT_CH0_MASK)
9559 
9560 #define GTM_gtm_cls3_TIO3_INVERT_CH1_MASK        (0x2U)
9561 #define GTM_gtm_cls3_TIO3_INVERT_CH1_SHIFT       (1U)
9562 #define GTM_gtm_cls3_TIO3_INVERT_CH1_WIDTH       (1U)
9563 #define GTM_gtm_cls3_TIO3_INVERT_CH1(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INVERT_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_INVERT_CH1_MASK)
9564 
9565 #define GTM_gtm_cls3_TIO3_INVERT_CH2_MASK        (0x4U)
9566 #define GTM_gtm_cls3_TIO3_INVERT_CH2_SHIFT       (2U)
9567 #define GTM_gtm_cls3_TIO3_INVERT_CH2_WIDTH       (1U)
9568 #define GTM_gtm_cls3_TIO3_INVERT_CH2(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INVERT_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_INVERT_CH2_MASK)
9569 
9570 #define GTM_gtm_cls3_TIO3_INVERT_CH3_MASK        (0x8U)
9571 #define GTM_gtm_cls3_TIO3_INVERT_CH3_SHIFT       (3U)
9572 #define GTM_gtm_cls3_TIO3_INVERT_CH3_WIDTH       (1U)
9573 #define GTM_gtm_cls3_TIO3_INVERT_CH3(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INVERT_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_INVERT_CH3_MASK)
9574 
9575 #define GTM_gtm_cls3_TIO3_INVERT_CH4_MASK        (0x10U)
9576 #define GTM_gtm_cls3_TIO3_INVERT_CH4_SHIFT       (4U)
9577 #define GTM_gtm_cls3_TIO3_INVERT_CH4_WIDTH       (1U)
9578 #define GTM_gtm_cls3_TIO3_INVERT_CH4(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INVERT_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_INVERT_CH4_MASK)
9579 
9580 #define GTM_gtm_cls3_TIO3_INVERT_CH5_MASK        (0x20U)
9581 #define GTM_gtm_cls3_TIO3_INVERT_CH5_SHIFT       (5U)
9582 #define GTM_gtm_cls3_TIO3_INVERT_CH5_WIDTH       (1U)
9583 #define GTM_gtm_cls3_TIO3_INVERT_CH5(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INVERT_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_INVERT_CH5_MASK)
9584 
9585 #define GTM_gtm_cls3_TIO3_INVERT_CH6_MASK        (0x40U)
9586 #define GTM_gtm_cls3_TIO3_INVERT_CH6_SHIFT       (6U)
9587 #define GTM_gtm_cls3_TIO3_INVERT_CH6_WIDTH       (1U)
9588 #define GTM_gtm_cls3_TIO3_INVERT_CH6(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INVERT_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_INVERT_CH6_MASK)
9589 
9590 #define GTM_gtm_cls3_TIO3_INVERT_CH7_MASK        (0x80U)
9591 #define GTM_gtm_cls3_TIO3_INVERT_CH7_SHIFT       (7U)
9592 #define GTM_gtm_cls3_TIO3_INVERT_CH7_WIDTH       (1U)
9593 #define GTM_gtm_cls3_TIO3_INVERT_CH7(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INVERT_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_INVERT_CH7_MASK)
9594 /*! @} */
9595 
9596 /*! @name TIO3_INPUT_MODE - TIO[i] input mode register */
9597 /*! @{ */
9598 
9599 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH0_MASK    (0x1U)
9600 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH0_SHIFT   (0U)
9601 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH0_WIDTH   (1U)
9602 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH0(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INPUT_MODE_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_INPUT_MODE_CH0_MASK)
9603 
9604 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH1_MASK    (0x2U)
9605 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH1_SHIFT   (1U)
9606 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH1_WIDTH   (1U)
9607 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH1(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INPUT_MODE_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_INPUT_MODE_CH1_MASK)
9608 
9609 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH2_MASK    (0x4U)
9610 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH2_SHIFT   (2U)
9611 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH2_WIDTH   (1U)
9612 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH2(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INPUT_MODE_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_INPUT_MODE_CH2_MASK)
9613 
9614 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH3_MASK    (0x8U)
9615 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH3_SHIFT   (3U)
9616 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH3_WIDTH   (1U)
9617 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH3(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INPUT_MODE_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_INPUT_MODE_CH3_MASK)
9618 
9619 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH4_MASK    (0x10U)
9620 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH4_SHIFT   (4U)
9621 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH4_WIDTH   (1U)
9622 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH4(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INPUT_MODE_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_INPUT_MODE_CH4_MASK)
9623 
9624 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH5_MASK    (0x20U)
9625 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH5_SHIFT   (5U)
9626 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH5_WIDTH   (1U)
9627 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH5(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INPUT_MODE_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_INPUT_MODE_CH5_MASK)
9628 
9629 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH6_MASK    (0x40U)
9630 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH6_SHIFT   (6U)
9631 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH6_WIDTH   (1U)
9632 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH6(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INPUT_MODE_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_INPUT_MODE_CH6_MASK)
9633 
9634 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH7_MASK    (0x80U)
9635 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH7_SHIFT   (7U)
9636 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH7_WIDTH   (1U)
9637 #define GTM_gtm_cls3_TIO3_INPUT_MODE_CH7(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_INPUT_MODE_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_INPUT_MODE_CH7_MASK)
9638 /*! @} */
9639 
9640 /*! @name TIO3_CYCLIC_MODE - TIO[i] cyclic mode register */
9641 /*! @{ */
9642 
9643 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH0_MASK   (0x1U)
9644 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH0_SHIFT  (0U)
9645 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH0_WIDTH  (1U)
9646 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH0(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH0_MASK)
9647 
9648 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH1_MASK   (0x2U)
9649 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH1_SHIFT  (1U)
9650 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH1_WIDTH  (1U)
9651 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH1(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH1_MASK)
9652 
9653 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH2_MASK   (0x4U)
9654 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH2_SHIFT  (2U)
9655 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH2_WIDTH  (1U)
9656 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH2(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH2_MASK)
9657 
9658 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH3_MASK   (0x8U)
9659 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH3_SHIFT  (3U)
9660 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH3_WIDTH  (1U)
9661 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH3(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH3_MASK)
9662 
9663 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH4_MASK   (0x10U)
9664 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH4_SHIFT  (4U)
9665 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH4_WIDTH  (1U)
9666 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH4(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH4_MASK)
9667 
9668 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH5_MASK   (0x20U)
9669 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH5_SHIFT  (5U)
9670 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH5_WIDTH  (1U)
9671 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH5(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH5_MASK)
9672 
9673 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH6_MASK   (0x40U)
9674 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH6_SHIFT  (6U)
9675 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH6_WIDTH  (1U)
9676 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH6(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH6_MASK)
9677 
9678 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH7_MASK   (0x80U)
9679 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH7_SHIFT  (7U)
9680 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH7_WIDTH  (1U)
9681 #define GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH7(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_CYCLIC_MODE_CH7_MASK)
9682 /*! @} */
9683 
9684 /*! @name TIO3_TRIG_OUT_GATE_EN - TIO[i] enable Trigger Output, output gating register */
9685 /*! @{ */
9686 
9687 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH0_MASK (0x1U)
9688 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH0_SHIFT (0U)
9689 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH0_WIDTH (1U)
9690 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH0_MASK)
9691 
9692 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH1_MASK (0x2U)
9693 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH1_SHIFT (1U)
9694 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH1_WIDTH (1U)
9695 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH1_MASK)
9696 
9697 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH2_MASK (0x4U)
9698 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH2_SHIFT (2U)
9699 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH2_WIDTH (1U)
9700 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH2_MASK)
9701 
9702 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH3_MASK (0x8U)
9703 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH3_SHIFT (3U)
9704 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH3_WIDTH (1U)
9705 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH3_MASK)
9706 
9707 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH4_MASK (0x10U)
9708 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH4_SHIFT (4U)
9709 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH4_WIDTH (1U)
9710 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH4_MASK)
9711 
9712 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH5_MASK (0x20U)
9713 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH5_SHIFT (5U)
9714 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH5_WIDTH (1U)
9715 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH5_MASK)
9716 
9717 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH6_MASK (0x40U)
9718 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH6_SHIFT (6U)
9719 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH6_WIDTH (1U)
9720 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH6_MASK)
9721 
9722 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH7_MASK (0x80U)
9723 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH7_SHIFT (7U)
9724 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH7_WIDTH (1U)
9725 #define GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_TRIG_OUT_GATE_EN_CH7_MASK)
9726 /*! @} */
9727 
9728 /*! @name TIO3_PLTRIG_OUT_GATE_EN - TIO[i] enable PL_TRIG_OUT output gating register */
9729 /*! @{ */
9730 
9731 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH0_MASK (0x1U)
9732 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH0_SHIFT (0U)
9733 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH0_WIDTH (1U)
9734 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH0_MASK)
9735 
9736 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH1_MASK (0x2U)
9737 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH1_SHIFT (1U)
9738 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH1_WIDTH (1U)
9739 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH1_MASK)
9740 
9741 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH2_MASK (0x4U)
9742 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH2_SHIFT (2U)
9743 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH2_WIDTH (1U)
9744 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH2_MASK)
9745 
9746 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH3_MASK (0x8U)
9747 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH3_SHIFT (3U)
9748 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH3_WIDTH (1U)
9749 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH3_MASK)
9750 
9751 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH4_MASK (0x10U)
9752 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH4_SHIFT (4U)
9753 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH4_WIDTH (1U)
9754 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH4_MASK)
9755 
9756 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH5_MASK (0x20U)
9757 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH5_SHIFT (5U)
9758 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH5_WIDTH (1U)
9759 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH5_MASK)
9760 
9761 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH6_MASK (0x40U)
9762 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH6_SHIFT (6U)
9763 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH6_WIDTH (1U)
9764 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH6_MASK)
9765 
9766 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH7_MASK (0x80U)
9767 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH7_SHIFT (7U)
9768 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH7_WIDTH (1U)
9769 #define GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_PLTRIG_OUT_GATE_EN_CH7_MASK)
9770 /*! @} */
9771 
9772 /*! @name TIO3_CS - TIO[i] clear signal sampling register */
9773 /*! @{ */
9774 
9775 #define GTM_gtm_cls3_TIO3_CS_CH0_MASK            (0x1U)
9776 #define GTM_gtm_cls3_TIO3_CS_CH0_SHIFT           (0U)
9777 #define GTM_gtm_cls3_TIO3_CS_CH0_WIDTH           (1U)
9778 #define GTM_gtm_cls3_TIO3_CS_CH0(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CS_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_CS_CH0_MASK)
9779 
9780 #define GTM_gtm_cls3_TIO3_CS_CH1_MASK            (0x2U)
9781 #define GTM_gtm_cls3_TIO3_CS_CH1_SHIFT           (1U)
9782 #define GTM_gtm_cls3_TIO3_CS_CH1_WIDTH           (1U)
9783 #define GTM_gtm_cls3_TIO3_CS_CH1(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CS_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_CS_CH1_MASK)
9784 
9785 #define GTM_gtm_cls3_TIO3_CS_CH2_MASK            (0x4U)
9786 #define GTM_gtm_cls3_TIO3_CS_CH2_SHIFT           (2U)
9787 #define GTM_gtm_cls3_TIO3_CS_CH2_WIDTH           (1U)
9788 #define GTM_gtm_cls3_TIO3_CS_CH2(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CS_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_CS_CH2_MASK)
9789 
9790 #define GTM_gtm_cls3_TIO3_CS_CH3_MASK            (0x8U)
9791 #define GTM_gtm_cls3_TIO3_CS_CH3_SHIFT           (3U)
9792 #define GTM_gtm_cls3_TIO3_CS_CH3_WIDTH           (1U)
9793 #define GTM_gtm_cls3_TIO3_CS_CH3(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CS_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_CS_CH3_MASK)
9794 
9795 #define GTM_gtm_cls3_TIO3_CS_CH4_MASK            (0x10U)
9796 #define GTM_gtm_cls3_TIO3_CS_CH4_SHIFT           (4U)
9797 #define GTM_gtm_cls3_TIO3_CS_CH4_WIDTH           (1U)
9798 #define GTM_gtm_cls3_TIO3_CS_CH4(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CS_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_CS_CH4_MASK)
9799 
9800 #define GTM_gtm_cls3_TIO3_CS_CH5_MASK            (0x20U)
9801 #define GTM_gtm_cls3_TIO3_CS_CH5_SHIFT           (5U)
9802 #define GTM_gtm_cls3_TIO3_CS_CH5_WIDTH           (1U)
9803 #define GTM_gtm_cls3_TIO3_CS_CH5(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CS_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_CS_CH5_MASK)
9804 
9805 #define GTM_gtm_cls3_TIO3_CS_CH6_MASK            (0x40U)
9806 #define GTM_gtm_cls3_TIO3_CS_CH6_SHIFT           (6U)
9807 #define GTM_gtm_cls3_TIO3_CS_CH6_WIDTH           (1U)
9808 #define GTM_gtm_cls3_TIO3_CS_CH6(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CS_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_CS_CH6_MASK)
9809 
9810 #define GTM_gtm_cls3_TIO3_CS_CH7_MASK            (0x80U)
9811 #define GTM_gtm_cls3_TIO3_CS_CH7_SHIFT           (7U)
9812 #define GTM_gtm_cls3_TIO3_CS_CH7_WIDTH           (1U)
9813 #define GTM_gtm_cls3_TIO3_CS_CH7(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CS_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_CS_CH7_MASK)
9814 /*! @} */
9815 
9816 /*! @name TIO3_CO - TIO[i] clear output register */
9817 /*! @{ */
9818 
9819 #define GTM_gtm_cls3_TIO3_CO_CH0_MASK            (0x1U)
9820 #define GTM_gtm_cls3_TIO3_CO_CH0_SHIFT           (0U)
9821 #define GTM_gtm_cls3_TIO3_CO_CH0_WIDTH           (1U)
9822 #define GTM_gtm_cls3_TIO3_CO_CH0(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CO_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_CO_CH0_MASK)
9823 
9824 #define GTM_gtm_cls3_TIO3_CO_CH1_MASK            (0x2U)
9825 #define GTM_gtm_cls3_TIO3_CO_CH1_SHIFT           (1U)
9826 #define GTM_gtm_cls3_TIO3_CO_CH1_WIDTH           (1U)
9827 #define GTM_gtm_cls3_TIO3_CO_CH1(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CO_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_CO_CH1_MASK)
9828 
9829 #define GTM_gtm_cls3_TIO3_CO_CH2_MASK            (0x4U)
9830 #define GTM_gtm_cls3_TIO3_CO_CH2_SHIFT           (2U)
9831 #define GTM_gtm_cls3_TIO3_CO_CH2_WIDTH           (1U)
9832 #define GTM_gtm_cls3_TIO3_CO_CH2(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CO_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_CO_CH2_MASK)
9833 
9834 #define GTM_gtm_cls3_TIO3_CO_CH3_MASK            (0x8U)
9835 #define GTM_gtm_cls3_TIO3_CO_CH3_SHIFT           (3U)
9836 #define GTM_gtm_cls3_TIO3_CO_CH3_WIDTH           (1U)
9837 #define GTM_gtm_cls3_TIO3_CO_CH3(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CO_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_CO_CH3_MASK)
9838 
9839 #define GTM_gtm_cls3_TIO3_CO_CH4_MASK            (0x10U)
9840 #define GTM_gtm_cls3_TIO3_CO_CH4_SHIFT           (4U)
9841 #define GTM_gtm_cls3_TIO3_CO_CH4_WIDTH           (1U)
9842 #define GTM_gtm_cls3_TIO3_CO_CH4(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CO_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_CO_CH4_MASK)
9843 
9844 #define GTM_gtm_cls3_TIO3_CO_CH5_MASK            (0x20U)
9845 #define GTM_gtm_cls3_TIO3_CO_CH5_SHIFT           (5U)
9846 #define GTM_gtm_cls3_TIO3_CO_CH5_WIDTH           (1U)
9847 #define GTM_gtm_cls3_TIO3_CO_CH5(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CO_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_CO_CH5_MASK)
9848 
9849 #define GTM_gtm_cls3_TIO3_CO_CH6_MASK            (0x40U)
9850 #define GTM_gtm_cls3_TIO3_CO_CH6_SHIFT           (6U)
9851 #define GTM_gtm_cls3_TIO3_CO_CH6_WIDTH           (1U)
9852 #define GTM_gtm_cls3_TIO3_CO_CH6(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CO_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_CO_CH6_MASK)
9853 
9854 #define GTM_gtm_cls3_TIO3_CO_CH7_MASK            (0x80U)
9855 #define GTM_gtm_cls3_TIO3_CO_CH7_SHIFT           (7U)
9856 #define GTM_gtm_cls3_TIO3_CO_CH7_WIDTH           (1U)
9857 #define GTM_gtm_cls3_TIO3_CO_CH7(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CO_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_CO_CH7_MASK)
9858 /*! @} */
9859 
9860 /*! @name TIO3_CENDIS - TIO[i] disable register */
9861 /*! @{ */
9862 
9863 #define GTM_gtm_cls3_TIO3_CENDIS_CH0_MASK        (0x1U)
9864 #define GTM_gtm_cls3_TIO3_CENDIS_CH0_SHIFT       (0U)
9865 #define GTM_gtm_cls3_TIO3_CENDIS_CH0_WIDTH       (1U)
9866 #define GTM_gtm_cls3_TIO3_CENDIS_CH0(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CENDIS_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_CENDIS_CH0_MASK)
9867 
9868 #define GTM_gtm_cls3_TIO3_CENDIS_CH1_MASK        (0x2U)
9869 #define GTM_gtm_cls3_TIO3_CENDIS_CH1_SHIFT       (1U)
9870 #define GTM_gtm_cls3_TIO3_CENDIS_CH1_WIDTH       (1U)
9871 #define GTM_gtm_cls3_TIO3_CENDIS_CH1(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CENDIS_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_CENDIS_CH1_MASK)
9872 
9873 #define GTM_gtm_cls3_TIO3_CENDIS_CH2_MASK        (0x4U)
9874 #define GTM_gtm_cls3_TIO3_CENDIS_CH2_SHIFT       (2U)
9875 #define GTM_gtm_cls3_TIO3_CENDIS_CH2_WIDTH       (1U)
9876 #define GTM_gtm_cls3_TIO3_CENDIS_CH2(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CENDIS_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_CENDIS_CH2_MASK)
9877 
9878 #define GTM_gtm_cls3_TIO3_CENDIS_CH3_MASK        (0x8U)
9879 #define GTM_gtm_cls3_TIO3_CENDIS_CH3_SHIFT       (3U)
9880 #define GTM_gtm_cls3_TIO3_CENDIS_CH3_WIDTH       (1U)
9881 #define GTM_gtm_cls3_TIO3_CENDIS_CH3(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CENDIS_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_CENDIS_CH3_MASK)
9882 
9883 #define GTM_gtm_cls3_TIO3_CENDIS_CH4_MASK        (0x10U)
9884 #define GTM_gtm_cls3_TIO3_CENDIS_CH4_SHIFT       (4U)
9885 #define GTM_gtm_cls3_TIO3_CENDIS_CH4_WIDTH       (1U)
9886 #define GTM_gtm_cls3_TIO3_CENDIS_CH4(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CENDIS_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_CENDIS_CH4_MASK)
9887 
9888 #define GTM_gtm_cls3_TIO3_CENDIS_CH5_MASK        (0x20U)
9889 #define GTM_gtm_cls3_TIO3_CENDIS_CH5_SHIFT       (5U)
9890 #define GTM_gtm_cls3_TIO3_CENDIS_CH5_WIDTH       (1U)
9891 #define GTM_gtm_cls3_TIO3_CENDIS_CH5(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CENDIS_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_CENDIS_CH5_MASK)
9892 
9893 #define GTM_gtm_cls3_TIO3_CENDIS_CH6_MASK        (0x40U)
9894 #define GTM_gtm_cls3_TIO3_CENDIS_CH6_SHIFT       (6U)
9895 #define GTM_gtm_cls3_TIO3_CENDIS_CH6_WIDTH       (1U)
9896 #define GTM_gtm_cls3_TIO3_CENDIS_CH6(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CENDIS_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_CENDIS_CH6_MASK)
9897 
9898 #define GTM_gtm_cls3_TIO3_CENDIS_CH7_MASK        (0x80U)
9899 #define GTM_gtm_cls3_TIO3_CENDIS_CH7_SHIFT       (7U)
9900 #define GTM_gtm_cls3_TIO3_CENDIS_CH7_WIDTH       (1U)
9901 #define GTM_gtm_cls3_TIO3_CENDIS_CH7(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CENDIS_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_CENDIS_CH7_MASK)
9902 /*! @} */
9903 
9904 /*! @name TIO3_CINVERT - TIO[i] clear signal invert register */
9905 /*! @{ */
9906 
9907 #define GTM_gtm_cls3_TIO3_CINVERT_CH0_MASK       (0x1U)
9908 #define GTM_gtm_cls3_TIO3_CINVERT_CH0_SHIFT      (0U)
9909 #define GTM_gtm_cls3_TIO3_CINVERT_CH0_WIDTH      (1U)
9910 #define GTM_gtm_cls3_TIO3_CINVERT_CH0(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINVERT_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_CINVERT_CH0_MASK)
9911 
9912 #define GTM_gtm_cls3_TIO3_CINVERT_CH1_MASK       (0x2U)
9913 #define GTM_gtm_cls3_TIO3_CINVERT_CH1_SHIFT      (1U)
9914 #define GTM_gtm_cls3_TIO3_CINVERT_CH1_WIDTH      (1U)
9915 #define GTM_gtm_cls3_TIO3_CINVERT_CH1(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINVERT_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_CINVERT_CH1_MASK)
9916 
9917 #define GTM_gtm_cls3_TIO3_CINVERT_CH2_MASK       (0x4U)
9918 #define GTM_gtm_cls3_TIO3_CINVERT_CH2_SHIFT      (2U)
9919 #define GTM_gtm_cls3_TIO3_CINVERT_CH2_WIDTH      (1U)
9920 #define GTM_gtm_cls3_TIO3_CINVERT_CH2(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINVERT_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_CINVERT_CH2_MASK)
9921 
9922 #define GTM_gtm_cls3_TIO3_CINVERT_CH3_MASK       (0x8U)
9923 #define GTM_gtm_cls3_TIO3_CINVERT_CH3_SHIFT      (3U)
9924 #define GTM_gtm_cls3_TIO3_CINVERT_CH3_WIDTH      (1U)
9925 #define GTM_gtm_cls3_TIO3_CINVERT_CH3(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINVERT_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_CINVERT_CH3_MASK)
9926 
9927 #define GTM_gtm_cls3_TIO3_CINVERT_CH4_MASK       (0x10U)
9928 #define GTM_gtm_cls3_TIO3_CINVERT_CH4_SHIFT      (4U)
9929 #define GTM_gtm_cls3_TIO3_CINVERT_CH4_WIDTH      (1U)
9930 #define GTM_gtm_cls3_TIO3_CINVERT_CH4(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINVERT_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_CINVERT_CH4_MASK)
9931 
9932 #define GTM_gtm_cls3_TIO3_CINVERT_CH5_MASK       (0x20U)
9933 #define GTM_gtm_cls3_TIO3_CINVERT_CH5_SHIFT      (5U)
9934 #define GTM_gtm_cls3_TIO3_CINVERT_CH5_WIDTH      (1U)
9935 #define GTM_gtm_cls3_TIO3_CINVERT_CH5(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINVERT_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_CINVERT_CH5_MASK)
9936 
9937 #define GTM_gtm_cls3_TIO3_CINVERT_CH6_MASK       (0x40U)
9938 #define GTM_gtm_cls3_TIO3_CINVERT_CH6_SHIFT      (6U)
9939 #define GTM_gtm_cls3_TIO3_CINVERT_CH6_WIDTH      (1U)
9940 #define GTM_gtm_cls3_TIO3_CINVERT_CH6(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINVERT_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_CINVERT_CH6_MASK)
9941 
9942 #define GTM_gtm_cls3_TIO3_CINVERT_CH7_MASK       (0x80U)
9943 #define GTM_gtm_cls3_TIO3_CINVERT_CH7_SHIFT      (7U)
9944 #define GTM_gtm_cls3_TIO3_CINVERT_CH7_WIDTH      (1U)
9945 #define GTM_gtm_cls3_TIO3_CINVERT_CH7(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINVERT_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_CINVERT_CH7_MASK)
9946 /*! @} */
9947 
9948 /*! @name TIO3_CINPUT_MODE - TIO[i] disable input mode register */
9949 /*! @{ */
9950 
9951 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH0_MASK   (0x1U)
9952 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH0_SHIFT  (0U)
9953 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH0_WIDTH  (1U)
9954 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH0(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINPUT_MODE_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_CINPUT_MODE_CH0_MASK)
9955 
9956 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH1_MASK   (0x2U)
9957 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH1_SHIFT  (1U)
9958 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH1_WIDTH  (1U)
9959 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH1(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINPUT_MODE_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_CINPUT_MODE_CH1_MASK)
9960 
9961 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH2_MASK   (0x4U)
9962 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH2_SHIFT  (2U)
9963 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH2_WIDTH  (1U)
9964 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH2(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINPUT_MODE_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_CINPUT_MODE_CH2_MASK)
9965 
9966 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH3_MASK   (0x8U)
9967 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH3_SHIFT  (3U)
9968 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH3_WIDTH  (1U)
9969 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH3(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINPUT_MODE_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_CINPUT_MODE_CH3_MASK)
9970 
9971 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH4_MASK   (0x10U)
9972 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH4_SHIFT  (4U)
9973 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH4_WIDTH  (1U)
9974 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH4(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINPUT_MODE_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_CINPUT_MODE_CH4_MASK)
9975 
9976 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH5_MASK   (0x20U)
9977 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH5_SHIFT  (5U)
9978 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH5_WIDTH  (1U)
9979 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH5(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINPUT_MODE_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_CINPUT_MODE_CH5_MASK)
9980 
9981 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH6_MASK   (0x40U)
9982 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH6_SHIFT  (6U)
9983 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH6_WIDTH  (1U)
9984 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH6(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINPUT_MODE_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_CINPUT_MODE_CH6_MASK)
9985 
9986 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH7_MASK   (0x80U)
9987 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH7_SHIFT  (7U)
9988 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH7_WIDTH  (1U)
9989 #define GTM_gtm_cls3_TIO3_CINPUT_MODE_CH7(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CINPUT_MODE_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_CINPUT_MODE_CH7_MASK)
9990 /*! @} */
9991 
9992 /*! @name TIO3_CCYCLIC_MODE - TIO[i] disable cyclic mode register */
9993 /*! @{ */
9994 
9995 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH0_MASK  (0x1U)
9996 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH0_SHIFT (0U)
9997 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH0_WIDTH (1U)
9998 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH0_MASK)
9999 
10000 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH1_MASK  (0x2U)
10001 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH1_SHIFT (1U)
10002 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH1_WIDTH (1U)
10003 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH1_MASK)
10004 
10005 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH2_MASK  (0x4U)
10006 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH2_SHIFT (2U)
10007 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH2_WIDTH (1U)
10008 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH2_MASK)
10009 
10010 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH3_MASK  (0x8U)
10011 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH3_SHIFT (3U)
10012 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH3_WIDTH (1U)
10013 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH3_MASK)
10014 
10015 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH4_MASK  (0x10U)
10016 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH4_SHIFT (4U)
10017 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH4_WIDTH (1U)
10018 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH4_MASK)
10019 
10020 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH5_MASK  (0x20U)
10021 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH5_SHIFT (5U)
10022 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH5_WIDTH (1U)
10023 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH5_MASK)
10024 
10025 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH6_MASK  (0x40U)
10026 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH6_SHIFT (6U)
10027 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH6_WIDTH (1U)
10028 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH6_MASK)
10029 
10030 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH7_MASK  (0x80U)
10031 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH7_SHIFT (7U)
10032 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH7_WIDTH (1U)
10033 #define GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_CCYCLIC_MODE_CH7_MASK)
10034 /*! @} */
10035 
10036 /*! @name TIO3_CTRIG_OUT_GATE_EN - TIO[i] clear Trigger Output, output gating register */
10037 /*! @{ */
10038 
10039 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH0_MASK (0x1U)
10040 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH0_SHIFT (0U)
10041 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH0_WIDTH (1U)
10042 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH0_MASK)
10043 
10044 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH1_MASK (0x2U)
10045 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH1_SHIFT (1U)
10046 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH1_WIDTH (1U)
10047 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH1_MASK)
10048 
10049 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH2_MASK (0x4U)
10050 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH2_SHIFT (2U)
10051 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH2_WIDTH (1U)
10052 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH2_MASK)
10053 
10054 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH3_MASK (0x8U)
10055 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH3_SHIFT (3U)
10056 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH3_WIDTH (1U)
10057 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH3_MASK)
10058 
10059 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH4_MASK (0x10U)
10060 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH4_SHIFT (4U)
10061 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH4_WIDTH (1U)
10062 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH4_MASK)
10063 
10064 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH5_MASK (0x20U)
10065 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH5_SHIFT (5U)
10066 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH5_WIDTH (1U)
10067 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH5_MASK)
10068 
10069 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH6_MASK (0x40U)
10070 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH6_SHIFT (6U)
10071 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH6_WIDTH (1U)
10072 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH6_MASK)
10073 
10074 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH7_MASK (0x80U)
10075 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH7_SHIFT (7U)
10076 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH7_WIDTH (1U)
10077 #define GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_CTRIG_OUT_GATE_EN_CH7_MASK)
10078 /*! @} */
10079 
10080 /*! @name TIO3_CPLTRIG_OUT_GATE_EN - TIO[i] clear PL_TRIG_OUT output gating register */
10081 /*! @{ */
10082 
10083 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH0_MASK (0x1U)
10084 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH0_SHIFT (0U)
10085 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH0_WIDTH (1U)
10086 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH0_MASK)
10087 
10088 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH1_MASK (0x2U)
10089 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH1_SHIFT (1U)
10090 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH1_WIDTH (1U)
10091 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH1_MASK)
10092 
10093 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH2_MASK (0x4U)
10094 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH2_SHIFT (2U)
10095 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH2_WIDTH (1U)
10096 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH2_MASK)
10097 
10098 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH3_MASK (0x8U)
10099 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH3_SHIFT (3U)
10100 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH3_WIDTH (1U)
10101 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH3_MASK)
10102 
10103 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH4_MASK (0x10U)
10104 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH4_SHIFT (4U)
10105 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH4_WIDTH (1U)
10106 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH4_MASK)
10107 
10108 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH5_MASK (0x20U)
10109 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH5_SHIFT (5U)
10110 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH5_WIDTH (1U)
10111 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH5_MASK)
10112 
10113 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH6_MASK (0x40U)
10114 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH6_SHIFT (6U)
10115 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH6_WIDTH (1U)
10116 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH6_MASK)
10117 
10118 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH7_MASK (0x80U)
10119 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH7_SHIFT (7U)
10120 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH7_WIDTH (1U)
10121 #define GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_CPLTRIG_OUT_GATE_EN_CH7_MASK)
10122 /*! @} */
10123 
10124 /*! @name TIO3_SS - TIO[i] set signal sampling register */
10125 /*! @{ */
10126 
10127 #define GTM_gtm_cls3_TIO3_SS_CH0_MASK            (0x1U)
10128 #define GTM_gtm_cls3_TIO3_SS_CH0_SHIFT           (0U)
10129 #define GTM_gtm_cls3_TIO3_SS_CH0_WIDTH           (1U)
10130 #define GTM_gtm_cls3_TIO3_SS_CH0(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SS_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_SS_CH0_MASK)
10131 
10132 #define GTM_gtm_cls3_TIO3_SS_CH1_MASK            (0x2U)
10133 #define GTM_gtm_cls3_TIO3_SS_CH1_SHIFT           (1U)
10134 #define GTM_gtm_cls3_TIO3_SS_CH1_WIDTH           (1U)
10135 #define GTM_gtm_cls3_TIO3_SS_CH1(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SS_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_SS_CH1_MASK)
10136 
10137 #define GTM_gtm_cls3_TIO3_SS_CH2_MASK            (0x4U)
10138 #define GTM_gtm_cls3_TIO3_SS_CH2_SHIFT           (2U)
10139 #define GTM_gtm_cls3_TIO3_SS_CH2_WIDTH           (1U)
10140 #define GTM_gtm_cls3_TIO3_SS_CH2(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SS_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_SS_CH2_MASK)
10141 
10142 #define GTM_gtm_cls3_TIO3_SS_CH3_MASK            (0x8U)
10143 #define GTM_gtm_cls3_TIO3_SS_CH3_SHIFT           (3U)
10144 #define GTM_gtm_cls3_TIO3_SS_CH3_WIDTH           (1U)
10145 #define GTM_gtm_cls3_TIO3_SS_CH3(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SS_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_SS_CH3_MASK)
10146 
10147 #define GTM_gtm_cls3_TIO3_SS_CH4_MASK            (0x10U)
10148 #define GTM_gtm_cls3_TIO3_SS_CH4_SHIFT           (4U)
10149 #define GTM_gtm_cls3_TIO3_SS_CH4_WIDTH           (1U)
10150 #define GTM_gtm_cls3_TIO3_SS_CH4(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SS_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_SS_CH4_MASK)
10151 
10152 #define GTM_gtm_cls3_TIO3_SS_CH5_MASK            (0x20U)
10153 #define GTM_gtm_cls3_TIO3_SS_CH5_SHIFT           (5U)
10154 #define GTM_gtm_cls3_TIO3_SS_CH5_WIDTH           (1U)
10155 #define GTM_gtm_cls3_TIO3_SS_CH5(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SS_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_SS_CH5_MASK)
10156 
10157 #define GTM_gtm_cls3_TIO3_SS_CH6_MASK            (0x40U)
10158 #define GTM_gtm_cls3_TIO3_SS_CH6_SHIFT           (6U)
10159 #define GTM_gtm_cls3_TIO3_SS_CH6_WIDTH           (1U)
10160 #define GTM_gtm_cls3_TIO3_SS_CH6(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SS_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_SS_CH6_MASK)
10161 
10162 #define GTM_gtm_cls3_TIO3_SS_CH7_MASK            (0x80U)
10163 #define GTM_gtm_cls3_TIO3_SS_CH7_SHIFT           (7U)
10164 #define GTM_gtm_cls3_TIO3_SS_CH7_WIDTH           (1U)
10165 #define GTM_gtm_cls3_TIO3_SS_CH7(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SS_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_SS_CH7_MASK)
10166 /*! @} */
10167 
10168 /*! @name TIO3_SO - TIO[i] set output register */
10169 /*! @{ */
10170 
10171 #define GTM_gtm_cls3_TIO3_SO_CH0_MASK            (0x1U)
10172 #define GTM_gtm_cls3_TIO3_SO_CH0_SHIFT           (0U)
10173 #define GTM_gtm_cls3_TIO3_SO_CH0_WIDTH           (1U)
10174 #define GTM_gtm_cls3_TIO3_SO_CH0(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SO_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_SO_CH0_MASK)
10175 
10176 #define GTM_gtm_cls3_TIO3_SO_CH1_MASK            (0x2U)
10177 #define GTM_gtm_cls3_TIO3_SO_CH1_SHIFT           (1U)
10178 #define GTM_gtm_cls3_TIO3_SO_CH1_WIDTH           (1U)
10179 #define GTM_gtm_cls3_TIO3_SO_CH1(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SO_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_SO_CH1_MASK)
10180 
10181 #define GTM_gtm_cls3_TIO3_SO_CH2_MASK            (0x4U)
10182 #define GTM_gtm_cls3_TIO3_SO_CH2_SHIFT           (2U)
10183 #define GTM_gtm_cls3_TIO3_SO_CH2_WIDTH           (1U)
10184 #define GTM_gtm_cls3_TIO3_SO_CH2(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SO_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_SO_CH2_MASK)
10185 
10186 #define GTM_gtm_cls3_TIO3_SO_CH3_MASK            (0x8U)
10187 #define GTM_gtm_cls3_TIO3_SO_CH3_SHIFT           (3U)
10188 #define GTM_gtm_cls3_TIO3_SO_CH3_WIDTH           (1U)
10189 #define GTM_gtm_cls3_TIO3_SO_CH3(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SO_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_SO_CH3_MASK)
10190 
10191 #define GTM_gtm_cls3_TIO3_SO_CH4_MASK            (0x10U)
10192 #define GTM_gtm_cls3_TIO3_SO_CH4_SHIFT           (4U)
10193 #define GTM_gtm_cls3_TIO3_SO_CH4_WIDTH           (1U)
10194 #define GTM_gtm_cls3_TIO3_SO_CH4(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SO_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_SO_CH4_MASK)
10195 
10196 #define GTM_gtm_cls3_TIO3_SO_CH5_MASK            (0x20U)
10197 #define GTM_gtm_cls3_TIO3_SO_CH5_SHIFT           (5U)
10198 #define GTM_gtm_cls3_TIO3_SO_CH5_WIDTH           (1U)
10199 #define GTM_gtm_cls3_TIO3_SO_CH5(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SO_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_SO_CH5_MASK)
10200 
10201 #define GTM_gtm_cls3_TIO3_SO_CH6_MASK            (0x40U)
10202 #define GTM_gtm_cls3_TIO3_SO_CH6_SHIFT           (6U)
10203 #define GTM_gtm_cls3_TIO3_SO_CH6_WIDTH           (1U)
10204 #define GTM_gtm_cls3_TIO3_SO_CH6(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SO_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_SO_CH6_MASK)
10205 
10206 #define GTM_gtm_cls3_TIO3_SO_CH7_MASK            (0x80U)
10207 #define GTM_gtm_cls3_TIO3_SO_CH7_SHIFT           (7U)
10208 #define GTM_gtm_cls3_TIO3_SO_CH7_WIDTH           (1U)
10209 #define GTM_gtm_cls3_TIO3_SO_CH7(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SO_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_SO_CH7_MASK)
10210 /*! @} */
10211 
10212 /*! @name TIO3_SENDIS - TIO[i] enable register */
10213 /*! @{ */
10214 
10215 #define GTM_gtm_cls3_TIO3_SENDIS_CH0_MASK        (0x1U)
10216 #define GTM_gtm_cls3_TIO3_SENDIS_CH0_SHIFT       (0U)
10217 #define GTM_gtm_cls3_TIO3_SENDIS_CH0_WIDTH       (1U)
10218 #define GTM_gtm_cls3_TIO3_SENDIS_CH0(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SENDIS_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_SENDIS_CH0_MASK)
10219 
10220 #define GTM_gtm_cls3_TIO3_SENDIS_CH1_MASK        (0x2U)
10221 #define GTM_gtm_cls3_TIO3_SENDIS_CH1_SHIFT       (1U)
10222 #define GTM_gtm_cls3_TIO3_SENDIS_CH1_WIDTH       (1U)
10223 #define GTM_gtm_cls3_TIO3_SENDIS_CH1(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SENDIS_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_SENDIS_CH1_MASK)
10224 
10225 #define GTM_gtm_cls3_TIO3_SENDIS_CH2_MASK        (0x4U)
10226 #define GTM_gtm_cls3_TIO3_SENDIS_CH2_SHIFT       (2U)
10227 #define GTM_gtm_cls3_TIO3_SENDIS_CH2_WIDTH       (1U)
10228 #define GTM_gtm_cls3_TIO3_SENDIS_CH2(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SENDIS_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_SENDIS_CH2_MASK)
10229 
10230 #define GTM_gtm_cls3_TIO3_SENDIS_CH3_MASK        (0x8U)
10231 #define GTM_gtm_cls3_TIO3_SENDIS_CH3_SHIFT       (3U)
10232 #define GTM_gtm_cls3_TIO3_SENDIS_CH3_WIDTH       (1U)
10233 #define GTM_gtm_cls3_TIO3_SENDIS_CH3(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SENDIS_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_SENDIS_CH3_MASK)
10234 
10235 #define GTM_gtm_cls3_TIO3_SENDIS_CH4_MASK        (0x10U)
10236 #define GTM_gtm_cls3_TIO3_SENDIS_CH4_SHIFT       (4U)
10237 #define GTM_gtm_cls3_TIO3_SENDIS_CH4_WIDTH       (1U)
10238 #define GTM_gtm_cls3_TIO3_SENDIS_CH4(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SENDIS_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_SENDIS_CH4_MASK)
10239 
10240 #define GTM_gtm_cls3_TIO3_SENDIS_CH5_MASK        (0x20U)
10241 #define GTM_gtm_cls3_TIO3_SENDIS_CH5_SHIFT       (5U)
10242 #define GTM_gtm_cls3_TIO3_SENDIS_CH5_WIDTH       (1U)
10243 #define GTM_gtm_cls3_TIO3_SENDIS_CH5(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SENDIS_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_SENDIS_CH5_MASK)
10244 
10245 #define GTM_gtm_cls3_TIO3_SENDIS_CH6_MASK        (0x40U)
10246 #define GTM_gtm_cls3_TIO3_SENDIS_CH6_SHIFT       (6U)
10247 #define GTM_gtm_cls3_TIO3_SENDIS_CH6_WIDTH       (1U)
10248 #define GTM_gtm_cls3_TIO3_SENDIS_CH6(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SENDIS_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_SENDIS_CH6_MASK)
10249 
10250 #define GTM_gtm_cls3_TIO3_SENDIS_CH7_MASK        (0x80U)
10251 #define GTM_gtm_cls3_TIO3_SENDIS_CH7_SHIFT       (7U)
10252 #define GTM_gtm_cls3_TIO3_SENDIS_CH7_WIDTH       (1U)
10253 #define GTM_gtm_cls3_TIO3_SENDIS_CH7(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SENDIS_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_SENDIS_CH7_MASK)
10254 /*! @} */
10255 
10256 /*! @name TIO3_SINVERT - TIO[i] set signal invert register */
10257 /*! @{ */
10258 
10259 #define GTM_gtm_cls3_TIO3_SINVERT_CH0_MASK       (0x1U)
10260 #define GTM_gtm_cls3_TIO3_SINVERT_CH0_SHIFT      (0U)
10261 #define GTM_gtm_cls3_TIO3_SINVERT_CH0_WIDTH      (1U)
10262 #define GTM_gtm_cls3_TIO3_SINVERT_CH0(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINVERT_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_SINVERT_CH0_MASK)
10263 
10264 #define GTM_gtm_cls3_TIO3_SINVERT_CH1_MASK       (0x2U)
10265 #define GTM_gtm_cls3_TIO3_SINVERT_CH1_SHIFT      (1U)
10266 #define GTM_gtm_cls3_TIO3_SINVERT_CH1_WIDTH      (1U)
10267 #define GTM_gtm_cls3_TIO3_SINVERT_CH1(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINVERT_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_SINVERT_CH1_MASK)
10268 
10269 #define GTM_gtm_cls3_TIO3_SINVERT_CH2_MASK       (0x4U)
10270 #define GTM_gtm_cls3_TIO3_SINVERT_CH2_SHIFT      (2U)
10271 #define GTM_gtm_cls3_TIO3_SINVERT_CH2_WIDTH      (1U)
10272 #define GTM_gtm_cls3_TIO3_SINVERT_CH2(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINVERT_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_SINVERT_CH2_MASK)
10273 
10274 #define GTM_gtm_cls3_TIO3_SINVERT_CH3_MASK       (0x8U)
10275 #define GTM_gtm_cls3_TIO3_SINVERT_CH3_SHIFT      (3U)
10276 #define GTM_gtm_cls3_TIO3_SINVERT_CH3_WIDTH      (1U)
10277 #define GTM_gtm_cls3_TIO3_SINVERT_CH3(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINVERT_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_SINVERT_CH3_MASK)
10278 
10279 #define GTM_gtm_cls3_TIO3_SINVERT_CH4_MASK       (0x10U)
10280 #define GTM_gtm_cls3_TIO3_SINVERT_CH4_SHIFT      (4U)
10281 #define GTM_gtm_cls3_TIO3_SINVERT_CH4_WIDTH      (1U)
10282 #define GTM_gtm_cls3_TIO3_SINVERT_CH4(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINVERT_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_SINVERT_CH4_MASK)
10283 
10284 #define GTM_gtm_cls3_TIO3_SINVERT_CH5_MASK       (0x20U)
10285 #define GTM_gtm_cls3_TIO3_SINVERT_CH5_SHIFT      (5U)
10286 #define GTM_gtm_cls3_TIO3_SINVERT_CH5_WIDTH      (1U)
10287 #define GTM_gtm_cls3_TIO3_SINVERT_CH5(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINVERT_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_SINVERT_CH5_MASK)
10288 
10289 #define GTM_gtm_cls3_TIO3_SINVERT_CH6_MASK       (0x40U)
10290 #define GTM_gtm_cls3_TIO3_SINVERT_CH6_SHIFT      (6U)
10291 #define GTM_gtm_cls3_TIO3_SINVERT_CH6_WIDTH      (1U)
10292 #define GTM_gtm_cls3_TIO3_SINVERT_CH6(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINVERT_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_SINVERT_CH6_MASK)
10293 
10294 #define GTM_gtm_cls3_TIO3_SINVERT_CH7_MASK       (0x80U)
10295 #define GTM_gtm_cls3_TIO3_SINVERT_CH7_SHIFT      (7U)
10296 #define GTM_gtm_cls3_TIO3_SINVERT_CH7_WIDTH      (1U)
10297 #define GTM_gtm_cls3_TIO3_SINVERT_CH7(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINVERT_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_SINVERT_CH7_MASK)
10298 /*! @} */
10299 
10300 /*! @name TIO3_SINPUT_MODE - TIO[i] enable input mode register */
10301 /*! @{ */
10302 
10303 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH0_MASK   (0x1U)
10304 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH0_SHIFT  (0U)
10305 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH0_WIDTH  (1U)
10306 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH0(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINPUT_MODE_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_SINPUT_MODE_CH0_MASK)
10307 
10308 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH1_MASK   (0x2U)
10309 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH1_SHIFT  (1U)
10310 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH1_WIDTH  (1U)
10311 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH1(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINPUT_MODE_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_SINPUT_MODE_CH1_MASK)
10312 
10313 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH2_MASK   (0x4U)
10314 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH2_SHIFT  (2U)
10315 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH2_WIDTH  (1U)
10316 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH2(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINPUT_MODE_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_SINPUT_MODE_CH2_MASK)
10317 
10318 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH3_MASK   (0x8U)
10319 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH3_SHIFT  (3U)
10320 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH3_WIDTH  (1U)
10321 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH3(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINPUT_MODE_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_SINPUT_MODE_CH3_MASK)
10322 
10323 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH4_MASK   (0x10U)
10324 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH4_SHIFT  (4U)
10325 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH4_WIDTH  (1U)
10326 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH4(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINPUT_MODE_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_SINPUT_MODE_CH4_MASK)
10327 
10328 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH5_MASK   (0x20U)
10329 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH5_SHIFT  (5U)
10330 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH5_WIDTH  (1U)
10331 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH5(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINPUT_MODE_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_SINPUT_MODE_CH5_MASK)
10332 
10333 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH6_MASK   (0x40U)
10334 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH6_SHIFT  (6U)
10335 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH6_WIDTH  (1U)
10336 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH6(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINPUT_MODE_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_SINPUT_MODE_CH6_MASK)
10337 
10338 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH7_MASK   (0x80U)
10339 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH7_SHIFT  (7U)
10340 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH7_WIDTH  (1U)
10341 #define GTM_gtm_cls3_TIO3_SINPUT_MODE_CH7(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SINPUT_MODE_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_SINPUT_MODE_CH7_MASK)
10342 /*! @} */
10343 
10344 /*! @name TIO3_SCYCLIC_MODE - TIO[i] enable cyclic mode register */
10345 /*! @{ */
10346 
10347 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH0_MASK  (0x1U)
10348 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH0_SHIFT (0U)
10349 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH0_WIDTH (1U)
10350 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH0_MASK)
10351 
10352 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH1_MASK  (0x2U)
10353 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH1_SHIFT (1U)
10354 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH1_WIDTH (1U)
10355 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH1_MASK)
10356 
10357 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH2_MASK  (0x4U)
10358 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH2_SHIFT (2U)
10359 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH2_WIDTH (1U)
10360 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH2_MASK)
10361 
10362 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH3_MASK  (0x8U)
10363 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH3_SHIFT (3U)
10364 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH3_WIDTH (1U)
10365 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH3_MASK)
10366 
10367 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH4_MASK  (0x10U)
10368 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH4_SHIFT (4U)
10369 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH4_WIDTH (1U)
10370 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH4_MASK)
10371 
10372 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH5_MASK  (0x20U)
10373 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH5_SHIFT (5U)
10374 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH5_WIDTH (1U)
10375 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH5_MASK)
10376 
10377 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH6_MASK  (0x40U)
10378 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH6_SHIFT (6U)
10379 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH6_WIDTH (1U)
10380 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH6_MASK)
10381 
10382 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH7_MASK  (0x80U)
10383 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH7_SHIFT (7U)
10384 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH7_WIDTH (1U)
10385 #define GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_SCYCLIC_MODE_CH7_MASK)
10386 /*! @} */
10387 
10388 /*! @name TIO3_STRIG_OUT_GATE_EN - TIO[i] set Trigger Output, output gating register */
10389 /*! @{ */
10390 
10391 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH0_MASK (0x1U)
10392 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH0_SHIFT (0U)
10393 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH0_WIDTH (1U)
10394 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH0_MASK)
10395 
10396 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH1_MASK (0x2U)
10397 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH1_SHIFT (1U)
10398 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH1_WIDTH (1U)
10399 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH1_MASK)
10400 
10401 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH2_MASK (0x4U)
10402 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH2_SHIFT (2U)
10403 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH2_WIDTH (1U)
10404 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH2_MASK)
10405 
10406 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH3_MASK (0x8U)
10407 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH3_SHIFT (3U)
10408 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH3_WIDTH (1U)
10409 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH3_MASK)
10410 
10411 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH4_MASK (0x10U)
10412 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH4_SHIFT (4U)
10413 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH4_WIDTH (1U)
10414 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH4_MASK)
10415 
10416 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH5_MASK (0x20U)
10417 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH5_SHIFT (5U)
10418 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH5_WIDTH (1U)
10419 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH5_MASK)
10420 
10421 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH6_MASK (0x40U)
10422 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH6_SHIFT (6U)
10423 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH6_WIDTH (1U)
10424 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH6_MASK)
10425 
10426 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH7_MASK (0x80U)
10427 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH7_SHIFT (7U)
10428 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH7_WIDTH (1U)
10429 #define GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_STRIG_OUT_GATE_EN_CH7_MASK)
10430 /*! @} */
10431 
10432 /*! @name TIO3_SPLTRIG_OUT_GATE_EN - TIO[i] set PL_TRIG_OUT output gating register */
10433 /*! @{ */
10434 
10435 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH0_MASK (0x1U)
10436 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH0_SHIFT (0U)
10437 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH0_WIDTH (1U)
10438 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH0_MASK)
10439 
10440 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH1_MASK (0x2U)
10441 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH1_SHIFT (1U)
10442 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH1_WIDTH (1U)
10443 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH1_MASK)
10444 
10445 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH2_MASK (0x4U)
10446 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH2_SHIFT (2U)
10447 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH2_WIDTH (1U)
10448 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH2_MASK)
10449 
10450 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH3_MASK (0x8U)
10451 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH3_SHIFT (3U)
10452 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH3_WIDTH (1U)
10453 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH3_MASK)
10454 
10455 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH4_MASK (0x10U)
10456 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH4_SHIFT (4U)
10457 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH4_WIDTH (1U)
10458 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH4_MASK)
10459 
10460 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH5_MASK (0x20U)
10461 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH5_SHIFT (5U)
10462 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH5_WIDTH (1U)
10463 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH5_MASK)
10464 
10465 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH6_MASK (0x40U)
10466 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH6_SHIFT (6U)
10467 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH6_WIDTH (1U)
10468 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH6_MASK)
10469 
10470 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH7_MASK (0x80U)
10471 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH7_SHIFT (7U)
10472 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH7_WIDTH (1U)
10473 #define GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_SPLTRIG_OUT_GATE_EN_CH7_MASK)
10474 /*! @} */
10475 
10476 /*! @name TIO3_IS - TIO[i] invert signal sampling register */
10477 /*! @{ */
10478 
10479 #define GTM_gtm_cls3_TIO3_IS_CH0_MASK            (0x1U)
10480 #define GTM_gtm_cls3_TIO3_IS_CH0_SHIFT           (0U)
10481 #define GTM_gtm_cls3_TIO3_IS_CH0_WIDTH           (1U)
10482 #define GTM_gtm_cls3_TIO3_IS_CH0(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IS_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_IS_CH0_MASK)
10483 
10484 #define GTM_gtm_cls3_TIO3_IS_CH1_MASK            (0x2U)
10485 #define GTM_gtm_cls3_TIO3_IS_CH1_SHIFT           (1U)
10486 #define GTM_gtm_cls3_TIO3_IS_CH1_WIDTH           (1U)
10487 #define GTM_gtm_cls3_TIO3_IS_CH1(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IS_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_IS_CH1_MASK)
10488 
10489 #define GTM_gtm_cls3_TIO3_IS_CH2_MASK            (0x4U)
10490 #define GTM_gtm_cls3_TIO3_IS_CH2_SHIFT           (2U)
10491 #define GTM_gtm_cls3_TIO3_IS_CH2_WIDTH           (1U)
10492 #define GTM_gtm_cls3_TIO3_IS_CH2(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IS_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_IS_CH2_MASK)
10493 
10494 #define GTM_gtm_cls3_TIO3_IS_CH3_MASK            (0x8U)
10495 #define GTM_gtm_cls3_TIO3_IS_CH3_SHIFT           (3U)
10496 #define GTM_gtm_cls3_TIO3_IS_CH3_WIDTH           (1U)
10497 #define GTM_gtm_cls3_TIO3_IS_CH3(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IS_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_IS_CH3_MASK)
10498 
10499 #define GTM_gtm_cls3_TIO3_IS_CH4_MASK            (0x10U)
10500 #define GTM_gtm_cls3_TIO3_IS_CH4_SHIFT           (4U)
10501 #define GTM_gtm_cls3_TIO3_IS_CH4_WIDTH           (1U)
10502 #define GTM_gtm_cls3_TIO3_IS_CH4(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IS_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_IS_CH4_MASK)
10503 
10504 #define GTM_gtm_cls3_TIO3_IS_CH5_MASK            (0x20U)
10505 #define GTM_gtm_cls3_TIO3_IS_CH5_SHIFT           (5U)
10506 #define GTM_gtm_cls3_TIO3_IS_CH5_WIDTH           (1U)
10507 #define GTM_gtm_cls3_TIO3_IS_CH5(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IS_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_IS_CH5_MASK)
10508 
10509 #define GTM_gtm_cls3_TIO3_IS_CH6_MASK            (0x40U)
10510 #define GTM_gtm_cls3_TIO3_IS_CH6_SHIFT           (6U)
10511 #define GTM_gtm_cls3_TIO3_IS_CH6_WIDTH           (1U)
10512 #define GTM_gtm_cls3_TIO3_IS_CH6(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IS_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_IS_CH6_MASK)
10513 
10514 #define GTM_gtm_cls3_TIO3_IS_CH7_MASK            (0x80U)
10515 #define GTM_gtm_cls3_TIO3_IS_CH7_SHIFT           (7U)
10516 #define GTM_gtm_cls3_TIO3_IS_CH7_WIDTH           (1U)
10517 #define GTM_gtm_cls3_TIO3_IS_CH7(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IS_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_IS_CH7_MASK)
10518 /*! @} */
10519 
10520 /*! @name TIO3_IO - TIO[i] invert output register */
10521 /*! @{ */
10522 
10523 #define GTM_gtm_cls3_TIO3_IO_CH0_MASK            (0x1U)
10524 #define GTM_gtm_cls3_TIO3_IO_CH0_SHIFT           (0U)
10525 #define GTM_gtm_cls3_TIO3_IO_CH0_WIDTH           (1U)
10526 #define GTM_gtm_cls3_TIO3_IO_CH0(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IO_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_IO_CH0_MASK)
10527 
10528 #define GTM_gtm_cls3_TIO3_IO_CH1_MASK            (0x2U)
10529 #define GTM_gtm_cls3_TIO3_IO_CH1_SHIFT           (1U)
10530 #define GTM_gtm_cls3_TIO3_IO_CH1_WIDTH           (1U)
10531 #define GTM_gtm_cls3_TIO3_IO_CH1(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IO_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_IO_CH1_MASK)
10532 
10533 #define GTM_gtm_cls3_TIO3_IO_CH2_MASK            (0x4U)
10534 #define GTM_gtm_cls3_TIO3_IO_CH2_SHIFT           (2U)
10535 #define GTM_gtm_cls3_TIO3_IO_CH2_WIDTH           (1U)
10536 #define GTM_gtm_cls3_TIO3_IO_CH2(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IO_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_IO_CH2_MASK)
10537 
10538 #define GTM_gtm_cls3_TIO3_IO_CH3_MASK            (0x8U)
10539 #define GTM_gtm_cls3_TIO3_IO_CH3_SHIFT           (3U)
10540 #define GTM_gtm_cls3_TIO3_IO_CH3_WIDTH           (1U)
10541 #define GTM_gtm_cls3_TIO3_IO_CH3(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IO_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_IO_CH3_MASK)
10542 
10543 #define GTM_gtm_cls3_TIO3_IO_CH4_MASK            (0x10U)
10544 #define GTM_gtm_cls3_TIO3_IO_CH4_SHIFT           (4U)
10545 #define GTM_gtm_cls3_TIO3_IO_CH4_WIDTH           (1U)
10546 #define GTM_gtm_cls3_TIO3_IO_CH4(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IO_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_IO_CH4_MASK)
10547 
10548 #define GTM_gtm_cls3_TIO3_IO_CH5_MASK            (0x20U)
10549 #define GTM_gtm_cls3_TIO3_IO_CH5_SHIFT           (5U)
10550 #define GTM_gtm_cls3_TIO3_IO_CH5_WIDTH           (1U)
10551 #define GTM_gtm_cls3_TIO3_IO_CH5(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IO_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_IO_CH5_MASK)
10552 
10553 #define GTM_gtm_cls3_TIO3_IO_CH6_MASK            (0x40U)
10554 #define GTM_gtm_cls3_TIO3_IO_CH6_SHIFT           (6U)
10555 #define GTM_gtm_cls3_TIO3_IO_CH6_WIDTH           (1U)
10556 #define GTM_gtm_cls3_TIO3_IO_CH6(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IO_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_IO_CH6_MASK)
10557 
10558 #define GTM_gtm_cls3_TIO3_IO_CH7_MASK            (0x80U)
10559 #define GTM_gtm_cls3_TIO3_IO_CH7_SHIFT           (7U)
10560 #define GTM_gtm_cls3_TIO3_IO_CH7_WIDTH           (1U)
10561 #define GTM_gtm_cls3_TIO3_IO_CH7(x)              (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IO_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_IO_CH7_MASK)
10562 /*! @} */
10563 
10564 /*! @name TIO3_IENDIS - TIO[i] toggle enable/disable register */
10565 /*! @{ */
10566 
10567 #define GTM_gtm_cls3_TIO3_IENDIS_CH0_MASK        (0x1U)
10568 #define GTM_gtm_cls3_TIO3_IENDIS_CH0_SHIFT       (0U)
10569 #define GTM_gtm_cls3_TIO3_IENDIS_CH0_WIDTH       (1U)
10570 #define GTM_gtm_cls3_TIO3_IENDIS_CH0(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IENDIS_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_IENDIS_CH0_MASK)
10571 
10572 #define GTM_gtm_cls3_TIO3_IENDIS_CH1_MASK        (0x2U)
10573 #define GTM_gtm_cls3_TIO3_IENDIS_CH1_SHIFT       (1U)
10574 #define GTM_gtm_cls3_TIO3_IENDIS_CH1_WIDTH       (1U)
10575 #define GTM_gtm_cls3_TIO3_IENDIS_CH1(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IENDIS_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_IENDIS_CH1_MASK)
10576 
10577 #define GTM_gtm_cls3_TIO3_IENDIS_CH2_MASK        (0x4U)
10578 #define GTM_gtm_cls3_TIO3_IENDIS_CH2_SHIFT       (2U)
10579 #define GTM_gtm_cls3_TIO3_IENDIS_CH2_WIDTH       (1U)
10580 #define GTM_gtm_cls3_TIO3_IENDIS_CH2(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IENDIS_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_IENDIS_CH2_MASK)
10581 
10582 #define GTM_gtm_cls3_TIO3_IENDIS_CH3_MASK        (0x8U)
10583 #define GTM_gtm_cls3_TIO3_IENDIS_CH3_SHIFT       (3U)
10584 #define GTM_gtm_cls3_TIO3_IENDIS_CH3_WIDTH       (1U)
10585 #define GTM_gtm_cls3_TIO3_IENDIS_CH3(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IENDIS_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_IENDIS_CH3_MASK)
10586 
10587 #define GTM_gtm_cls3_TIO3_IENDIS_CH4_MASK        (0x10U)
10588 #define GTM_gtm_cls3_TIO3_IENDIS_CH4_SHIFT       (4U)
10589 #define GTM_gtm_cls3_TIO3_IENDIS_CH4_WIDTH       (1U)
10590 #define GTM_gtm_cls3_TIO3_IENDIS_CH4(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IENDIS_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_IENDIS_CH4_MASK)
10591 
10592 #define GTM_gtm_cls3_TIO3_IENDIS_CH5_MASK        (0x20U)
10593 #define GTM_gtm_cls3_TIO3_IENDIS_CH5_SHIFT       (5U)
10594 #define GTM_gtm_cls3_TIO3_IENDIS_CH5_WIDTH       (1U)
10595 #define GTM_gtm_cls3_TIO3_IENDIS_CH5(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IENDIS_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_IENDIS_CH5_MASK)
10596 
10597 #define GTM_gtm_cls3_TIO3_IENDIS_CH6_MASK        (0x40U)
10598 #define GTM_gtm_cls3_TIO3_IENDIS_CH6_SHIFT       (6U)
10599 #define GTM_gtm_cls3_TIO3_IENDIS_CH6_WIDTH       (1U)
10600 #define GTM_gtm_cls3_TIO3_IENDIS_CH6(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IENDIS_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_IENDIS_CH6_MASK)
10601 
10602 #define GTM_gtm_cls3_TIO3_IENDIS_CH7_MASK        (0x80U)
10603 #define GTM_gtm_cls3_TIO3_IENDIS_CH7_SHIFT       (7U)
10604 #define GTM_gtm_cls3_TIO3_IENDIS_CH7_WIDTH       (1U)
10605 #define GTM_gtm_cls3_TIO3_IENDIS_CH7(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IENDIS_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_IENDIS_CH7_MASK)
10606 /*! @} */
10607 
10608 /*! @name TIO3_IINVERT - TIO[i] toggle signal invert register */
10609 /*! @{ */
10610 
10611 #define GTM_gtm_cls3_TIO3_IINVERT_CH0_MASK       (0x1U)
10612 #define GTM_gtm_cls3_TIO3_IINVERT_CH0_SHIFT      (0U)
10613 #define GTM_gtm_cls3_TIO3_IINVERT_CH0_WIDTH      (1U)
10614 #define GTM_gtm_cls3_TIO3_IINVERT_CH0(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINVERT_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_IINVERT_CH0_MASK)
10615 
10616 #define GTM_gtm_cls3_TIO3_IINVERT_CH1_MASK       (0x2U)
10617 #define GTM_gtm_cls3_TIO3_IINVERT_CH1_SHIFT      (1U)
10618 #define GTM_gtm_cls3_TIO3_IINVERT_CH1_WIDTH      (1U)
10619 #define GTM_gtm_cls3_TIO3_IINVERT_CH1(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINVERT_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_IINVERT_CH1_MASK)
10620 
10621 #define GTM_gtm_cls3_TIO3_IINVERT_CH2_MASK       (0x4U)
10622 #define GTM_gtm_cls3_TIO3_IINVERT_CH2_SHIFT      (2U)
10623 #define GTM_gtm_cls3_TIO3_IINVERT_CH2_WIDTH      (1U)
10624 #define GTM_gtm_cls3_TIO3_IINVERT_CH2(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINVERT_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_IINVERT_CH2_MASK)
10625 
10626 #define GTM_gtm_cls3_TIO3_IINVERT_CH3_MASK       (0x8U)
10627 #define GTM_gtm_cls3_TIO3_IINVERT_CH3_SHIFT      (3U)
10628 #define GTM_gtm_cls3_TIO3_IINVERT_CH3_WIDTH      (1U)
10629 #define GTM_gtm_cls3_TIO3_IINVERT_CH3(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINVERT_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_IINVERT_CH3_MASK)
10630 
10631 #define GTM_gtm_cls3_TIO3_IINVERT_CH4_MASK       (0x10U)
10632 #define GTM_gtm_cls3_TIO3_IINVERT_CH4_SHIFT      (4U)
10633 #define GTM_gtm_cls3_TIO3_IINVERT_CH4_WIDTH      (1U)
10634 #define GTM_gtm_cls3_TIO3_IINVERT_CH4(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINVERT_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_IINVERT_CH4_MASK)
10635 
10636 #define GTM_gtm_cls3_TIO3_IINVERT_CH5_MASK       (0x20U)
10637 #define GTM_gtm_cls3_TIO3_IINVERT_CH5_SHIFT      (5U)
10638 #define GTM_gtm_cls3_TIO3_IINVERT_CH5_WIDTH      (1U)
10639 #define GTM_gtm_cls3_TIO3_IINVERT_CH5(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINVERT_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_IINVERT_CH5_MASK)
10640 
10641 #define GTM_gtm_cls3_TIO3_IINVERT_CH6_MASK       (0x40U)
10642 #define GTM_gtm_cls3_TIO3_IINVERT_CH6_SHIFT      (6U)
10643 #define GTM_gtm_cls3_TIO3_IINVERT_CH6_WIDTH      (1U)
10644 #define GTM_gtm_cls3_TIO3_IINVERT_CH6(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINVERT_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_IINVERT_CH6_MASK)
10645 
10646 #define GTM_gtm_cls3_TIO3_IINVERT_CH7_MASK       (0x80U)
10647 #define GTM_gtm_cls3_TIO3_IINVERT_CH7_SHIFT      (7U)
10648 #define GTM_gtm_cls3_TIO3_IINVERT_CH7_WIDTH      (1U)
10649 #define GTM_gtm_cls3_TIO3_IINVERT_CH7(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINVERT_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_IINVERT_CH7_MASK)
10650 /*! @} */
10651 
10652 /*! @name TIO3_IINPUT_MODE - TIO[i] enable input mode register */
10653 /*! @{ */
10654 
10655 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH0_MASK   (0x1U)
10656 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH0_SHIFT  (0U)
10657 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH0_WIDTH  (1U)
10658 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH0(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINPUT_MODE_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_IINPUT_MODE_CH0_MASK)
10659 
10660 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH1_MASK   (0x2U)
10661 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH1_SHIFT  (1U)
10662 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH1_WIDTH  (1U)
10663 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH1(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINPUT_MODE_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_IINPUT_MODE_CH1_MASK)
10664 
10665 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH2_MASK   (0x4U)
10666 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH2_SHIFT  (2U)
10667 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH2_WIDTH  (1U)
10668 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH2(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINPUT_MODE_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_IINPUT_MODE_CH2_MASK)
10669 
10670 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH3_MASK   (0x8U)
10671 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH3_SHIFT  (3U)
10672 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH3_WIDTH  (1U)
10673 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH3(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINPUT_MODE_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_IINPUT_MODE_CH3_MASK)
10674 
10675 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH4_MASK   (0x10U)
10676 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH4_SHIFT  (4U)
10677 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH4_WIDTH  (1U)
10678 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH4(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINPUT_MODE_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_IINPUT_MODE_CH4_MASK)
10679 
10680 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH5_MASK   (0x20U)
10681 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH5_SHIFT  (5U)
10682 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH5_WIDTH  (1U)
10683 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH5(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINPUT_MODE_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_IINPUT_MODE_CH5_MASK)
10684 
10685 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH6_MASK   (0x40U)
10686 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH6_SHIFT  (6U)
10687 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH6_WIDTH  (1U)
10688 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH6(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINPUT_MODE_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_IINPUT_MODE_CH6_MASK)
10689 
10690 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH7_MASK   (0x80U)
10691 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH7_SHIFT  (7U)
10692 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH7_WIDTH  (1U)
10693 #define GTM_gtm_cls3_TIO3_IINPUT_MODE_CH7(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_IINPUT_MODE_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_IINPUT_MODE_CH7_MASK)
10694 /*! @} */
10695 
10696 /*! @name TIO3_ICYCLIC_MODE - TIO[i] enable cyclic mode register */
10697 /*! @{ */
10698 
10699 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH0_MASK  (0x1U)
10700 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH0_SHIFT (0U)
10701 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH0_WIDTH (1U)
10702 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH0_MASK)
10703 
10704 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH1_MASK  (0x2U)
10705 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH1_SHIFT (1U)
10706 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH1_WIDTH (1U)
10707 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH1_MASK)
10708 
10709 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH2_MASK  (0x4U)
10710 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH2_SHIFT (2U)
10711 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH2_WIDTH (1U)
10712 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH2_MASK)
10713 
10714 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH3_MASK  (0x8U)
10715 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH3_SHIFT (3U)
10716 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH3_WIDTH (1U)
10717 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH3_MASK)
10718 
10719 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH4_MASK  (0x10U)
10720 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH4_SHIFT (4U)
10721 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH4_WIDTH (1U)
10722 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH4_MASK)
10723 
10724 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH5_MASK  (0x20U)
10725 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH5_SHIFT (5U)
10726 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH5_WIDTH (1U)
10727 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH5_MASK)
10728 
10729 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH6_MASK  (0x40U)
10730 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH6_SHIFT (6U)
10731 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH6_WIDTH (1U)
10732 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH6_MASK)
10733 
10734 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH7_MASK  (0x80U)
10735 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH7_SHIFT (7U)
10736 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH7_WIDTH (1U)
10737 #define GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_ICYCLIC_MODE_CH7_MASK)
10738 /*! @} */
10739 
10740 /*! @name TIO3_FUPD - TIO[i] force update register */
10741 /*! @{ */
10742 
10743 #define GTM_gtm_cls3_TIO3_FUPD_CH0_MASK          (0x1U)
10744 #define GTM_gtm_cls3_TIO3_FUPD_CH0_SHIFT         (0U)
10745 #define GTM_gtm_cls3_TIO3_FUPD_CH0_WIDTH         (1U)
10746 #define GTM_gtm_cls3_TIO3_FUPD_CH0(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_FUPD_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_FUPD_CH0_MASK)
10747 
10748 #define GTM_gtm_cls3_TIO3_FUPD_CH1_MASK          (0x2U)
10749 #define GTM_gtm_cls3_TIO3_FUPD_CH1_SHIFT         (1U)
10750 #define GTM_gtm_cls3_TIO3_FUPD_CH1_WIDTH         (1U)
10751 #define GTM_gtm_cls3_TIO3_FUPD_CH1(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_FUPD_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_FUPD_CH1_MASK)
10752 
10753 #define GTM_gtm_cls3_TIO3_FUPD_CH2_MASK          (0x4U)
10754 #define GTM_gtm_cls3_TIO3_FUPD_CH2_SHIFT         (2U)
10755 #define GTM_gtm_cls3_TIO3_FUPD_CH2_WIDTH         (1U)
10756 #define GTM_gtm_cls3_TIO3_FUPD_CH2(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_FUPD_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_FUPD_CH2_MASK)
10757 
10758 #define GTM_gtm_cls3_TIO3_FUPD_CH3_MASK          (0x8U)
10759 #define GTM_gtm_cls3_TIO3_FUPD_CH3_SHIFT         (3U)
10760 #define GTM_gtm_cls3_TIO3_FUPD_CH3_WIDTH         (1U)
10761 #define GTM_gtm_cls3_TIO3_FUPD_CH3(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_FUPD_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_FUPD_CH3_MASK)
10762 
10763 #define GTM_gtm_cls3_TIO3_FUPD_CH4_MASK          (0x10U)
10764 #define GTM_gtm_cls3_TIO3_FUPD_CH4_SHIFT         (4U)
10765 #define GTM_gtm_cls3_TIO3_FUPD_CH4_WIDTH         (1U)
10766 #define GTM_gtm_cls3_TIO3_FUPD_CH4(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_FUPD_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_FUPD_CH4_MASK)
10767 
10768 #define GTM_gtm_cls3_TIO3_FUPD_CH5_MASK          (0x20U)
10769 #define GTM_gtm_cls3_TIO3_FUPD_CH5_SHIFT         (5U)
10770 #define GTM_gtm_cls3_TIO3_FUPD_CH5_WIDTH         (1U)
10771 #define GTM_gtm_cls3_TIO3_FUPD_CH5(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_FUPD_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_FUPD_CH5_MASK)
10772 
10773 #define GTM_gtm_cls3_TIO3_FUPD_CH6_MASK          (0x40U)
10774 #define GTM_gtm_cls3_TIO3_FUPD_CH6_SHIFT         (6U)
10775 #define GTM_gtm_cls3_TIO3_FUPD_CH6_WIDTH         (1U)
10776 #define GTM_gtm_cls3_TIO3_FUPD_CH6(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_FUPD_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_FUPD_CH6_MASK)
10777 
10778 #define GTM_gtm_cls3_TIO3_FUPD_CH7_MASK          (0x80U)
10779 #define GTM_gtm_cls3_TIO3_FUPD_CH7_SHIFT         (7U)
10780 #define GTM_gtm_cls3_TIO3_FUPD_CH7_WIDTH         (1U)
10781 #define GTM_gtm_cls3_TIO3_FUPD_CH7(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_FUPD_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_FUPD_CH7_MASK)
10782 /*! @} */
10783 
10784 /*! @name TIO3_HW_CONF - TIO[i] configuration register */
10785 /*! @{ */
10786 
10787 #define GTM_gtm_cls3_TIO3_HW_CONF_NTIO_CH8_MASK  (0x3U)
10788 #define GTM_gtm_cls3_TIO3_HW_CONF_NTIO_CH8_SHIFT (0U)
10789 #define GTM_gtm_cls3_TIO3_HW_CONF_NTIO_CH8_WIDTH (2U)
10790 #define GTM_gtm_cls3_TIO3_HW_CONF_NTIO_CH8(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_HW_CONF_NTIO_CH8_SHIFT)) & GTM_gtm_cls3_TIO3_HW_CONF_NTIO_CH8_MASK)
10791 
10792 #define GTM_gtm_cls3_TIO3_HW_CONF_TIO_PLUS_MASK  (0x10U)
10793 #define GTM_gtm_cls3_TIO3_HW_CONF_TIO_PLUS_SHIFT (4U)
10794 #define GTM_gtm_cls3_TIO3_HW_CONF_TIO_PLUS_WIDTH (1U)
10795 #define GTM_gtm_cls3_TIO3_HW_CONF_TIO_PLUS(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_HW_CONF_TIO_PLUS_SHIFT)) & GTM_gtm_cls3_TIO3_HW_CONF_TIO_PLUS_MASK)
10796 /*! @} */
10797 
10798 /*! @name TIO3_RSEL_CTRL1 - TIO[i] resource selection control register 1 */
10799 /*! @{ */
10800 
10801 #define GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN6_0_MASK (0x1000000U)
10802 #define GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN6_0_SHIFT (24U)
10803 #define GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN6_0_WIDTH (1U)
10804 #define GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN6_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN6_0_SHIFT)) & GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN6_0_MASK)
10805 
10806 #define GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN7_0_MASK (0x10000000U)
10807 #define GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN7_0_SHIFT (28U)
10808 #define GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN7_0_WIDTH (1U)
10809 #define GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN7_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN7_0_SHIFT)) & GTM_gtm_cls3_TIO3_RSEL_CTRL1_SEL_CLKEN7_0_MASK)
10810 /*! @} */
10811 
10812 /*! @name TIO3_RSEL_CTRL2 - TIO[i] resource selection control register 2 */
10813 /*! @{ */
10814 
10815 #define GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB1_0_MASK (0x10U)
10816 #define GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB1_0_SHIFT (4U)
10817 #define GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB1_0_WIDTH (1U)
10818 #define GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB1_0_SHIFT)) & GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB1_0_MASK)
10819 
10820 #define GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB2_0_MASK (0x100U)
10821 #define GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB2_0_SHIFT (8U)
10822 #define GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB2_0_WIDTH (1U)
10823 #define GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB2_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB2_0_SHIFT)) & GTM_gtm_cls3_TIO3_RSEL_CTRL2_SEL_TB2_0_MASK)
10824 /*! @} */
10825 
10826 /*! @name TIO3_PL_SWRST - TIO[i] software reset for TIO Plus functionality */
10827 /*! @{ */
10828 
10829 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH0_MASK      (0x1U)
10830 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH0_SHIFT     (0U)
10831 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH0_WIDTH     (1U)
10832 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH0(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PL_SWRST_CH0_SHIFT)) & GTM_gtm_cls3_TIO3_PL_SWRST_CH0_MASK)
10833 
10834 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH1_MASK      (0x2U)
10835 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH1_SHIFT     (1U)
10836 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH1_WIDTH     (1U)
10837 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PL_SWRST_CH1_SHIFT)) & GTM_gtm_cls3_TIO3_PL_SWRST_CH1_MASK)
10838 
10839 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH2_MASK      (0x4U)
10840 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH2_SHIFT     (2U)
10841 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH2_WIDTH     (1U)
10842 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH2(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PL_SWRST_CH2_SHIFT)) & GTM_gtm_cls3_TIO3_PL_SWRST_CH2_MASK)
10843 
10844 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH3_MASK      (0x8U)
10845 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH3_SHIFT     (3U)
10846 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH3_WIDTH     (1U)
10847 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH3(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PL_SWRST_CH3_SHIFT)) & GTM_gtm_cls3_TIO3_PL_SWRST_CH3_MASK)
10848 
10849 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH4_MASK      (0x10U)
10850 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH4_SHIFT     (4U)
10851 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH4_WIDTH     (1U)
10852 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH4(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PL_SWRST_CH4_SHIFT)) & GTM_gtm_cls3_TIO3_PL_SWRST_CH4_MASK)
10853 
10854 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH5_MASK      (0x20U)
10855 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH5_SHIFT     (5U)
10856 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH5_WIDTH     (1U)
10857 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH5(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PL_SWRST_CH5_SHIFT)) & GTM_gtm_cls3_TIO3_PL_SWRST_CH5_MASK)
10858 
10859 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH6_MASK      (0x40U)
10860 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH6_SHIFT     (6U)
10861 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH6_WIDTH     (1U)
10862 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH6(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PL_SWRST_CH6_SHIFT)) & GTM_gtm_cls3_TIO3_PL_SWRST_CH6_MASK)
10863 
10864 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH7_MASK      (0x80U)
10865 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH7_SHIFT     (7U)
10866 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH7_WIDTH     (1U)
10867 #define GTM_gtm_cls3_TIO3_PL_SWRST_CH7(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_TIO3_PL_SWRST_CH7_SHIFT)) & GTM_gtm_cls3_TIO3_PL_SWRST_CH7_MASK)
10868 /*! @} */
10869 
10870 /*! @name CCM3_ARP0_CTRL - CCM[i] Address Range Protector [a] Control Register */
10871 /*! @{ */
10872 
10873 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_ADDR_MASK    (0xFFFFU)
10874 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_ADDR_SHIFT   (0U)
10875 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_ADDR_WIDTH   (16U)
10876 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_CTRL_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_CTRL_ADDR_MASK)
10877 
10878 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_SIZE_MASK    (0xF0000U)
10879 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_SIZE_SHIFT   (16U)
10880 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_SIZE_WIDTH   (4U)
10881 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_CTRL_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_CTRL_SIZE_MASK)
10882 
10883 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_DIS_PROT_MASK (0x1000000U)
10884 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_DIS_PROT_SHIFT (24U)
10885 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_DIS_PROT_WIDTH (1U)
10886 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_DIS_PROT(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_CTRL_DIS_PROT_MASK)
10887 
10888 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_WPROT_AEI_MASK (0x80000000U)
10889 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_WPROT_AEI_SHIFT (31U)
10890 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_WPROT_AEI_WIDTH (1U)
10891 #define GTM_gtm_cls3_CCM3_ARP0_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_CTRL_WPROT_AEI_MASK)
10892 /*! @} */
10893 
10894 /*! @name CCM3_ARP0_PROT - CCM[i] Address Range Protector [a] Protection Register */
10895 /*! @{ */
10896 
10897 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT0_MASK  (0x1U)
10898 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT0_SHIFT (0U)
10899 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT0_WIDTH (1U)
10900 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT0_MASK)
10901 
10902 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT1_MASK  (0x2U)
10903 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT1_SHIFT (1U)
10904 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT1_WIDTH (1U)
10905 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT1_MASK)
10906 
10907 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT2_MASK  (0x4U)
10908 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT2_SHIFT (2U)
10909 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT2_WIDTH (1U)
10910 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT2_MASK)
10911 
10912 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT3_MASK  (0x8U)
10913 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT3_SHIFT (3U)
10914 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT3_WIDTH (1U)
10915 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT3_MASK)
10916 
10917 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT4_MASK  (0x10U)
10918 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT4_SHIFT (4U)
10919 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT4_WIDTH (1U)
10920 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT4_MASK)
10921 
10922 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT5_MASK  (0x20U)
10923 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT5_SHIFT (5U)
10924 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT5_WIDTH (1U)
10925 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT5_MASK)
10926 
10927 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT6_MASK  (0x40U)
10928 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT6_SHIFT (6U)
10929 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT6_WIDTH (1U)
10930 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT6_MASK)
10931 
10932 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT7_MASK  (0x80U)
10933 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT7_SHIFT (7U)
10934 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT7_WIDTH (1U)
10935 #define GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_CCM3_ARP0_PROT_WPROT7_MASK)
10936 /*! @} */
10937 
10938 /*! @name CCM3_ARP1_CTRL - CCM[i] Address Range Protector [a] Control Register */
10939 /*! @{ */
10940 
10941 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_ADDR_MASK    (0xFFFFU)
10942 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_ADDR_SHIFT   (0U)
10943 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_ADDR_WIDTH   (16U)
10944 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_CTRL_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_CTRL_ADDR_MASK)
10945 
10946 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_SIZE_MASK    (0xF0000U)
10947 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_SIZE_SHIFT   (16U)
10948 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_SIZE_WIDTH   (4U)
10949 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_CTRL_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_CTRL_SIZE_MASK)
10950 
10951 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_DIS_PROT_MASK (0x1000000U)
10952 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_DIS_PROT_SHIFT (24U)
10953 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_DIS_PROT_WIDTH (1U)
10954 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_DIS_PROT(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_CTRL_DIS_PROT_MASK)
10955 
10956 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_WPROT_AEI_MASK (0x80000000U)
10957 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_WPROT_AEI_SHIFT (31U)
10958 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_WPROT_AEI_WIDTH (1U)
10959 #define GTM_gtm_cls3_CCM3_ARP1_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_CTRL_WPROT_AEI_MASK)
10960 /*! @} */
10961 
10962 /*! @name CCM3_ARP1_PROT - CCM[i] Address Range Protector [a] Protection Register */
10963 /*! @{ */
10964 
10965 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT0_MASK  (0x1U)
10966 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT0_SHIFT (0U)
10967 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT0_WIDTH (1U)
10968 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT0_MASK)
10969 
10970 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT1_MASK  (0x2U)
10971 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT1_SHIFT (1U)
10972 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT1_WIDTH (1U)
10973 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT1_MASK)
10974 
10975 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT2_MASK  (0x4U)
10976 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT2_SHIFT (2U)
10977 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT2_WIDTH (1U)
10978 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT2_MASK)
10979 
10980 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT3_MASK  (0x8U)
10981 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT3_SHIFT (3U)
10982 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT3_WIDTH (1U)
10983 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT3_MASK)
10984 
10985 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT4_MASK  (0x10U)
10986 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT4_SHIFT (4U)
10987 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT4_WIDTH (1U)
10988 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT4_MASK)
10989 
10990 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT5_MASK  (0x20U)
10991 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT5_SHIFT (5U)
10992 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT5_WIDTH (1U)
10993 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT5_MASK)
10994 
10995 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT6_MASK  (0x40U)
10996 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT6_SHIFT (6U)
10997 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT6_WIDTH (1U)
10998 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT6_MASK)
10999 
11000 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT7_MASK  (0x80U)
11001 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT7_SHIFT (7U)
11002 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT7_WIDTH (1U)
11003 #define GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_CCM3_ARP1_PROT_WPROT7_MASK)
11004 /*! @} */
11005 
11006 /*! @name CCM3_ARP2_CTRL - CCM[i] Address Range Protector [a] Control Register */
11007 /*! @{ */
11008 
11009 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_ADDR_MASK    (0xFFFFU)
11010 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_ADDR_SHIFT   (0U)
11011 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_ADDR_WIDTH   (16U)
11012 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_CTRL_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_CTRL_ADDR_MASK)
11013 
11014 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_SIZE_MASK    (0xF0000U)
11015 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_SIZE_SHIFT   (16U)
11016 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_SIZE_WIDTH   (4U)
11017 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_CTRL_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_CTRL_SIZE_MASK)
11018 
11019 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_DIS_PROT_MASK (0x1000000U)
11020 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_DIS_PROT_SHIFT (24U)
11021 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_DIS_PROT_WIDTH (1U)
11022 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_DIS_PROT(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_CTRL_DIS_PROT_MASK)
11023 
11024 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_WPROT_AEI_MASK (0x80000000U)
11025 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_WPROT_AEI_SHIFT (31U)
11026 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_WPROT_AEI_WIDTH (1U)
11027 #define GTM_gtm_cls3_CCM3_ARP2_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_CTRL_WPROT_AEI_MASK)
11028 /*! @} */
11029 
11030 /*! @name CCM3_ARP2_PROT - CCM[i] Address Range Protector [a] Protection Register */
11031 /*! @{ */
11032 
11033 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT0_MASK  (0x1U)
11034 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT0_SHIFT (0U)
11035 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT0_WIDTH (1U)
11036 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT0_MASK)
11037 
11038 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT1_MASK  (0x2U)
11039 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT1_SHIFT (1U)
11040 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT1_WIDTH (1U)
11041 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT1_MASK)
11042 
11043 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT2_MASK  (0x4U)
11044 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT2_SHIFT (2U)
11045 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT2_WIDTH (1U)
11046 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT2_MASK)
11047 
11048 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT3_MASK  (0x8U)
11049 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT3_SHIFT (3U)
11050 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT3_WIDTH (1U)
11051 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT3_MASK)
11052 
11053 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT4_MASK  (0x10U)
11054 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT4_SHIFT (4U)
11055 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT4_WIDTH (1U)
11056 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT4_MASK)
11057 
11058 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT5_MASK  (0x20U)
11059 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT5_SHIFT (5U)
11060 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT5_WIDTH (1U)
11061 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT5_MASK)
11062 
11063 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT6_MASK  (0x40U)
11064 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT6_SHIFT (6U)
11065 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT6_WIDTH (1U)
11066 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT6_MASK)
11067 
11068 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT7_MASK  (0x80U)
11069 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT7_SHIFT (7U)
11070 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT7_WIDTH (1U)
11071 #define GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_CCM3_ARP2_PROT_WPROT7_MASK)
11072 /*! @} */
11073 
11074 /*! @name CCM3_ARP3_CTRL - CCM[i] Address Range Protector [a] Control Register */
11075 /*! @{ */
11076 
11077 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_ADDR_MASK    (0xFFFFU)
11078 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_ADDR_SHIFT   (0U)
11079 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_ADDR_WIDTH   (16U)
11080 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_CTRL_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_CTRL_ADDR_MASK)
11081 
11082 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_SIZE_MASK    (0xF0000U)
11083 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_SIZE_SHIFT   (16U)
11084 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_SIZE_WIDTH   (4U)
11085 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_CTRL_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_CTRL_SIZE_MASK)
11086 
11087 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_DIS_PROT_MASK (0x1000000U)
11088 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_DIS_PROT_SHIFT (24U)
11089 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_DIS_PROT_WIDTH (1U)
11090 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_DIS_PROT(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_CTRL_DIS_PROT_MASK)
11091 
11092 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_WPROT_AEI_MASK (0x80000000U)
11093 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_WPROT_AEI_SHIFT (31U)
11094 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_WPROT_AEI_WIDTH (1U)
11095 #define GTM_gtm_cls3_CCM3_ARP3_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_CTRL_WPROT_AEI_MASK)
11096 /*! @} */
11097 
11098 /*! @name CCM3_ARP3_PROT - CCM[i] Address Range Protector [a] Protection Register */
11099 /*! @{ */
11100 
11101 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT0_MASK  (0x1U)
11102 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT0_SHIFT (0U)
11103 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT0_WIDTH (1U)
11104 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT0_MASK)
11105 
11106 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT1_MASK  (0x2U)
11107 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT1_SHIFT (1U)
11108 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT1_WIDTH (1U)
11109 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT1_MASK)
11110 
11111 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT2_MASK  (0x4U)
11112 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT2_SHIFT (2U)
11113 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT2_WIDTH (1U)
11114 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT2_MASK)
11115 
11116 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT3_MASK  (0x8U)
11117 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT3_SHIFT (3U)
11118 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT3_WIDTH (1U)
11119 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT3_MASK)
11120 
11121 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT4_MASK  (0x10U)
11122 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT4_SHIFT (4U)
11123 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT4_WIDTH (1U)
11124 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT4_MASK)
11125 
11126 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT5_MASK  (0x20U)
11127 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT5_SHIFT (5U)
11128 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT5_WIDTH (1U)
11129 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT5_MASK)
11130 
11131 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT6_MASK  (0x40U)
11132 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT6_SHIFT (6U)
11133 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT6_WIDTH (1U)
11134 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT6_MASK)
11135 
11136 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT7_MASK  (0x80U)
11137 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT7_SHIFT (7U)
11138 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT7_WIDTH (1U)
11139 #define GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_CCM3_ARP3_PROT_WPROT7_MASK)
11140 /*! @} */
11141 
11142 /*! @name CCM3_ARP4_CTRL - CCM[i] Address Range Protector [a] Control Register */
11143 /*! @{ */
11144 
11145 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_ADDR_MASK    (0xFFFFU)
11146 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_ADDR_SHIFT   (0U)
11147 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_ADDR_WIDTH   (16U)
11148 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_CTRL_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_CTRL_ADDR_MASK)
11149 
11150 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_SIZE_MASK    (0xF0000U)
11151 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_SIZE_SHIFT   (16U)
11152 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_SIZE_WIDTH   (4U)
11153 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_CTRL_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_CTRL_SIZE_MASK)
11154 
11155 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_DIS_PROT_MASK (0x1000000U)
11156 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_DIS_PROT_SHIFT (24U)
11157 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_DIS_PROT_WIDTH (1U)
11158 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_DIS_PROT(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_CTRL_DIS_PROT_MASK)
11159 
11160 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_WPROT_AEI_MASK (0x80000000U)
11161 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_WPROT_AEI_SHIFT (31U)
11162 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_WPROT_AEI_WIDTH (1U)
11163 #define GTM_gtm_cls3_CCM3_ARP4_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_CTRL_WPROT_AEI_MASK)
11164 /*! @} */
11165 
11166 /*! @name CCM3_ARP4_PROT - CCM[i] Address Range Protector [a] Protection Register */
11167 /*! @{ */
11168 
11169 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT0_MASK  (0x1U)
11170 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT0_SHIFT (0U)
11171 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT0_WIDTH (1U)
11172 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT0_MASK)
11173 
11174 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT1_MASK  (0x2U)
11175 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT1_SHIFT (1U)
11176 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT1_WIDTH (1U)
11177 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT1_MASK)
11178 
11179 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT2_MASK  (0x4U)
11180 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT2_SHIFT (2U)
11181 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT2_WIDTH (1U)
11182 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT2_MASK)
11183 
11184 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT3_MASK  (0x8U)
11185 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT3_SHIFT (3U)
11186 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT3_WIDTH (1U)
11187 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT3_MASK)
11188 
11189 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT4_MASK  (0x10U)
11190 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT4_SHIFT (4U)
11191 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT4_WIDTH (1U)
11192 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT4_MASK)
11193 
11194 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT5_MASK  (0x20U)
11195 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT5_SHIFT (5U)
11196 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT5_WIDTH (1U)
11197 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT5_MASK)
11198 
11199 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT6_MASK  (0x40U)
11200 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT6_SHIFT (6U)
11201 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT6_WIDTH (1U)
11202 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT6_MASK)
11203 
11204 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT7_MASK  (0x80U)
11205 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT7_SHIFT (7U)
11206 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT7_WIDTH (1U)
11207 #define GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_CCM3_ARP4_PROT_WPROT7_MASK)
11208 /*! @} */
11209 
11210 /*! @name CCM3_ARP5_CTRL - CCM[i] Address Range Protector [a] Control Register */
11211 /*! @{ */
11212 
11213 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_ADDR_MASK    (0xFFFFU)
11214 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_ADDR_SHIFT   (0U)
11215 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_ADDR_WIDTH   (16U)
11216 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_CTRL_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_CTRL_ADDR_MASK)
11217 
11218 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_SIZE_MASK    (0xF0000U)
11219 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_SIZE_SHIFT   (16U)
11220 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_SIZE_WIDTH   (4U)
11221 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_CTRL_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_CTRL_SIZE_MASK)
11222 
11223 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_DIS_PROT_MASK (0x1000000U)
11224 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_DIS_PROT_SHIFT (24U)
11225 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_DIS_PROT_WIDTH (1U)
11226 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_DIS_PROT(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_CTRL_DIS_PROT_MASK)
11227 
11228 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_WPROT_AEI_MASK (0x80000000U)
11229 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_WPROT_AEI_SHIFT (31U)
11230 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_WPROT_AEI_WIDTH (1U)
11231 #define GTM_gtm_cls3_CCM3_ARP5_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_CTRL_WPROT_AEI_MASK)
11232 /*! @} */
11233 
11234 /*! @name CCM3_ARP5_PROT - CCM[i] Address Range Protector [a] Protection Register */
11235 /*! @{ */
11236 
11237 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT0_MASK  (0x1U)
11238 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT0_SHIFT (0U)
11239 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT0_WIDTH (1U)
11240 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT0_MASK)
11241 
11242 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT1_MASK  (0x2U)
11243 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT1_SHIFT (1U)
11244 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT1_WIDTH (1U)
11245 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT1_MASK)
11246 
11247 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT2_MASK  (0x4U)
11248 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT2_SHIFT (2U)
11249 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT2_WIDTH (1U)
11250 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT2_MASK)
11251 
11252 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT3_MASK  (0x8U)
11253 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT3_SHIFT (3U)
11254 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT3_WIDTH (1U)
11255 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT3_MASK)
11256 
11257 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT4_MASK  (0x10U)
11258 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT4_SHIFT (4U)
11259 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT4_WIDTH (1U)
11260 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT4_MASK)
11261 
11262 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT5_MASK  (0x20U)
11263 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT5_SHIFT (5U)
11264 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT5_WIDTH (1U)
11265 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT5_MASK)
11266 
11267 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT6_MASK  (0x40U)
11268 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT6_SHIFT (6U)
11269 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT6_WIDTH (1U)
11270 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT6_MASK)
11271 
11272 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT7_MASK  (0x80U)
11273 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT7_SHIFT (7U)
11274 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT7_WIDTH (1U)
11275 #define GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_CCM3_ARP5_PROT_WPROT7_MASK)
11276 /*! @} */
11277 
11278 /*! @name CCM3_ARP6_CTRL - CCM[i] Address Range Protector [a] Control Register */
11279 /*! @{ */
11280 
11281 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_ADDR_MASK    (0xFFFFU)
11282 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_ADDR_SHIFT   (0U)
11283 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_ADDR_WIDTH   (16U)
11284 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_CTRL_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_CTRL_ADDR_MASK)
11285 
11286 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_SIZE_MASK    (0xF0000U)
11287 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_SIZE_SHIFT   (16U)
11288 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_SIZE_WIDTH   (4U)
11289 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_CTRL_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_CTRL_SIZE_MASK)
11290 
11291 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_DIS_PROT_MASK (0x1000000U)
11292 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_DIS_PROT_SHIFT (24U)
11293 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_DIS_PROT_WIDTH (1U)
11294 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_DIS_PROT(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_CTRL_DIS_PROT_MASK)
11295 
11296 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_WPROT_AEI_MASK (0x80000000U)
11297 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_WPROT_AEI_SHIFT (31U)
11298 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_WPROT_AEI_WIDTH (1U)
11299 #define GTM_gtm_cls3_CCM3_ARP6_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_CTRL_WPROT_AEI_MASK)
11300 /*! @} */
11301 
11302 /*! @name CCM3_ARP6_PROT - CCM[i] Address Range Protector [a] Protection Register */
11303 /*! @{ */
11304 
11305 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT0_MASK  (0x1U)
11306 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT0_SHIFT (0U)
11307 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT0_WIDTH (1U)
11308 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT0_MASK)
11309 
11310 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT1_MASK  (0x2U)
11311 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT1_SHIFT (1U)
11312 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT1_WIDTH (1U)
11313 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT1_MASK)
11314 
11315 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT2_MASK  (0x4U)
11316 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT2_SHIFT (2U)
11317 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT2_WIDTH (1U)
11318 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT2_MASK)
11319 
11320 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT3_MASK  (0x8U)
11321 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT3_SHIFT (3U)
11322 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT3_WIDTH (1U)
11323 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT3_MASK)
11324 
11325 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT4_MASK  (0x10U)
11326 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT4_SHIFT (4U)
11327 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT4_WIDTH (1U)
11328 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT4_MASK)
11329 
11330 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT5_MASK  (0x20U)
11331 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT5_SHIFT (5U)
11332 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT5_WIDTH (1U)
11333 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT5_MASK)
11334 
11335 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT6_MASK  (0x40U)
11336 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT6_SHIFT (6U)
11337 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT6_WIDTH (1U)
11338 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT6_MASK)
11339 
11340 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT7_MASK  (0x80U)
11341 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT7_SHIFT (7U)
11342 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT7_WIDTH (1U)
11343 #define GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_CCM3_ARP6_PROT_WPROT7_MASK)
11344 /*! @} */
11345 
11346 /*! @name CCM3_ARP7_CTRL - CCM[i] Address Range Protector [a] Control Register */
11347 /*! @{ */
11348 
11349 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_ADDR_MASK    (0xFFFFU)
11350 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_ADDR_SHIFT   (0U)
11351 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_ADDR_WIDTH   (16U)
11352 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_CTRL_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_CTRL_ADDR_MASK)
11353 
11354 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_SIZE_MASK    (0xF0000U)
11355 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_SIZE_SHIFT   (16U)
11356 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_SIZE_WIDTH   (4U)
11357 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_CTRL_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_CTRL_SIZE_MASK)
11358 
11359 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_DIS_PROT_MASK (0x1000000U)
11360 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_DIS_PROT_SHIFT (24U)
11361 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_DIS_PROT_WIDTH (1U)
11362 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_DIS_PROT(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_CTRL_DIS_PROT_MASK)
11363 
11364 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_WPROT_AEI_MASK (0x80000000U)
11365 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_WPROT_AEI_SHIFT (31U)
11366 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_WPROT_AEI_WIDTH (1U)
11367 #define GTM_gtm_cls3_CCM3_ARP7_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_CTRL_WPROT_AEI_MASK)
11368 /*! @} */
11369 
11370 /*! @name CCM3_ARP7_PROT - CCM[i] Address Range Protector [a] Protection Register */
11371 /*! @{ */
11372 
11373 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT0_MASK  (0x1U)
11374 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT0_SHIFT (0U)
11375 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT0_WIDTH (1U)
11376 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT0_MASK)
11377 
11378 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT1_MASK  (0x2U)
11379 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT1_SHIFT (1U)
11380 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT1_WIDTH (1U)
11381 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT1_MASK)
11382 
11383 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT2_MASK  (0x4U)
11384 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT2_SHIFT (2U)
11385 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT2_WIDTH (1U)
11386 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT2_MASK)
11387 
11388 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT3_MASK  (0x8U)
11389 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT3_SHIFT (3U)
11390 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT3_WIDTH (1U)
11391 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT3_MASK)
11392 
11393 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT4_MASK  (0x10U)
11394 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT4_SHIFT (4U)
11395 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT4_WIDTH (1U)
11396 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT4_MASK)
11397 
11398 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT5_MASK  (0x20U)
11399 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT5_SHIFT (5U)
11400 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT5_WIDTH (1U)
11401 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT5_MASK)
11402 
11403 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT6_MASK  (0x40U)
11404 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT6_SHIFT (6U)
11405 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT6_WIDTH (1U)
11406 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT6_MASK)
11407 
11408 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT7_MASK  (0x80U)
11409 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT7_SHIFT (7U)
11410 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT7_WIDTH (1U)
11411 #define GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_CCM3_ARP7_PROT_WPROT7_MASK)
11412 /*! @} */
11413 
11414 /*! @name CCM3_ARP8_CTRL - CCM[i] Address Range Protector [a] Control Register */
11415 /*! @{ */
11416 
11417 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_ADDR_MASK    (0xFFFFU)
11418 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_ADDR_SHIFT   (0U)
11419 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_ADDR_WIDTH   (16U)
11420 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_CTRL_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_CTRL_ADDR_MASK)
11421 
11422 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_SIZE_MASK    (0xF0000U)
11423 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_SIZE_SHIFT   (16U)
11424 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_SIZE_WIDTH   (4U)
11425 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_CTRL_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_CTRL_SIZE_MASK)
11426 
11427 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_DIS_PROT_MASK (0x1000000U)
11428 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_DIS_PROT_SHIFT (24U)
11429 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_DIS_PROT_WIDTH (1U)
11430 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_DIS_PROT(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_CTRL_DIS_PROT_MASK)
11431 
11432 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_WPROT_AEI_MASK (0x80000000U)
11433 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_WPROT_AEI_SHIFT (31U)
11434 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_WPROT_AEI_WIDTH (1U)
11435 #define GTM_gtm_cls3_CCM3_ARP8_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_CTRL_WPROT_AEI_MASK)
11436 /*! @} */
11437 
11438 /*! @name CCM3_ARP8_PROT - CCM[i] Address Range Protector [a] Protection Register */
11439 /*! @{ */
11440 
11441 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT0_MASK  (0x1U)
11442 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT0_SHIFT (0U)
11443 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT0_WIDTH (1U)
11444 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT0_MASK)
11445 
11446 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT1_MASK  (0x2U)
11447 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT1_SHIFT (1U)
11448 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT1_WIDTH (1U)
11449 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT1_MASK)
11450 
11451 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT2_MASK  (0x4U)
11452 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT2_SHIFT (2U)
11453 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT2_WIDTH (1U)
11454 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT2_MASK)
11455 
11456 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT3_MASK  (0x8U)
11457 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT3_SHIFT (3U)
11458 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT3_WIDTH (1U)
11459 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT3_MASK)
11460 
11461 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT4_MASK  (0x10U)
11462 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT4_SHIFT (4U)
11463 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT4_WIDTH (1U)
11464 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT4_MASK)
11465 
11466 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT5_MASK  (0x20U)
11467 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT5_SHIFT (5U)
11468 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT5_WIDTH (1U)
11469 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT5_MASK)
11470 
11471 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT6_MASK  (0x40U)
11472 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT6_SHIFT (6U)
11473 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT6_WIDTH (1U)
11474 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT6_MASK)
11475 
11476 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT7_MASK  (0x80U)
11477 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT7_SHIFT (7U)
11478 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT7_WIDTH (1U)
11479 #define GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_CCM3_ARP8_PROT_WPROT7_MASK)
11480 /*! @} */
11481 
11482 /*! @name CCM3_ARP9_CTRL - CCM[i] Address Range Protector [a] Control Register */
11483 /*! @{ */
11484 
11485 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_ADDR_MASK    (0xFFFFU)
11486 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_ADDR_SHIFT   (0U)
11487 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_ADDR_WIDTH   (16U)
11488 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_ADDR(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_CTRL_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_CTRL_ADDR_MASK)
11489 
11490 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_SIZE_MASK    (0xF0000U)
11491 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_SIZE_SHIFT   (16U)
11492 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_SIZE_WIDTH   (4U)
11493 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_SIZE(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_CTRL_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_CTRL_SIZE_MASK)
11494 
11495 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_DIS_PROT_MASK (0x1000000U)
11496 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_DIS_PROT_SHIFT (24U)
11497 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_DIS_PROT_WIDTH (1U)
11498 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_DIS_PROT(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_CTRL_DIS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_CTRL_DIS_PROT_MASK)
11499 
11500 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_WPROT_AEI_MASK (0x80000000U)
11501 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_WPROT_AEI_SHIFT (31U)
11502 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_WPROT_AEI_WIDTH (1U)
11503 #define GTM_gtm_cls3_CCM3_ARP9_CTRL_WPROT_AEI(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_CTRL_WPROT_AEI_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_CTRL_WPROT_AEI_MASK)
11504 /*! @} */
11505 
11506 /*! @name CCM3_ARP9_PROT - CCM[i] Address Range Protector [a] Protection Register */
11507 /*! @{ */
11508 
11509 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT0_MASK  (0x1U)
11510 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT0_SHIFT (0U)
11511 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT0_WIDTH (1U)
11512 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT0_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT0_MASK)
11513 
11514 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT1_MASK  (0x2U)
11515 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT1_SHIFT (1U)
11516 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT1_WIDTH (1U)
11517 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT1_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT1_MASK)
11518 
11519 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT2_MASK  (0x4U)
11520 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT2_SHIFT (2U)
11521 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT2_WIDTH (1U)
11522 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT2_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT2_MASK)
11523 
11524 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT3_MASK  (0x8U)
11525 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT3_SHIFT (3U)
11526 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT3_WIDTH (1U)
11527 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT3_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT3_MASK)
11528 
11529 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT4_MASK  (0x10U)
11530 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT4_SHIFT (4U)
11531 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT4_WIDTH (1U)
11532 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT4(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT4_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT4_MASK)
11533 
11534 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT5_MASK  (0x20U)
11535 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT5_SHIFT (5U)
11536 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT5_WIDTH (1U)
11537 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT5(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT5_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT5_MASK)
11538 
11539 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT6_MASK  (0x40U)
11540 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT6_SHIFT (6U)
11541 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT6_WIDTH (1U)
11542 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT6(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT6_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT6_MASK)
11543 
11544 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT7_MASK  (0x80U)
11545 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT7_SHIFT (7U)
11546 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT7_WIDTH (1U)
11547 #define GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT7(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT7_SHIFT)) & GTM_gtm_cls3_CCM3_ARP9_PROT_WPROT7_MASK)
11548 /*! @} */
11549 
11550 /*! @name CCM3_TIO_G0_OUT - CCM[i] TIO Group 0,1 Output Register */
11551 /*! @{ */
11552 
11553 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT0_MASK (0x1U)
11554 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT0_SHIFT (0U)
11555 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT0_WIDTH (1U)
11556 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT0_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT0_MASK)
11557 
11558 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT1_MASK (0x2U)
11559 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT1_SHIFT (1U)
11560 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT1_WIDTH (1U)
11561 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT1_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT1_MASK)
11562 
11563 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT2_MASK (0x4U)
11564 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT2_SHIFT (2U)
11565 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT2_WIDTH (1U)
11566 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT2_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT2_MASK)
11567 
11568 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT3_MASK (0x8U)
11569 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT3_SHIFT (3U)
11570 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT3_WIDTH (1U)
11571 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT3_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT3_MASK)
11572 
11573 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT4_MASK (0x10U)
11574 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT4_SHIFT (4U)
11575 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT4_WIDTH (1U)
11576 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT4_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT4_MASK)
11577 
11578 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT5_MASK (0x20U)
11579 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT5_SHIFT (5U)
11580 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT5_WIDTH (1U)
11581 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT5_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT5_MASK)
11582 
11583 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT6_MASK (0x40U)
11584 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT6_SHIFT (6U)
11585 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT6_WIDTH (1U)
11586 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT6_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT6_MASK)
11587 
11588 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT7_MASK (0x80U)
11589 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT7_SHIFT (7U)
11590 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT7_WIDTH (1U)
11591 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT7_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT7_MASK)
11592 
11593 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N0_MASK (0x10000U)
11594 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N0_SHIFT (16U)
11595 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N0_WIDTH (1U)
11596 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N0_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N0_MASK)
11597 
11598 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N1_MASK (0x20000U)
11599 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N1_SHIFT (17U)
11600 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N1_WIDTH (1U)
11601 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N1_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N1_MASK)
11602 
11603 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N2_MASK (0x40000U)
11604 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N2_SHIFT (18U)
11605 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N2_WIDTH (1U)
11606 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N2_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N2_MASK)
11607 
11608 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N3_MASK (0x80000U)
11609 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N3_SHIFT (19U)
11610 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N3_WIDTH (1U)
11611 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N3_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N3_MASK)
11612 
11613 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N4_MASK (0x100000U)
11614 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N4_SHIFT (20U)
11615 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N4_WIDTH (1U)
11616 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N4_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N4_MASK)
11617 
11618 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N5_MASK (0x200000U)
11619 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N5_SHIFT (21U)
11620 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N5_WIDTH (1U)
11621 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N5_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N5_MASK)
11622 
11623 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N6_MASK (0x400000U)
11624 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N6_SHIFT (22U)
11625 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N6_WIDTH (1U)
11626 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N6_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N6_MASK)
11627 
11628 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N7_MASK (0x800000U)
11629 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N7_SHIFT (23U)
11630 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N7_WIDTH (1U)
11631 #define GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N7_SHIFT)) & GTM_gtm_cls3_CCM3_TIO_G0_OUT_TIO_G0_OUT_N7_MASK)
11632 /*! @} */
11633 
11634 /*! @name CCM3_HW_CONF2 - CCM[i] 2. Hardware Configuration Register */
11635 /*! @{ */
11636 
11637 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_ID_WIDTH_MASK (0x1FU)
11638 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_ID_WIDTH_SHIFT (0U)
11639 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_ID_WIDTH_WIDTH (5U)
11640 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_ID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_ID_WIDTH_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_ID_WIDTH_MASK)
11641 
11642 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_PRIV_ACC_MASK (0x20U)
11643 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_PRIV_ACC_SHIFT (5U)
11644 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_PRIV_ACC_WIDTH (1U)
11645 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_PRIV_ACC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_PRIV_ACC_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_PRIV_ACC_MASK)
11646 
11647 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_SEC_ACC_MASK (0x40U)
11648 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_SEC_ACC_SHIFT (6U)
11649 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_SEC_ACC_WIDTH (1U)
11650 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_SEC_ACC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_SEC_ACC_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_SEC_ACC_MASK)
11651 
11652 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_POSTED_WRITE_MASK (0x80U)
11653 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_POSTED_WRITE_SHIFT (7U)
11654 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_POSTED_WRITE_WIDTH (1U)
11655 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_POSTED_WRITE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_POSTED_WRITE_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_POSTED_WRITE_MASK)
11656 
11657 #define GTM_gtm_cls3_CCM3_HW_CONF2_TIO_OUT_RST_MASK (0x200U)
11658 #define GTM_gtm_cls3_CCM3_HW_CONF2_TIO_OUT_RST_SHIFT (9U)
11659 #define GTM_gtm_cls3_CCM3_HW_CONF2_TIO_OUT_RST_WIDTH (1U)
11660 #define GTM_gtm_cls3_CCM3_HW_CONF2_TIO_OUT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF2_TIO_OUT_RST_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF2_TIO_OUT_RST_MASK)
11661 
11662 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIS_DATA_SIZE_MASK (0x10000U)
11663 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIS_DATA_SIZE_SHIFT (16U)
11664 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIS_DATA_SIZE_WIDTH (1U)
11665 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIS_DATA_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF2_AXIS_DATA_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF2_AXIS_DATA_SIZE_MASK)
11666 
11667 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_DATA_SIZE_MASK (0x40000U)
11668 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_DATA_SIZE_SHIFT (18U)
11669 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_DATA_SIZE_WIDTH (1U)
11670 #define GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_DATA_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_DATA_SIZE_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF2_AXIM_DATA_SIZE_MASK)
11671 /*! @} */
11672 
11673 /*! @name CCM3_AEIM_STA - CCM[i] MCS Bus Master Status Register */
11674 /*! @{ */
11675 
11676 #define GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_ADDR_MASK (0xFFFFU)
11677 #define GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_ADDR_SHIFT (0U)
11678 #define GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_ADDR_WIDTH (16U)
11679 #define GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_ADDR_SHIFT)) & GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_ADDR_MASK)
11680 
11681 #define GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_STA_MASK (0x3000000U)
11682 #define GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_STA_SHIFT (24U)
11683 #define GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_STA_WIDTH (2U)
11684 #define GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_STA(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_STA_SHIFT)) & GTM_gtm_cls3_CCM3_AEIM_STA_AEIM_XPT_STA_MASK)
11685 /*! @} */
11686 
11687 /*! @name CCM3_HW_CONF - CCM[i] Hardware Configuration Register */
11688 /*! @{ */
11689 
11690 #define GTM_gtm_cls3_CCM3_HW_CONF_GRSTEN_MASK    (0x1U)
11691 #define GTM_gtm_cls3_CCM3_HW_CONF_GRSTEN_SHIFT   (0U)
11692 #define GTM_gtm_cls3_CCM3_HW_CONF_GRSTEN_WIDTH   (1U)
11693 #define GTM_gtm_cls3_CCM3_HW_CONF_GRSTEN(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_GRSTEN_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_GRSTEN_MASK)
11694 
11695 #define GTM_gtm_cls3_CCM3_HW_CONF_BRIDGE_MODE_RST_MASK (0x2U)
11696 #define GTM_gtm_cls3_CCM3_HW_CONF_BRIDGE_MODE_RST_SHIFT (1U)
11697 #define GTM_gtm_cls3_CCM3_HW_CONF_BRIDGE_MODE_RST_WIDTH (1U)
11698 #define GTM_gtm_cls3_CCM3_HW_CONF_BRIDGE_MODE_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_BRIDGE_MODE_RST_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_BRIDGE_MODE_RST_MASK)
11699 
11700 #define GTM_gtm_cls3_CCM3_HW_CONF_SYNC_INPUT_REG_MASK (0x4U)
11701 #define GTM_gtm_cls3_CCM3_HW_CONF_SYNC_INPUT_REG_SHIFT (2U)
11702 #define GTM_gtm_cls3_CCM3_HW_CONF_SYNC_INPUT_REG_WIDTH (1U)
11703 #define GTM_gtm_cls3_CCM3_HW_CONF_SYNC_INPUT_REG(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_SYNC_INPUT_REG_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_SYNC_INPUT_REG_MASK)
11704 
11705 #define GTM_gtm_cls3_CCM3_HW_CONF_CFG_CLOCK_RATE_MASK (0x8U)
11706 #define GTM_gtm_cls3_CCM3_HW_CONF_CFG_CLOCK_RATE_SHIFT (3U)
11707 #define GTM_gtm_cls3_CCM3_HW_CONF_CFG_CLOCK_RATE_WIDTH (1U)
11708 #define GTM_gtm_cls3_CCM3_HW_CONF_CFG_CLOCK_RATE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_CFG_CLOCK_RATE_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_CFG_CLOCK_RATE_MASK)
11709 
11710 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_OUT_RST_MASK (0x10U)
11711 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_OUT_RST_SHIFT (4U)
11712 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_OUT_RST_WIDTH (1U)
11713 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_OUT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_ATOM_OUT_RST_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_ATOM_OUT_RST_MASK)
11714 
11715 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_CHAIN_MASK (0xE0U)
11716 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_CHAIN_SHIFT (5U)
11717 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_CHAIN_WIDTH (3U)
11718 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_CHAIN_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_CHAIN_MASK)
11719 
11720 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_OUT_RST_MASK (0x100U)
11721 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_OUT_RST_SHIFT (8U)
11722 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_OUT_RST_WIDTH (1U)
11723 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_OUT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_TOM_OUT_RST_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_TOM_OUT_RST_MASK)
11724 
11725 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_CHAIN_MASK (0xE00U)
11726 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_CHAIN_SHIFT (9U)
11727 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_CHAIN_WIDTH (3U)
11728 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_CHAIN_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_CHAIN_MASK)
11729 
11730 #define GTM_gtm_cls3_CCM3_HW_CONF_RAM_INIT_RST_MASK (0x1000U)
11731 #define GTM_gtm_cls3_CCM3_HW_CONF_RAM_INIT_RST_SHIFT (12U)
11732 #define GTM_gtm_cls3_CCM3_HW_CONF_RAM_INIT_RST_WIDTH (1U)
11733 #define GTM_gtm_cls3_CCM3_HW_CONF_RAM_INIT_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_RAM_INIT_RST_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_RAM_INIT_RST_MASK)
11734 
11735 #define GTM_gtm_cls3_CCM3_HW_CONF_ERM_MASK       (0x2000U)
11736 #define GTM_gtm_cls3_CCM3_HW_CONF_ERM_SHIFT      (13U)
11737 #define GTM_gtm_cls3_CCM3_HW_CONF_ERM_WIDTH      (1U)
11738 #define GTM_gtm_cls3_CCM3_HW_CONF_ERM(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_ERM_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_ERM_MASK)
11739 
11740 #define GTM_gtm_cls3_CCM3_HW_CONF_RESET_ACTIVE_MASK (0x8000U)
11741 #define GTM_gtm_cls3_CCM3_HW_CONF_RESET_ACTIVE_SHIFT (15U)
11742 #define GTM_gtm_cls3_CCM3_HW_CONF_RESET_ACTIVE_WIDTH (1U)
11743 #define GTM_gtm_cls3_CCM3_HW_CONF_RESET_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_RESET_ACTIVE_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_RESET_ACTIVE_MASK)
11744 
11745 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_LEVEL_MASK (0x10000U)
11746 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_LEVEL_SHIFT (16U)
11747 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_LEVEL_WIDTH (1U)
11748 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_LEVEL_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_LEVEL_MASK)
11749 
11750 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_MASK (0x20000U)
11751 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_SHIFT (17U)
11752 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_WIDTH (1U)
11753 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_MASK)
11754 
11755 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_NOTIFY_MASK (0x40000U)
11756 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_NOTIFY_SHIFT (18U)
11757 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_NOTIFY_WIDTH (1U)
11758 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_NOTIFY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_NOTIFY_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_PULSE_NOTIFY_MASK)
11759 
11760 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_SINGLE_PULSE_MASK (0x80000U)
11761 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_SINGLE_PULSE_SHIFT (19U)
11762 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_SINGLE_PULSE_WIDTH (1U)
11763 #define GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_SINGLE_PULSE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_SINGLE_PULSE_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_IRQ_MODE_SINGLE_PULSE_MASK)
11764 
11765 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_INTCHAIN_MASK (0xF00000U)
11766 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_INTCHAIN_SHIFT (20U)
11767 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_INTCHAIN_WIDTH (4U)
11768 #define GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_INTCHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_INTCHAIN_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_ATOM_TRIG_INTCHAIN_MASK)
11769 
11770 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_INTCHAIN_MASK (0x1F000000U)
11771 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_INTCHAIN_SHIFT (24U)
11772 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_INTCHAIN_WIDTH (5U)
11773 #define GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_INTCHAIN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_INTCHAIN_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_TOM_TRIG_INTCHAIN_MASK)
11774 
11775 #define GTM_gtm_cls3_CCM3_HW_CONF_INT_CLK_EN_GEN_MASK (0x20000000U)
11776 #define GTM_gtm_cls3_CCM3_HW_CONF_INT_CLK_EN_GEN_SHIFT (29U)
11777 #define GTM_gtm_cls3_CCM3_HW_CONF_INT_CLK_EN_GEN_WIDTH (1U)
11778 #define GTM_gtm_cls3_CCM3_HW_CONF_INT_CLK_EN_GEN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_INT_CLK_EN_GEN_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_INT_CLK_EN_GEN_MASK)
11779 
11780 #define GTM_gtm_cls3_CCM3_HW_CONF_AEI_ADDR_PIPELINE_STAGE_MASK (0x40000000U)
11781 #define GTM_gtm_cls3_CCM3_HW_CONF_AEI_ADDR_PIPELINE_STAGE_SHIFT (30U)
11782 #define GTM_gtm_cls3_CCM3_HW_CONF_AEI_ADDR_PIPELINE_STAGE_WIDTH (1U)
11783 #define GTM_gtm_cls3_CCM3_HW_CONF_AEI_ADDR_PIPELINE_STAGE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_AEI_ADDR_PIPELINE_STAGE_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_AEI_ADDR_PIPELINE_STAGE_MASK)
11784 
11785 #define GTM_gtm_cls3_CCM3_HW_CONF_AEI_RDATA_PIPELINE_STAGE_MASK (0x80000000U)
11786 #define GTM_gtm_cls3_CCM3_HW_CONF_AEI_RDATA_PIPELINE_STAGE_SHIFT (31U)
11787 #define GTM_gtm_cls3_CCM3_HW_CONF_AEI_RDATA_PIPELINE_STAGE_WIDTH (1U)
11788 #define GTM_gtm_cls3_CCM3_HW_CONF_AEI_RDATA_PIPELINE_STAGE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_HW_CONF_AEI_RDATA_PIPELINE_STAGE_SHIFT)) & GTM_gtm_cls3_CCM3_HW_CONF_AEI_RDATA_PIPELINE_STAGE_MASK)
11789 /*! @} */
11790 
11791 /*! @name CCM3_ATOM_OUT - CCM[i] ATOM Output Register */
11792 /*! @{ */
11793 
11794 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT0_MASK (0x1U)
11795 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT0_SHIFT (0U)
11796 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT0_WIDTH (1U)
11797 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT0_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT0_MASK)
11798 
11799 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT1_MASK (0x2U)
11800 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT1_SHIFT (1U)
11801 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT1_WIDTH (1U)
11802 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT1_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT1_MASK)
11803 
11804 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT2_MASK (0x4U)
11805 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT2_SHIFT (2U)
11806 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT2_WIDTH (1U)
11807 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT2_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT2_MASK)
11808 
11809 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT3_MASK (0x8U)
11810 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT3_SHIFT (3U)
11811 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT3_WIDTH (1U)
11812 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT3_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT3_MASK)
11813 
11814 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT4_MASK (0x10U)
11815 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT4_SHIFT (4U)
11816 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT4_WIDTH (1U)
11817 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT4_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT4_MASK)
11818 
11819 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT5_MASK (0x20U)
11820 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT5_SHIFT (5U)
11821 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT5_WIDTH (1U)
11822 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT5_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT5_MASK)
11823 
11824 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT6_MASK (0x40U)
11825 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT6_SHIFT (6U)
11826 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT6_WIDTH (1U)
11827 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT6_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT6_MASK)
11828 
11829 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT7_MASK (0x80U)
11830 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT7_SHIFT (7U)
11831 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT7_WIDTH (1U)
11832 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT7_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT7_MASK)
11833 
11834 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N0_MASK (0x100U)
11835 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N0_SHIFT (8U)
11836 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N0_WIDTH (1U)
11837 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N0_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N0_MASK)
11838 
11839 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N1_MASK (0x200U)
11840 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N1_SHIFT (9U)
11841 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N1_WIDTH (1U)
11842 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N1_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N1_MASK)
11843 
11844 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N2_MASK (0x400U)
11845 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N2_SHIFT (10U)
11846 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N2_WIDTH (1U)
11847 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N2_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N2_MASK)
11848 
11849 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N3_MASK (0x800U)
11850 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N3_SHIFT (11U)
11851 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N3_WIDTH (1U)
11852 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N3_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N3_MASK)
11853 
11854 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N4_MASK (0x1000U)
11855 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N4_SHIFT (12U)
11856 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N4_WIDTH (1U)
11857 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N4(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N4_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N4_MASK)
11858 
11859 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N5_MASK (0x2000U)
11860 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N5_SHIFT (13U)
11861 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N5_WIDTH (1U)
11862 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N5(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N5_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N5_MASK)
11863 
11864 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N6_MASK (0x4000U)
11865 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N6_SHIFT (14U)
11866 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N6_WIDTH (1U)
11867 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N6(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N6_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N6_MASK)
11868 
11869 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N7_MASK (0x8000U)
11870 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N7_SHIFT (15U)
11871 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N7_WIDTH (1U)
11872 #define GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N7(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N7_SHIFT)) & GTM_gtm_cls3_CCM3_ATOM_OUT_ATOM_I_OUT_N7_MASK)
11873 /*! @} */
11874 
11875 /*! @name CCM3_CMU_CLK_CFG - CCM[i] CMU Clock Configuration Register */
11876 /*! @{ */
11877 
11878 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK0_SRC_MASK (0x3U)
11879 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK0_SRC_SHIFT (0U)
11880 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK0_SRC_WIDTH (2U)
11881 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK0_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK0_SRC_SHIFT)) & GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK0_SRC_MASK)
11882 
11883 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK1_SRC_MASK (0x30U)
11884 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK1_SRC_SHIFT (4U)
11885 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK1_SRC_WIDTH (2U)
11886 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK1_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK1_SRC_SHIFT)) & GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK1_SRC_MASK)
11887 
11888 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK2_SRC_MASK (0x300U)
11889 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK2_SRC_SHIFT (8U)
11890 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK2_SRC_WIDTH (2U)
11891 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK2_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK2_SRC_SHIFT)) & GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK2_SRC_MASK)
11892 
11893 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK3_SRC_MASK (0x3000U)
11894 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK3_SRC_SHIFT (12U)
11895 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK3_SRC_WIDTH (2U)
11896 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK3_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK3_SRC_SHIFT)) & GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK3_SRC_MASK)
11897 
11898 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK4_SRC_MASK (0x30000U)
11899 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK4_SRC_SHIFT (16U)
11900 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK4_SRC_WIDTH (2U)
11901 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK4_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK4_SRC_SHIFT)) & GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK4_SRC_MASK)
11902 
11903 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK5_SRC_MASK (0x300000U)
11904 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK5_SRC_SHIFT (20U)
11905 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK5_SRC_WIDTH (2U)
11906 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK5_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK5_SRC_SHIFT)) & GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK5_SRC_MASK)
11907 
11908 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK6_SRC_MASK (0x3000000U)
11909 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK6_SRC_SHIFT (24U)
11910 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK6_SRC_WIDTH (2U)
11911 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK6_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK6_SRC_SHIFT)) & GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK6_SRC_MASK)
11912 
11913 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK7_SRC_MASK (0x30000000U)
11914 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK7_SRC_SHIFT (28U)
11915 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK7_SRC_WIDTH (2U)
11916 #define GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK7_SRC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK7_SRC_SHIFT)) & GTM_gtm_cls3_CCM3_CMU_CLK_CFG_CLK7_SRC_MASK)
11917 /*! @} */
11918 
11919 /*! @name CCM3_CFG - CCM[i] Configuration Register */
11920 /*! @{ */
11921 
11922 #define GTM_gtm_cls3_CCM3_CFG_EN_ATOM_ADTM_MASK  (0x4U)
11923 #define GTM_gtm_cls3_CCM3_CFG_EN_ATOM_ADTM_SHIFT (2U)
11924 #define GTM_gtm_cls3_CCM3_CFG_EN_ATOM_ADTM_WIDTH (1U)
11925 #define GTM_gtm_cls3_CCM3_CFG_EN_ATOM_ADTM(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CFG_EN_ATOM_ADTM_SHIFT)) & GTM_gtm_cls3_CCM3_CFG_EN_ATOM_ADTM_MASK)
11926 
11927 #define GTM_gtm_cls3_CCM3_CFG_EN_MCS_MASK        (0x8U)
11928 #define GTM_gtm_cls3_CCM3_CFG_EN_MCS_SHIFT       (3U)
11929 #define GTM_gtm_cls3_CCM3_CFG_EN_MCS_WIDTH       (1U)
11930 #define GTM_gtm_cls3_CCM3_CFG_EN_MCS(x)          (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CFG_EN_MCS_SHIFT)) & GTM_gtm_cls3_CCM3_CFG_EN_MCS_MASK)
11931 
11932 #define GTM_gtm_cls3_CCM3_CFG_EN_TIO_DTM_MASK    (0x100U)
11933 #define GTM_gtm_cls3_CCM3_CFG_EN_TIO_DTM_SHIFT   (8U)
11934 #define GTM_gtm_cls3_CCM3_CFG_EN_TIO_DTM_WIDTH   (1U)
11935 #define GTM_gtm_cls3_CCM3_CFG_EN_TIO_DTM(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CFG_EN_TIO_DTM_SHIFT)) & GTM_gtm_cls3_CCM3_CFG_EN_TIO_DTM_MASK)
11936 
11937 #define GTM_gtm_cls3_CCM3_CFG_CLS_CLK_DIV_MASK   (0x30000U)
11938 #define GTM_gtm_cls3_CCM3_CFG_CLS_CLK_DIV_SHIFT  (16U)
11939 #define GTM_gtm_cls3_CCM3_CFG_CLS_CLK_DIV_WIDTH  (2U)
11940 #define GTM_gtm_cls3_CCM3_CFG_CLS_CLK_DIV(x)     (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CFG_CLS_CLK_DIV_SHIFT)) & GTM_gtm_cls3_CCM3_CFG_CLS_CLK_DIV_MASK)
11941 
11942 #define GTM_gtm_cls3_CCM3_CFG_TBU_DIR1_MASK      (0x40000000U)
11943 #define GTM_gtm_cls3_CCM3_CFG_TBU_DIR1_SHIFT     (30U)
11944 #define GTM_gtm_cls3_CCM3_CFG_TBU_DIR1_WIDTH     (1U)
11945 #define GTM_gtm_cls3_CCM3_CFG_TBU_DIR1(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CFG_TBU_DIR1_SHIFT)) & GTM_gtm_cls3_CCM3_CFG_TBU_DIR1_MASK)
11946 
11947 #define GTM_gtm_cls3_CCM3_CFG_TBU_DIR2_MASK      (0x80000000U)
11948 #define GTM_gtm_cls3_CCM3_CFG_TBU_DIR2_SHIFT     (31U)
11949 #define GTM_gtm_cls3_CCM3_CFG_TBU_DIR2_WIDTH     (1U)
11950 #define GTM_gtm_cls3_CCM3_CFG_TBU_DIR2(x)        (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_CFG_TBU_DIR2_SHIFT)) & GTM_gtm_cls3_CCM3_CFG_TBU_DIR2_MASK)
11951 /*! @} */
11952 
11953 /*! @name CCM3_PROT - CCM[i] Protection Register */
11954 /*! @{ */
11955 
11956 #define GTM_gtm_cls3_CCM3_PROT_CLS_PROT_MASK     (0x1U)
11957 #define GTM_gtm_cls3_CCM3_PROT_CLS_PROT_SHIFT    (0U)
11958 #define GTM_gtm_cls3_CCM3_PROT_CLS_PROT_WIDTH    (1U)
11959 #define GTM_gtm_cls3_CCM3_PROT_CLS_PROT(x)       (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CCM3_PROT_CLS_PROT_SHIFT)) & GTM_gtm_cls3_CCM3_PROT_CLS_PROT_MASK)
11960 /*! @} */
11961 
11962 /*! @name CDTM3_DTM4_CTRL - CDTM[i]_DTM[d] global configuration and control register */
11963 /*! @{ */
11964 
11965 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_CLK_SEL_MASK (0x3U)
11966 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_CLK_SEL_SHIFT (0U)
11967 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_CLK_SEL_WIDTH (2U)
11968 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_CLK_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL_CLK_SEL_MASK)
11969 
11970 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_DTM_SEL_MASK (0xCU)
11971 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_DTM_SEL_SHIFT (2U)
11972 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_DTM_SEL_WIDTH (2U)
11973 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_DTM_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL_DTM_SEL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL_DTM_SEL_MASK)
11974 
11975 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_UPD_MODE_MASK (0x70U)
11976 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_UPD_MODE_SHIFT (4U)
11977 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_UPD_MODE_WIDTH (3U)
11978 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_UPD_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL_UPD_MODE_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL_UPD_MODE_MASK)
11979 
11980 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_CH_SHUTOFF_EN_MASK (0x80U)
11981 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_CH_SHUTOFF_EN_SHIFT (7U)
11982 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_CH_SHUTOFF_EN_WIDTH (1U)
11983 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_CH_SHUTOFF_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL_CH_SHUTOFF_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL_CH_SHUTOFF_EN_MASK)
11984 
11985 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_SR_UPD_EN_MASK (0x100U)
11986 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_SR_UPD_EN_SHIFT (8U)
11987 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_SR_UPD_EN_WIDTH (1U)
11988 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_SR_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL_SR_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL_SR_UPD_EN_MASK)
11989 
11990 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_SHUT_OFF_RST_MASK (0x10000U)
11991 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_SHUT_OFF_RST_SHIFT (16U)
11992 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_SHUT_OFF_RST_WIDTH (1U)
11993 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL_SHUT_OFF_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL_SHUT_OFF_RST_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL_SHUT_OFF_RST_MASK)
11994 /*! @} */
11995 
11996 /*! @name CDTM3_DTM4_CH_CTRL1 - CDTM[i]_DTM[d] channel control register 1 */
11997 /*! @{ */
11998 
11999 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_0_MASK (0x1U)
12000 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_0_SHIFT (0U)
12001 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_0_WIDTH (1U)
12002 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_0_MASK)
12003 
12004 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_0_MASK (0x8U)
12005 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_0_SHIFT (3U)
12006 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_0_WIDTH (1U)
12007 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_0_MASK)
12008 
12009 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_0_MASK (0x30U)
12010 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_0_SHIFT (4U)
12011 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_0_WIDTH (2U)
12012 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_0_MASK)
12013 
12014 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_0_1_MASK (0x40U)
12015 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_0_1_SHIFT (6U)
12016 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_0_1_WIDTH (1U)
12017 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_0_1_MASK)
12018 
12019 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_1_MASK (0x100U)
12020 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_1_SHIFT (8U)
12021 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_1_WIDTH (1U)
12022 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_1_MASK)
12023 
12024 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_1_MASK (0x200U)
12025 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_1_SHIFT (9U)
12026 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_1_WIDTH (1U)
12027 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_1_MASK)
12028 
12029 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_1_MASK (0x400U)
12030 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_1_SHIFT (10U)
12031 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_1_WIDTH (1U)
12032 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_1_MASK)
12033 
12034 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_1_MASK (0x800U)
12035 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_1_SHIFT (11U)
12036 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_1_WIDTH (1U)
12037 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_1_MASK)
12038 
12039 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_1_MASK (0x3000U)
12040 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_1_SHIFT (12U)
12041 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_1_WIDTH (2U)
12042 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_1_MASK)
12043 
12044 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_2_MASK (0x10000U)
12045 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_2_SHIFT (16U)
12046 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_2_WIDTH (1U)
12047 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_2_MASK)
12048 
12049 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_2_MASK (0x20000U)
12050 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_2_SHIFT (17U)
12051 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_2_WIDTH (1U)
12052 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_2_MASK)
12053 
12054 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_2_MASK (0x40000U)
12055 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_2_SHIFT (18U)
12056 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_2_WIDTH (1U)
12057 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_2_MASK)
12058 
12059 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_2_MASK (0x80000U)
12060 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_2_SHIFT (19U)
12061 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_2_WIDTH (1U)
12062 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_2_MASK)
12063 
12064 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_2_MASK (0x300000U)
12065 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_2_SHIFT (20U)
12066 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_2_WIDTH (2U)
12067 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_2_MASK)
12068 
12069 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_2_3_MASK (0x400000U)
12070 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_2_3_SHIFT (22U)
12071 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_2_3_WIDTH (1U)
12072 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_2_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_XDT_EN_2_3_MASK)
12073 
12074 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_3_MASK (0x1000000U)
12075 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_3_SHIFT (24U)
12076 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_3_WIDTH (1U)
12077 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1SEL_3_MASK)
12078 
12079 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_3_MASK (0x2000000U)
12080 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_3_SHIFT (25U)
12081 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_3_WIDTH (1U)
12082 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_I1SEL_3_MASK)
12083 
12084 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_3_MASK (0x4000000U)
12085 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_3_SHIFT (26U)
12086 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_3_WIDTH (1U)
12087 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SH_EN_3_MASK)
12088 
12089 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_3_MASK (0x8000000U)
12090 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_3_SHIFT (27U)
12091 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_3_WIDTH (1U)
12092 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_SWAP_3_MASK)
12093 
12094 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_3_MASK (0x30000000U)
12095 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_3_SHIFT (28U)
12096 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_3_WIDTH (2U)
12097 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL1_O1F_3_MASK)
12098 /*! @} */
12099 
12100 /*! @name CDTM3_DTM4_CH_CTRL2 - CDTM[i]_DTM[d] channel control register 2 */
12101 /*! @{ */
12102 
12103 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_0_MASK (0x1U)
12104 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_0_SHIFT (0U)
12105 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_0_WIDTH (1U)
12106 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_0_MASK)
12107 
12108 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_0_MASK (0x2U)
12109 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_0_SHIFT (1U)
12110 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_0_WIDTH (1U)
12111 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_0_MASK)
12112 
12113 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_0_MASK (0x4U)
12114 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_0_SHIFT (2U)
12115 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_0_WIDTH (1U)
12116 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_0_MASK)
12117 
12118 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_0_MASK (0x8U)
12119 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_0_SHIFT (3U)
12120 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_0_WIDTH (1U)
12121 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_0_MASK)
12122 
12123 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_0_MASK (0x10U)
12124 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_0_SHIFT (4U)
12125 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_0_WIDTH (1U)
12126 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_0_MASK)
12127 
12128 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_0_MASK (0x20U)
12129 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_0_SHIFT (5U)
12130 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_0_WIDTH (1U)
12131 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_0_MASK)
12132 
12133 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_0_MASK (0x40U)
12134 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_0_SHIFT (6U)
12135 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_0_WIDTH (1U)
12136 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_0_MASK)
12137 
12138 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_0_MASK (0x80U)
12139 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_0_SHIFT (7U)
12140 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_0_WIDTH (1U)
12141 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_0_MASK)
12142 
12143 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_1_MASK (0x100U)
12144 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_1_SHIFT (8U)
12145 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_1_WIDTH (1U)
12146 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_1_MASK)
12147 
12148 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_1_MASK (0x200U)
12149 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_1_SHIFT (9U)
12150 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_1_WIDTH (1U)
12151 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_1_MASK)
12152 
12153 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_1_MASK (0x400U)
12154 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_1_SHIFT (10U)
12155 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_1_WIDTH (1U)
12156 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_1_MASK)
12157 
12158 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_1_MASK (0x800U)
12159 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_1_SHIFT (11U)
12160 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_1_WIDTH (1U)
12161 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_1_MASK)
12162 
12163 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_1_MASK (0x1000U)
12164 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_1_SHIFT (12U)
12165 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_1_WIDTH (1U)
12166 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_1_MASK)
12167 
12168 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_1_MASK (0x2000U)
12169 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_1_SHIFT (13U)
12170 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_1_WIDTH (1U)
12171 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_1_MASK)
12172 
12173 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_1_MASK (0x4000U)
12174 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_1_SHIFT (14U)
12175 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_1_WIDTH (1U)
12176 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_1_MASK)
12177 
12178 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_1_MASK (0x8000U)
12179 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_1_SHIFT (15U)
12180 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_1_WIDTH (1U)
12181 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_1_MASK)
12182 
12183 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_2_MASK (0x10000U)
12184 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_2_SHIFT (16U)
12185 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_2_WIDTH (1U)
12186 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_2_MASK)
12187 
12188 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_2_MASK (0x20000U)
12189 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_2_SHIFT (17U)
12190 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_2_WIDTH (1U)
12191 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_2_MASK)
12192 
12193 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_2_MASK (0x40000U)
12194 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_2_SHIFT (18U)
12195 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_2_WIDTH (1U)
12196 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_2_MASK)
12197 
12198 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_2_MASK (0x80000U)
12199 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_2_SHIFT (19U)
12200 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_2_WIDTH (1U)
12201 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_2_MASK)
12202 
12203 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_2_MASK (0x100000U)
12204 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_2_SHIFT (20U)
12205 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_2_WIDTH (1U)
12206 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_2_MASK)
12207 
12208 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_2_MASK (0x200000U)
12209 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_2_SHIFT (21U)
12210 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_2_WIDTH (1U)
12211 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_2_MASK)
12212 
12213 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_2_MASK (0x400000U)
12214 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_2_SHIFT (22U)
12215 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_2_WIDTH (1U)
12216 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_2_MASK)
12217 
12218 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_2_MASK (0x800000U)
12219 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_2_SHIFT (23U)
12220 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_2_WIDTH (1U)
12221 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_2_MASK)
12222 
12223 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_3_MASK (0x1000000U)
12224 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_3_SHIFT (24U)
12225 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_3_WIDTH (1U)
12226 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL0_3_MASK)
12227 
12228 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_3_MASK (0x2000000U)
12229 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_3_SHIFT (25U)
12230 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_3_WIDTH (1U)
12231 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC0_3_MASK)
12232 
12233 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_3_MASK (0x4000000U)
12234 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_3_SHIFT (26U)
12235 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_3_WIDTH (1U)
12236 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL0_3_MASK)
12237 
12238 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_3_MASK (0x8000000U)
12239 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_3_SHIFT (27U)
12240 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_3_WIDTH (1U)
12241 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT0_3_MASK)
12242 
12243 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_3_MASK (0x10000000U)
12244 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_3_SHIFT (28U)
12245 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_3_WIDTH (1U)
12246 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_POL1_3_MASK)
12247 
12248 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_3_MASK (0x20000000U)
12249 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_3_SHIFT (29U)
12250 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_3_WIDTH (1U)
12251 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_OC1_3_MASK)
12252 
12253 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_3_MASK (0x40000000U)
12254 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_3_SHIFT (30U)
12255 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_3_WIDTH (1U)
12256 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SL1_3_MASK)
12257 
12258 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_3_MASK (0x80000000U)
12259 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_3_SHIFT (31U)
12260 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_3_WIDTH (1U)
12261 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_DT1_3_MASK)
12262 /*! @} */
12263 
12264 /*! @name CDTM3_DTM4_CH_CTRL2_SR - CDTM[i] DTM[j] channel control register 2 shadow */
12265 /*! @{ */
12266 
12267 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_0_SR_MASK (0x1U)
12268 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_0_SR_SHIFT (0U)
12269 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_0_SR_WIDTH (1U)
12270 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_0_SR_MASK)
12271 
12272 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_0_SR_MASK (0x2U)
12273 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_0_SR_SHIFT (1U)
12274 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_0_SR_WIDTH (1U)
12275 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_0_SR_MASK)
12276 
12277 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_0_SR_MASK (0x4U)
12278 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_0_SR_SHIFT (2U)
12279 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_0_SR_WIDTH (1U)
12280 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_0_SR_MASK)
12281 
12282 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_0_SR_MASK (0x8U)
12283 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_0_SR_SHIFT (3U)
12284 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_0_SR_WIDTH (1U)
12285 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_0_SR_MASK)
12286 
12287 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_0_SR_MASK (0x10U)
12288 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_0_SR_SHIFT (4U)
12289 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_0_SR_WIDTH (1U)
12290 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_0_SR_MASK)
12291 
12292 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_0_SR_MASK (0x20U)
12293 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_0_SR_SHIFT (5U)
12294 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_0_SR_WIDTH (1U)
12295 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_0_SR_MASK)
12296 
12297 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_0_SR_MASK (0x40U)
12298 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_0_SR_SHIFT (6U)
12299 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_0_SR_WIDTH (1U)
12300 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_0_SR_MASK)
12301 
12302 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_0_SR_MASK (0x80U)
12303 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_0_SR_SHIFT (7U)
12304 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_0_SR_WIDTH (1U)
12305 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_0_SR_MASK)
12306 
12307 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_1_SR_MASK (0x100U)
12308 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_1_SR_SHIFT (8U)
12309 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_1_SR_WIDTH (1U)
12310 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_1_SR_MASK)
12311 
12312 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_1_SR_MASK (0x200U)
12313 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_1_SR_SHIFT (9U)
12314 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_1_SR_WIDTH (1U)
12315 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_1_SR_MASK)
12316 
12317 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_1_SR_MASK (0x400U)
12318 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_1_SR_SHIFT (10U)
12319 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_1_SR_WIDTH (1U)
12320 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_1_SR_MASK)
12321 
12322 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_1_SR_MASK (0x800U)
12323 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_1_SR_SHIFT (11U)
12324 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_1_SR_WIDTH (1U)
12325 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_1_SR_MASK)
12326 
12327 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_1_SR_MASK (0x1000U)
12328 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_1_SR_SHIFT (12U)
12329 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_1_SR_WIDTH (1U)
12330 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_1_SR_MASK)
12331 
12332 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_1_SR_MASK (0x2000U)
12333 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_1_SR_SHIFT (13U)
12334 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_1_SR_WIDTH (1U)
12335 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_1_SR_MASK)
12336 
12337 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_1_SR_MASK (0x4000U)
12338 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_1_SR_SHIFT (14U)
12339 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_1_SR_WIDTH (1U)
12340 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_1_SR_MASK)
12341 
12342 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_1_SR_MASK (0x8000U)
12343 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_1_SR_SHIFT (15U)
12344 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_1_SR_WIDTH (1U)
12345 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_1_SR_MASK)
12346 
12347 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_2_SR_MASK (0x10000U)
12348 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_2_SR_SHIFT (16U)
12349 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_2_SR_WIDTH (1U)
12350 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_2_SR_MASK)
12351 
12352 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_2_SR_MASK (0x20000U)
12353 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_2_SR_SHIFT (17U)
12354 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_2_SR_WIDTH (1U)
12355 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_2_SR_MASK)
12356 
12357 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_2_SR_MASK (0x40000U)
12358 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_2_SR_SHIFT (18U)
12359 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_2_SR_WIDTH (1U)
12360 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_2_SR_MASK)
12361 
12362 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_2_SR_MASK (0x80000U)
12363 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_2_SR_SHIFT (19U)
12364 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_2_SR_WIDTH (1U)
12365 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_2_SR_MASK)
12366 
12367 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_2_SR_MASK (0x100000U)
12368 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_2_SR_SHIFT (20U)
12369 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_2_SR_WIDTH (1U)
12370 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_2_SR_MASK)
12371 
12372 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_2_SR_MASK (0x200000U)
12373 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_2_SR_SHIFT (21U)
12374 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_2_SR_WIDTH (1U)
12375 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_2_SR_MASK)
12376 
12377 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_2_SR_MASK (0x400000U)
12378 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_2_SR_SHIFT (22U)
12379 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_2_SR_WIDTH (1U)
12380 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_2_SR_MASK)
12381 
12382 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_2_SR_MASK (0x800000U)
12383 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_2_SR_SHIFT (23U)
12384 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_2_SR_WIDTH (1U)
12385 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_2_SR_MASK)
12386 
12387 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_3_SR_MASK (0x1000000U)
12388 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_3_SR_SHIFT (24U)
12389 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_3_SR_WIDTH (1U)
12390 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL0_3_SR_MASK)
12391 
12392 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_3_SR_MASK (0x2000000U)
12393 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_3_SR_SHIFT (25U)
12394 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_3_SR_WIDTH (1U)
12395 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC0_3_SR_MASK)
12396 
12397 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_3_SR_MASK (0x4000000U)
12398 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_3_SR_SHIFT (26U)
12399 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_3_SR_WIDTH (1U)
12400 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL0_3_SR_MASK)
12401 
12402 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_3_SR_MASK (0x8000000U)
12403 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_3_SR_SHIFT (27U)
12404 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_3_SR_WIDTH (1U)
12405 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT0_3_SR_MASK)
12406 
12407 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_3_SR_MASK (0x10000000U)
12408 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_3_SR_SHIFT (28U)
12409 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_3_SR_WIDTH (1U)
12410 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_POL1_3_SR_MASK)
12411 
12412 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_3_SR_MASK (0x20000000U)
12413 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_3_SR_SHIFT (29U)
12414 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_3_SR_WIDTH (1U)
12415 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_OC1_3_SR_MASK)
12416 
12417 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_3_SR_MASK (0x40000000U)
12418 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_3_SR_SHIFT (30U)
12419 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_3_SR_WIDTH (1U)
12420 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_SL1_3_SR_MASK)
12421 
12422 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_3_SR_MASK (0x80000000U)
12423 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_3_SR_SHIFT (31U)
12424 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_3_SR_WIDTH (1U)
12425 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL2_SR_DT1_3_SR_MASK)
12426 /*! @} */
12427 
12428 /*! @name CDTM3_DTM4_PS_CTRL - CDTM[i]_DTM[d] phase shift unit configuration and control register */
12429 /*! @{ */
12430 
12431 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_RELBLK_MASK (0x3FFU)
12432 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_RELBLK_SHIFT (0U)
12433 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_RELBLK_WIDTH (10U)
12434 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_RELBLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_RELBLK_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_RELBLK_MASK)
12435 
12436 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_PSU_IN_SEL_MASK (0x10000U)
12437 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_PSU_IN_SEL_SHIFT (16U)
12438 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_PSU_IN_SEL_WIDTH (1U)
12439 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_PSU_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_PSU_IN_SEL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_PSU_IN_SEL_MASK)
12440 
12441 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_IN_POL_MASK (0x20000U)
12442 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_IN_POL_SHIFT (17U)
12443 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_IN_POL_WIDTH (1U)
12444 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_IN_POL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_IN_POL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_IN_POL_MASK)
12445 
12446 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_TIM_SEL_MASK (0x40000U)
12447 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_TIM_SEL_SHIFT (18U)
12448 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_TIM_SEL_WIDTH (1U)
12449 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_TIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_TIM_SEL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_TIM_SEL_MASK)
12450 
12451 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_SHIFT_SEL_MASK (0x300000U)
12452 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_SHIFT_SEL_SHIFT (20U)
12453 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_SHIFT_SEL_WIDTH (2U)
12454 #define GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_SHIFT_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_SHIFT_SEL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_PS_CTRL_SHIFT_SEL_MASK)
12455 /*! @} */
12456 
12457 /*! @name CDTM3_DTM4_CH_DTV - CDTM[i]_DTM[d] channel [x] dead time reload values */
12458 /*! @{ */
12459 
12460 #define GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELRISE_MASK (0x1FFFU)
12461 #define GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELRISE_SHIFT (0U)
12462 #define GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELRISE_WIDTH (13U)
12463 #define GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELRISE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELRISE_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELRISE_MASK)
12464 
12465 #define GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELFALL_MASK (0x1FFF0000U)
12466 #define GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELFALL_SHIFT (16U)
12467 #define GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELFALL_WIDTH (13U)
12468 #define GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELFALL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELFALL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_DTV_RELFALL_MASK)
12469 /*! @} */
12470 
12471 /*! @name CDTM3_DTM4_CH_SR - CDTM[i]_DTM[d] channel shadow register */
12472 /*! @{ */
12473 
12474 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_0_SR_SR_MASK (0x1U)
12475 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_0_SR_SR_SHIFT (0U)
12476 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_0_SR_SR_WIDTH (1U)
12477 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_0_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_0_SR_SR_MASK)
12478 
12479 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_0_SR_SR_MASK (0x2U)
12480 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_0_SR_SR_SHIFT (1U)
12481 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_0_SR_SR_WIDTH (1U)
12482 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_0_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_0_SR_SR_MASK)
12483 
12484 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_1_SR_SR_MASK (0x4U)
12485 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_1_SR_SR_SHIFT (2U)
12486 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_1_SR_SR_WIDTH (1U)
12487 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_1_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_1_SR_SR_MASK)
12488 
12489 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_1_SR_SR_MASK (0x8U)
12490 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_1_SR_SR_SHIFT (3U)
12491 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_1_SR_SR_WIDTH (1U)
12492 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_1_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_1_SR_SR_MASK)
12493 
12494 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_2_SR_SR_MASK (0x10U)
12495 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_2_SR_SR_SHIFT (4U)
12496 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_2_SR_SR_WIDTH (1U)
12497 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_2_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_2_SR_SR_MASK)
12498 
12499 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_2_SR_SR_MASK (0x20U)
12500 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_2_SR_SR_SHIFT (5U)
12501 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_2_SR_SR_WIDTH (1U)
12502 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_2_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_2_SR_SR_MASK)
12503 
12504 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_3_SR_SR_MASK (0x40U)
12505 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_3_SR_SR_SHIFT (6U)
12506 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_3_SR_SR_WIDTH (1U)
12507 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_3_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL0_3_SR_SR_MASK)
12508 
12509 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_3_SR_SR_MASK (0x80U)
12510 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_3_SR_SR_SHIFT (7U)
12511 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_3_SR_SR_WIDTH (1U)
12512 #define GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_3_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_SR_SL1_3_SR_SR_MASK)
12513 /*! @} */
12514 
12515 /*! @name CDTM3_DTM4_CH_CTRL3 - CDTM[i]_DTM[d] channel control register 3 */
12516 /*! @{ */
12517 
12518 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII0_MASK (0x1U)
12519 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII0_SHIFT (0U)
12520 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII0_WIDTH (1U)
12521 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII0_MASK)
12522 
12523 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS0_MASK (0x2U)
12524 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS0_SHIFT (1U)
12525 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS0_WIDTH (1U)
12526 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS0_MASK)
12527 
12528 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_0_MASK (0x4U)
12529 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_0_SHIFT (2U)
12530 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_0_WIDTH (1U)
12531 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_0_MASK)
12532 
12533 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_0_MASK (0x8U)
12534 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_0_SHIFT (3U)
12535 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_0_WIDTH (1U)
12536 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_0_MASK)
12537 
12538 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII1_MASK (0x100U)
12539 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII1_SHIFT (8U)
12540 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII1_WIDTH (1U)
12541 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII1_MASK)
12542 
12543 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS1_MASK (0x200U)
12544 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS1_SHIFT (9U)
12545 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS1_WIDTH (1U)
12546 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS1_MASK)
12547 
12548 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_1_MASK (0x400U)
12549 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_1_SHIFT (10U)
12550 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_1_WIDTH (1U)
12551 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_1_MASK)
12552 
12553 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_1_MASK (0x800U)
12554 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_1_SHIFT (11U)
12555 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_1_WIDTH (1U)
12556 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_1_MASK)
12557 
12558 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII2_MASK (0x10000U)
12559 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII2_SHIFT (16U)
12560 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII2_WIDTH (1U)
12561 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII2_MASK)
12562 
12563 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS2_MASK (0x20000U)
12564 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS2_SHIFT (17U)
12565 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS2_WIDTH (1U)
12566 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS2_MASK)
12567 
12568 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_2_MASK (0x40000U)
12569 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_2_SHIFT (18U)
12570 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_2_WIDTH (1U)
12571 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_2_MASK)
12572 
12573 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_2_MASK (0x80000U)
12574 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_2_SHIFT (19U)
12575 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_2_WIDTH (1U)
12576 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_2_MASK)
12577 
12578 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII3_MASK (0x1000000U)
12579 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII3_SHIFT (24U)
12580 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII3_WIDTH (1U)
12581 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CII3_MASK)
12582 
12583 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS3_MASK (0x2000000U)
12584 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS3_SHIFT (25U)
12585 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS3_WIDTH (1U)
12586 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_CIS3_MASK)
12587 
12588 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_3_MASK (0x4000000U)
12589 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_3_SHIFT (26U)
12590 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_3_WIDTH (1U)
12591 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL0_3_MASK)
12592 
12593 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_3_MASK (0x8000000U)
12594 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_3_SHIFT (27U)
12595 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_3_WIDTH (1U)
12596 #define GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH_CTRL3_TSEL1_3_MASK)
12597 /*! @} */
12598 
12599 /*! @name CDTM3_DTM4_CTRL2 - CDTM[i]_DTM[d] global configuration and control register 2 */
12600 /*! @{ */
12601 
12602 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_0_MASK (0x7U)
12603 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_0_SHIFT (0U)
12604 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_0_WIDTH (3U)
12605 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_0_MASK)
12606 
12607 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_0_MASK (0x8U)
12608 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_0_SHIFT (3U)
12609 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_0_WIDTH (1U)
12610 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_0_MASK)
12611 
12612 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_0_MASK (0x30U)
12613 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_0_SHIFT (4U)
12614 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_0_WIDTH (2U)
12615 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_0_MASK)
12616 
12617 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_0_MASK (0x40U)
12618 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_0_SHIFT (6U)
12619 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_0_WIDTH (1U)
12620 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_0_MASK)
12621 
12622 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_0_MASK (0x80U)
12623 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_0_SHIFT (7U)
12624 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_0_WIDTH (1U)
12625 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_0_MASK)
12626 
12627 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_1_MASK (0x700U)
12628 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_1_SHIFT (8U)
12629 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_1_WIDTH (3U)
12630 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_1_MASK)
12631 
12632 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_1_MASK (0x800U)
12633 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_1_SHIFT (11U)
12634 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_1_WIDTH (1U)
12635 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_1_MASK)
12636 
12637 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_1_MASK (0x3000U)
12638 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_1_SHIFT (12U)
12639 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_1_WIDTH (2U)
12640 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_1_MASK)
12641 
12642 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_1_MASK (0x4000U)
12643 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_1_SHIFT (14U)
12644 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_1_WIDTH (1U)
12645 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_1_MASK)
12646 
12647 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_1_MASK (0x8000U)
12648 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_1_SHIFT (15U)
12649 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_1_WIDTH (1U)
12650 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_1_MASK)
12651 
12652 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_2_MASK (0x70000U)
12653 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_2_SHIFT (16U)
12654 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_2_WIDTH (3U)
12655 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_2_MASK)
12656 
12657 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_2_MASK (0x80000U)
12658 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_2_SHIFT (19U)
12659 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_2_WIDTH (1U)
12660 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_2_MASK)
12661 
12662 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_2_MASK (0x300000U)
12663 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_2_SHIFT (20U)
12664 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_2_WIDTH (2U)
12665 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_2_MASK)
12666 
12667 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_2_MASK (0x400000U)
12668 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_2_SHIFT (22U)
12669 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_2_WIDTH (1U)
12670 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_2_MASK)
12671 
12672 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_2_MASK (0x800000U)
12673 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_2_SHIFT (23U)
12674 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_2_WIDTH (1U)
12675 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_2_MASK)
12676 
12677 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_3_MASK (0x7000000U)
12678 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_3_SHIFT (24U)
12679 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_3_WIDTH (3U)
12680 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_SEL_3_MASK)
12681 
12682 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_3_MASK (0x8000000U)
12683 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_3_SHIFT (27U)
12684 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_3_WIDTH (1U)
12685 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUTOFF_POL_3_MASK)
12686 
12687 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_3_MASK (0x30000000U)
12688 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_3_SHIFT (28U)
12689 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_3_WIDTH (2U)
12690 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_UPD_MODE_3_MASK)
12691 
12692 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_3_MASK (0x40000000U)
12693 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_3_SHIFT (30U)
12694 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_3_WIDTH (1U)
12695 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_SHUT_OFF_RST_3_MASK)
12696 
12697 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_3_MASK (0x80000000U)
12698 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_3_SHIFT (31U)
12699 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_3_WIDTH (1U)
12700 #define GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CTRL2_WR_EN_3_MASK)
12701 /*! @} */
12702 
12703 /*! @name CDTM3_DTM4_CH0_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */
12704 /*! @{ */
12705 
12706 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_SR_MASK (0x1FFFU)
12707 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_SR_SHIFT (0U)
12708 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_SR_WIDTH (13U)
12709 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_SR_MASK)
12710 
12711 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U)
12712 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U)
12713 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U)
12714 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK)
12715 
12716 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U)
12717 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT (15U)
12718 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_WIDTH (1U)
12719 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELRISE_UPD_EN_MASK)
12720 
12721 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U)
12722 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_SR_SHIFT (16U)
12723 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_SR_WIDTH (13U)
12724 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_SR_MASK)
12725 
12726 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U)
12727 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U)
12728 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U)
12729 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK)
12730 
12731 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U)
12732 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT (31U)
12733 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_WIDTH (1U)
12734 #define GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH0_DTV_SR_RELFALL_UPD_EN_MASK)
12735 /*! @} */
12736 
12737 /*! @name CDTM3_DTM4_CH1_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */
12738 /*! @{ */
12739 
12740 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_SR_MASK (0x1FFFU)
12741 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_SR_SHIFT (0U)
12742 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_SR_WIDTH (13U)
12743 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_SR_MASK)
12744 
12745 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U)
12746 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U)
12747 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U)
12748 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK)
12749 
12750 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U)
12751 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT (15U)
12752 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_WIDTH (1U)
12753 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELRISE_UPD_EN_MASK)
12754 
12755 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U)
12756 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_SR_SHIFT (16U)
12757 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_SR_WIDTH (13U)
12758 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_SR_MASK)
12759 
12760 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U)
12761 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U)
12762 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U)
12763 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK)
12764 
12765 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U)
12766 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT (31U)
12767 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_WIDTH (1U)
12768 #define GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH1_DTV_SR_RELFALL_UPD_EN_MASK)
12769 /*! @} */
12770 
12771 /*! @name CDTM3_DTM4_CH2_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */
12772 /*! @{ */
12773 
12774 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_SR_MASK (0x1FFFU)
12775 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_SR_SHIFT (0U)
12776 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_SR_WIDTH (13U)
12777 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_SR_MASK)
12778 
12779 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U)
12780 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U)
12781 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U)
12782 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK)
12783 
12784 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U)
12785 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT (15U)
12786 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_WIDTH (1U)
12787 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELRISE_UPD_EN_MASK)
12788 
12789 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U)
12790 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_SR_SHIFT (16U)
12791 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_SR_WIDTH (13U)
12792 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_SR_MASK)
12793 
12794 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U)
12795 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U)
12796 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U)
12797 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK)
12798 
12799 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U)
12800 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT (31U)
12801 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_WIDTH (1U)
12802 #define GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH2_DTV_SR_RELFALL_UPD_EN_MASK)
12803 /*! @} */
12804 
12805 /*! @name CDTM3_DTM4_CH3_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */
12806 /*! @{ */
12807 
12808 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_SR_MASK (0x1FFFU)
12809 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_SR_SHIFT (0U)
12810 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_SR_WIDTH (13U)
12811 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_SR_MASK)
12812 
12813 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U)
12814 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U)
12815 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U)
12816 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK)
12817 
12818 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U)
12819 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT (15U)
12820 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_WIDTH (1U)
12821 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELRISE_UPD_EN_MASK)
12822 
12823 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U)
12824 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_SR_SHIFT (16U)
12825 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_SR_WIDTH (13U)
12826 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_SR_MASK)
12827 
12828 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U)
12829 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U)
12830 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U)
12831 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK)
12832 
12833 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U)
12834 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT (31U)
12835 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_WIDTH (1U)
12836 #define GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM4_CH3_DTV_SR_RELFALL_UPD_EN_MASK)
12837 /*! @} */
12838 
12839 /*! @name CDTM3_DTM5_CTRL - CDTM[i]_DTM[d] global configuration and control register */
12840 /*! @{ */
12841 
12842 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_CLK_SEL_MASK (0x3U)
12843 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_CLK_SEL_SHIFT (0U)
12844 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_CLK_SEL_WIDTH (2U)
12845 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_CLK_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL_CLK_SEL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL_CLK_SEL_MASK)
12846 
12847 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_DTM_SEL_MASK (0xCU)
12848 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_DTM_SEL_SHIFT (2U)
12849 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_DTM_SEL_WIDTH (2U)
12850 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_DTM_SEL(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL_DTM_SEL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL_DTM_SEL_MASK)
12851 
12852 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_UPD_MODE_MASK (0x70U)
12853 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_UPD_MODE_SHIFT (4U)
12854 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_UPD_MODE_WIDTH (3U)
12855 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_UPD_MODE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL_UPD_MODE_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL_UPD_MODE_MASK)
12856 
12857 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_CH_SHUTOFF_EN_MASK (0x80U)
12858 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_CH_SHUTOFF_EN_SHIFT (7U)
12859 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_CH_SHUTOFF_EN_WIDTH (1U)
12860 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_CH_SHUTOFF_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL_CH_SHUTOFF_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL_CH_SHUTOFF_EN_MASK)
12861 
12862 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_SR_UPD_EN_MASK (0x100U)
12863 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_SR_UPD_EN_SHIFT (8U)
12864 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_SR_UPD_EN_WIDTH (1U)
12865 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_SR_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL_SR_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL_SR_UPD_EN_MASK)
12866 
12867 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_SHUT_OFF_RST_MASK (0x10000U)
12868 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_SHUT_OFF_RST_SHIFT (16U)
12869 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_SHUT_OFF_RST_WIDTH (1U)
12870 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL_SHUT_OFF_RST(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL_SHUT_OFF_RST_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL_SHUT_OFF_RST_MASK)
12871 /*! @} */
12872 
12873 /*! @name CDTM3_DTM5_CH_CTRL1 - CDTM[i]_DTM[d] channel control register 1 */
12874 /*! @{ */
12875 
12876 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_0_MASK (0x1U)
12877 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_0_SHIFT (0U)
12878 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_0_WIDTH (1U)
12879 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_0_MASK)
12880 
12881 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_0_MASK (0x2U)
12882 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_0_SHIFT (1U)
12883 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_0_WIDTH (1U)
12884 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_0_MASK)
12885 
12886 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_0_MASK (0x8U)
12887 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_0_SHIFT (3U)
12888 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_0_WIDTH (1U)
12889 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_0_MASK)
12890 
12891 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_0_MASK (0x30U)
12892 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_0_SHIFT (4U)
12893 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_0_WIDTH (2U)
12894 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_0_MASK)
12895 
12896 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_0_1_MASK (0x40U)
12897 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_0_1_SHIFT (6U)
12898 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_0_1_WIDTH (1U)
12899 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_0_1_MASK)
12900 
12901 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_1_MASK (0x100U)
12902 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_1_SHIFT (8U)
12903 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_1_WIDTH (1U)
12904 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_1_MASK)
12905 
12906 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_1_MASK (0x200U)
12907 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_1_SHIFT (9U)
12908 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_1_WIDTH (1U)
12909 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_1_MASK)
12910 
12911 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_1_MASK (0x400U)
12912 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_1_SHIFT (10U)
12913 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_1_WIDTH (1U)
12914 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_1_MASK)
12915 
12916 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_1_MASK (0x800U)
12917 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_1_SHIFT (11U)
12918 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_1_WIDTH (1U)
12919 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_1_MASK)
12920 
12921 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_1_MASK (0x3000U)
12922 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_1_SHIFT (12U)
12923 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_1_WIDTH (2U)
12924 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_1_MASK)
12925 
12926 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_2_MASK (0x10000U)
12927 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_2_SHIFT (16U)
12928 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_2_WIDTH (1U)
12929 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_2_MASK)
12930 
12931 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_2_MASK (0x20000U)
12932 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_2_SHIFT (17U)
12933 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_2_WIDTH (1U)
12934 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_2_MASK)
12935 
12936 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_2_MASK (0x40000U)
12937 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_2_SHIFT (18U)
12938 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_2_WIDTH (1U)
12939 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_2_MASK)
12940 
12941 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_2_MASK (0x80000U)
12942 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_2_SHIFT (19U)
12943 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_2_WIDTH (1U)
12944 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_2_MASK)
12945 
12946 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_2_MASK (0x300000U)
12947 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_2_SHIFT (20U)
12948 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_2_WIDTH (2U)
12949 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_2_MASK)
12950 
12951 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_2_3_MASK (0x400000U)
12952 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_2_3_SHIFT (22U)
12953 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_2_3_WIDTH (1U)
12954 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_2_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_2_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_XDT_EN_2_3_MASK)
12955 
12956 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_3_MASK (0x1000000U)
12957 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_3_SHIFT (24U)
12958 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_3_WIDTH (1U)
12959 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1SEL_3_MASK)
12960 
12961 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_3_MASK (0x2000000U)
12962 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_3_SHIFT (25U)
12963 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_3_WIDTH (1U)
12964 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_I1SEL_3_MASK)
12965 
12966 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_3_MASK (0x4000000U)
12967 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_3_SHIFT (26U)
12968 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_3_WIDTH (1U)
12969 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SH_EN_3_MASK)
12970 
12971 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_3_MASK (0x8000000U)
12972 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_3_SHIFT (27U)
12973 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_3_WIDTH (1U)
12974 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_SWAP_3_MASK)
12975 
12976 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_3_MASK (0x30000000U)
12977 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_3_SHIFT (28U)
12978 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_3_WIDTH (2U)
12979 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL1_O1F_3_MASK)
12980 /*! @} */
12981 
12982 /*! @name CDTM3_DTM5_CH_CTRL2 - CDTM[i]_DTM[d] channel control register 2 */
12983 /*! @{ */
12984 
12985 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_0_MASK (0x1U)
12986 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_0_SHIFT (0U)
12987 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_0_WIDTH (1U)
12988 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_0_MASK)
12989 
12990 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_0_MASK (0x2U)
12991 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_0_SHIFT (1U)
12992 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_0_WIDTH (1U)
12993 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_0_MASK)
12994 
12995 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_0_MASK (0x4U)
12996 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_0_SHIFT (2U)
12997 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_0_WIDTH (1U)
12998 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_0_MASK)
12999 
13000 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_0_MASK (0x8U)
13001 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_0_SHIFT (3U)
13002 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_0_WIDTH (1U)
13003 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_0_MASK)
13004 
13005 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_0_MASK (0x10U)
13006 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_0_SHIFT (4U)
13007 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_0_WIDTH (1U)
13008 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_0_MASK)
13009 
13010 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_0_MASK (0x20U)
13011 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_0_SHIFT (5U)
13012 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_0_WIDTH (1U)
13013 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_0_MASK)
13014 
13015 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_0_MASK (0x40U)
13016 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_0_SHIFT (6U)
13017 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_0_WIDTH (1U)
13018 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_0_MASK)
13019 
13020 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_0_MASK (0x80U)
13021 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_0_SHIFT (7U)
13022 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_0_WIDTH (1U)
13023 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_0_MASK)
13024 
13025 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_1_MASK (0x100U)
13026 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_1_SHIFT (8U)
13027 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_1_WIDTH (1U)
13028 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_1_MASK)
13029 
13030 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_1_MASK (0x200U)
13031 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_1_SHIFT (9U)
13032 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_1_WIDTH (1U)
13033 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_1_MASK)
13034 
13035 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_1_MASK (0x400U)
13036 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_1_SHIFT (10U)
13037 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_1_WIDTH (1U)
13038 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_1_MASK)
13039 
13040 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_1_MASK (0x800U)
13041 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_1_SHIFT (11U)
13042 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_1_WIDTH (1U)
13043 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_1_MASK)
13044 
13045 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_1_MASK (0x1000U)
13046 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_1_SHIFT (12U)
13047 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_1_WIDTH (1U)
13048 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_1_MASK)
13049 
13050 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_1_MASK (0x2000U)
13051 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_1_SHIFT (13U)
13052 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_1_WIDTH (1U)
13053 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_1_MASK)
13054 
13055 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_1_MASK (0x4000U)
13056 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_1_SHIFT (14U)
13057 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_1_WIDTH (1U)
13058 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_1_MASK)
13059 
13060 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_1_MASK (0x8000U)
13061 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_1_SHIFT (15U)
13062 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_1_WIDTH (1U)
13063 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_1_MASK)
13064 
13065 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_2_MASK (0x10000U)
13066 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_2_SHIFT (16U)
13067 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_2_WIDTH (1U)
13068 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_2_MASK)
13069 
13070 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_2_MASK (0x20000U)
13071 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_2_SHIFT (17U)
13072 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_2_WIDTH (1U)
13073 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_2_MASK)
13074 
13075 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_2_MASK (0x40000U)
13076 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_2_SHIFT (18U)
13077 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_2_WIDTH (1U)
13078 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_2_MASK)
13079 
13080 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_2_MASK (0x80000U)
13081 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_2_SHIFT (19U)
13082 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_2_WIDTH (1U)
13083 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_2_MASK)
13084 
13085 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_2_MASK (0x100000U)
13086 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_2_SHIFT (20U)
13087 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_2_WIDTH (1U)
13088 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_2_MASK)
13089 
13090 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_2_MASK (0x200000U)
13091 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_2_SHIFT (21U)
13092 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_2_WIDTH (1U)
13093 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_2_MASK)
13094 
13095 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_2_MASK (0x400000U)
13096 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_2_SHIFT (22U)
13097 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_2_WIDTH (1U)
13098 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_2_MASK)
13099 
13100 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_2_MASK (0x800000U)
13101 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_2_SHIFT (23U)
13102 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_2_WIDTH (1U)
13103 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_2_MASK)
13104 
13105 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_3_MASK (0x1000000U)
13106 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_3_SHIFT (24U)
13107 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_3_WIDTH (1U)
13108 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL0_3_MASK)
13109 
13110 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_3_MASK (0x2000000U)
13111 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_3_SHIFT (25U)
13112 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_3_WIDTH (1U)
13113 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC0_3_MASK)
13114 
13115 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_3_MASK (0x4000000U)
13116 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_3_SHIFT (26U)
13117 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_3_WIDTH (1U)
13118 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL0_3_MASK)
13119 
13120 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_3_MASK (0x8000000U)
13121 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_3_SHIFT (27U)
13122 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_3_WIDTH (1U)
13123 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT0_3_MASK)
13124 
13125 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_3_MASK (0x10000000U)
13126 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_3_SHIFT (28U)
13127 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_3_WIDTH (1U)
13128 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_POL1_3_MASK)
13129 
13130 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_3_MASK (0x20000000U)
13131 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_3_SHIFT (29U)
13132 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_3_WIDTH (1U)
13133 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_OC1_3_MASK)
13134 
13135 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_3_MASK (0x40000000U)
13136 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_3_SHIFT (30U)
13137 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_3_WIDTH (1U)
13138 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SL1_3_MASK)
13139 
13140 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_3_MASK (0x80000000U)
13141 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_3_SHIFT (31U)
13142 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_3_WIDTH (1U)
13143 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_DT1_3_MASK)
13144 /*! @} */
13145 
13146 /*! @name CDTM3_DTM5_CH_CTRL2_SR - CDTM[i] DTM[j] channel control register 2 shadow */
13147 /*! @{ */
13148 
13149 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_0_SR_MASK (0x1U)
13150 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_0_SR_SHIFT (0U)
13151 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_0_SR_WIDTH (1U)
13152 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_0_SR_MASK)
13153 
13154 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_0_SR_MASK (0x2U)
13155 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_0_SR_SHIFT (1U)
13156 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_0_SR_WIDTH (1U)
13157 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_0_SR_MASK)
13158 
13159 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_0_SR_MASK (0x4U)
13160 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_0_SR_SHIFT (2U)
13161 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_0_SR_WIDTH (1U)
13162 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_0_SR_MASK)
13163 
13164 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_0_SR_MASK (0x8U)
13165 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_0_SR_SHIFT (3U)
13166 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_0_SR_WIDTH (1U)
13167 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_0_SR_MASK)
13168 
13169 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_0_SR_MASK (0x10U)
13170 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_0_SR_SHIFT (4U)
13171 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_0_SR_WIDTH (1U)
13172 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_0_SR_MASK)
13173 
13174 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_0_SR_MASK (0x20U)
13175 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_0_SR_SHIFT (5U)
13176 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_0_SR_WIDTH (1U)
13177 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_0_SR_MASK)
13178 
13179 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_0_SR_MASK (0x40U)
13180 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_0_SR_SHIFT (6U)
13181 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_0_SR_WIDTH (1U)
13182 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_0_SR_MASK)
13183 
13184 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_0_SR_MASK (0x80U)
13185 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_0_SR_SHIFT (7U)
13186 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_0_SR_WIDTH (1U)
13187 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_0_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_0_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_0_SR_MASK)
13188 
13189 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_1_SR_MASK (0x100U)
13190 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_1_SR_SHIFT (8U)
13191 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_1_SR_WIDTH (1U)
13192 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_1_SR_MASK)
13193 
13194 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_1_SR_MASK (0x200U)
13195 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_1_SR_SHIFT (9U)
13196 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_1_SR_WIDTH (1U)
13197 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_1_SR_MASK)
13198 
13199 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_1_SR_MASK (0x400U)
13200 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_1_SR_SHIFT (10U)
13201 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_1_SR_WIDTH (1U)
13202 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_1_SR_MASK)
13203 
13204 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_1_SR_MASK (0x800U)
13205 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_1_SR_SHIFT (11U)
13206 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_1_SR_WIDTH (1U)
13207 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_1_SR_MASK)
13208 
13209 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_1_SR_MASK (0x1000U)
13210 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_1_SR_SHIFT (12U)
13211 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_1_SR_WIDTH (1U)
13212 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_1_SR_MASK)
13213 
13214 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_1_SR_MASK (0x2000U)
13215 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_1_SR_SHIFT (13U)
13216 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_1_SR_WIDTH (1U)
13217 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_1_SR_MASK)
13218 
13219 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_1_SR_MASK (0x4000U)
13220 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_1_SR_SHIFT (14U)
13221 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_1_SR_WIDTH (1U)
13222 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_1_SR_MASK)
13223 
13224 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_1_SR_MASK (0x8000U)
13225 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_1_SR_SHIFT (15U)
13226 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_1_SR_WIDTH (1U)
13227 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_1_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_1_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_1_SR_MASK)
13228 
13229 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_2_SR_MASK (0x10000U)
13230 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_2_SR_SHIFT (16U)
13231 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_2_SR_WIDTH (1U)
13232 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_2_SR_MASK)
13233 
13234 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_2_SR_MASK (0x20000U)
13235 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_2_SR_SHIFT (17U)
13236 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_2_SR_WIDTH (1U)
13237 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_2_SR_MASK)
13238 
13239 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_2_SR_MASK (0x40000U)
13240 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_2_SR_SHIFT (18U)
13241 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_2_SR_WIDTH (1U)
13242 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_2_SR_MASK)
13243 
13244 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_2_SR_MASK (0x80000U)
13245 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_2_SR_SHIFT (19U)
13246 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_2_SR_WIDTH (1U)
13247 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_2_SR_MASK)
13248 
13249 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_2_SR_MASK (0x100000U)
13250 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_2_SR_SHIFT (20U)
13251 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_2_SR_WIDTH (1U)
13252 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_2_SR_MASK)
13253 
13254 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_2_SR_MASK (0x200000U)
13255 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_2_SR_SHIFT (21U)
13256 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_2_SR_WIDTH (1U)
13257 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_2_SR_MASK)
13258 
13259 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_2_SR_MASK (0x400000U)
13260 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_2_SR_SHIFT (22U)
13261 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_2_SR_WIDTH (1U)
13262 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_2_SR_MASK)
13263 
13264 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_2_SR_MASK (0x800000U)
13265 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_2_SR_SHIFT (23U)
13266 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_2_SR_WIDTH (1U)
13267 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_2_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_2_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_2_SR_MASK)
13268 
13269 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_3_SR_MASK (0x1000000U)
13270 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_3_SR_SHIFT (24U)
13271 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_3_SR_WIDTH (1U)
13272 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL0_3_SR_MASK)
13273 
13274 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_3_SR_MASK (0x2000000U)
13275 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_3_SR_SHIFT (25U)
13276 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_3_SR_WIDTH (1U)
13277 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC0_3_SR_MASK)
13278 
13279 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_3_SR_MASK (0x4000000U)
13280 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_3_SR_SHIFT (26U)
13281 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_3_SR_WIDTH (1U)
13282 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL0_3_SR_MASK)
13283 
13284 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_3_SR_MASK (0x8000000U)
13285 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_3_SR_SHIFT (27U)
13286 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_3_SR_WIDTH (1U)
13287 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT0_3_SR_MASK)
13288 
13289 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_3_SR_MASK (0x10000000U)
13290 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_3_SR_SHIFT (28U)
13291 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_3_SR_WIDTH (1U)
13292 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_POL1_3_SR_MASK)
13293 
13294 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_3_SR_MASK (0x20000000U)
13295 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_3_SR_SHIFT (29U)
13296 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_3_SR_WIDTH (1U)
13297 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_OC1_3_SR_MASK)
13298 
13299 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_3_SR_MASK (0x40000000U)
13300 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_3_SR_SHIFT (30U)
13301 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_3_SR_WIDTH (1U)
13302 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_SL1_3_SR_MASK)
13303 
13304 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_3_SR_MASK (0x80000000U)
13305 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_3_SR_SHIFT (31U)
13306 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_3_SR_WIDTH (1U)
13307 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_3_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_3_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL2_SR_DT1_3_SR_MASK)
13308 /*! @} */
13309 
13310 /*! @name CDTM3_DTM5_PS_CTRL - CDTM[i]_DTM[d] phase shift unit configuration and control register */
13311 /*! @{ */
13312 
13313 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_RELBLK_MASK (0x3FFU)
13314 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_RELBLK_SHIFT (0U)
13315 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_RELBLK_WIDTH (10U)
13316 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_RELBLK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_RELBLK_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_RELBLK_MASK)
13317 
13318 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_PSU_IN_SEL_MASK (0x10000U)
13319 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_PSU_IN_SEL_SHIFT (16U)
13320 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_PSU_IN_SEL_WIDTH (1U)
13321 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_PSU_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_PSU_IN_SEL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_PSU_IN_SEL_MASK)
13322 
13323 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_IN_POL_MASK (0x20000U)
13324 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_IN_POL_SHIFT (17U)
13325 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_IN_POL_WIDTH (1U)
13326 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_IN_POL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_IN_POL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_IN_POL_MASK)
13327 
13328 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_TIM_SEL_MASK (0x40000U)
13329 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_TIM_SEL_SHIFT (18U)
13330 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_TIM_SEL_WIDTH (1U)
13331 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_TIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_TIM_SEL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_TIM_SEL_MASK)
13332 
13333 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_SHIFT_SEL_MASK (0x300000U)
13334 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_SHIFT_SEL_SHIFT (20U)
13335 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_SHIFT_SEL_WIDTH (2U)
13336 #define GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_SHIFT_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_SHIFT_SEL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_PS_CTRL_SHIFT_SEL_MASK)
13337 /*! @} */
13338 
13339 /*! @name CDTM3_DTM5_CH_DTV - CDTM[i]_DTM[d] channel [x] dead time reload values */
13340 /*! @{ */
13341 
13342 #define GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELRISE_MASK (0x1FFFU)
13343 #define GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELRISE_SHIFT (0U)
13344 #define GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELRISE_WIDTH (13U)
13345 #define GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELRISE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELRISE_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELRISE_MASK)
13346 
13347 #define GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELFALL_MASK (0x1FFF0000U)
13348 #define GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELFALL_SHIFT (16U)
13349 #define GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELFALL_WIDTH (13U)
13350 #define GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELFALL(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELFALL_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_DTV_RELFALL_MASK)
13351 /*! @} */
13352 
13353 /*! @name CDTM3_DTM5_CH_SR - CDTM[i]_DTM[d] channel shadow register */
13354 /*! @{ */
13355 
13356 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_0_SR_SR_MASK (0x1U)
13357 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_0_SR_SR_SHIFT (0U)
13358 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_0_SR_SR_WIDTH (1U)
13359 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_0_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_0_SR_SR_MASK)
13360 
13361 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_0_SR_SR_MASK (0x2U)
13362 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_0_SR_SR_SHIFT (1U)
13363 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_0_SR_SR_WIDTH (1U)
13364 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_0_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_0_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_0_SR_SR_MASK)
13365 
13366 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_1_SR_SR_MASK (0x4U)
13367 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_1_SR_SR_SHIFT (2U)
13368 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_1_SR_SR_WIDTH (1U)
13369 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_1_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_1_SR_SR_MASK)
13370 
13371 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_1_SR_SR_MASK (0x8U)
13372 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_1_SR_SR_SHIFT (3U)
13373 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_1_SR_SR_WIDTH (1U)
13374 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_1_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_1_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_1_SR_SR_MASK)
13375 
13376 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_2_SR_SR_MASK (0x10U)
13377 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_2_SR_SR_SHIFT (4U)
13378 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_2_SR_SR_WIDTH (1U)
13379 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_2_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_2_SR_SR_MASK)
13380 
13381 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_2_SR_SR_MASK (0x20U)
13382 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_2_SR_SR_SHIFT (5U)
13383 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_2_SR_SR_WIDTH (1U)
13384 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_2_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_2_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_2_SR_SR_MASK)
13385 
13386 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_3_SR_SR_MASK (0x40U)
13387 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_3_SR_SR_SHIFT (6U)
13388 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_3_SR_SR_WIDTH (1U)
13389 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_3_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL0_3_SR_SR_MASK)
13390 
13391 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_3_SR_SR_MASK (0x80U)
13392 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_3_SR_SR_SHIFT (7U)
13393 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_3_SR_SR_WIDTH (1U)
13394 #define GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_3_SR_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_3_SR_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_SR_SL1_3_SR_SR_MASK)
13395 /*! @} */
13396 
13397 /*! @name CDTM3_DTM5_CH_CTRL3 - CDTM[i]_DTM[d] channel control register 3 */
13398 /*! @{ */
13399 
13400 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII0_MASK (0x1U)
13401 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII0_SHIFT (0U)
13402 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII0_WIDTH (1U)
13403 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII0_MASK)
13404 
13405 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS0_MASK (0x2U)
13406 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS0_SHIFT (1U)
13407 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS0_WIDTH (1U)
13408 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS0_MASK)
13409 
13410 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_0_MASK (0x4U)
13411 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_0_SHIFT (2U)
13412 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_0_WIDTH (1U)
13413 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_0_MASK)
13414 
13415 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_0_MASK (0x8U)
13416 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_0_SHIFT (3U)
13417 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_0_WIDTH (1U)
13418 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_0_MASK)
13419 
13420 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII1_MASK (0x100U)
13421 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII1_SHIFT (8U)
13422 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII1_WIDTH (1U)
13423 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII1_MASK)
13424 
13425 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS1_MASK (0x200U)
13426 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS1_SHIFT (9U)
13427 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS1_WIDTH (1U)
13428 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS1_MASK)
13429 
13430 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_1_MASK (0x400U)
13431 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_1_SHIFT (10U)
13432 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_1_WIDTH (1U)
13433 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_1_MASK)
13434 
13435 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_1_MASK (0x800U)
13436 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_1_SHIFT (11U)
13437 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_1_WIDTH (1U)
13438 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_1_MASK)
13439 
13440 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII2_MASK (0x10000U)
13441 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII2_SHIFT (16U)
13442 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII2_WIDTH (1U)
13443 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII2_MASK)
13444 
13445 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS2_MASK (0x20000U)
13446 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS2_SHIFT (17U)
13447 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS2_WIDTH (1U)
13448 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS2_MASK)
13449 
13450 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_2_MASK (0x40000U)
13451 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_2_SHIFT (18U)
13452 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_2_WIDTH (1U)
13453 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_2_MASK)
13454 
13455 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_2_MASK (0x80000U)
13456 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_2_SHIFT (19U)
13457 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_2_WIDTH (1U)
13458 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_2_MASK)
13459 
13460 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII3_MASK (0x1000000U)
13461 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII3_SHIFT (24U)
13462 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII3_WIDTH (1U)
13463 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CII3_MASK)
13464 
13465 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS3_MASK (0x2000000U)
13466 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS3_SHIFT (25U)
13467 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS3_WIDTH (1U)
13468 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_CIS3_MASK)
13469 
13470 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_3_MASK (0x4000000U)
13471 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_3_SHIFT (26U)
13472 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_3_WIDTH (1U)
13473 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL0_3_MASK)
13474 
13475 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_3_MASK (0x8000000U)
13476 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_3_SHIFT (27U)
13477 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_3_WIDTH (1U)
13478 #define GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH_CTRL3_TSEL1_3_MASK)
13479 /*! @} */
13480 
13481 /*! @name CDTM3_DTM5_CTRL2 - CDTM[i]_DTM[d] global configuration and control register 2 */
13482 /*! @{ */
13483 
13484 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_0_MASK (0x7U)
13485 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_0_SHIFT (0U)
13486 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_0_WIDTH (3U)
13487 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_0_MASK)
13488 
13489 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_0_MASK (0x8U)
13490 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_0_SHIFT (3U)
13491 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_0_WIDTH (1U)
13492 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_0_MASK)
13493 
13494 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_0_MASK (0x30U)
13495 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_0_SHIFT (4U)
13496 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_0_WIDTH (2U)
13497 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_0_MASK)
13498 
13499 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_0_MASK (0x40U)
13500 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_0_SHIFT (6U)
13501 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_0_WIDTH (1U)
13502 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_0_MASK)
13503 
13504 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_0_MASK (0x80U)
13505 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_0_SHIFT (7U)
13506 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_0_WIDTH (1U)
13507 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_0(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_0_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_0_MASK)
13508 
13509 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_1_MASK (0x700U)
13510 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_1_SHIFT (8U)
13511 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_1_WIDTH (3U)
13512 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_1_MASK)
13513 
13514 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_1_MASK (0x800U)
13515 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_1_SHIFT (11U)
13516 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_1_WIDTH (1U)
13517 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_1_MASK)
13518 
13519 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_1_MASK (0x3000U)
13520 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_1_SHIFT (12U)
13521 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_1_WIDTH (2U)
13522 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_1_MASK)
13523 
13524 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_1_MASK (0x4000U)
13525 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_1_SHIFT (14U)
13526 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_1_WIDTH (1U)
13527 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_1_MASK)
13528 
13529 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_1_MASK (0x8000U)
13530 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_1_SHIFT (15U)
13531 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_1_WIDTH (1U)
13532 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_1_MASK)
13533 
13534 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_2_MASK (0x70000U)
13535 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_2_SHIFT (16U)
13536 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_2_WIDTH (3U)
13537 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_2_MASK)
13538 
13539 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_2_MASK (0x80000U)
13540 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_2_SHIFT (19U)
13541 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_2_WIDTH (1U)
13542 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_2_MASK)
13543 
13544 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_2_MASK (0x300000U)
13545 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_2_SHIFT (20U)
13546 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_2_WIDTH (2U)
13547 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_2_MASK)
13548 
13549 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_2_MASK (0x400000U)
13550 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_2_SHIFT (22U)
13551 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_2_WIDTH (1U)
13552 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_2_MASK)
13553 
13554 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_2_MASK (0x800000U)
13555 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_2_SHIFT (23U)
13556 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_2_WIDTH (1U)
13557 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_2(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_2_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_2_MASK)
13558 
13559 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_3_MASK (0x7000000U)
13560 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_3_SHIFT (24U)
13561 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_3_WIDTH (3U)
13562 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_SEL_3_MASK)
13563 
13564 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_3_MASK (0x8000000U)
13565 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_3_SHIFT (27U)
13566 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_3_WIDTH (1U)
13567 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUTOFF_POL_3_MASK)
13568 
13569 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_3_MASK (0x30000000U)
13570 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_3_SHIFT (28U)
13571 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_3_WIDTH (2U)
13572 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_UPD_MODE_3_MASK)
13573 
13574 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_3_MASK (0x40000000U)
13575 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_3_SHIFT (30U)
13576 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_3_WIDTH (1U)
13577 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_SHUT_OFF_RST_3_MASK)
13578 
13579 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_3_MASK (0x80000000U)
13580 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_3_SHIFT (31U)
13581 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_3_WIDTH (1U)
13582 #define GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_3(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_3_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CTRL2_WR_EN_3_MASK)
13583 /*! @} */
13584 
13585 /*! @name CDTM3_DTM5_CH0_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */
13586 /*! @{ */
13587 
13588 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_SR_MASK (0x1FFFU)
13589 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_SR_SHIFT (0U)
13590 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_SR_WIDTH (13U)
13591 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_SR_MASK)
13592 
13593 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U)
13594 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U)
13595 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U)
13596 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_FE0RE1_MASK)
13597 
13598 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U)
13599 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT (15U)
13600 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_WIDTH (1U)
13601 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELRISE_UPD_EN_MASK)
13602 
13603 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U)
13604 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_SR_SHIFT (16U)
13605 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_SR_WIDTH (13U)
13606 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_SR_MASK)
13607 
13608 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U)
13609 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U)
13610 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U)
13611 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_FE0RE1_MASK)
13612 
13613 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U)
13614 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT (31U)
13615 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_WIDTH (1U)
13616 #define GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH0_DTV_SR_RELFALL_UPD_EN_MASK)
13617 /*! @} */
13618 
13619 /*! @name CDTM3_DTM5_CH1_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */
13620 /*! @{ */
13621 
13622 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_SR_MASK (0x1FFFU)
13623 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_SR_SHIFT (0U)
13624 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_SR_WIDTH (13U)
13625 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_SR_MASK)
13626 
13627 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U)
13628 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U)
13629 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U)
13630 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_FE0RE1_MASK)
13631 
13632 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U)
13633 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT (15U)
13634 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_WIDTH (1U)
13635 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELRISE_UPD_EN_MASK)
13636 
13637 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U)
13638 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_SR_SHIFT (16U)
13639 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_SR_WIDTH (13U)
13640 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_SR_MASK)
13641 
13642 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U)
13643 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U)
13644 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U)
13645 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_FE0RE1_MASK)
13646 
13647 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U)
13648 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT (31U)
13649 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_WIDTH (1U)
13650 #define GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH1_DTV_SR_RELFALL_UPD_EN_MASK)
13651 /*! @} */
13652 
13653 /*! @name CDTM3_DTM5_CH2_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */
13654 /*! @{ */
13655 
13656 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_SR_MASK (0x1FFFU)
13657 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_SR_SHIFT (0U)
13658 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_SR_WIDTH (13U)
13659 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_SR_MASK)
13660 
13661 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U)
13662 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U)
13663 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U)
13664 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_FE0RE1_MASK)
13665 
13666 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U)
13667 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT (15U)
13668 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_WIDTH (1U)
13669 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELRISE_UPD_EN_MASK)
13670 
13671 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U)
13672 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_SR_SHIFT (16U)
13673 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_SR_WIDTH (13U)
13674 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_SR_MASK)
13675 
13676 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U)
13677 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U)
13678 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U)
13679 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_FE0RE1_MASK)
13680 
13681 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U)
13682 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT (31U)
13683 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_WIDTH (1U)
13684 #define GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH2_DTV_SR_RELFALL_UPD_EN_MASK)
13685 /*! @} */
13686 
13687 /*! @name CDTM3_DTM5_CH3_DTV_SR - CDTM[i]_DTM[d] channel [x] dead time shadow values */
13688 /*! @{ */
13689 
13690 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_SR_MASK (0x1FFFU)
13691 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_SR_SHIFT (0U)
13692 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_SR_WIDTH (13U)
13693 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_SR_MASK)
13694 
13695 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK (0x4000U)
13696 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT (14U)
13697 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_WIDTH (1U)
13698 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_FE0RE1_MASK)
13699 
13700 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_MASK (0x8000U)
13701 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT (15U)
13702 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_WIDTH (1U)
13703 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELRISE_UPD_EN_MASK)
13704 
13705 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_SR_MASK (0x1FFF0000U)
13706 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_SR_SHIFT (16U)
13707 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_SR_WIDTH (13U)
13708 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_SR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_SR_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_SR_MASK)
13709 
13710 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK (0x40000000U)
13711 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT (30U)
13712 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_WIDTH (1U)
13713 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_FE0RE1_MASK)
13714 
13715 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_MASK (0x80000000U)
13716 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT (31U)
13717 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_WIDTH (1U)
13718 #define GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_EN(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_SHIFT)) & GTM_gtm_cls3_CDTM3_DTM5_CH3_DTV_SR_RELFALL_UPD_EN_MASK)
13719 /*! @} */
13720 
13721 /*! @name AXIM3_FREE - AXIM[i] slot allocation status. */
13722 /*! @{ */
13723 
13724 #define GTM_gtm_cls3_AXIM3_FREE_FREE0_MASK       (0x1U)
13725 #define GTM_gtm_cls3_AXIM3_FREE_FREE0_SHIFT      (0U)
13726 #define GTM_gtm_cls3_AXIM3_FREE_FREE0_WIDTH      (1U)
13727 #define GTM_gtm_cls3_AXIM3_FREE_FREE0(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_FREE_FREE0_SHIFT)) & GTM_gtm_cls3_AXIM3_FREE_FREE0_MASK)
13728 
13729 #define GTM_gtm_cls3_AXIM3_FREE_FREE1_MASK       (0x2U)
13730 #define GTM_gtm_cls3_AXIM3_FREE_FREE1_SHIFT      (1U)
13731 #define GTM_gtm_cls3_AXIM3_FREE_FREE1_WIDTH      (1U)
13732 #define GTM_gtm_cls3_AXIM3_FREE_FREE1(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_FREE_FREE1_SHIFT)) & GTM_gtm_cls3_AXIM3_FREE_FREE1_MASK)
13733 
13734 #define GTM_gtm_cls3_AXIM3_FREE_FREE2_MASK       (0x4U)
13735 #define GTM_gtm_cls3_AXIM3_FREE_FREE2_SHIFT      (2U)
13736 #define GTM_gtm_cls3_AXIM3_FREE_FREE2_WIDTH      (1U)
13737 #define GTM_gtm_cls3_AXIM3_FREE_FREE2(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_FREE_FREE2_SHIFT)) & GTM_gtm_cls3_AXIM3_FREE_FREE2_MASK)
13738 
13739 #define GTM_gtm_cls3_AXIM3_FREE_FREE3_MASK       (0x8U)
13740 #define GTM_gtm_cls3_AXIM3_FREE_FREE3_SHIFT      (3U)
13741 #define GTM_gtm_cls3_AXIM3_FREE_FREE3_WIDTH      (1U)
13742 #define GTM_gtm_cls3_AXIM3_FREE_FREE3(x)         (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_FREE_FREE3_SHIFT)) & GTM_gtm_cls3_AXIM3_FREE_FREE3_MASK)
13743 /*! @} */
13744 
13745 /*! @name AXIM3_REQUEST - AXIM[i] slot request (allocation). */
13746 /*! @{ */
13747 
13748 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT0_MASK (0x1U)
13749 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT0_SHIFT (0U)
13750 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT0_WIDTH (1U)
13751 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT0(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT0_SHIFT)) & GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT0_MASK)
13752 
13753 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT1_MASK (0x2U)
13754 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT1_SHIFT (1U)
13755 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT1_WIDTH (1U)
13756 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT1(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT1_SHIFT)) & GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT1_MASK)
13757 
13758 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT2_MASK (0x4U)
13759 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT2_SHIFT (2U)
13760 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT2_WIDTH (1U)
13761 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT2(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT2_SHIFT)) & GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT2_MASK)
13762 
13763 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT3_MASK (0x8U)
13764 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT3_SHIFT (3U)
13765 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT3_WIDTH (1U)
13766 #define GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT3(x)   (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT3_SHIFT)) & GTM_gtm_cls3_AXIM3_REQUEST_REQ1HOT3_MASK)
13767 
13768 #define GTM_gtm_cls3_AXIM3_REQUEST_REQID_MASK    (0xFF000000U)
13769 #define GTM_gtm_cls3_AXIM3_REQUEST_REQID_SHIFT   (24U)
13770 #define GTM_gtm_cls3_AXIM3_REQUEST_REQID_WIDTH   (8U)
13771 #define GTM_gtm_cls3_AXIM3_REQUEST_REQID(x)      (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_REQUEST_REQID_SHIFT)) & GTM_gtm_cls3_AXIM3_REQUEST_REQID_MASK)
13772 /*! @} */
13773 
13774 /*! @name AXIM3_RELEASE - AXIM[i] slot release (de-allocation). */
13775 /*! @{ */
13776 
13777 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ0_MASK  (0x1U)
13778 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ0_SHIFT (0U)
13779 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ0_WIDTH (1U)
13780 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ0(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_RELEASE_RELREQ0_SHIFT)) & GTM_gtm_cls3_AXIM3_RELEASE_RELREQ0_MASK)
13781 
13782 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ1_MASK  (0x2U)
13783 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ1_SHIFT (1U)
13784 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ1_WIDTH (1U)
13785 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ1(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_RELEASE_RELREQ1_SHIFT)) & GTM_gtm_cls3_AXIM3_RELEASE_RELREQ1_MASK)
13786 
13787 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ2_MASK  (0x4U)
13788 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ2_SHIFT (2U)
13789 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ2_WIDTH (1U)
13790 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ2(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_RELEASE_RELREQ2_SHIFT)) & GTM_gtm_cls3_AXIM3_RELEASE_RELREQ2_MASK)
13791 
13792 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ3_MASK  (0x8U)
13793 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ3_SHIFT (3U)
13794 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ3_WIDTH (1U)
13795 #define GTM_gtm_cls3_AXIM3_RELEASE_RELREQ3(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_RELEASE_RELREQ3_SHIFT)) & GTM_gtm_cls3_AXIM3_RELEASE_RELREQ3_MASK)
13796 /*! @} */
13797 
13798 /*! @name AXIM3_SLOT0_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */
13799 /*! @{ */
13800 
13801 #define GTM_gtm_cls3_AXIM3_SLOT0_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU)
13802 #define GTM_gtm_cls3_AXIM3_SLOT0_ADDR_LOW_AXI_ADDR_SHIFT (0U)
13803 #define GTM_gtm_cls3_AXIM3_SLOT0_ADDR_LOW_AXI_ADDR_WIDTH (32U)
13804 #define GTM_gtm_cls3_AXIM3_SLOT0_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_ADDR_LOW_AXI_ADDR_MASK)
13805 /*! @} */
13806 
13807 /*! @name AXIM3_SLOT0_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */
13808 /*! @{ */
13809 
13810 #define GTM_gtm_cls3_AXIM3_SLOT0_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU)
13811 #define GTM_gtm_cls3_AXIM3_SLOT0_DATA_LOW_AXI_DATA_LOW_SHIFT (0U)
13812 #define GTM_gtm_cls3_AXIM3_SLOT0_DATA_LOW_AXI_DATA_LOW_WIDTH (32U)
13813 #define GTM_gtm_cls3_AXIM3_SLOT0_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_DATA_LOW_AXI_DATA_LOW_MASK)
13814 /*! @} */
13815 
13816 /*! @name AXIM3_SLOT0_CFG1 - AXIM[i] slot [s] configuration 1 */
13817 /*! @{ */
13818 
13819 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_INCR_MASK  (0xFU)
13820 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_INCR_SHIFT (0U)
13821 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_INCR_WIDTH (4U)
13822 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_INCR(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_CFG1_INCR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_CFG1_INCR_MASK)
13823 
13824 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AUTO_INCR_MASK (0x10U)
13825 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AUTO_INCR_SHIFT (4U)
13826 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AUTO_INCR_WIDTH (1U)
13827 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AUTO_INCR_MASK)
13828 
13829 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_PRIO_MASK  (0x60U)
13830 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_PRIO_SHIFT (5U)
13831 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_PRIO_WIDTH (2U)
13832 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_PRIO(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_CFG1_PRIO_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_CFG1_PRIO_MASK)
13833 
13834 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_PROT_MASK (0x3800U)
13835 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_PROT_SHIFT (11U)
13836 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_PROT_WIDTH (3U)
13837 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_PROT_MASK)
13838 
13839 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_CACHE_MASK (0x3C000U)
13840 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_CACHE_SHIFT (14U)
13841 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_CACHE_WIDTH (4U)
13842 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_CACHE_MASK)
13843 
13844 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_LOCK_MASK (0xC0000U)
13845 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_LOCK_SHIFT (18U)
13846 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_LOCK_WIDTH (2U)
13847 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_LOCK_MASK)
13848 
13849 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_SIZE_MASK (0x1C00000U)
13850 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_SIZE_SHIFT (22U)
13851 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_SIZE_WIDTH (3U)
13852 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_SIZE_MASK)
13853 
13854 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_RW_MASK (0x2000000U)
13855 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_RW_SHIFT (25U)
13856 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_RW_WIDTH (1U)
13857 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_RW(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_CFG1_AXI_RW_MASK)
13858 /*! @} */
13859 
13860 /*! @name AXIM3_SLOT0_CFG2 - AXIM[i] slot[s] configuration 2 */
13861 /*! @{ */
13862 
13863 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG2_AXI_ID_MASK (0xFFFFU)
13864 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG2_AXI_ID_SHIFT (0U)
13865 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG2_AXI_ID_WIDTH (16U)
13866 #define GTM_gtm_cls3_AXIM3_SLOT0_CFG2_AXI_ID(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_CFG2_AXI_ID_MASK)
13867 /*! @} */
13868 
13869 /*! @name AXIM3_SLOT0_STATUS - AXIM[i] slot[s] status */
13870 /*! @{ */
13871 
13872 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_ALLOC_MASK (0x1U)
13873 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_ALLOC_SHIFT (0U)
13874 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_ALLOC_WIDTH (1U)
13875 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_STATUS_ALLOC_MASK)
13876 
13877 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_QUEUED_MASK (0x2U)
13878 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_QUEUED_SHIFT (1U)
13879 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_QUEUED_WIDTH (1U)
13880 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_STATUS_QUEUED_MASK)
13881 
13882 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_STARTED_MASK (0x4U)
13883 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_STARTED_SHIFT (2U)
13884 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_STARTED_WIDTH (1U)
13885 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_STATUS_STARTED_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_STATUS_STARTED_MASK)
13886 
13887 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_READY_MASK (0x8U)
13888 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_READY_SHIFT (3U)
13889 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_READY_WIDTH (1U)
13890 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_STATUS_READY_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_STATUS_READY_MASK)
13891 
13892 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_RESP_MASK (0x30U)
13893 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_RESP_SHIFT (4U)
13894 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_RESP_WIDTH (2U)
13895 #define GTM_gtm_cls3_AXIM3_SLOT0_STATUS_RESP(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT0_STATUS_RESP_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT0_STATUS_RESP_MASK)
13896 /*! @} */
13897 
13898 /*! @name AXIM3_SLOT1_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */
13899 /*! @{ */
13900 
13901 #define GTM_gtm_cls3_AXIM3_SLOT1_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU)
13902 #define GTM_gtm_cls3_AXIM3_SLOT1_ADDR_LOW_AXI_ADDR_SHIFT (0U)
13903 #define GTM_gtm_cls3_AXIM3_SLOT1_ADDR_LOW_AXI_ADDR_WIDTH (32U)
13904 #define GTM_gtm_cls3_AXIM3_SLOT1_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_ADDR_LOW_AXI_ADDR_MASK)
13905 /*! @} */
13906 
13907 /*! @name AXIM3_SLOT1_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */
13908 /*! @{ */
13909 
13910 #define GTM_gtm_cls3_AXIM3_SLOT1_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU)
13911 #define GTM_gtm_cls3_AXIM3_SLOT1_DATA_LOW_AXI_DATA_LOW_SHIFT (0U)
13912 #define GTM_gtm_cls3_AXIM3_SLOT1_DATA_LOW_AXI_DATA_LOW_WIDTH (32U)
13913 #define GTM_gtm_cls3_AXIM3_SLOT1_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_DATA_LOW_AXI_DATA_LOW_MASK)
13914 /*! @} */
13915 
13916 /*! @name AXIM3_SLOT1_CFG1 - AXIM[i] slot [s] configuration 1 */
13917 /*! @{ */
13918 
13919 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_INCR_MASK  (0xFU)
13920 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_INCR_SHIFT (0U)
13921 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_INCR_WIDTH (4U)
13922 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_INCR(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_CFG1_INCR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_CFG1_INCR_MASK)
13923 
13924 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AUTO_INCR_MASK (0x10U)
13925 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AUTO_INCR_SHIFT (4U)
13926 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AUTO_INCR_WIDTH (1U)
13927 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AUTO_INCR_MASK)
13928 
13929 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_PRIO_MASK  (0x60U)
13930 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_PRIO_SHIFT (5U)
13931 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_PRIO_WIDTH (2U)
13932 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_PRIO(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_CFG1_PRIO_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_CFG1_PRIO_MASK)
13933 
13934 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_PROT_MASK (0x3800U)
13935 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_PROT_SHIFT (11U)
13936 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_PROT_WIDTH (3U)
13937 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_PROT_MASK)
13938 
13939 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_CACHE_MASK (0x3C000U)
13940 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_CACHE_SHIFT (14U)
13941 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_CACHE_WIDTH (4U)
13942 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_CACHE_MASK)
13943 
13944 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_LOCK_MASK (0xC0000U)
13945 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_LOCK_SHIFT (18U)
13946 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_LOCK_WIDTH (2U)
13947 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_LOCK_MASK)
13948 
13949 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_SIZE_MASK (0x1C00000U)
13950 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_SIZE_SHIFT (22U)
13951 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_SIZE_WIDTH (3U)
13952 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_SIZE_MASK)
13953 
13954 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_RW_MASK (0x2000000U)
13955 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_RW_SHIFT (25U)
13956 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_RW_WIDTH (1U)
13957 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_RW(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_CFG1_AXI_RW_MASK)
13958 /*! @} */
13959 
13960 /*! @name AXIM3_SLOT1_CFG2 - AXIM[i] slot[s] configuration 2 */
13961 /*! @{ */
13962 
13963 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG2_AXI_ID_MASK (0xFFFFU)
13964 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG2_AXI_ID_SHIFT (0U)
13965 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG2_AXI_ID_WIDTH (16U)
13966 #define GTM_gtm_cls3_AXIM3_SLOT1_CFG2_AXI_ID(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_CFG2_AXI_ID_MASK)
13967 /*! @} */
13968 
13969 /*! @name AXIM3_SLOT1_STATUS - AXIM[i] slot[s] status */
13970 /*! @{ */
13971 
13972 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_ALLOC_MASK (0x1U)
13973 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_ALLOC_SHIFT (0U)
13974 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_ALLOC_WIDTH (1U)
13975 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_STATUS_ALLOC_MASK)
13976 
13977 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_QUEUED_MASK (0x2U)
13978 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_QUEUED_SHIFT (1U)
13979 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_QUEUED_WIDTH (1U)
13980 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_STATUS_QUEUED_MASK)
13981 
13982 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_STARTED_MASK (0x4U)
13983 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_STARTED_SHIFT (2U)
13984 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_STARTED_WIDTH (1U)
13985 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_STATUS_STARTED_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_STATUS_STARTED_MASK)
13986 
13987 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_READY_MASK (0x8U)
13988 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_READY_SHIFT (3U)
13989 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_READY_WIDTH (1U)
13990 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_STATUS_READY_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_STATUS_READY_MASK)
13991 
13992 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_RESP_MASK (0x30U)
13993 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_RESP_SHIFT (4U)
13994 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_RESP_WIDTH (2U)
13995 #define GTM_gtm_cls3_AXIM3_SLOT1_STATUS_RESP(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT1_STATUS_RESP_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT1_STATUS_RESP_MASK)
13996 /*! @} */
13997 
13998 /*! @name AXIM3_SLOT2_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */
13999 /*! @{ */
14000 
14001 #define GTM_gtm_cls3_AXIM3_SLOT2_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU)
14002 #define GTM_gtm_cls3_AXIM3_SLOT2_ADDR_LOW_AXI_ADDR_SHIFT (0U)
14003 #define GTM_gtm_cls3_AXIM3_SLOT2_ADDR_LOW_AXI_ADDR_WIDTH (32U)
14004 #define GTM_gtm_cls3_AXIM3_SLOT2_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_ADDR_LOW_AXI_ADDR_MASK)
14005 /*! @} */
14006 
14007 /*! @name AXIM3_SLOT2_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */
14008 /*! @{ */
14009 
14010 #define GTM_gtm_cls3_AXIM3_SLOT2_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU)
14011 #define GTM_gtm_cls3_AXIM3_SLOT2_DATA_LOW_AXI_DATA_LOW_SHIFT (0U)
14012 #define GTM_gtm_cls3_AXIM3_SLOT2_DATA_LOW_AXI_DATA_LOW_WIDTH (32U)
14013 #define GTM_gtm_cls3_AXIM3_SLOT2_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_DATA_LOW_AXI_DATA_LOW_MASK)
14014 /*! @} */
14015 
14016 /*! @name AXIM3_SLOT2_CFG1 - AXIM[i] slot [s] configuration 1 */
14017 /*! @{ */
14018 
14019 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_INCR_MASK  (0xFU)
14020 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_INCR_SHIFT (0U)
14021 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_INCR_WIDTH (4U)
14022 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_INCR(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_CFG1_INCR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_CFG1_INCR_MASK)
14023 
14024 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AUTO_INCR_MASK (0x10U)
14025 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AUTO_INCR_SHIFT (4U)
14026 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AUTO_INCR_WIDTH (1U)
14027 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AUTO_INCR_MASK)
14028 
14029 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_PRIO_MASK  (0x60U)
14030 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_PRIO_SHIFT (5U)
14031 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_PRIO_WIDTH (2U)
14032 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_PRIO(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_CFG1_PRIO_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_CFG1_PRIO_MASK)
14033 
14034 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_PROT_MASK (0x3800U)
14035 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_PROT_SHIFT (11U)
14036 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_PROT_WIDTH (3U)
14037 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_PROT_MASK)
14038 
14039 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_CACHE_MASK (0x3C000U)
14040 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_CACHE_SHIFT (14U)
14041 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_CACHE_WIDTH (4U)
14042 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_CACHE_MASK)
14043 
14044 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_LOCK_MASK (0xC0000U)
14045 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_LOCK_SHIFT (18U)
14046 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_LOCK_WIDTH (2U)
14047 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_LOCK_MASK)
14048 
14049 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_SIZE_MASK (0x1C00000U)
14050 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_SIZE_SHIFT (22U)
14051 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_SIZE_WIDTH (3U)
14052 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_SIZE_MASK)
14053 
14054 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_RW_MASK (0x2000000U)
14055 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_RW_SHIFT (25U)
14056 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_RW_WIDTH (1U)
14057 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_RW(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_CFG1_AXI_RW_MASK)
14058 /*! @} */
14059 
14060 /*! @name AXIM3_SLOT2_CFG2 - AXIM[i] slot[s] configuration 2 */
14061 /*! @{ */
14062 
14063 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG2_AXI_ID_MASK (0xFFFFU)
14064 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG2_AXI_ID_SHIFT (0U)
14065 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG2_AXI_ID_WIDTH (16U)
14066 #define GTM_gtm_cls3_AXIM3_SLOT2_CFG2_AXI_ID(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_CFG2_AXI_ID_MASK)
14067 /*! @} */
14068 
14069 /*! @name AXIM3_SLOT2_STATUS - AXIM[i] slot[s] status */
14070 /*! @{ */
14071 
14072 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_ALLOC_MASK (0x1U)
14073 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_ALLOC_SHIFT (0U)
14074 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_ALLOC_WIDTH (1U)
14075 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_STATUS_ALLOC_MASK)
14076 
14077 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_QUEUED_MASK (0x2U)
14078 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_QUEUED_SHIFT (1U)
14079 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_QUEUED_WIDTH (1U)
14080 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_STATUS_QUEUED_MASK)
14081 
14082 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_STARTED_MASK (0x4U)
14083 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_STARTED_SHIFT (2U)
14084 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_STARTED_WIDTH (1U)
14085 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_STATUS_STARTED_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_STATUS_STARTED_MASK)
14086 
14087 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_READY_MASK (0x8U)
14088 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_READY_SHIFT (3U)
14089 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_READY_WIDTH (1U)
14090 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_STATUS_READY_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_STATUS_READY_MASK)
14091 
14092 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_RESP_MASK (0x30U)
14093 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_RESP_SHIFT (4U)
14094 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_RESP_WIDTH (2U)
14095 #define GTM_gtm_cls3_AXIM3_SLOT2_STATUS_RESP(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT2_STATUS_RESP_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT2_STATUS_RESP_MASK)
14096 /*! @} */
14097 
14098 /*! @name AXIM3_SLOT3_ADDR_LOW - AXIM[i] slot[s] address bits 31:0 of AXI transaction. */
14099 /*! @{ */
14100 
14101 #define GTM_gtm_cls3_AXIM3_SLOT3_ADDR_LOW_AXI_ADDR_MASK (0xFFFFFFFFU)
14102 #define GTM_gtm_cls3_AXIM3_SLOT3_ADDR_LOW_AXI_ADDR_SHIFT (0U)
14103 #define GTM_gtm_cls3_AXIM3_SLOT3_ADDR_LOW_AXI_ADDR_WIDTH (32U)
14104 #define GTM_gtm_cls3_AXIM3_SLOT3_ADDR_LOW_AXI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_ADDR_LOW_AXI_ADDR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_ADDR_LOW_AXI_ADDR_MASK)
14105 /*! @} */
14106 
14107 /*! @name AXIM3_SLOT3_DATA_LOW - AXIM[i] slot[s] data bits 31:0 of AXI transaction. */
14108 /*! @{ */
14109 
14110 #define GTM_gtm_cls3_AXIM3_SLOT3_DATA_LOW_AXI_DATA_LOW_MASK (0xFFFFFFFFU)
14111 #define GTM_gtm_cls3_AXIM3_SLOT3_DATA_LOW_AXI_DATA_LOW_SHIFT (0U)
14112 #define GTM_gtm_cls3_AXIM3_SLOT3_DATA_LOW_AXI_DATA_LOW_WIDTH (32U)
14113 #define GTM_gtm_cls3_AXIM3_SLOT3_DATA_LOW_AXI_DATA_LOW(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_DATA_LOW_AXI_DATA_LOW_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_DATA_LOW_AXI_DATA_LOW_MASK)
14114 /*! @} */
14115 
14116 /*! @name AXIM3_SLOT3_CFG1 - AXIM[i] slot [s] configuration 1 */
14117 /*! @{ */
14118 
14119 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_INCR_MASK  (0xFU)
14120 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_INCR_SHIFT (0U)
14121 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_INCR_WIDTH (4U)
14122 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_INCR(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_CFG1_INCR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_CFG1_INCR_MASK)
14123 
14124 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AUTO_INCR_MASK (0x10U)
14125 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AUTO_INCR_SHIFT (4U)
14126 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AUTO_INCR_WIDTH (1U)
14127 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AUTO_INCR(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AUTO_INCR_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AUTO_INCR_MASK)
14128 
14129 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_PRIO_MASK  (0x60U)
14130 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_PRIO_SHIFT (5U)
14131 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_PRIO_WIDTH (2U)
14132 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_PRIO(x)    (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_CFG1_PRIO_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_CFG1_PRIO_MASK)
14133 
14134 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_PROT_MASK (0x3800U)
14135 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_PROT_SHIFT (11U)
14136 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_PROT_WIDTH (3U)
14137 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_PROT(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_PROT_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_PROT_MASK)
14138 
14139 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_CACHE_MASK (0x3C000U)
14140 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_CACHE_SHIFT (14U)
14141 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_CACHE_WIDTH (4U)
14142 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_CACHE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_CACHE_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_CACHE_MASK)
14143 
14144 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_LOCK_MASK (0xC0000U)
14145 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_LOCK_SHIFT (18U)
14146 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_LOCK_WIDTH (2U)
14147 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_LOCK_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_LOCK_MASK)
14148 
14149 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_SIZE_MASK (0x1C00000U)
14150 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_SIZE_SHIFT (22U)
14151 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_SIZE_WIDTH (3U)
14152 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_SIZE_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_SIZE_MASK)
14153 
14154 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_RW_MASK (0x2000000U)
14155 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_RW_SHIFT (25U)
14156 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_RW_WIDTH (1U)
14157 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_RW(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_RW_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_CFG1_AXI_RW_MASK)
14158 /*! @} */
14159 
14160 /*! @name AXIM3_SLOT3_CFG2 - AXIM[i] slot[s] configuration 2 */
14161 /*! @{ */
14162 
14163 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG2_AXI_ID_MASK (0xFFFFU)
14164 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG2_AXI_ID_SHIFT (0U)
14165 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG2_AXI_ID_WIDTH (16U)
14166 #define GTM_gtm_cls3_AXIM3_SLOT3_CFG2_AXI_ID(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_CFG2_AXI_ID_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_CFG2_AXI_ID_MASK)
14167 /*! @} */
14168 
14169 /*! @name AXIM3_SLOT3_STATUS - AXIM[i] slot[s] status */
14170 /*! @{ */
14171 
14172 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_ALLOC_MASK (0x1U)
14173 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_ALLOC_SHIFT (0U)
14174 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_ALLOC_WIDTH (1U)
14175 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_STATUS_ALLOC_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_STATUS_ALLOC_MASK)
14176 
14177 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_QUEUED_MASK (0x2U)
14178 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_QUEUED_SHIFT (1U)
14179 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_QUEUED_WIDTH (1U)
14180 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_QUEUED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_STATUS_QUEUED_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_STATUS_QUEUED_MASK)
14181 
14182 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_STARTED_MASK (0x4U)
14183 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_STARTED_SHIFT (2U)
14184 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_STARTED_WIDTH (1U)
14185 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_STATUS_STARTED_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_STATUS_STARTED_MASK)
14186 
14187 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_READY_MASK (0x8U)
14188 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_READY_SHIFT (3U)
14189 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_READY_WIDTH (1U)
14190 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_STATUS_READY_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_STATUS_READY_MASK)
14191 
14192 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_RESP_MASK (0x30U)
14193 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_RESP_SHIFT (4U)
14194 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_RESP_WIDTH (2U)
14195 #define GTM_gtm_cls3_AXIM3_SLOT3_STATUS_RESP(x)  (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_AXIM3_SLOT3_STATUS_RESP_SHIFT)) & GTM_gtm_cls3_AXIM3_SLOT3_STATUS_RESP_MASK)
14196 /*! @} */
14197 
14198 /*! @name MCS3_MEM - MCS[i] memory region */
14199 /*! @{ */
14200 
14201 #define GTM_gtm_cls3_MCS3_MEM_DATA_MASK          (0xFFFFFFFFU)
14202 #define GTM_gtm_cls3_MCS3_MEM_DATA_SHIFT         (0U)
14203 #define GTM_gtm_cls3_MCS3_MEM_DATA_WIDTH         (32U)
14204 #define GTM_gtm_cls3_MCS3_MEM_DATA(x)            (((uint32_t)(((uint32_t)(x)) << GTM_gtm_cls3_MCS3_MEM_DATA_SHIFT)) & GTM_gtm_cls3_MCS3_MEM_DATA_MASK)
14205 /*! @} */
14206 
14207 /*!
14208  * @}
14209  */ /* end of group GTM_gtm_cls3_Register_Masks */
14210 
14211 /*!
14212  * @}
14213  */ /* end of group GTM_gtm_cls3_Peripheral_Access_Layer */
14214 
14215 #endif  /* #if !defined(S32Z2_GTM_gtm_cls3_H_) */
14216