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Searched refs:CASPER_CTRL1_MODE_MASK (Results 1 – 25 of 27) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S06/
DLPC55S06.h5880 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5884 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S04/
DLPC55S04.h5880 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5884 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h5725 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5729 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h5724 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5728 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S16/
DLPC55S16.h6312 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
6316 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S14/
DLPC55S14.h6311 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
6315 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core1.h5725 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5729 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
DLPC55S66_cm33_core0.h5725 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5729 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h5724 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5728 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
DLPC55S69_cm33_core0.h5724 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5728 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6664 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
6667 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h6664 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
6667 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1670 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
1673 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
DMIMXRT595S_cm33.h7887 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
7890 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7883 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
7886 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7886 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
7889 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/
DMIMX8UD7_dsp1.h4807 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
4810 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
DMIMX8UD7_dsp0.h4890 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
4893 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
DMIMX8UD7_cm33.h5216 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5219 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/
DMIMX8UD3_cm33.h5216 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5219 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
DMIMX8UD3_dsp0.h4890 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
4893 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/
DMIMX8UD5_cm33.h5216 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
5219 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
DMIMX8UD5_dsp0.h4890 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
4893 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/
DMIMX8US5_dsp0.h4890 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
4893 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/
DMIMX8US3_dsp0.h4890 #define CASPER_CTRL1_MODE_MASK (0xFF00U) macro
4893 … (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)

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