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Searched refs:CAN_FDCBT_FPSEG1_MASK (Results 1 – 25 of 93) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_FLEXCAN.h1195 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
1198 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
DS32K118_FLEXCAN.h1187 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
1190 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
DS32K116_FLEXCAN.h1187 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
1190 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
DS32K142W_FLEXCAN.h1214 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
1217 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
DS32K146_FLEXCAN.h1205 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
1208 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
DS32K142_FLEXCAN.h1201 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
1204 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
DS32K144_FLEXCAN.h1205 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
1208 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
DS32K144W_FLEXCAN.h1214 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
1217 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/s32/mcux/devices/S32K344/
DS32K344_device.h2195 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
2199 …N_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexcan/
Dfsl_flexcan.c71 #define MAX_FPSEG1 (CAN_FDCBT_FPSEG1_MASK >> CAN_FDCBT_FPSEG1_SHIFT)
1546 (base->FDCBT & (CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | in FLEXCAN_SetFDTimingConfig()
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h1712 #define CAN_FDCBT_FPSEG1_MASK FLEXCAN_FDCBT_FPSEG1_MASK macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h3826 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
3829 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h3826 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
3829 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h3826 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
3829 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h3826 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
3829 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h3826 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
3829 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h3826 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
3829 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h6143 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
6146 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h6145 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
6148 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h6220 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
6223 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h6302 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
6305 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h6224 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
6227 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h5482 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
5485 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h7973 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
7976 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h7955 #define CAN_FDCBT_FPSEG1_MASK (0xE0U) macro
7958 … (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)

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