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Searched refs:CAN_ERFSR_ERFWMI_MASK (Results 1 – 25 of 44) sorted by relevance

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/hal_nxp-latest/s32/mcux/devices/S32K344/
DS32K344_device.h2349 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
2355 …N_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexcan/
Dfsl_flexcan.c2574 … |= CAN_ERFSR_ERFCLR_MASK | CAN_ERFSR_ERFUFW_MASK | CAN_ERFSR_ERFOVF_MASK | CAN_ERFSR_ERFWMI_MASK | in FLEXCAN_SetEnhancedRxFifoConfig()
2596 … |= CAN_ERFSR_ERFCLR_MASK | CAN_ERFSR_ERFUFW_MASK | CAN_ERFSR_ERFOVF_MASK | CAN_ERFSR_ERFWMI_MASK | in FLEXCAN_SetEnhancedRxFifoConfig()
4697 base->ERFSR = CAN_ERFSR_ERFWMI_MASK; in FLEXCAN_SubHandlerForEhancedRxFifo()
Dfsl_flexcan.h488 …FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFWMI_MASK), /*!< Enhanced Rx FIFO watermark Interrupt Flag. …
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h1828 #define CAN_ERFSR_ERFWMI_MASK FLEXCAN_ERFSR_ERFWMI_MASK macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h3969 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
3975 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h3969 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
3975 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h3969 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
3975 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h3969 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
3975 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h3969 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
3975 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h3969 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
3975 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h5625 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
5631 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h8116 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
8122 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h8098 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
8104 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h5826 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
5832 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h10412 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
10418 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
DMCXN546_cm33_core1.h10412 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
10418 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h10412 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
10418 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
DMCXN547_cm33_core1.h10412 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
10418 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h10446 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
10452 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
DMCXN947_cm33_core0.h10446 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
10452 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h10446 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
10452 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
DMCXN946_cm33_core1.h10446 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
10452 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/
DMIMXRT1182.h15232 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
15238 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/
DMIMXRT1181.h15232 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
15238 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/
DMIMX9131.h10721 #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) macro
10727 … (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)

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