1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2024 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_CANXL_RAMECC.h
10  * @version 2.3
11  * @date 2024-05-03
12  * @brief Peripheral Access Layer for S32Z2_CANXL_RAMECC
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_CANXL_RAMECC_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_CANXL_RAMECC_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- CANXL_RAMECC Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup CANXL_RAMECC_Peripheral_Access_Layer CANXL_RAMECC Peripheral Access Layer
68  * @{
69  */
70 
71 /** CANXL_RAMECC - Register Layout Typedef */
72 typedef struct {
73   __IO uint32_t DRMEC;                             /**< Data RAM Error Control, offset: 0x0 */
74   __IO uint32_t DRERRIA;                           /**< Data RAM Error Injection Address, offset: 0x4 */
75   __IO uint32_t DRERRIDP;                          /**< Data RAM Error Injection Data Pattern, offset: 0x8 */
76   __IO uint32_t DRERRIPP;                          /**< Data RAM Error Injection Parity Pattern, offset: 0xC */
77   __I  uint32_t DRRERRA;                           /**< Data RAM Error Report Address, offset: 0x10 */
78   __I  uint32_t DRRERRD;                           /**< Data RAM Error Report Data, offset: 0x14 */
79   __I  uint32_t DRRERRSYN;                         /**< Data RAM Error Report Syndrome, offset: 0x18 */
80   __IO uint32_t DRERRS;                            /**< Data RAM Error Status, offset: 0x1C */
81 } CANXL_RAMECC_Type, *CANXL_RAMECC_MemMapPtr;
82 
83 /** Number of instances of the CANXL_RAMECC module. */
84 #define CANXL_RAMECC_INSTANCE_COUNT              (2u)
85 
86 /* CANXL_RAMECC - Peripheral instance base addresses */
87 /** Peripheral CANXL_0__RAMECC base address */
88 #define IP_CANXL_0__RAMECC_BASE                  (0x47460000u)
89 /** Peripheral CANXL_0__RAMECC base pointer */
90 #define IP_CANXL_0__RAMECC                       ((CANXL_RAMECC_Type *)IP_CANXL_0__RAMECC_BASE)
91 /** Peripheral CANXL_1__RAMECC base address */
92 #define IP_CANXL_1__RAMECC_BASE                  (0x47560000u)
93 /** Peripheral CANXL_1__RAMECC base pointer */
94 #define IP_CANXL_1__RAMECC                       ((CANXL_RAMECC_Type *)IP_CANXL_1__RAMECC_BASE)
95 /** Array initializer of CANXL_RAMECC peripheral base addresses */
96 #define IP_CANXL_RAMECC_BASE_ADDRS               { IP_CANXL_0__RAMECC_BASE, IP_CANXL_1__RAMECC_BASE }
97 /** Array initializer of CANXL_RAMECC peripheral base pointers */
98 #define IP_CANXL_RAMECC_BASE_PTRS                { IP_CANXL_0__RAMECC, IP_CANXL_1__RAMECC }
99 
100 /* ----------------------------------------------------------------------------
101    -- CANXL_RAMECC Register Masks
102    ---------------------------------------------------------------------------- */
103 
104 /*!
105  * @addtogroup CANXL_RAMECC_Register_Masks CANXL_RAMECC Register Masks
106  * @{
107  */
108 
109 /*! @name DRMEC - Data RAM Error Control */
110 /*! @{ */
111 
112 #define CANXL_RAMECC_DRMEC_ECCDIS_MASK           (0x100U)
113 #define CANXL_RAMECC_DRMEC_ECCDIS_SHIFT          (8U)
114 #define CANXL_RAMECC_DRMEC_ECCDIS_WIDTH          (1U)
115 #define CANXL_RAMECC_DRMEC_ECCDIS(x)             (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRMEC_ECCDIS_SHIFT)) & CANXL_RAMECC_DRMEC_ECCDIS_MASK)
116 
117 #define CANXL_RAMECC_DRMEC_ERRRPTDIS_MASK        (0x200U)
118 #define CANXL_RAMECC_DRMEC_ERRRPTDIS_SHIFT       (9U)
119 #define CANXL_RAMECC_DRMEC_ERRRPTDIS_WIDTH       (1U)
120 #define CANXL_RAMECC_DRMEC_ERRRPTDIS(x)          (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRMEC_ERRRPTDIS_SHIFT)) & CANXL_RAMECC_DRMEC_ERRRPTDIS_MASK)
121 
122 #define CANXL_RAMECC_DRMEC_ERRINJEN_MASK         (0x4000U)
123 #define CANXL_RAMECC_DRMEC_ERRINJEN_SHIFT        (14U)
124 #define CANXL_RAMECC_DRMEC_ERRINJEN_WIDTH        (1U)
125 #define CANXL_RAMECC_DRMEC_ERRINJEN(x)           (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRMEC_ERRINJEN_SHIFT)) & CANXL_RAMECC_DRMEC_ERRINJEN_MASK)
126 
127 #define CANXL_RAMECC_DRMEC_CEIEN_MASK            (0x10000U)
128 #define CANXL_RAMECC_DRMEC_CEIEN_SHIFT           (16U)
129 #define CANXL_RAMECC_DRMEC_CEIEN_WIDTH           (1U)
130 #define CANXL_RAMECC_DRMEC_CEIEN(x)              (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRMEC_CEIEN_SHIFT)) & CANXL_RAMECC_DRMEC_CEIEN_MASK)
131 
132 #define CANXL_RAMECC_DRMEC_NCEIEN_MASK           (0x40000U)
133 #define CANXL_RAMECC_DRMEC_NCEIEN_SHIFT          (18U)
134 #define CANXL_RAMECC_DRMEC_NCEIEN_WIDTH          (1U)
135 #define CANXL_RAMECC_DRMEC_NCEIEN(x)             (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRMEC_NCEIEN_SHIFT)) & CANXL_RAMECC_DRMEC_NCEIEN_MASK)
136 
137 #define CANXL_RAMECC_DRMEC_ECRWRDIS_MASK         (0x80000000U)
138 #define CANXL_RAMECC_DRMEC_ECRWRDIS_SHIFT        (31U)
139 #define CANXL_RAMECC_DRMEC_ECRWRDIS_WIDTH        (1U)
140 #define CANXL_RAMECC_DRMEC_ECRWRDIS(x)           (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRMEC_ECRWRDIS_SHIFT)) & CANXL_RAMECC_DRMEC_ECRWRDIS_MASK)
141 /*! @} */
142 
143 /*! @name DRERRIA - Data RAM Error Injection Address */
144 /*! @{ */
145 
146 #define CANXL_RAMECC_DRERRIA_INJADDR_L_MASK      (0x3U)
147 #define CANXL_RAMECC_DRERRIA_INJADDR_L_SHIFT     (0U)
148 #define CANXL_RAMECC_DRERRIA_INJADDR_L_WIDTH     (2U)
149 #define CANXL_RAMECC_DRERRIA_INJADDR_L(x)        (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRIA_INJADDR_L_SHIFT)) & CANXL_RAMECC_DRERRIA_INJADDR_L_MASK)
150 
151 #define CANXL_RAMECC_DRERRIA_INJADDR_H_MASK      (0x7FFCU)
152 #define CANXL_RAMECC_DRERRIA_INJADDR_H_SHIFT     (2U)
153 #define CANXL_RAMECC_DRERRIA_INJADDR_H_WIDTH     (13U)
154 #define CANXL_RAMECC_DRERRIA_INJADDR_H(x)        (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRIA_INJADDR_H_SHIFT)) & CANXL_RAMECC_DRERRIA_INJADDR_H_MASK)
155 /*! @} */
156 
157 /*! @name DRERRIDP - Data RAM Error Injection Data Pattern */
158 /*! @{ */
159 
160 #define CANXL_RAMECC_DRERRIDP_DFLIP_MASK         (0xFFFFFFFFU)
161 #define CANXL_RAMECC_DRERRIDP_DFLIP_SHIFT        (0U)
162 #define CANXL_RAMECC_DRERRIDP_DFLIP_WIDTH        (32U)
163 #define CANXL_RAMECC_DRERRIDP_DFLIP(x)           (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRIDP_DFLIP_SHIFT)) & CANXL_RAMECC_DRERRIDP_DFLIP_MASK)
164 /*! @} */
165 
166 /*! @name DRERRIPP - Data RAM Error Injection Parity Pattern */
167 /*! @{ */
168 
169 #define CANXL_RAMECC_DRERRIPP_PFLIP0_MASK        (0x1FU)
170 #define CANXL_RAMECC_DRERRIPP_PFLIP0_SHIFT       (0U)
171 #define CANXL_RAMECC_DRERRIPP_PFLIP0_WIDTH       (5U)
172 #define CANXL_RAMECC_DRERRIPP_PFLIP0(x)          (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRIPP_PFLIP0_SHIFT)) & CANXL_RAMECC_DRERRIPP_PFLIP0_MASK)
173 
174 #define CANXL_RAMECC_DRERRIPP_PFLIP1_MASK        (0x1F00U)
175 #define CANXL_RAMECC_DRERRIPP_PFLIP1_SHIFT       (8U)
176 #define CANXL_RAMECC_DRERRIPP_PFLIP1_WIDTH       (5U)
177 #define CANXL_RAMECC_DRERRIPP_PFLIP1(x)          (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRIPP_PFLIP1_SHIFT)) & CANXL_RAMECC_DRERRIPP_PFLIP1_MASK)
178 
179 #define CANXL_RAMECC_DRERRIPP_PFLIP2_MASK        (0x1F0000U)
180 #define CANXL_RAMECC_DRERRIPP_PFLIP2_SHIFT       (16U)
181 #define CANXL_RAMECC_DRERRIPP_PFLIP2_WIDTH       (5U)
182 #define CANXL_RAMECC_DRERRIPP_PFLIP2(x)          (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRIPP_PFLIP2_SHIFT)) & CANXL_RAMECC_DRERRIPP_PFLIP2_MASK)
183 
184 #define CANXL_RAMECC_DRERRIPP_PFLIP3_MASK        (0x1F000000U)
185 #define CANXL_RAMECC_DRERRIPP_PFLIP3_SHIFT       (24U)
186 #define CANXL_RAMECC_DRERRIPP_PFLIP3_WIDTH       (5U)
187 #define CANXL_RAMECC_DRERRIPP_PFLIP3(x)          (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRIPP_PFLIP3_SHIFT)) & CANXL_RAMECC_DRERRIPP_PFLIP3_MASK)
188 /*! @} */
189 
190 /*! @name DRRERRA - Data RAM Error Report Address */
191 /*! @{ */
192 
193 #define CANXL_RAMECC_DRRERRA_ERRADDR_MASK        (0x7FFFU)
194 #define CANXL_RAMECC_DRRERRA_ERRADDR_SHIFT       (0U)
195 #define CANXL_RAMECC_DRRERRA_ERRADDR_WIDTH       (15U)
196 #define CANXL_RAMECC_DRRERRA_ERRADDR(x)          (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRA_ERRADDR_SHIFT)) & CANXL_RAMECC_DRRERRA_ERRADDR_MASK)
197 
198 #define CANXL_RAMECC_DRRERRA_NCE_MASK            (0x1000000U)
199 #define CANXL_RAMECC_DRRERRA_NCE_SHIFT           (24U)
200 #define CANXL_RAMECC_DRRERRA_NCE_WIDTH           (1U)
201 #define CANXL_RAMECC_DRRERRA_NCE(x)              (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRA_NCE_SHIFT)) & CANXL_RAMECC_DRRERRA_NCE_MASK)
202 /*! @} */
203 
204 /*! @name DRRERRD - Data RAM Error Report Data */
205 /*! @{ */
206 
207 #define CANXL_RAMECC_DRRERRD_RDATA_MASK          (0xFFFFFFFFU)
208 #define CANXL_RAMECC_DRRERRD_RDATA_SHIFT         (0U)
209 #define CANXL_RAMECC_DRRERRD_RDATA_WIDTH         (32U)
210 #define CANXL_RAMECC_DRRERRD_RDATA(x)            (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRD_RDATA_SHIFT)) & CANXL_RAMECC_DRRERRD_RDATA_MASK)
211 /*! @} */
212 
213 /*! @name DRRERRSYN - Data RAM Error Report Syndrome */
214 /*! @{ */
215 
216 #define CANXL_RAMECC_DRRERRSYN_SYND0_MASK        (0x1FU)
217 #define CANXL_RAMECC_DRRERRSYN_SYND0_SHIFT       (0U)
218 #define CANXL_RAMECC_DRRERRSYN_SYND0_WIDTH       (5U)
219 #define CANXL_RAMECC_DRRERRSYN_SYND0(x)          (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRSYN_SYND0_SHIFT)) & CANXL_RAMECC_DRRERRSYN_SYND0_MASK)
220 
221 #define CANXL_RAMECC_DRRERRSYN_BE0_MASK          (0x80U)
222 #define CANXL_RAMECC_DRRERRSYN_BE0_SHIFT         (7U)
223 #define CANXL_RAMECC_DRRERRSYN_BE0_WIDTH         (1U)
224 #define CANXL_RAMECC_DRRERRSYN_BE0(x)            (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRSYN_BE0_SHIFT)) & CANXL_RAMECC_DRRERRSYN_BE0_MASK)
225 
226 #define CANXL_RAMECC_DRRERRSYN_SYND1_MASK        (0x1F00U)
227 #define CANXL_RAMECC_DRRERRSYN_SYND1_SHIFT       (8U)
228 #define CANXL_RAMECC_DRRERRSYN_SYND1_WIDTH       (5U)
229 #define CANXL_RAMECC_DRRERRSYN_SYND1(x)          (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRSYN_SYND1_SHIFT)) & CANXL_RAMECC_DRRERRSYN_SYND1_MASK)
230 
231 #define CANXL_RAMECC_DRRERRSYN_BE1_MASK          (0x8000U)
232 #define CANXL_RAMECC_DRRERRSYN_BE1_SHIFT         (15U)
233 #define CANXL_RAMECC_DRRERRSYN_BE1_WIDTH         (1U)
234 #define CANXL_RAMECC_DRRERRSYN_BE1(x)            (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRSYN_BE1_SHIFT)) & CANXL_RAMECC_DRRERRSYN_BE1_MASK)
235 
236 #define CANXL_RAMECC_DRRERRSYN_SYND2_MASK        (0x1F0000U)
237 #define CANXL_RAMECC_DRRERRSYN_SYND2_SHIFT       (16U)
238 #define CANXL_RAMECC_DRRERRSYN_SYND2_WIDTH       (5U)
239 #define CANXL_RAMECC_DRRERRSYN_SYND2(x)          (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRSYN_SYND2_SHIFT)) & CANXL_RAMECC_DRRERRSYN_SYND2_MASK)
240 
241 #define CANXL_RAMECC_DRRERRSYN_BE2_MASK          (0x800000U)
242 #define CANXL_RAMECC_DRRERRSYN_BE2_SHIFT         (23U)
243 #define CANXL_RAMECC_DRRERRSYN_BE2_WIDTH         (1U)
244 #define CANXL_RAMECC_DRRERRSYN_BE2(x)            (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRSYN_BE2_SHIFT)) & CANXL_RAMECC_DRRERRSYN_BE2_MASK)
245 
246 #define CANXL_RAMECC_DRRERRSYN_SYND3_MASK        (0x1F000000U)
247 #define CANXL_RAMECC_DRRERRSYN_SYND3_SHIFT       (24U)
248 #define CANXL_RAMECC_DRRERRSYN_SYND3_WIDTH       (5U)
249 #define CANXL_RAMECC_DRRERRSYN_SYND3(x)          (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRSYN_SYND3_SHIFT)) & CANXL_RAMECC_DRRERRSYN_SYND3_MASK)
250 
251 #define CANXL_RAMECC_DRRERRSYN_BE3_MASK          (0x80000000U)
252 #define CANXL_RAMECC_DRRERRSYN_BE3_SHIFT         (31U)
253 #define CANXL_RAMECC_DRRERRSYN_BE3_WIDTH         (1U)
254 #define CANXL_RAMECC_DRRERRSYN_BE3(x)            (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRRERRSYN_BE3_SHIFT)) & CANXL_RAMECC_DRRERRSYN_BE3_MASK)
255 /*! @} */
256 
257 /*! @name DRERRS - Data RAM Error Status */
258 /*! @{ */
259 
260 #define CANXL_RAMECC_DRERRS_CEIOF_MASK           (0x1U)
261 #define CANXL_RAMECC_DRERRS_CEIOF_SHIFT          (0U)
262 #define CANXL_RAMECC_DRERRS_CEIOF_WIDTH          (1U)
263 #define CANXL_RAMECC_DRERRS_CEIOF(x)             (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRS_CEIOF_SHIFT)) & CANXL_RAMECC_DRERRS_CEIOF_MASK)
264 
265 #define CANXL_RAMECC_DRERRS_NCEIOF_MASK          (0x4U)
266 #define CANXL_RAMECC_DRERRS_NCEIOF_SHIFT         (2U)
267 #define CANXL_RAMECC_DRERRS_NCEIOF_WIDTH         (1U)
268 #define CANXL_RAMECC_DRERRS_NCEIOF(x)            (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRS_NCEIOF_SHIFT)) & CANXL_RAMECC_DRERRS_NCEIOF_MASK)
269 
270 #define CANXL_RAMECC_DRERRS_CEIF_MASK            (0x10000U)
271 #define CANXL_RAMECC_DRERRS_CEIF_SHIFT           (16U)
272 #define CANXL_RAMECC_DRERRS_CEIF_WIDTH           (1U)
273 #define CANXL_RAMECC_DRERRS_CEIF(x)              (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRS_CEIF_SHIFT)) & CANXL_RAMECC_DRERRS_CEIF_MASK)
274 
275 #define CANXL_RAMECC_DRERRS_NCEIF_MASK           (0x40000U)
276 #define CANXL_RAMECC_DRERRS_NCEIF_SHIFT          (18U)
277 #define CANXL_RAMECC_DRERRS_NCEIF_WIDTH          (1U)
278 #define CANXL_RAMECC_DRERRS_NCEIF(x)             (((uint32_t)(((uint32_t)(x)) << CANXL_RAMECC_DRERRS_NCEIF_SHIFT)) & CANXL_RAMECC_DRERRS_NCEIF_MASK)
279 /*! @} */
280 
281 /*!
282  * @}
283  */ /* end of group CANXL_RAMECC_Register_Masks */
284 
285 /*!
286  * @}
287  */ /* end of group CANXL_RAMECC_Peripheral_Access_Layer */
288 
289 #endif  /* #if !defined(S32Z2_CANXL_RAMECC_H_) */
290