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Searched refs:CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (Results 1 – 25 of 27) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1147 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
1149 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
DMIMXRT685S_cm33.h6489 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
6491 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6489 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
6491 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1516 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
1518 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
DMIMXRT595S_cm33.h7706 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
7708 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h3000 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
3002 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h3000 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
3002 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7702 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
7704 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7705 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
7707 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2999 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
3001 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8265 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
8267 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
DMCXN546_cm33_core1.h8265 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
8267 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8265 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
8267 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
DMCXN547_cm33_core1.h8265 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
8267 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16889 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
16891 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
DMIMXRT798S_cm33_core0.h16948 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
16950 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
DMIMXRT798S_ezhv.h16449 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
16451 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16449 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
16451 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
DMIMXRT735S_cm33_core0.h16948 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
16950 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16948 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
16950 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8299 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
8301 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
DMCXN947_cm33_core0.h8299 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
8301 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8299 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
8301 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
DMCXN946_cm33_core1.h8299 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
8301 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13504 #define CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT (10U) macro
13506 …EG0_TOP_REG0_TOP(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_REG0_TOP_REG0_TOP_SHIFT)) …

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