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Searched refs:CACHE64_CTRL_BASE_ADDRS (Results 1 – 25 of 38) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6418 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_BASE } macro
6431 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h6418 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_BASE } macro
6431 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_BASE } macro
DMIMXRT685S_dsp.h1105 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2930 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
2943 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2930 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
2943 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7627 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
7644 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h7631 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
7648 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
DMIMXRT595S_dsp.h1474 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7630 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
7647 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2929 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
2942 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8193 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
8206 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
DMCXN546_cm33_core1.h8193 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
8206 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8193 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
8206 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
DMCXN547_cm33_core1.h8193 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
8206 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16832 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
16849 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
DMIMXRT798S_cm33_core0.h16875 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
16892 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_cm33_core0.h16875 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
16892 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
DMIMXRT735S_ezhv.h16405 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16875 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
16892 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8227 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
8240 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
DMCXN947_cm33_core0.h8227 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
8240 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8227 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
8240 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
DMCXN946_cm33_core1.h8227 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
8240 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13429 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
13446 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h13429 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro
13446 #define CACHE64_CTRL_BASE_ADDRS { CACHE64_CTRL0_BASE, CACHE64_CTRL1_BASE } macro

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