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Searched refs:CAAM_CHAVID_LS_SNW8VID_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h14611 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14613 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
DMIMXRT1175_cm7.h14614 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14616 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h14302 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14304 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
DMIMXRT1165_cm4.h14299 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14301 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h14614 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14616 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h14314 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14316 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
DMIMXRT1166_cm7.h14317 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14319 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h14623 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14625 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
DMIMXRT1173_cm7.h14626 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14628 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h14629 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14631 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h14631 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14633 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
DMIMXRT1176_cm4.h14628 #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) macro
14630 … (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)