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Searched refs:C5 (Results 1 – 25 of 136) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/lpsci/
Dfsl_lpsci.h413 base->C5 |= UART0_C5_TDMAE_MASK; in LPSCI_EnableTxDMA()
418 base->C5 &= ~UART0_C5_TDMAE_MASK; in LPSCI_EnableTxDMA()
435 base->C5 |= UART0_C5_RDMAE_MASK; in LPSCI_EnableRxDMA()
440 base->C5 &= ~UART0_C5_RDMAE_MASK; in LPSCI_EnableRxDMA()
/hal_nxp-latest/mcux/mcux-sdk/drivers/uart/
Dfsl_uart.h551 base->C5 |= (uint8_t)UART_C5_TDMAS_MASK; in UART_EnableTxDMA()
560 base->C5 &= ~(uint8_t)UART_C5_TDMAS_MASK; in UART_EnableTxDMA()
581 base->C5 |= (uint8_t)UART_C5_RDMAS_MASK; in UART_EnableRxDMA()
590 base->C5 &= ~(uint8_t)UART_C5_RDMAS_MASK; in UART_EnableRxDMA()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/drivers/
Dfsl_clock.c80 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
84 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
765 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
770 MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); in CLOCK_EnablePll0()
1673 MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/drivers/
Dfsl_clock.c80 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
84 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
818 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
823 MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); in CLOCK_EnablePll0()
1772 MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/drivers/
Dfsl_clock.c80 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
84 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
818 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
823 MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); in CLOCK_EnablePll0()
1772 MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
871 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
876 MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); in CLOCK_EnablePll0()
2326 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
950 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
955 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2208 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV56F24/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
950 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
955 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2208 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1007 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1012 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2288 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F25612/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
992 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
997 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2266 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1005 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1010 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2323 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1064 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1069 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2375 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK24F12/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1012 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1017 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2323 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1011 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1016 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2322 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F25612/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1043 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1048 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2361 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F51212/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1055 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1060 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2372 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1022 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1027 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2333 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
861 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
866 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2322 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
899 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
904 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2367 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1064 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1069 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2375 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1283 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1288 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2667 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK26F18/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1283 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1288 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2667 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1242 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1247 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2626 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1242 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1247 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2626 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK66F18/drivers/
Dfsl_clock.c62 #define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
1282 MCG->C5 = mcg_c5; /* Disable the PLL first. */ in CLOCK_EnablePll0()
1287 MCG->C5 |= ((uint8_t)kMCG_PllEnableIndependent | (uint8_t)config->enableMode); in CLOCK_EnablePll0()
2666 MCG->C5 &= ~(uint8_t)kMCG_PllEnableIndependent; in CLOCK_SetMcgConfig()

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