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Searched refs:C4 (Results 1 – 25 of 137) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1032 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1044 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1060 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1064 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1108 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1120 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1147 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1153 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
Dsystem_MKW40Z4.c132 …MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SC… in SystemInit()
135 …MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MA… in SystemInit()
161 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG-… in SystemInit()
182 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG… in SystemInit()
247 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
Dsystem_MKW20Z4.c132 …MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SC… in SystemInit()
135 …MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MA… in SystemInit()
161 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG-… in SystemInit()
182 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG… in SystemInit()
247 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
Dsystem_MKW30Z4.c132 …MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SC… in SystemInit()
135 …MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MA… in SystemInit()
161 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG-… in SystemInit()
182 …MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG… in SystemInit()
247 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/drivers/
Dfsl_clock.c105 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
106 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
909 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
921 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
937 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
941 …MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_D… in CLOCK_SetFeiMode()
969 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
981 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1009 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1014 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1049 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1061 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1077 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1081 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1125 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1137 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1164 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1170 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1049 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1061 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1077 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1081 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1125 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1137 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1164 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1170 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1160 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1172 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1188 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1192 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1236 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1248 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1276 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1282 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12810/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1251 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1263 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1279 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1283 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1327 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1339 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1367 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1373 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1163 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1175 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1191 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1195 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1239 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1251 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1279 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1285 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1168 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1180 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1196 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1200 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1244 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1256 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1284 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1290 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/drivers/
Dfsl_clock.c77 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
78 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1077 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1089 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1105 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1109 …MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_D… in CLOCK_SetFeiMode()
1137 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1149 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1176 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1181 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1361 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1373 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1389 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1393 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1437 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1449 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1477 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1483 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1396 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1408 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1424 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1428 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1472 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1484 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1511 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1517 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV56F24/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1396 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1408 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1424 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1428 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1472 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1484 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1511 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1517 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1453 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1465 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1481 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1485 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1529 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1541 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1569 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1575 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F25612/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1438 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1450 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1466 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1470 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1514 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1526 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1554 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1560 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/drivers/
Dfsl_clock.c77 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
78 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1160 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1172 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1188 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1192 …MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_D… in CLOCK_SetFeiMode()
1220 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1232 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1260 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1265 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/drivers/
Dfsl_clock.c77 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
78 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1160 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1172 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1188 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1192 …MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_D… in CLOCK_SetFeiMode()
1220 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1232 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1260 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1265 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1488 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1500 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1516 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1520 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1564 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1576 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1604 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1610 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1547 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1559 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1575 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1579 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1623 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1635 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1663 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1669 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK24F12/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1495 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1507 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1523 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1527 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1571 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1583 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1611 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1617 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1494 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1506 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1522 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1526 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1570 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1582 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1610 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1616 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F25612/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1526 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1538 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1554 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1558 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1602 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1614 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1642 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1648 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F51212/drivers/
Dfsl_clock.c59 #define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
60 #define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
1538 mcg_c4 = MCG->C4; in CLOCK_SetFeiMode()
1550 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeiMode()
1566 MCG->C4 = mcg_c4; in CLOCK_SetFeiMode()
1570 MCG->C4 = (uint8_t)((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | in CLOCK_SetFeiMode()
1614 mcg_c4 = MCG->C4; in CLOCK_SetFeeMode()
1626 MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); in CLOCK_SetFeeMode()
1654 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
1660 MCG->C4 = mcg_c4; in CLOCK_SetFeeMode()
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