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/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z1284/drivers/
Dfsl_clock.c20 #define ICS_C2_BDIV_VAL ((ICS->C2 & ICS_C2_BDIV_MASK) >> ICS_C2_BDIV_SHIFT)
27 #define ICS_C2_LP_VAL ((ICS->C2 & ICS_C2_LP_MASK) >> ICS_C2_LP_SHIFT)
382 if ((ICS->C2 & ICS_C2_LP_MASK) != 0U) in CLOCK_GetFllFreq()
592 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFeiMode()
643 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFeeMode()
701 ICS->C2 = (uint8_t)((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFbiMode()
746 ICS->C2 = (uint8_t)((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFbeMode()
800 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_SetBilpMode()
825 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_SetBelpMode()
882 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_BootToBilpMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE06Z4/drivers/
Dfsl_clock.c20 #define ICS_C2_BDIV_VAL ((ICS->C2 & ICS_C2_BDIV_MASK) >> ICS_C2_BDIV_SHIFT)
27 #define ICS_C2_LP_VAL ((ICS->C2 & ICS_C2_LP_MASK) >> ICS_C2_LP_SHIFT)
382 if ((ICS->C2 & ICS_C2_LP_MASK) != 0U) in CLOCK_GetFllFreq()
592 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFeiMode()
643 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFeeMode()
701 ICS->C2 = (uint8_t)((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFbiMode()
746 ICS->C2 = (uint8_t)((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFbeMode()
800 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_SetBilpMode()
825 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_SetBelpMode()
882 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_BootToBilpMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z4/drivers/
Dfsl_clock.c20 #define ICS_C2_BDIV_VAL ((ICS->C2 & ICS_C2_BDIV_MASK) >> ICS_C2_BDIV_SHIFT)
27 #define ICS_C2_LP_VAL ((ICS->C2 & ICS_C2_LP_MASK) >> ICS_C2_LP_SHIFT)
382 if ((ICS->C2 & ICS_C2_LP_MASK) != 0U) in CLOCK_GetFllFreq()
588 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFeiMode()
639 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFeeMode()
696 ICS->C2 = (uint8_t)((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFbiMode()
740 ICS->C2 = (uint8_t)((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFbeMode()
794 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_SetBilpMode()
819 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_SetBelpMode()
876 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_BootToBilpMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE02Z4/drivers/
Dfsl_clock.c20 #define ICS_C2_BDIV_VAL ((ICS->C2 & ICS_C2_BDIV_MASK) >> ICS_C2_BDIV_SHIFT)
27 #define ICS_C2_LP_VAL ((ICS->C2 & ICS_C2_LP_MASK) >> ICS_C2_LP_SHIFT)
362 if ((ICS->C2 & ICS_C2_LP_MASK) != 0U) in CLOCK_GetFllFreq()
568 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFeiMode()
618 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFeeMode()
675 ICS->C2 = (uint8_t)((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFbiMode()
720 ICS->C2 = (uint8_t)((ICS->C2 & (~(ICS_C2_BDIV_MASK | ICS_C2_LP_MASK))) | ICS_C2_BDIV(bDiv)); in CLOCK_SetFbeMode()
774 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_SetBilpMode()
799 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_SetBelpMode()
856 ICS->C2 = (uint8_t)((ICS->C2 & (~ICS_C2_BDIV_MASK)) | ICS_C2_BDIV(bDiv) | ICS_C2_LP_MASK); in CLOCK_BootToBilpMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/uart/
Dfsl_uart.c272 base->C2 &= ~((uint8_t)UART_C2_TE_MASK | (uint8_t)UART_C2_RE_MASK); in UART_Init()
334 temp = base->C2; in UART_Init()
346 base->C2 = temp; in UART_Init()
372 base->C2 = 0; in UART_Deinit()
480 oldCtrl = base->C2; in UART_SetBaudRate()
483 base->C2 &= ~((uint8_t)UART_C2_TE_MASK | (uint8_t)UART_C2_RE_MASK); in UART_SetBaudRate()
494 base->C2 = oldCtrl; in UART_SetBaudRate()
573 base->C2 |= (uint8_t)(mask >> 8); in UART_EnableInterrupts()
601 base->C2 &= ~(uint8_t)(mask >> 8); in UART_DisableInterrupts()
634 temp |= ((uint32_t)(base->C2) << 8); in UART_GetEnabledInterrupts()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/drivers/
Dfsl_clock.c100 #define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
101 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
512 if ((MCG->C2 & MCG_C2_LP_MASK) in CLOCK_GetFllFreq()
619 MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
629 MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); in CLOCK_SetInternalRefClkConfig()
658 MCG->C2 &= ~MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
662 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
714 MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
728 MCG->C2 &= ~OSC_MODE_MASK; in CLOCK_DeinitOsc0()
993 if (MCG->C2 & MCG_C2_EREFS_MASK) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
515 if (0U != (MCG->C2 & MCG_C2_LP_MASK)) in CLOCK_GetFllFreq()
636 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
647 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
681 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
685 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
770 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
790 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1131 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
650 if (0U != (MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) in CLOCK_GetFllFreq()
829 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
840 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
904 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
908 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1077 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1097 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1461 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2…
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
515 if (0U != (MCG->C2 & MCG_C2_LP_MASK)) in CLOCK_GetFllFreq()
650 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
661 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
695 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
699 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
784 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
804 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1148 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2…
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
515 if (0U != (MCG->C2 & MCG_C2_LP_MASK)) in CLOCK_GetFllFreq()
650 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
661 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
695 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
699 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
784 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
804 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1148 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2…
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
621 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
819 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
830 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
894 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
898 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1067 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1087 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1454 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2…
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
659 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
857 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
868 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
932 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
936 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1105 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1125 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1492 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2…
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
597 if (0U != (MCG->C2 & MCG_C2_LP_MASK)) in CLOCK_GetFllFreq()
761 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
772 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
806 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
810 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
895 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
915 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1260 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12810/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2…
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
653 if (0U != (MCG->C2 & MCG_C2_LP_MASK)) in CLOCK_GetFllFreq()
817 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
828 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
862 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
866 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
986 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1006 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1351 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
600 if (0U != (MCG->C2 & MCG_C2_LP_MASK)) in CLOCK_GetFllFreq()
764 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
775 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
809 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
813 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
898 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
918 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1263 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
605 if (0U != (MCG->C2 & MCG_C2_LP_MASK)) in CLOCK_GetFllFreq()
769 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
780 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
814 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
818 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
903 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
923 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1268 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/drivers/
Dfsl_clock.c72 #define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
73 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
537 if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) in CLOCK_GetFllFreq()
637 MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
647 MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); in CLOCK_SetInternalRefClkConfig()
791 MCG->C2 &= ~MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
795 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
872 MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
886 MCG->C2 &= ~OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1160 if (MCG->C2 & MCG_C2_EREFS_MASK) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
Dsystem_MKW40Z4.c138 …MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_… in SystemInit()
160 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
165 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ in SystemInit()
171 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
189 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL in bypass mode */ in SystemInit()
227 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
277 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
Dsystem_MKW20Z4.c138 …MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_… in SystemInit()
160 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
165 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ in SystemInit()
171 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
189 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL in bypass mode */ in SystemInit()
227 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
277 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
Dsystem_MKW30Z4.c138 …MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_… in SystemInit()
160 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
165 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */ in SystemInit()
171 …MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C… in SystemInit()
189 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL in bypass mode */ in SystemInit()
227 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
277 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/drivers/
Dfsl_clock.c72 #define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
73 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
561 if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) in CLOCK_GetFllFreq()
690 MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
700 MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); in CLOCK_SetInternalRefClkConfig()
844 MCG->C2 &= ~MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
848 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
955 MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
969 MCG->C2 &= ~OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1244 if (MCG->C2 & MCG_C2_EREFS_MASK) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/drivers/
Dfsl_clock.c72 #define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
73 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
561 if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) in CLOCK_GetFllFreq()
690 MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
700 MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); in CLOCK_SetInternalRefClkConfig()
844 MCG->C2 &= ~MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
848 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
955 MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
969 MCG->C2 &= ~OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1244 if (MCG->C2 & MCG_C2_EREFS_MASK) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
613 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
790 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
801 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
983 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
987 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1119 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1139 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1495 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV56F24/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2_LP_SHIFT)
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
613 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
790 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
801 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
983 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
987 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1119 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1139 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1495 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/drivers/
Dfsl_clock.c54 #define MCG_C2_LP_VAL (((uint32_t)MCG->C2 & (uint32_t)MCG_C2_LP_MASK) >> (uint32_t)MCG_C2…
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
644 if ((((MCG->C2 & MCG_C2_LP_MASK) != 0U) || ((MCG->S & MCG_S_PLLST_MASK) != 0U))) in CLOCK_GetFllFreq()
849 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); in CLOCK_SetInternalRefClkConfig()
860 MCG->C2 = (uint8_t)((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs))); in CLOCK_SetInternalRefClkConfig()
1040 MCG->C2 &= ~(uint8_t)MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1044 MCG->C2 |= MCG_C2_LOCRE0_MASK; in CLOCK_SetOsc0MonitorMode()
1176 … MCG->C2 = (uint8_t)((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); in CLOCK_InitOsc0()
1196 MCG->C2 &= ~(uint8_t)OSC_MODE_MASK; in CLOCK_DeinitOsc0()
1553 if (0U != (MCG->C2 & MCG_C2_EREFS_MASK)) in CLOCK_SetFeeMode()
[all …]

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