1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_Boot.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_Boot 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_Boot_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_Boot_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- Boot Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup Boot_Peripheral_Access_Layer Boot Peripheral Access Layer 68 * @{ 69 */ 70 71 /** Boot - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t BOOT_GPR_BMR1; /**< Boot Configuration 1, offset: 0x0, available only on: BMR (missing on POR) */ 74 __I uint32_t BOOT_GPR_BMR2; /**< Boot Configuration 2, offset: 0x4, available only on: BMR (missing on POR) */ 75 uint8_t RESERVED_0[100]; 76 __IO uint32_t BOOT_POR_CTRL_REG; /**< Boot POR Control, offset: 0x6C, available only on: POR (missing on BMR) */ 77 __IO uint32_t BOOT_POR_C1_REG; /**< BOOT POR Control 1 Register, offset: 0x70, available only on: POR (missing on BMR) */ 78 uint8_t RESERVED_1[4]; 79 __IO uint32_t BOOT_DEST_C0_REG; /**< BOOT DEST Control 0 Register, offset: 0x78, available only on: POR (missing on BMR) */ 80 uint8_t RESERVED_2[8]; 81 __IO uint32_t BOOT_FUNC_C0_REG; /**< BOOT FUNC Control 0 Register, offset: 0x84, available only on: POR (missing on BMR) */ 82 } Boot_Type, *Boot_MemMapPtr; 83 84 /** Number of instances of the Boot module. */ 85 #define Boot_INSTANCE_COUNT (2u) 86 87 /* Boot - Peripheral instance base addresses */ 88 /** Peripheral BMR base address */ 89 #define IP_BMR_BASE (0x42280000u) 90 /** Peripheral BMR base pointer */ 91 #define IP_BMR ((Boot_Type *)IP_BMR_BASE) 92 /** Peripheral POR base address */ 93 #define IP_POR_BASE (0x42060000u) 94 /** Peripheral POR base pointer */ 95 #define IP_POR ((Boot_Type *)IP_POR_BASE) 96 /** Array initializer of Boot peripheral base addresses */ 97 #define IP_Boot_BASE_ADDRS { IP_BMR_BASE, IP_POR_BASE } 98 /** Array initializer of Boot peripheral base pointers */ 99 #define IP_Boot_BASE_PTRS { IP_BMR, IP_POR } 100 101 /* ---------------------------------------------------------------------------- 102 -- Boot Register Masks 103 ---------------------------------------------------------------------------- */ 104 105 /*! 106 * @addtogroup Boot_Register_Masks Boot Register Masks 107 * @{ 108 */ 109 110 /*! @name BOOT_GPR_BMR1 - Boot Configuration 1 */ 111 /*! @{ */ 112 113 #define Boot_BOOT_GPR_BMR1_BOOT_CFG_MASK (0xFFFFFFFFU) 114 #define Boot_BOOT_GPR_BMR1_BOOT_CFG_SHIFT (0U) 115 #define Boot_BOOT_GPR_BMR1_BOOT_CFG_WIDTH (32U) 116 #define Boot_BOOT_GPR_BMR1_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_GPR_BMR1_BOOT_CFG_SHIFT)) & Boot_BOOT_GPR_BMR1_BOOT_CFG_MASK) 117 /*! @} */ 118 119 /*! @name BOOT_GPR_BMR2 - Boot Configuration 2 */ 120 /*! @{ */ 121 122 #define Boot_BOOT_GPR_BMR2_FUSE_SEL_MASK (0x10U) 123 #define Boot_BOOT_GPR_BMR2_FUSE_SEL_SHIFT (4U) 124 #define Boot_BOOT_GPR_BMR2_FUSE_SEL_WIDTH (1U) 125 #define Boot_BOOT_GPR_BMR2_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_GPR_BMR2_FUSE_SEL_SHIFT)) & Boot_BOOT_GPR_BMR2_FUSE_SEL_MASK) 126 127 #define Boot_BOOT_GPR_BMR2_BOOTMODE2_MASK (0x1000000U) 128 #define Boot_BOOT_GPR_BMR2_BOOTMODE2_SHIFT (24U) 129 #define Boot_BOOT_GPR_BMR2_BOOTMODE2_WIDTH (1U) 130 #define Boot_BOOT_GPR_BMR2_BOOTMODE2(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_GPR_BMR2_BOOTMODE2_SHIFT)) & Boot_BOOT_GPR_BMR2_BOOTMODE2_MASK) 131 132 #define Boot_BOOT_GPR_BMR2_BOOTMODE1_MASK (0x2000000U) 133 #define Boot_BOOT_GPR_BMR2_BOOTMODE1_SHIFT (25U) 134 #define Boot_BOOT_GPR_BMR2_BOOTMODE1_WIDTH (1U) 135 #define Boot_BOOT_GPR_BMR2_BOOTMODE1(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_GPR_BMR2_BOOTMODE1_SHIFT)) & Boot_BOOT_GPR_BMR2_BOOTMODE1_MASK) 136 /*! @} */ 137 138 /*! @name BOOT_POR_CTRL_REG - Boot POR Control */ 139 /*! @{ */ 140 141 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_A_MASK (0xFFU) 142 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_A_SHIFT (0U) 143 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_A_WIDTH (8U) 144 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_A(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_A_SHIFT)) & Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_A_MASK) 145 146 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_B_MASK (0xFF00U) 147 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_B_SHIFT (8U) 148 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_B_WIDTH (8U) 149 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_B(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_B_SHIFT)) & Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_COUNT_B_MASK) 150 151 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_MARKER_MASK (0xFFFF0000U) 152 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_MARKER_SHIFT (16U) 153 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_MARKER_WIDTH (16U) 154 #define Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_MARKER(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_MARKER_SHIFT)) & Boot_BOOT_POR_CTRL_REG_HSE_FW_ROLLBACK_MARKER_MASK) 155 /*! @} */ 156 157 /*! @name BOOT_POR_C1_REG - BOOT POR Control 1 Register */ 158 /*! @{ */ 159 160 #define Boot_BOOT_POR_C1_REG_SELF_TEST_DCD_IMAGE_MASK (0xFFU) 161 #define Boot_BOOT_POR_C1_REG_SELF_TEST_DCD_IMAGE_SHIFT (0U) 162 #define Boot_BOOT_POR_C1_REG_SELF_TEST_DCD_IMAGE_WIDTH (8U) 163 #define Boot_BOOT_POR_C1_REG_SELF_TEST_DCD_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_POR_C1_REG_SELF_TEST_DCD_IMAGE_SHIFT)) & Boot_BOOT_POR_C1_REG_SELF_TEST_DCD_IMAGE_MASK) 164 165 #define Boot_BOOT_POR_C1_REG_DCD_IMAGE_SELECT_MASK (0xFF00U) 166 #define Boot_BOOT_POR_C1_REG_DCD_IMAGE_SELECT_SHIFT (8U) 167 #define Boot_BOOT_POR_C1_REG_DCD_IMAGE_SELECT_WIDTH (8U) 168 #define Boot_BOOT_POR_C1_REG_DCD_IMAGE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_POR_C1_REG_DCD_IMAGE_SELECT_SHIFT)) & Boot_BOOT_POR_C1_REG_DCD_IMAGE_SELECT_MASK) 169 170 #define Boot_BOOT_POR_C1_REG_APP_IMAGE_MASK (0xFF0000U) 171 #define Boot_BOOT_POR_C1_REG_APP_IMAGE_SHIFT (16U) 172 #define Boot_BOOT_POR_C1_REG_APP_IMAGE_WIDTH (8U) 173 #define Boot_BOOT_POR_C1_REG_APP_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_POR_C1_REG_APP_IMAGE_SHIFT)) & Boot_BOOT_POR_C1_REG_APP_IMAGE_MASK) 174 175 #define Boot_BOOT_POR_C1_REG_DDRC_IIA_IMAGE_MASK (0xFF000000U) 176 #define Boot_BOOT_POR_C1_REG_DDRC_IIA_IMAGE_SHIFT (24U) 177 #define Boot_BOOT_POR_C1_REG_DDRC_IIA_IMAGE_WIDTH (8U) 178 #define Boot_BOOT_POR_C1_REG_DDRC_IIA_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_POR_C1_REG_DDRC_IIA_IMAGE_SHIFT)) & Boot_BOOT_POR_C1_REG_DDRC_IIA_IMAGE_MASK) 179 /*! @} */ 180 181 /*! @name BOOT_DEST_C0_REG - BOOT DEST Control 0 Register */ 182 /*! @{ */ 183 184 #define Boot_BOOT_DEST_C0_REG_LPDDR4_FUNC_RESET_COUNTER_MASK (0x7U) 185 #define Boot_BOOT_DEST_C0_REG_LPDDR4_FUNC_RESET_COUNTER_SHIFT (0U) 186 #define Boot_BOOT_DEST_C0_REG_LPDDR4_FUNC_RESET_COUNTER_WIDTH (3U) 187 #define Boot_BOOT_DEST_C0_REG_LPDDR4_FUNC_RESET_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_DEST_C0_REG_LPDDR4_FUNC_RESET_COUNTER_SHIFT)) & Boot_BOOT_DEST_C0_REG_LPDDR4_FUNC_RESET_COUNTER_MASK) 188 /*! @} */ 189 190 /*! @name BOOT_FUNC_C0_REG - BOOT FUNC Control 0 Register */ 191 /*! @{ */ 192 193 #define Boot_BOOT_FUNC_C0_REG_DDRC_IIA_STATUS_MASK (0xFFFFFFFFU) 194 #define Boot_BOOT_FUNC_C0_REG_DDRC_IIA_STATUS_SHIFT (0U) 195 #define Boot_BOOT_FUNC_C0_REG_DDRC_IIA_STATUS_WIDTH (32U) 196 #define Boot_BOOT_FUNC_C0_REG_DDRC_IIA_STATUS(x) (((uint32_t)(((uint32_t)(x)) << Boot_BOOT_FUNC_C0_REG_DDRC_IIA_STATUS_SHIFT)) & Boot_BOOT_FUNC_C0_REG_DDRC_IIA_STATUS_MASK) 197 /*! @} */ 198 199 /*! 200 * @} 201 */ /* end of group Boot_Register_Masks */ 202 203 /*! 204 * @} 205 */ /* end of group Boot_Peripheral_Access_Layer */ 206 207 #endif /* #if !defined(S32Z2_Boot_H_) */ 208
