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Searched refs:BaseAddr (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/
DQspi_Ip_HwAccess.h54 static inline void Qspi_Ip_IpTrigger(QuadSPI_Type *BaseAddr, in Qspi_Ip_IpTrigger() argument
62 BaseAddr->IPCR = QuadSPI_IPCR_SEQID(SeqID) in Qspi_Ip_IpTrigger()
71 static inline void Qspi_Ip_ClearRxBuf(QuadSPI_Type *BaseAddr) in Qspi_Ip_ClearRxBuf() argument
73 BaseAddr->MCR |= QuadSPI_MCR_CLR_RXF_MASK; in Qspi_Ip_ClearRxBuf()
81 static inline void Qspi_Ip_ClearTxBuf(QuadSPI_Type *BaseAddr) in Qspi_Ip_ClearTxBuf() argument
83 BaseAddr->MCR |= QuadSPI_MCR_CLR_TXF_MASK; in Qspi_Ip_ClearTxBuf()
92 static inline boolean Qspi_Ip_GetClrTxStatus(const QuadSPI_Type *BaseAddr) in Qspi_Ip_GetClrTxStatus() argument
94 uint32 RegValue = (uint32)BaseAddr->MCR; in Qspi_Ip_GetClrTxStatus()
105 static inline void Qspi_Ip_ClearAhbBuf(QuadSPI_Type *BaseAddr) in Qspi_Ip_ClearAhbBuf() argument
107 BaseAddr->SPTRCLR |= QuadSPI_SPTRCLR_ABRT_CLR_MASK; in Qspi_Ip_ClearAhbBuf()
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DQspi_Ip_TrustedFunctions.h80 extern void Qspi_Ip_Sfp_ClearLatchedErrors_Privileged(QuadSPI_Type * BaseAddr);
82 extern void Qspi_Ip_ResetPrivilegedRegisters_Privileged(QuadSPI_Type * BaseAddr);
/hal_nxp-latest/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h55 static inline void Qspi_Ip_IpTrigger(QuadSPI_Type *BaseAddr, in Qspi_Ip_IpTrigger() argument
60 BaseAddr->IPCR = QuadSPI_IPCR_SEQID(SeqID) in Qspi_Ip_IpTrigger()
68 static inline void Qspi_Ip_ClearRxBuf(QuadSPI_Type *BaseAddr) in Qspi_Ip_ClearRxBuf() argument
70 BaseAddr->MCR |= QuadSPI_MCR_CLR_RXF_MASK; in Qspi_Ip_ClearRxBuf()
78 static inline void Qspi_Ip_ClearTxBuf(QuadSPI_Type *BaseAddr) in Qspi_Ip_ClearTxBuf() argument
80 BaseAddr->MCR |= QuadSPI_MCR_CLR_TXF_MASK; in Qspi_Ip_ClearTxBuf()
89 static inline boolean Qspi_Ip_GetClrTxStatus(const QuadSPI_Type *BaseAddr) in Qspi_Ip_GetClrTxStatus() argument
91 uint32 RegValue = (uint32)BaseAddr->MCR; in Qspi_Ip_GetClrTxStatus()
102 static inline void Qspi_Ip_ClearAhbBuf(QuadSPI_Type *BaseAddr) in Qspi_Ip_ClearAhbBuf() argument
104 BaseAddr->SPTRCLR |= QuadSPI_SPTRCLR_ABRT_CLR_MASK; in Qspi_Ip_ClearAhbBuf()
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DQspi_Ip_TrustedFunctions.h80 extern void Qspi_Ip_Sfp_ClearLatchedErrors_Privileged(QuadSPI_Type * BaseAddr);
82 extern void Qspi_Ip_ResetPrivilegedRegisters_Privileged(QuadSPI_Type * BaseAddr);
/hal_nxp-latest/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Controller.c225 void Qspi_Ip_ResetPrivilegedRegisters_Privileged(QuadSPI_Type *BaseAddr);
226 void Qspi_Ip_Sfp_ClearLatchedErrors_Privileged(QuadSPI_Type * BaseAddr);
230 inline static void Qspi_Ip_ResetAllRegisters(QuadSPI_Type *BaseAddr);
1125 QuadSPI_Type * BaseAddr) in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged() argument
1127 BaseAddr->ERRSTAT |= 0x1FFUL; in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged()
1128 BaseAddr->FLSEQREQ |= QuadSPI_FLSEQREQ_CLR_MASK; in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged()
1129 BaseAddr->IPSERROR |= QuadSPI_IPSERROR_CLR_MASK; in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged()
1133 BaseAddr->MDAD[Mdad].TGSFARS |= QuadSPI_TGSFARS_CLR_MASK; in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged()
1134 BaseAddr->MDAD[Mdad].TGIPCRS |= QuadSPI_TGIPCRS_CLR_MASK; in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged()
1229 QuadSPI_Type *BaseAddr = Qspi_Ip_BaseAddress[Instance]; in Qspi_Ip_WriteLuts_Privileged() local
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/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/src/
DQspi_Ip_Controller.c227 void Qspi_Ip_ResetPrivilegedRegisters_Privileged(QuadSPI_Type *BaseAddr);
228 void Qspi_Ip_Sfp_ClearLatchedErrors_Privileged(QuadSPI_Type * BaseAddr);
232 static inline void Qspi_Ip_ResetAllRegisters(QuadSPI_Type *BaseAddr);
1356 QuadSPI_Type * BaseAddr) in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged() argument
1358 BaseAddr->ERRSTAT |= 0x1FFUL; in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged()
1359 BaseAddr->FLSEQREQ |= QuadSPI_FLSEQREQ_CLR_MASK; in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged()
1360 BaseAddr->IPSERROR |= QuadSPI_IPSERROR_CLR_MASK; in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged()
1364 BaseAddr->MDAD[Mdad].TGSFARS |= QuadSPI_TGSFARS_CLR_MASK; in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged()
1365 BaseAddr->MDAD[Mdad].TGIPCRS |= QuadSPI_TGIPCRS_CLR_MASK; in Qspi_Ip_Sfp_ClearLatchedErrors_Privileged()
1466 QuadSPI_Type *BaseAddr = Qspi_Ip_BaseAddress[Instance]; in Qspi_Ip_WriteLuts_Privileged() local
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/hal_nxp-latest/mcux/mcux-sdk/drivers/lpflexcomm/
Dfsl_lpflexcomm.c115 pvoid_to_u32_t BaseAddr; in LP_FLEXCOMM_GetInstance() local
116 BaseAddr.pvoid = base; in LP_FLEXCOMM_GetInstance()
120 if (MSDK_REG_SECURE_ADDR(BaseAddr.u32) == MSDK_REG_SECURE_ADDR(s_lpflexcommBaseAddrs[i])) in LP_FLEXCOMM_GetInstance()
/hal_nxp-latest/s32/drivers/s32k3/Icu/src/
DEmios_Icu_Ip.c115 …all_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr) OsIf_Trusted_Call1param(Emios_Icu_Ip_SetUserAccess… argument
117 #define Call_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr)
120 #define Call_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr)
/hal_nxp-latest/s32/drivers/s32ze/Icu/src/
DEmios_Icu_Ip.c119 …all_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr) OsIf_Trusted_Call1param(Emios_Icu_Ip_SetUserAccess… argument
121 #define Call_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr)
124 #define Call_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr)