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123

/hal_nxp-latest/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h139 static inline boolean Emios_Pwm_Ip_GetDebugMode(const Emios_Pwm_Ip_HwAddrType *const Base) in Emios_Pwm_Ip_GetDebugMode() argument
141 return (((Base->MCR & eMIOS_MCR_FRZ_MASK) >> eMIOS_MCR_FRZ_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetDebugMode()
151 static inline void Emios_Pwm_Ip_SetOutputUpdate(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetOutputUpdate() argument
155 Base->OUDIS = Base->OUDIS | (eMIOS_OUDIS_OU0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetOutputUpdate()
163 static inline boolean Emios_Pwm_Ip_GetOutputUpdate(const Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_GetOutputUpdate() argument
166 …return (((Base->OUDIS & (uint32)((uint32)eMIOS_OUDIS_OU0_MASK << (uint32)Channel)) >> Channel) == … in Emios_Pwm_Ip_GetOutputUpdate()
173 static inline uint32 Emios_Pwm_Ip_GetOutputUpdateInstance(const Emios_Pwm_Ip_HwAddrType *const Base) in Emios_Pwm_Ip_GetOutputUpdateInstance() argument
175 return (Base->OUDIS); in Emios_Pwm_Ip_GetOutputUpdateInstance()
185 static inline void Emios_Pwm_Ip_SetChannelEnable(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetChannelEnable() argument
189 Base->UCDIS = Base->UCDIS | (eMIOS_UCDIS_UCDIS0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetChannelEnable()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h156 static inline boolean Emios_Pwm_Ip_GetDebugMode(const Emios_Pwm_Ip_HwAddrType *const Base) in Emios_Pwm_Ip_GetDebugMode() argument
158 return (((Base->MCR & eMIOS_MCR_FRZ_MASK) >> eMIOS_MCR_FRZ_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetDebugMode()
168 static inline void Emios_Pwm_Ip_SetOutputUpdate(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetOutputUpdate() argument
173 Base->OUDIS = Base->OUDIS | (eMIOS_OUDIS_OU0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetOutputUpdate()
181 static inline boolean Emios_Pwm_Ip_GetOutputUpdate(const Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_GetOutputUpdate() argument
185 …return (((Base->OUDIS & (uint32)((uint32)eMIOS_OUDIS_OU0_MASK << (uint32)Channel)) >> Channel) == … in Emios_Pwm_Ip_GetOutputUpdate()
192 static inline uint32 Emios_Pwm_Ip_GetOutputUpdateInstance(const Emios_Pwm_Ip_HwAddrType *const Base) in Emios_Pwm_Ip_GetOutputUpdateInstance() argument
194 return (Base->OUDIS); in Emios_Pwm_Ip_GetOutputUpdateInstance()
204 static inline void Emios_Pwm_Ip_SetUCRegA(Emios_Pwm_Ip_HwAddrType *const Base, in Emios_Pwm_Ip_SetUCRegA() argument
209 Base->CH.UC[Channel].A = eMIOS_A_A(Value); in Emios_Pwm_Ip_SetUCRegA()
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/hal_nxp-latest/s32/drivers/s32k3/Pwm/src/
DEmios_Pwm_Ip.c297 const Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_GetCounterBusMode() local
302 …CounterBusMode = (Emios_Pwm_Ip_MasterBusModeType)Emios_Pwm_Ip_GetChannelPwmMode(Base, EMIOS_PWM_IP… in Emios_Pwm_Ip_GetCounterBusMode()
305 …CounterBusMode = (Emios_Pwm_Ip_MasterBusModeType)Emios_Pwm_Ip_GetChannelPwmMode(Base, (Channel & (… in Emios_Pwm_Ip_GetCounterBusMode()
308 …CounterBusMode = (Emios_Pwm_Ip_MasterBusModeType)Emios_Pwm_Ip_GetChannelPwmMode(Base, EMIOS_PWM_IP… in Emios_Pwm_Ip_GetCounterBusMode()
343 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode() local
347 Emios_Pwm_Ip_SetCounterBus(Base, UserChCfg->ChannelId, UserChCfg->Timebase); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
349 Emios_Pwm_Ip_SetUCRegA(Base, UserChCfg->ChannelId, UserChCfg->DutyCycle); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
351 Emios_Pwm_Ip_SetUCRegB(Base, UserChCfg->ChannelId, UserChCfg->PeriodCount); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
361 Emios_Pwm_Ip_SetEdgePolarity(Base, UserChCfg->ChannelId, UserChCfg->OutputPolarity); in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
368 …Emios_Pwm_Ip_SetEdgePolarity(Base, UserChCfg->ChannelId,(UserChCfg->OutputPolarity == EMIOS_PWM_IP… in Emios_Pwm_Ip_InitPeriodDutyCycleOpwfmbMode()
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/hal_nxp-latest/s32/drivers/s32ze/Uart/src/
DLinflexd_Uart_Ip.c220 static void Linflexd_Uart_Ip_FlushRxFifo(const LINFLEXD_Type *Base,const Linflexd_Uart_Ip_WordLengt…
237 static void Linflexd_Uart_Ip_SetTransmitterState(LINFLEXD_Type *Base, boolean Enable);
238 static void Linflexd_Uart_Ip_SetReceiverState(LINFLEXD_Type *Base, boolean Enable);
239 static void Linflexd_Uart_Ip_SetInterruptMode(LINFLEXD_Type * Base, Linflexd_Uart_Ip_InterruptType …
245 static boolean Linflexd_Uart_Ip_SetUp_EnterInitMode(LINFLEXD_Type *Base);
262 LINFLEXD_Type * Base; in Linflexd_Uart_Ip_SetBaudrate() local
275 Base = Linflexd_Uart_Ip_apBases[Instance]; in Linflexd_Uart_Ip_SetBaudrate()
287 Base->UARTCR &= ~LINFLEXD_UARTCR_ROSE(1); in Linflexd_Uart_Ip_SetBaudrate()
305 if (Linflexd_Uart_Ip_GetLinState(Base) != LINFLEXD_STATE_INIT_MODE) in Linflexd_Uart_Ip_SetBaudrate()
308 if (Linflexd_Uart_Ip_SetUp_EnterInitMode(Base) != TRUE) in Linflexd_Uart_Ip_SetBaudrate()
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/hal_nxp-latest/s32/drivers/s32ze/Pwm/src/
DEmios_Pwm_Ip.c300 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetOutputToNormalOpwfm() local
304 …Emios_Pwm_Ip_SetPwmModePol(Base, Channel, Mode, (Polarity == EMIOS_PWM_IP_ACTIVE_HIGH) ? EMIOS_PWM… in Emios_Pwm_Ip_SetOutputToNormalOpwfm()
308 …Emios_Pwm_Ip_SetPwmModePol(Base, Channel, Mode, (Polarity == EMIOS_PWM_IP_ACTIVE_HIGH) ? EMIOS_PWM… in Emios_Pwm_Ip_SetOutputToNormalOpwfm()
311 Emios_Pwm_Ip_SetPwmMode(Base, Channel, Mode); in Emios_Pwm_Ip_SetOutputToNormalOpwfm()
315 …Emios_Pwm_Ip_SetPwmModePol(Base, Channel, Mode, (Polarity == EMIOS_PWM_IP_ACTIVE_HIGH) ? EMIOS_PWM… in Emios_Pwm_Ip_SetOutputToNormalOpwfm()
338 Emios_Pwm_Ip_HwAddrType *const Base = Emios_Pwm_Ip_aBasePtr[Instance]; in Emios_Pwm_Ip_SetOutputToNormalOpwm() local
345 …Emios_Pwm_Ip_SetPwmModePol(Base, Channel, Mode, (Polarity == EMIOS_PWM_IP_ACTIVE_HIGH) ? EMIOS_PWM… in Emios_Pwm_Ip_SetOutputToNormalOpwm()
349 …Emios_Pwm_Ip_SetPwmModePol(Base, Channel, Mode, (Polarity == EMIOS_PWM_IP_ACTIVE_HIGH) ? EMIOS_PWM… in Emios_Pwm_Ip_SetOutputToNormalOpwm()
352 Emios_Pwm_Ip_SetPwmMode(Base, Channel, Mode); in Emios_Pwm_Ip_SetOutputToNormalOpwm()
357 …Emios_Pwm_Ip_SetPwmModePol(Base, Channel, Mode, (Polarity == EMIOS_PWM_IP_ACTIVE_HIGH) ? EMIOS_PWM… in Emios_Pwm_Ip_SetOutputToNormalOpwm()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Uart/include/
DLinflexd_Uart_Ip_HwAccess.h246 static inline void Linflexd_Uart_Ip_EnterInitMode(LINFLEXD_Type *Base) in Linflexd_Uart_Ip_EnterInitMode() argument
250 RegValTemp = Base->LINCR1; in Linflexd_Uart_Ip_EnterInitMode()
253 Base->LINCR1 = RegValTemp; in Linflexd_Uart_Ip_EnterInitMode()
264 static inline void Linflexd_Uart_Ip_EnterNormalMode(LINFLEXD_Type *Base) in Linflexd_Uart_Ip_EnterNormalMode() argument
268 RegValTemp = Base->LINCR1; in Linflexd_Uart_Ip_EnterNormalMode()
271 Base->LINCR1 = RegValTemp; in Linflexd_Uart_Ip_EnterNormalMode()
283 static inline void Linflexd_Uart_Ip_SetMode(LINFLEXD_Type *Base, Linflexd_Uart_Ip_ModeType Mode) in Linflexd_Uart_Ip_SetMode() argument
287 RegValTemp = Base->UARTCR; in Linflexd_Uart_Ip_SetMode()
290 Base->UARTCR = RegValTemp; in Linflexd_Uart_Ip_SetMode()
303 static inline void Linflexd_Uart_Ip_EnableMonitorIdleState(LINFLEXD_Type *Base, boolean Enable) in Linflexd_Uart_Ip_EnableMonitorIdleState() argument
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/hal_nxp-latest/s32/drivers/s32k3/Eth_GMAC/src/
DGmac_Ip.c284 static void Gmac_Ip_InitSafetyEvents(GMAC_Type *Base,
297 static void Gmac_Ip_InitMAC(GMAC_Type *Base,
300 static void Gmac_Ip_GetTimestamp(const GMAC_Type *Base,
368 const GMAC_Type *Base; in Gmac_Ip_ReadTimeStampInfo() local
374 Base = Gmac_apxBases[Instance]; in Gmac_Ip_ReadTimeStampInfo()
382 CurrTimeSec = (uint32)(Base->MAC_SYSTEM_TIME_SECONDS); in Gmac_Ip_ReadTimeStampInfo()
383 CurrTimeSecHi = (uint16)(Base->MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS); in Gmac_Ip_ReadTimeStampInfo()
419 GMAC_Type *Base; in Gmac_Ip_InitDMA() local
425 Base = Gmac_apxBases[Instance]; in Gmac_Ip_InitDMA()
428 Base->DMA_MODE |= GMAC_DMA_MODE_SWR_MASK; in Gmac_Ip_InitDMA()
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DGmac_Ip_Hw_Access.c211 const GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_IrqFSMDPPHandler() local
225 GMAC_IrqFSMHandler(Instance, ErrorStatusFlags, Base->MAC_FSM_CONTROL); in GMAC_IrqFSMDPPHandler()
255 const GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_MACIRQHandler() local
258 if ((Base->DMA_INTERRUPT_STATUS & GMAC_DMA_INTERRUPT_STATUS_MACIS_MASK) != 0U) in GMAC_MACIRQHandler()
261 Flags = Base->MAC_INTERRUPT_STATUS; in GMAC_MACIRQHandler()
272 (void)Base->MAC_PHYIF_CONTROL_STATUS; in GMAC_MACIRQHandler()
277 (void)Base->MAC_FPE_CTRL_STS; in GMAC_MACIRQHandler()
282 (void)Base->MAC_RX_TX_STATUS; in GMAC_MACIRQHandler()
333 Gmac_Ip_StatusType GMAC_WriteManagementFrame(GMAC_Type * Base, in GMAC_WriteManagementFrame() argument
342 Base->MAC_MDIO_ADDRESS &= ~(GMAC_MAC_MDIO_ADDRESS_PA_MASK | in GMAC_WriteManagementFrame()
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/hal_nxp-latest/s32/drivers/s32ze/Platform/src/
DMru_Ip_Irq.c373 SMU_MRU_Type* Base = Mru_Ip_apxSMU_Bases[MRU_IP_SMU_MRU_INSTANCE]; in ISR() local
389 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
397 SMU_MRU_Type* Base = Mru_Ip_apxSMU_Bases[MRU_IP_SMU_MRU_INSTANCE]; in ISR() local
413 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
424 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU0_INSTANCE]; in ISR() local
440 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
448 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU0_INSTANCE]; in ISR() local
464 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
475 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU1_INSTANCE]; in ISR() local
491 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
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/hal_nxp-latest/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c259 static uint16 Spi_Ip_WriteCmdFifo(Spi_Ip_StateStructureType* State, SPI_Type *Base) in Spi_Ip_WriteCmdFifo() argument
264 NumberOfCmdWrites = (uint16)((Base->SREX) & SPI_SREX_CMDCTR_MASK) >> SPI_SREX_CMDCTR_SHIFT; in Spi_Ip_WriteCmdFifo()
283 Base->PUSHR.FIFO.CMD = State->PushrCmds[State->NbCmdsIndex]; in Spi_Ip_WriteCmdFifo()
299 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_TransferProcess() local
308 SrStatusRegister = Base->SR; in Spi_Ip_TransferProcess()
309 Base->SR &= 0xFFFF0000u; in Spi_Ip_TransferProcess()
319 NumberOfReads = (uint16)(((Base->SR) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT); in Spi_Ip_TransferProcess()
332 (void)Spi_Ip_WriteCmdFifo(State, Base); in Spi_Ip_TransferProcess()
361 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_TransferProcess()
365 Base->RSER = 0U; in Spi_Ip_TransferProcess()
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/hal_nxp-latest/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip.c169 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_Init() local
185 Base->MCR &= ~eMIOS_MCR_GPREN_MASK; in Emios_Mcl_Ip_Init()
186 …Base->MCR = eMIOS_MCR_GPRE(ConfigPtr->emiosGlobalConfig->clkDivVal) | eMIOS_MCR_FRZ(((uint32)Confi… in Emios_Mcl_Ip_Init()
194 … Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_FREN_MASK; in Emios_Mcl_Ip_Init()
198 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C2 |= eMIOS_C2_UCEXTPRE((*Con… in Emios_Mcl_Ip_Init()
203 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
206 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
209 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].B = 0; in Emios_Mcl_Ip_Init()
210 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
213 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Mcl/src/
DEmios_Mcl_Ip.c169 eMIOS_Type* Base = Emios_Ip_paxBase[Instance]; in Emios_Mcl_Ip_Init() local
185 Base->MCR &= ~eMIOS_MCR_GPREN_MASK; in Emios_Mcl_Ip_Init()
186 …Base->MCR = eMIOS_MCR_GPRE(ConfigPtr->emiosGlobalConfig->clkDivVal) | eMIOS_MCR_FRZ(((uint32)Confi… in Emios_Mcl_Ip_Init()
194 … Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_FREN_MASK; in Emios_Mcl_Ip_Init()
198 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C2 |= eMIOS_C2_UCEXTPRE((*Con… in Emios_Mcl_Ip_Init()
203 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
206 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
209 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].B = 0; in Emios_Mcl_Ip_Init()
210 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
213 …Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusCon… in Emios_Mcl_Ip_Init()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Eth_GMAC/include/
DGmac_Ip_Hw_Access.h160 void GMAC_AddToHashTable(const GMAC_Type * Base,
169 void GMAC_RemoveFromHashTable(const GMAC_Type * Base,
178 void GMAC_AddVlanToHashTable(GMAC_Type * Base,
187 void GMAC_RemoveVlanFromHashTable(GMAC_Type * Base,
205 Gmac_Ip_StatusType GMAC_WriteManagementFrame(GMAC_Type * Base,
215 static inline uint16 GMAC_ReadManagementFrameData(const GMAC_Type * Base) in GMAC_ReadManagementFrameData() argument
217 return (uint16)(Base->MAC_MDIO_DATA & GMAC_MAC_MDIO_DATA_GD_MASK); in GMAC_ReadManagementFrameData()
272 Gmac_Ip_PowerStateType GMAC_GetPowerState(const GMAC_Type * Base);
280 void GMAC_SetPowerState(GMAC_Type * Base, Gmac_Ip_PowerStateType PowerState);
288 void GMAC_SetSpeed(GMAC_Type * Base, Gmac_Ip_SpeedType Speed);
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/hal_nxp-latest/mcux/mcux-sdk/components/rtt/RTT/
DSEGGER_RTT_printf.c145 unsigned Base, in _PrintUnsigned() argument
163 while (Number >= Base) in _PrintUnsigned()
165 Number = (Number / Base); in _PrintUnsigned()
215 if (Div < Base) in _PrintUnsigned()
220 Digit *= Base; in _PrintUnsigned()
234 Digit /= Base; in _PrintUnsigned()
263 unsigned Base, in _PrintInt() argument
277 while (Number >= (int)Base) in _PrintInt()
279 Number = (Number / (int)Base); in _PrintInt()
353 _PrintUnsigned(pBufferDesc, (unsigned)v, Base, NumDigits, FieldWidth, FormatFlags); in _PrintInt()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1180/
Dboard.c203 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
205 extern uint32_t Image$$RW_m_ncache_aux$$Base[]; in BOARD_ConfigMPU()
206 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; in BOARD_ConfigMPU()
207 uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; in BOARD_ConfigMPU()
221 extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; in BOARD_ConfigMPU()
223 extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; in BOARD_ConfigMPU()
224 uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; in BOARD_ConfigMPU()
225 uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart; in BOARD_ConfigMPU()
407 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
409 extern uint32_t Image$$RW_m_ncache_aux$$Base[]; in BOARD_ConfigMPU()
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/hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/include/
DCanEXCEL_Ip_HwAccess.h555 static inline void CanXL_SetXLErrorResponse(CANXL_SIC_Type * Base, boolean Enable) in CanXL_SetXLErrorResponse() argument
557 …Base->BCFG2 = (Base->BCFG2 & ~CANXL_SIC_BCFG2_XLER_MASK) | CANXL_SIC_BCFG2_XLER(Enable ? 1UL : 0UL… in CanXL_SetXLErrorResponse()
565 static inline void CanXL_SetPwmModeEnable(CANXL_SIC_Type * Base, boolean Enable) in CanXL_SetPwmModeEnable() argument
567 …Base->BCFG2 = (Base->BCFG2 & ~CANXL_SIC_BCFG2_TMSE_MASK) | CANXL_SIC_BCFG2_TMSE(Enable ? 1UL : 0UL… in CanXL_SetPwmModeEnable()
576 static inline boolean CanXL_IsPwmModeEnable(const CANXL_SIC_Type * Base) in CanXL_IsPwmModeEnable() argument
578 return (((Base->BCFG2 & (CANXL_SIC_BCFG2_TMSE_MASK)) != 0U) ? TRUE : FALSE); in CanXL_IsPwmModeEnable()
585 static inline void CanXL_SetPWMPhases(CANXL_SIC_Type * Base, uint8 PWMS, uint8 PWML, uint8 PWMO) in CanXL_SetPWMPhases() argument
587 …Base->BMICI &= ~(CANXL_SIC_BMICI_PWMS_MASK | CANXL_SIC_BMICI_PWML_MASK | CANXL_SIC_BMICI_PWMO_MASK… in CanXL_SetPWMPhases()
588 …Base->BMICI |= (CANXL_SIC_BMICI_PWMS(PWMS) | CANXL_SIC_BMICI_PWML(PWML) | CANXL_SIC_BMICI_PWMO(PWM… in CanXL_SetPWMPhases()
/hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip.c1753 CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_SetFDBaudRate() local
1760 if (TRUE == CanXL_IsFreezeMode(Base)) in Canexcel_Ip_SetFDBaudRate()
1762 if (TRUE == CanXL_IsFDModeEnabled(Base)) in Canexcel_Ip_SetFDBaudRate()
1764 CanXL_SetFDEnabled(Base, TRUE, BitRateSwitch); in Canexcel_Ip_SetFDBaudRate()
1765 CanXL_SetFDBaudRate(Base, TimeSeg); in Canexcel_Ip_SetFDBaudRate()
1783 CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_SetXLBaudRate() local
1790 if (TRUE == CanXL_IsFreezeMode(Base)) in Canexcel_Ip_SetXLBaudRate()
1792 if (TRUE == CanXL_IsXLModeEnabled(Base)) in Canexcel_Ip_SetXLBaudRate()
1794 CanXL_SetXLBaudRate(Base, TimeSeg); in Canexcel_Ip_SetXLBaudRate()
1812 CANXL_SIC_Type * Base = CANEXCEL.EXL_SIC[Instance]; in Canexcel_Ip_SetBaudRate() local
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1160/
Dboard.c265 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
267 extern uint32_t Image$$RW_m_ncache_unused$$Base[]; in BOARD_ConfigMPU()
269 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; in BOARD_ConfigMPU()
270 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? in BOARD_ConfigMPU()
466 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
468 extern uint32_t Image$$RW_m_ncache_unused$$Base[]; in BOARD_ConfigMPU()
470 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; in BOARD_ConfigMPU()
471 uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? in BOARD_ConfigMPU()
487 extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; in BOARD_ConfigMPU()
489 extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[]; in BOARD_ConfigMPU()
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/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1170/
Dboard.c265 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
267 extern uint32_t Image$$RW_m_ncache_unused$$Base[]; in BOARD_ConfigMPU()
269 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; in BOARD_ConfigMPU()
270 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? in BOARD_ConfigMPU()
466 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
468 extern uint32_t Image$$RW_m_ncache_unused$$Base[]; in BOARD_ConfigMPU()
470 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; in BOARD_ConfigMPU()
471 uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? in BOARD_ConfigMPU()
487 extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; in BOARD_ConfigMPU()
489 extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[]; in BOARD_ConfigMPU()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1170/
Dboard.c265 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
267 extern uint32_t Image$$RW_m_ncache_unused$$Base[]; in BOARD_ConfigMPU()
269 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; in BOARD_ConfigMPU()
270 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? in BOARD_ConfigMPU()
466 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
468 extern uint32_t Image$$RW_m_ncache_unused$$Base[]; in BOARD_ConfigMPU()
470 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; in BOARD_ConfigMPU()
471 uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? in BOARD_ConfigMPU()
487 extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; in BOARD_ConfigMPU()
489 extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[]; in BOARD_ConfigMPU()
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/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1180/xip/
Devkmimxrt1180_flexspi_nor_config.h112 extern uint32_t Image$$ER_m_container_image_offset$$ZI$$Base[];
113 extern uint32_t Image$$VECTOR_ROM$$Base[];
115 #define IMAGE_OFFSET ((uint32_t)Image$$ER_m_container_image_offset$$ZI$$Base)
117 #define IMAGE_LOAD_ADDRESS ((uint32_t)Image$$VECTOR_ROM$$Base)
118 #define IMAGE_ENTRY_ADDRESS ((uint32_t)Image$$VECTOR_ROM$$Base)
/hal_nxp-latest/mcux/mcux-sdk/drivers/common/
Dfsl_common_arm.c26 extern uint32_t Image$$VECTOR_ROM$$Base[]; in InstallIRQHandler()
27 extern uint32_t Image$$VECTOR_RAM$$Base[]; in InstallIRQHandler()
30 #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base in InstallIRQHandler()
31 #define __VECTOR_RAM Image$$VECTOR_RAM$$Base in InstallIRQHandler()
32 …AM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base)) in InstallIRQHandler()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1015/
Dboard.c55 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
57 extern uint32_t Image$$RW_m_ncache_unused$$Base[]; in BOARD_ConfigMPU()
59 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; in BOARD_ConfigMPU()
60 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? in BOARD_ConfigMPU()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1010/
Dboard.c55 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
57 extern uint32_t Image$$RW_m_ncache_unused$$Base[]; in BOARD_ConfigMPU()
59 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; in BOARD_ConfigMPU()
60 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? in BOARD_ConfigMPU()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1020/
Dboard.c55 extern uint32_t Image$$RW_m_ncache$$Base[]; in BOARD_ConfigMPU()
57 extern uint32_t Image$$RW_m_ncache_unused$$Base[]; in BOARD_ConfigMPU()
59 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; in BOARD_ConfigMPU()
60 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? in BOARD_ConfigMPU()

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