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Searched refs:AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h10895 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10905 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
DMIMXRT1175_cm7.h10898 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10908 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h10586 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10596 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
DMIMXRT1165_cm4.h10583 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10593 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h10898 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10908 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h10598 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10608 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
DMIMXRT1166_cm7.h10601 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10611 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h10907 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10917 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
DMIMXRT1173_cm7.h10910 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10920 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h10913 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10923 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h10915 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10925 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
DMIMXRT1176_cm4.h10912 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) macro
10922 …t32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)