1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_ATP.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_ATP 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_ATP_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_ATP_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ATP Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ATP_Peripheral_Access_Layer ATP Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ATP - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t PLLC; /**< PLL Control, offset: 0x0 */ 74 __IO uint32_t PLLS; /**< PLL Status, offset: 0x4 */ 75 __IO uint32_t PLLDIV; /**< PLL Divider, offset: 0x8 */ 76 uint8_t RESERVED_0[12]; 77 __IO uint32_t PLLCAL_2; /**< PLL Calibration 2, offset: 0x18 */ 78 uint8_t RESERVED_1[4]; 79 __IO uint32_t PLLCKMUX; /**< PLL Clock MUX, offset: 0x20 */ 80 uint8_t RESERVED_2[732]; 81 __I uint32_t ALS; /**< AL Status, offset: 0x300 */ 82 uint8_t RESERVED_3[4]; 83 __IO uint32_t ALGC; /**< AL General Control, offset: 0x308 */ 84 __IO uint32_t ALTC; /**< AL Training Control, offset: 0x30C */ 85 uint8_t RESERVED_4[304]; 86 __IO uint32_t LVDSTX; /**< LVDS TX IO Configuration, offset: 0x440 */ 87 __IO uint32_t LVDSRX; /**< LVDS RX IO Configuration, offset: 0x444 */ 88 __IO uint32_t LVDSTXOBE; /**< LVDS TX OBE Configuration, offset: 0x448 */ 89 uint8_t RESERVED_5[52]; 90 __IO uint32_t CIAC; /**< CIA Control, offset: 0x480 */ 91 uint8_t RESERVED_6[4]; 92 __IO uint32_t ATPE; /**< Aurora Trace Port Enable, offset: 0x488 */ 93 uint8_t RESERVED_7[2676]; 94 __I uint32_t ITCTRL; /**< Integration Mode Control, offset: 0xF00 */ 95 uint8_t RESERVED_8[156]; 96 __I uint32_t CLAIMSET; /**< Claim Tag Set, offset: 0xFA0 */ 97 __I uint32_t CLAIMCLR; /**< Claim Tag Clear, offset: 0xFA4 */ 98 __I uint32_t DEVAFF0; /**< Device Affinity 0, offset: 0xFA8 */ 99 __I uint32_t DEVAFF1; /**< Device Affinity 1, offset: 0xFAC */ 100 __O uint32_t LAR; /**< Lock Access Register, offset: 0xFB0 */ 101 __I uint32_t LSR; /**< Lock Status Register, offset: 0xFB4 */ 102 __I uint32_t AUTHSTATUS; /**< Authentication Status, offset: 0xFB8 */ 103 __I uint32_t DEVARCH; /**< Device Architecture, offset: 0xFBC */ 104 __I uint32_t DEVID2; /**< Device Configuration 2, offset: 0xFC0 */ 105 __I uint32_t DEVID1; /**< Device Configuration 1, offset: 0xFC4 */ 106 __I uint32_t DEVID; /**< Device Configuration, offset: 0xFC8 */ 107 __I uint32_t DEVTYPE; /**< Device Type Identifier, offset: 0xFCC */ 108 __I uint32_t PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ 109 uint8_t RESERVED_9[12]; 110 __I uint32_t PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ 111 __I uint32_t PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ 112 __I uint32_t PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ 113 __I uint32_t PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ 114 __I uint32_t CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ 115 __I uint32_t CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ 116 __I uint32_t CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ 117 __I uint32_t CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ 118 } ATP_Type, *ATP_MemMapPtr; 119 120 /** Number of instances of the ATP module. */ 121 #define ATP_INSTANCE_COUNT (1u) 122 123 /* ATP - Peripheral instance base addresses */ 124 /** Peripheral ATP base address */ 125 #define IP_ATP_BASE (0x4D190000u) 126 /** Peripheral ATP base pointer */ 127 #define IP_ATP ((ATP_Type *)IP_ATP_BASE) 128 /** Array initializer of ATP peripheral base addresses */ 129 #define IP_ATP_BASE_ADDRS { IP_ATP_BASE } 130 /** Array initializer of ATP peripheral base pointers */ 131 #define IP_ATP_BASE_PTRS { IP_ATP } 132 133 /* ---------------------------------------------------------------------------- 134 -- ATP Register Masks 135 ---------------------------------------------------------------------------- */ 136 137 /*! 138 * @addtogroup ATP_Register_Masks ATP Register Masks 139 * @{ 140 */ 141 142 /*! @name PLLC - PLL Control */ 143 /*! @{ */ 144 145 #define ATP_PLLC_PLLPD_MASK (0x80000000U) 146 #define ATP_PLLC_PLLPD_SHIFT (31U) 147 #define ATP_PLLC_PLLPD_WIDTH (1U) 148 #define ATP_PLLC_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << ATP_PLLC_PLLPD_SHIFT)) & ATP_PLLC_PLLPD_MASK) 149 /*! @} */ 150 151 /*! @name PLLS - PLL Status */ 152 /*! @{ */ 153 154 #define ATP_PLLS_LOCK_MASK (0x4U) 155 #define ATP_PLLS_LOCK_SHIFT (2U) 156 #define ATP_PLLS_LOCK_WIDTH (1U) 157 #define ATP_PLLS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << ATP_PLLS_LOCK_SHIFT)) & ATP_PLLS_LOCK_MASK) 158 159 #define ATP_PLLS_LOL_MASK (0x8U) 160 #define ATP_PLLS_LOL_SHIFT (3U) 161 #define ATP_PLLS_LOL_WIDTH (1U) 162 #define ATP_PLLS_LOL(x) (((uint32_t)(((uint32_t)(x)) << ATP_PLLS_LOL_SHIFT)) & ATP_PLLS_LOL_MASK) 163 /*! @} */ 164 165 /*! @name PLLDIV - PLL Divider */ 166 /*! @{ */ 167 168 #define ATP_PLLDIV_MFID_MASK (0xFFU) 169 #define ATP_PLLDIV_MFID_SHIFT (0U) 170 #define ATP_PLLDIV_MFID_WIDTH (8U) 171 #define ATP_PLLDIV_MFID(x) (((uint32_t)(((uint32_t)(x)) << ATP_PLLDIV_MFID_SHIFT)) & ATP_PLLDIV_MFID_MASK) 172 173 #define ATP_PLLDIV_RDIV_MASK (0x7000U) 174 #define ATP_PLLDIV_RDIV_SHIFT (12U) 175 #define ATP_PLLDIV_RDIV_WIDTH (3U) 176 #define ATP_PLLDIV_RDIV(x) (((uint32_t)(((uint32_t)(x)) << ATP_PLLDIV_RDIV_SHIFT)) & ATP_PLLDIV_RDIV_MASK) 177 178 #define ATP_PLLDIV_ODIV1_MASK (0x3F0000U) 179 #define ATP_PLLDIV_ODIV1_SHIFT (16U) 180 #define ATP_PLLDIV_ODIV1_WIDTH (6U) 181 #define ATP_PLLDIV_ODIV1(x) (((uint32_t)(((uint32_t)(x)) << ATP_PLLDIV_ODIV1_SHIFT)) & ATP_PLLDIV_ODIV1_MASK) 182 /*! @} */ 183 184 /*! @name PLLCAL_2 - PLL Calibration 2 */ 185 /*! @{ */ 186 187 #define ATP_PLLCAL_2_CALDPER_MASK (0x60000U) 188 #define ATP_PLLCAL_2_CALDPER_SHIFT (17U) 189 #define ATP_PLLCAL_2_CALDPER_WIDTH (2U) 190 #define ATP_PLLCAL_2_CALDPER(x) (((uint32_t)(((uint32_t)(x)) << ATP_PLLCAL_2_CALDPER_SHIFT)) & ATP_PLLCAL_2_CALDPER_MASK) 191 /*! @} */ 192 193 /*! @name PLLCKMUX - PLL Clock MUX */ 194 /*! @{ */ 195 196 #define ATP_PLLCKMUX_REFCLKSEL_MASK (0x3U) 197 #define ATP_PLLCKMUX_REFCLKSEL_SHIFT (0U) 198 #define ATP_PLLCKMUX_REFCLKSEL_WIDTH (2U) 199 #define ATP_PLLCKMUX_REFCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << ATP_PLLCKMUX_REFCLKSEL_SHIFT)) & ATP_PLLCKMUX_REFCLKSEL_MASK) 200 /*! @} */ 201 202 /*! @name ALS - AL Status */ 203 /*! @{ */ 204 205 #define ATP_ALS_AS_MASK (0x1U) 206 #define ATP_ALS_AS_SHIFT (0U) 207 #define ATP_ALS_AS_WIDTH (1U) 208 #define ATP_ALS_AS(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALS_AS_SHIFT)) & ATP_ALS_AS_MASK) 209 210 #define ATP_ALS_CS_MASK (0x2U) 211 #define ATP_ALS_CS_SHIFT (1U) 212 #define ATP_ALS_CS_WIDTH (1U) 213 #define ATP_ALS_CS(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALS_CS_SHIFT)) & ATP_ALS_CS_MASK) 214 215 #define ATP_ALS_TS_MASK (0xCU) 216 #define ATP_ALS_TS_SHIFT (2U) 217 #define ATP_ALS_TS_WIDTH (2U) 218 #define ATP_ALS_TS(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALS_TS_SHIFT)) & ATP_ALS_TS_MASK) 219 220 #define ATP_ALS_PRST_MASK (0x200U) 221 #define ATP_ALS_PRST_SHIFT (9U) 222 #define ATP_ALS_PRST_WIDTH (1U) 223 #define ATP_ALS_PRST(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALS_PRST_SHIFT)) & ATP_ALS_PRST_MASK) 224 225 #define ATP_ALS_TXCFG_MASK (0x1C00U) 226 #define ATP_ALS_TXCFG_SHIFT (10U) 227 #define ATP_ALS_TXCFG_WIDTH (3U) 228 #define ATP_ALS_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALS_TXCFG_SHIFT)) & ATP_ALS_TXCFG_MASK) 229 /*! @} */ 230 231 /*! @name ALGC - AL General Control */ 232 /*! @{ */ 233 234 #define ATP_ALGC_CCOEN_MASK (0x4U) 235 #define ATP_ALGC_CCOEN_SHIFT (2U) 236 #define ATP_ALGC_CCOEN_WIDTH (1U) 237 #define ATP_ALGC_CCOEN(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALGC_CCOEN_SHIFT)) & ATP_ALGC_CCOEN_MASK) 238 239 #define ATP_ALGC_CRCEN_MASK (0x8U) 240 #define ATP_ALGC_CRCEN_SHIFT (3U) 241 #define ATP_ALGC_CRCEN_WIDTH (1U) 242 #define ATP_ALGC_CRCEN(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALGC_CRCEN_SHIFT)) & ATP_ALGC_CRCEN_MASK) 243 244 #define ATP_ALGC_PCRST_MASK (0x4000U) 245 #define ATP_ALGC_PCRST_SHIFT (14U) 246 #define ATP_ALGC_PCRST_WIDTH (1U) 247 #define ATP_ALGC_PCRST(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALGC_PCRST_SHIFT)) & ATP_ALGC_PCRST_MASK) 248 249 #define ATP_ALGC_RST_MASK (0x80000000U) 250 #define ATP_ALGC_RST_SHIFT (31U) 251 #define ATP_ALGC_RST_WIDTH (1U) 252 #define ATP_ALGC_RST(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALGC_RST_SHIFT)) & ATP_ALGC_RST_MASK) 253 /*! @} */ 254 255 /*! @name ALTC - AL Training Control */ 256 /*! @{ */ 257 258 #define ATP_ALTC_VTC_MASK (0xFU) 259 #define ATP_ALTC_VTC_SHIFT (0U) 260 #define ATP_ALTC_VTC_WIDTH (4U) 261 #define ATP_ALTC_VTC(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALTC_VTC_SHIFT)) & ATP_ALTC_VTC_MASK) 262 263 #define ATP_ALTC_BTC_MASK (0x3C00U) 264 #define ATP_ALTC_BTC_SHIFT (10U) 265 #define ATP_ALTC_BTC_WIDTH (4U) 266 #define ATP_ALTC_BTC(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALTC_BTC_SHIFT)) & ATP_ALTC_BTC_MASK) 267 268 #define ATP_ALTC_ATC_MASK (0x780000U) 269 #define ATP_ALTC_ATC_SHIFT (19U) 270 #define ATP_ALTC_ATC_WIDTH (4U) 271 #define ATP_ALTC_ATC(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALTC_ATC_SHIFT)) & ATP_ALTC_ATC_MASK) 272 273 #define ATP_ALTC_VHD_MASK (0x10000000U) 274 #define ATP_ALTC_VHD_SHIFT (28U) 275 #define ATP_ALTC_VHD_WIDTH (1U) 276 #define ATP_ALTC_VHD(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALTC_VHD_SHIFT)) & ATP_ALTC_VHD_MASK) 277 278 #define ATP_ALTC_BHD_MASK (0x20000000U) 279 #define ATP_ALTC_BHD_SHIFT (29U) 280 #define ATP_ALTC_BHD_WIDTH (1U) 281 #define ATP_ALTC_BHD(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALTC_BHD_SHIFT)) & ATP_ALTC_BHD_MASK) 282 283 #define ATP_ALTC_AHD_MASK (0x40000000U) 284 #define ATP_ALTC_AHD_SHIFT (30U) 285 #define ATP_ALTC_AHD_WIDTH (1U) 286 #define ATP_ALTC_AHD(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALTC_AHD_SHIFT)) & ATP_ALTC_AHD_MASK) 287 288 #define ATP_ALTC_STE_MASK (0x80000000U) 289 #define ATP_ALTC_STE_SHIFT (31U) 290 #define ATP_ALTC_STE_WIDTH (1U) 291 #define ATP_ALTC_STE(x) (((uint32_t)(((uint32_t)(x)) << ATP_ALTC_STE_SHIFT)) & ATP_ALTC_STE_MASK) 292 /*! @} */ 293 294 /*! @name LVDSTX - LVDS TX IO Configuration */ 295 /*! @{ */ 296 297 #define ATP_LVDSTX_TXAMODE_MASK (0x1U) 298 #define ATP_LVDSTX_TXAMODE_SHIFT (0U) 299 #define ATP_LVDSTX_TXAMODE_WIDTH (1U) 300 #define ATP_LVDSTX_TXAMODE(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSTX_TXAMODE_SHIFT)) & ATP_LVDSTX_TXAMODE_MASK) 301 302 #define ATP_LVDSTX_CREF_EN_MASK (0x2U) 303 #define ATP_LVDSTX_CREF_EN_SHIFT (1U) 304 #define ATP_LVDSTX_CREF_EN_WIDTH (1U) 305 #define ATP_LVDSTX_CREF_EN(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSTX_CREF_EN_SHIFT)) & ATP_LVDSTX_CREF_EN_MASK) 306 307 #define ATP_LVDSTX_TX_TREF_EN_MASK (0x4U) 308 #define ATP_LVDSTX_TX_TREF_EN_SHIFT (2U) 309 #define ATP_LVDSTX_TX_TREF_EN_WIDTH (1U) 310 #define ATP_LVDSTX_TX_TREF_EN(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSTX_TX_TREF_EN_SHIFT)) & ATP_LVDSTX_TX_TREF_EN_MASK) 311 312 #define ATP_LVDSTX_PREMPH_MASK (0x60U) 313 #define ATP_LVDSTX_PREMPH_SHIFT (5U) 314 #define ATP_LVDSTX_PREMPH_WIDTH (2U) 315 #define ATP_LVDSTX_PREMPH(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSTX_PREMPH_SHIFT)) & ATP_LVDSTX_PREMPH_MASK) 316 317 #define ATP_LVDSTX_TX_CONF_MASK (0xF000U) 318 #define ATP_LVDSTX_TX_CONF_SHIFT (12U) 319 #define ATP_LVDSTX_TX_CONF_WIDTH (4U) 320 #define ATP_LVDSTX_TX_CONF(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSTX_TX_CONF_SHIFT)) & ATP_LVDSTX_TX_CONF_MASK) 321 322 #define ATP_LVDSTX_PADS_TX_CONF_EN_MASK (0x10000U) 323 #define ATP_LVDSTX_PADS_TX_CONF_EN_SHIFT (16U) 324 #define ATP_LVDSTX_PADS_TX_CONF_EN_WIDTH (1U) 325 #define ATP_LVDSTX_PADS_TX_CONF_EN(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSTX_PADS_TX_CONF_EN_SHIFT)) & ATP_LVDSTX_PADS_TX_CONF_EN_MASK) 326 /*! @} */ 327 328 /*! @name LVDSRX - LVDS RX IO Configuration */ 329 /*! @{ */ 330 331 #define ATP_LVDSRX_RXICE_MASK (0x2U) 332 #define ATP_LVDSRX_RXICE_SHIFT (1U) 333 #define ATP_LVDSRX_RXICE_WIDTH (1U) 334 #define ATP_LVDSRX_RXICE(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSRX_RXICE_SHIFT)) & ATP_LVDSRX_RXICE_MASK) 335 336 #define ATP_LVDSRX_RXCB_MASK (0x8U) 337 #define ATP_LVDSRX_RXCB_SHIFT (3U) 338 #define ATP_LVDSRX_RXCB_WIDTH (1U) 339 #define ATP_LVDSRX_RXCB(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSRX_RXCB_SHIFT)) & ATP_LVDSRX_RXCB_MASK) 340 341 #define ATP_LVDSRX_RX_TREF_EN_MASK (0x10000U) 342 #define ATP_LVDSRX_RX_TREF_EN_SHIFT (16U) 343 #define ATP_LVDSRX_RX_TREF_EN_WIDTH (1U) 344 #define ATP_LVDSRX_RX_TREF_EN(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSRX_RX_TREF_EN_SHIFT)) & ATP_LVDSRX_RX_TREF_EN_MASK) 345 /*! @} */ 346 347 /*! @name LVDSTXOBE - LVDS TX OBE Configuration */ 348 /*! @{ */ 349 350 #define ATP_LVDSTXOBE_OBETX0_MASK (0x1U) 351 #define ATP_LVDSTXOBE_OBETX0_SHIFT (0U) 352 #define ATP_LVDSTXOBE_OBETX0_WIDTH (1U) 353 #define ATP_LVDSTXOBE_OBETX0(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSTXOBE_OBETX0_SHIFT)) & ATP_LVDSTXOBE_OBETX0_MASK) 354 355 #define ATP_LVDSTXOBE_OBETX1_MASK (0x2U) 356 #define ATP_LVDSTXOBE_OBETX1_SHIFT (1U) 357 #define ATP_LVDSTXOBE_OBETX1_WIDTH (1U) 358 #define ATP_LVDSTXOBE_OBETX1(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSTXOBE_OBETX1_SHIFT)) & ATP_LVDSTXOBE_OBETX1_MASK) 359 360 #define ATP_LVDSTXOBE_OBETX2_MASK (0x4U) 361 #define ATP_LVDSTXOBE_OBETX2_SHIFT (2U) 362 #define ATP_LVDSTXOBE_OBETX2_WIDTH (1U) 363 #define ATP_LVDSTXOBE_OBETX2(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSTXOBE_OBETX2_SHIFT)) & ATP_LVDSTXOBE_OBETX2_MASK) 364 365 #define ATP_LVDSTXOBE_OBETX3_MASK (0x8U) 366 #define ATP_LVDSTXOBE_OBETX3_SHIFT (3U) 367 #define ATP_LVDSTXOBE_OBETX3_WIDTH (1U) 368 #define ATP_LVDSTXOBE_OBETX3(x) (((uint32_t)(((uint32_t)(x)) << ATP_LVDSTXOBE_OBETX3_SHIFT)) & ATP_LVDSTXOBE_OBETX3_MASK) 369 /*! @} */ 370 371 /*! @name CIAC - CIA Control */ 372 /*! @{ */ 373 374 #define ATP_CIAC_NUM_LANE_MASK (0xFU) 375 #define ATP_CIAC_NUM_LANE_SHIFT (0U) 376 #define ATP_CIAC_NUM_LANE_WIDTH (4U) 377 #define ATP_CIAC_NUM_LANE(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIAC_NUM_LANE_SHIFT)) & ATP_CIAC_NUM_LANE_MASK) 378 379 #define ATP_CIAC_TPIUCM_MASK (0x70U) 380 #define ATP_CIAC_TPIUCM_SHIFT (4U) 381 #define ATP_CIAC_TPIUCM_WIDTH (3U) 382 #define ATP_CIAC_TPIUCM(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIAC_TPIUCM_SHIFT)) & ATP_CIAC_TPIUCM_MASK) 383 384 #define ATP_CIAC_DBITR_MASK (0x100U) 385 #define ATP_CIAC_DBITR_SHIFT (8U) 386 #define ATP_CIAC_DBITR_WIDTH (1U) 387 #define ATP_CIAC_DBITR(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIAC_DBITR_SHIFT)) & ATP_CIAC_DBITR_MASK) 388 389 #define ATP_CIAC_DBYTER_MASK (0x200U) 390 #define ATP_CIAC_DBYTER_SHIFT (9U) 391 #define ATP_CIAC_DBYTER_WIDTH (1U) 392 #define ATP_CIAC_DBYTER(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIAC_DBYTER_SHIFT)) & ATP_CIAC_DBYTER_MASK) 393 394 #define ATP_CIAC_TPIU_CLK_SEL_MASK (0x10000000U) 395 #define ATP_CIAC_TPIU_CLK_SEL_SHIFT (28U) 396 #define ATP_CIAC_TPIU_CLK_SEL_WIDTH (1U) 397 #define ATP_CIAC_TPIU_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIAC_TPIU_CLK_SEL_SHIFT)) & ATP_CIAC_TPIU_CLK_SEL_MASK) 398 399 #define ATP_CIAC_TPIU_CLK_DISABLE_MASK (0x20000000U) 400 #define ATP_CIAC_TPIU_CLK_DISABLE_SHIFT (29U) 401 #define ATP_CIAC_TPIU_CLK_DISABLE_WIDTH (1U) 402 #define ATP_CIAC_TPIU_CLK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIAC_TPIU_CLK_DISABLE_SHIFT)) & ATP_CIAC_TPIU_CLK_DISABLE_MASK) 403 /*! @} */ 404 405 /*! @name ATPE - Aurora Trace Port Enable */ 406 /*! @{ */ 407 408 #define ATP_ATPE_ATPEN_MASK (0x1U) 409 #define ATP_ATPE_ATPEN_SHIFT (0U) 410 #define ATP_ATPE_ATPEN_WIDTH (1U) 411 #define ATP_ATPE_ATPEN(x) (((uint32_t)(((uint32_t)(x)) << ATP_ATPE_ATPEN_SHIFT)) & ATP_ATPE_ATPEN_MASK) 412 413 #define ATP_ATPE_APHYEN_MASK (0x2U) 414 #define ATP_ATPE_APHYEN_SHIFT (1U) 415 #define ATP_ATPE_APHYEN_WIDTH (1U) 416 #define ATP_ATPE_APHYEN(x) (((uint32_t)(((uint32_t)(x)) << ATP_ATPE_APHYEN_SHIFT)) & ATP_ATPE_APHYEN_MASK) 417 /*! @} */ 418 419 /*! @name ITCTRL - Integration Mode Control */ 420 /*! @{ */ 421 422 #define ATP_ITCTRL_IME_MASK (0x1U) 423 #define ATP_ITCTRL_IME_SHIFT (0U) 424 #define ATP_ITCTRL_IME_WIDTH (1U) 425 #define ATP_ITCTRL_IME(x) (((uint32_t)(((uint32_t)(x)) << ATP_ITCTRL_IME_SHIFT)) & ATP_ITCTRL_IME_MASK) 426 /*! @} */ 427 428 /*! @name CLAIMSET - Claim Tag Set */ 429 /*! @{ */ 430 431 #define ATP_CLAIMSET_SET_MASK (0xFFFFFFFFU) 432 #define ATP_CLAIMSET_SET_SHIFT (0U) 433 #define ATP_CLAIMSET_SET_WIDTH (32U) 434 #define ATP_CLAIMSET_SET(x) (((uint32_t)(((uint32_t)(x)) << ATP_CLAIMSET_SET_SHIFT)) & ATP_CLAIMSET_SET_MASK) 435 /*! @} */ 436 437 /*! @name CLAIMCLR - Claim Tag Clear */ 438 /*! @{ */ 439 440 #define ATP_CLAIMCLR_CLR_MASK (0xFFFFFFFFU) 441 #define ATP_CLAIMCLR_CLR_SHIFT (0U) 442 #define ATP_CLAIMCLR_CLR_WIDTH (32U) 443 #define ATP_CLAIMCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << ATP_CLAIMCLR_CLR_SHIFT)) & ATP_CLAIMCLR_CLR_MASK) 444 /*! @} */ 445 446 /*! @name DEVAFF0 - Device Affinity 0 */ 447 /*! @{ */ 448 449 #define ATP_DEVAFF0_DEVAFF0_MASK (0xFFFFFFFFU) 450 #define ATP_DEVAFF0_DEVAFF0_SHIFT (0U) 451 #define ATP_DEVAFF0_DEVAFF0_WIDTH (32U) 452 #define ATP_DEVAFF0_DEVAFF0(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVAFF0_DEVAFF0_SHIFT)) & ATP_DEVAFF0_DEVAFF0_MASK) 453 /*! @} */ 454 455 /*! @name DEVAFF1 - Device Affinity 1 */ 456 /*! @{ */ 457 458 #define ATP_DEVAFF1_DEVAFF1_MASK (0xFFFFFFFFU) 459 #define ATP_DEVAFF1_DEVAFF1_SHIFT (0U) 460 #define ATP_DEVAFF1_DEVAFF1_WIDTH (32U) 461 #define ATP_DEVAFF1_DEVAFF1(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVAFF1_DEVAFF1_SHIFT)) & ATP_DEVAFF1_DEVAFF1_MASK) 462 /*! @} */ 463 464 /*! @name LAR - Lock Access Register */ 465 /*! @{ */ 466 467 #define ATP_LAR_KEY_MASK (0xFFFFFFFFU) 468 #define ATP_LAR_KEY_SHIFT (0U) 469 #define ATP_LAR_KEY_WIDTH (32U) 470 #define ATP_LAR_KEY(x) (((uint32_t)(((uint32_t)(x)) << ATP_LAR_KEY_SHIFT)) & ATP_LAR_KEY_MASK) 471 /*! @} */ 472 473 /*! @name LSR - Lock Status Register */ 474 /*! @{ */ 475 476 #define ATP_LSR_SLI_MASK (0x1U) 477 #define ATP_LSR_SLI_SHIFT (0U) 478 #define ATP_LSR_SLI_WIDTH (1U) 479 #define ATP_LSR_SLI(x) (((uint32_t)(((uint32_t)(x)) << ATP_LSR_SLI_SHIFT)) & ATP_LSR_SLI_MASK) 480 481 #define ATP_LSR_SLK_MASK (0x2U) 482 #define ATP_LSR_SLK_SHIFT (1U) 483 #define ATP_LSR_SLK_WIDTH (1U) 484 #define ATP_LSR_SLK(x) (((uint32_t)(((uint32_t)(x)) << ATP_LSR_SLK_SHIFT)) & ATP_LSR_SLK_MASK) 485 486 #define ATP_LSR_nTT_MASK (0x4U) 487 #define ATP_LSR_nTT_SHIFT (2U) 488 #define ATP_LSR_nTT_WIDTH (1U) 489 #define ATP_LSR_nTT(x) (((uint32_t)(((uint32_t)(x)) << ATP_LSR_nTT_SHIFT)) & ATP_LSR_nTT_MASK) 490 /*! @} */ 491 492 /*! @name AUTHSTATUS - Authentication Status */ 493 /*! @{ */ 494 495 #define ATP_AUTHSTATUS_AUTHSTATUS_MASK (0xFFU) 496 #define ATP_AUTHSTATUS_AUTHSTATUS_SHIFT (0U) 497 #define ATP_AUTHSTATUS_AUTHSTATUS_WIDTH (8U) 498 #define ATP_AUTHSTATUS_AUTHSTATUS(x) (((uint32_t)(((uint32_t)(x)) << ATP_AUTHSTATUS_AUTHSTATUS_SHIFT)) & ATP_AUTHSTATUS_AUTHSTATUS_MASK) 499 /*! @} */ 500 501 /*! @name DEVARCH - Device Architecture */ 502 /*! @{ */ 503 504 #define ATP_DEVARCH_ARCHID_MASK (0xFFFFU) 505 #define ATP_DEVARCH_ARCHID_SHIFT (0U) 506 #define ATP_DEVARCH_ARCHID_WIDTH (16U) 507 #define ATP_DEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVARCH_ARCHID_SHIFT)) & ATP_DEVARCH_ARCHID_MASK) 508 509 #define ATP_DEVARCH_REVISION_MASK (0xF0000U) 510 #define ATP_DEVARCH_REVISION_SHIFT (16U) 511 #define ATP_DEVARCH_REVISION_WIDTH (4U) 512 #define ATP_DEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVARCH_REVISION_SHIFT)) & ATP_DEVARCH_REVISION_MASK) 513 514 #define ATP_DEVARCH_PRESENT_MASK (0x100000U) 515 #define ATP_DEVARCH_PRESENT_SHIFT (20U) 516 #define ATP_DEVARCH_PRESENT_WIDTH (1U) 517 #define ATP_DEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVARCH_PRESENT_SHIFT)) & ATP_DEVARCH_PRESENT_MASK) 518 519 #define ATP_DEVARCH_ARCHITECT_MASK (0xFFE00000U) 520 #define ATP_DEVARCH_ARCHITECT_SHIFT (21U) 521 #define ATP_DEVARCH_ARCHITECT_WIDTH (11U) 522 #define ATP_DEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVARCH_ARCHITECT_SHIFT)) & ATP_DEVARCH_ARCHITECT_MASK) 523 /*! @} */ 524 525 /*! @name DEVID2 - Device Configuration 2 */ 526 /*! @{ */ 527 528 #define ATP_DEVID2_DEVID2_MASK (0xFFFFFFFFU) 529 #define ATP_DEVID2_DEVID2_SHIFT (0U) 530 #define ATP_DEVID2_DEVID2_WIDTH (32U) 531 #define ATP_DEVID2_DEVID2(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVID2_DEVID2_SHIFT)) & ATP_DEVID2_DEVID2_MASK) 532 /*! @} */ 533 534 /*! @name DEVID1 - Device Configuration 1 */ 535 /*! @{ */ 536 537 #define ATP_DEVID1_DEVID1_MASK (0xFFFFFFFFU) 538 #define ATP_DEVID1_DEVID1_SHIFT (0U) 539 #define ATP_DEVID1_DEVID1_WIDTH (32U) 540 #define ATP_DEVID1_DEVID1(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVID1_DEVID1_SHIFT)) & ATP_DEVID1_DEVID1_MASK) 541 /*! @} */ 542 543 /*! @name DEVID - Device Configuration */ 544 /*! @{ */ 545 546 #define ATP_DEVID_DEVID_MASK (0xFFFFFFFFU) 547 #define ATP_DEVID_DEVID_SHIFT (0U) 548 #define ATP_DEVID_DEVID_WIDTH (32U) 549 #define ATP_DEVID_DEVID(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVID_DEVID_SHIFT)) & ATP_DEVID_DEVID_MASK) 550 /*! @} */ 551 552 /*! @name DEVTYPE - Device Type Identifier */ 553 /*! @{ */ 554 555 #define ATP_DEVTYPE_MAJOR_MASK (0xFU) 556 #define ATP_DEVTYPE_MAJOR_SHIFT (0U) 557 #define ATP_DEVTYPE_MAJOR_WIDTH (4U) 558 #define ATP_DEVTYPE_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVTYPE_MAJOR_SHIFT)) & ATP_DEVTYPE_MAJOR_MASK) 559 560 #define ATP_DEVTYPE_SUB_MASK (0xF0U) 561 #define ATP_DEVTYPE_SUB_SHIFT (4U) 562 #define ATP_DEVTYPE_SUB_WIDTH (4U) 563 #define ATP_DEVTYPE_SUB(x) (((uint32_t)(((uint32_t)(x)) << ATP_DEVTYPE_SUB_SHIFT)) & ATP_DEVTYPE_SUB_MASK) 564 /*! @} */ 565 566 /*! @name PIDR4 - Peripheral Identification Register 4 */ 567 /*! @{ */ 568 569 #define ATP_PIDR4_DES_2_MASK (0xFU) 570 #define ATP_PIDR4_DES_2_SHIFT (0U) 571 #define ATP_PIDR4_DES_2_WIDTH (4U) 572 #define ATP_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << ATP_PIDR4_DES_2_SHIFT)) & ATP_PIDR4_DES_2_MASK) 573 574 #define ATP_PIDR4_SIZE_MASK (0xF0U) 575 #define ATP_PIDR4_SIZE_SHIFT (4U) 576 #define ATP_PIDR4_SIZE_WIDTH (4U) 577 #define ATP_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ATP_PIDR4_SIZE_SHIFT)) & ATP_PIDR4_SIZE_MASK) 578 /*! @} */ 579 580 /*! @name PIDR0 - Peripheral Identification Register 0 */ 581 /*! @{ */ 582 583 #define ATP_PIDR0_PART_0_MASK (0xFFU) 584 #define ATP_PIDR0_PART_0_SHIFT (0U) 585 #define ATP_PIDR0_PART_0_WIDTH (8U) 586 #define ATP_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << ATP_PIDR0_PART_0_SHIFT)) & ATP_PIDR0_PART_0_MASK) 587 /*! @} */ 588 589 /*! @name PIDR1 - Peripheral Identification Register 1 */ 590 /*! @{ */ 591 592 #define ATP_PIDR1_PART_1_MASK (0xFU) 593 #define ATP_PIDR1_PART_1_SHIFT (0U) 594 #define ATP_PIDR1_PART_1_WIDTH (4U) 595 #define ATP_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << ATP_PIDR1_PART_1_SHIFT)) & ATP_PIDR1_PART_1_MASK) 596 597 #define ATP_PIDR1_DES_0_MASK (0xF0U) 598 #define ATP_PIDR1_DES_0_SHIFT (4U) 599 #define ATP_PIDR1_DES_0_WIDTH (4U) 600 #define ATP_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << ATP_PIDR1_DES_0_SHIFT)) & ATP_PIDR1_DES_0_MASK) 601 /*! @} */ 602 603 /*! @name PIDR2 - Peripheral Identification Register 2 */ 604 /*! @{ */ 605 606 #define ATP_PIDR2_DES_1_MASK (0x7U) 607 #define ATP_PIDR2_DES_1_SHIFT (0U) 608 #define ATP_PIDR2_DES_1_WIDTH (3U) 609 #define ATP_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << ATP_PIDR2_DES_1_SHIFT)) & ATP_PIDR2_DES_1_MASK) 610 611 #define ATP_PIDR2_JEDEC_MASK (0x8U) 612 #define ATP_PIDR2_JEDEC_SHIFT (3U) 613 #define ATP_PIDR2_JEDEC_WIDTH (1U) 614 #define ATP_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << ATP_PIDR2_JEDEC_SHIFT)) & ATP_PIDR2_JEDEC_MASK) 615 616 #define ATP_PIDR2_REVISION_MASK (0xF0U) 617 #define ATP_PIDR2_REVISION_SHIFT (4U) 618 #define ATP_PIDR2_REVISION_WIDTH (4U) 619 #define ATP_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << ATP_PIDR2_REVISION_SHIFT)) & ATP_PIDR2_REVISION_MASK) 620 /*! @} */ 621 622 /*! @name PIDR3 - Peripheral Identification Register 3 */ 623 /*! @{ */ 624 625 #define ATP_PIDR3_REVAND_MASK (0xFU) 626 #define ATP_PIDR3_REVAND_SHIFT (0U) 627 #define ATP_PIDR3_REVAND_WIDTH (4U) 628 #define ATP_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << ATP_PIDR3_REVAND_SHIFT)) & ATP_PIDR3_REVAND_MASK) 629 630 #define ATP_PIDR3_CMOD_MASK (0xF0U) 631 #define ATP_PIDR3_CMOD_SHIFT (4U) 632 #define ATP_PIDR3_CMOD_WIDTH (4U) 633 #define ATP_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << ATP_PIDR3_CMOD_SHIFT)) & ATP_PIDR3_CMOD_MASK) 634 /*! @} */ 635 636 /*! @name CIDR0 - Component Identification Register 0 */ 637 /*! @{ */ 638 639 #define ATP_CIDR0_PRMBL_0_MASK (0xFFU) 640 #define ATP_CIDR0_PRMBL_0_SHIFT (0U) 641 #define ATP_CIDR0_PRMBL_0_WIDTH (8U) 642 #define ATP_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIDR0_PRMBL_0_SHIFT)) & ATP_CIDR0_PRMBL_0_MASK) 643 /*! @} */ 644 645 /*! @name CIDR1 - Component Identification Register 1 */ 646 /*! @{ */ 647 648 #define ATP_CIDR1_PRMBL_1_MASK (0xFU) 649 #define ATP_CIDR1_PRMBL_1_SHIFT (0U) 650 #define ATP_CIDR1_PRMBL_1_WIDTH (4U) 651 #define ATP_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIDR1_PRMBL_1_SHIFT)) & ATP_CIDR1_PRMBL_1_MASK) 652 653 #define ATP_CIDR1_CLASS_MASK (0xF0U) 654 #define ATP_CIDR1_CLASS_SHIFT (4U) 655 #define ATP_CIDR1_CLASS_WIDTH (4U) 656 #define ATP_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIDR1_CLASS_SHIFT)) & ATP_CIDR1_CLASS_MASK) 657 /*! @} */ 658 659 /*! @name CIDR2 - Component Identification Register 2 */ 660 /*! @{ */ 661 662 #define ATP_CIDR2_PRMBL_2_MASK (0xFFU) 663 #define ATP_CIDR2_PRMBL_2_SHIFT (0U) 664 #define ATP_CIDR2_PRMBL_2_WIDTH (8U) 665 #define ATP_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIDR2_PRMBL_2_SHIFT)) & ATP_CIDR2_PRMBL_2_MASK) 666 /*! @} */ 667 668 /*! @name CIDR3 - Component Identification Register 3 */ 669 /*! @{ */ 670 671 #define ATP_CIDR3_PRMBL_3_MASK (0xFFU) 672 #define ATP_CIDR3_PRMBL_3_SHIFT (0U) 673 #define ATP_CIDR3_PRMBL_3_WIDTH (8U) 674 #define ATP_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << ATP_CIDR3_PRMBL_3_SHIFT)) & ATP_CIDR3_PRMBL_3_MASK) 675 /*! @} */ 676 677 /*! 678 * @} 679 */ /* end of group ATP_Register_Masks */ 680 681 /*! 682 * @} 683 */ /* end of group ATP_Peripheral_Access_Layer */ 684 685 #endif /* #if !defined(S32Z2_ATP_H_) */ 686
