1 /**************************************************************************//**
2 * @file timer_armv8a.h
3 * @brief CMSIS Cortex-Axx Generic Timer API header file
4 * @version V1.0.0
5 * @date 05. october 2021
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2021 Arm Limited. All rights reserved.
9 * Copyright 2021-2022 NXP
10 *
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26 #ifndef __TIMER_ARMV8A_H
27 #define __TIMER_ARMV8A_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 /*******************************************************************************
34 * Timer Data Types
35 ******************************************************************************/
36
37 /** \brief ARMv8-A Generic Timer types */
38 typedef enum _ARM_TIMER_TYPE {
39 ARM_TIMER_PHYSICAL, /** Physical Timer */
40 ARM_TIMER_VIRTUAL, /** Virtual Timer */
41 ARM_TIMER_HYPERVISOR_PHYSICAL, /** Hypervisor Physical Timer */
42 ARM_TIMER_PHYSICAL_SECURE, /** Physical Secure Timer */
43 } ARM_TIMER_type_t;
44
45
46 /*******************************************************************************
47 * Timer Functions
48 ******************************************************************************/
49
ARM_TIMER_Initialize(ARM_TIMER_type_t timer)50 __STATIC_INLINE void ARM_TIMER_Initialize(ARM_TIMER_type_t timer)
51 {
52 }
53
ARM_TIMER_GetFreq(uint32_t * pVal)54 __STATIC_INLINE void ARM_TIMER_GetFreq(uint32_t *pVal)
55 {
56 __MRS(CNTFRQ_EL0, pVal);
57 }
58
ARM_TIMER_SetInterval(ARM_TIMER_type_t timer,uint32_t val)59 __STATIC_INLINE void ARM_TIMER_SetInterval(ARM_TIMER_type_t timer, uint32_t val)
60 {
61 switch (timer) {
62 case ARM_TIMER_PHYSICAL:
63 __MSR(CNTP_TVAL_EL0, val);
64 break;
65 case ARM_TIMER_VIRTUAL:
66 __MSR(CNTV_TVAL_EL0, val);
67 break;
68 case ARM_TIMER_HYPERVISOR_PHYSICAL:
69 __MSR(CNTHP_TVAL_EL2, val);
70 break;
71 case ARM_TIMER_PHYSICAL_SECURE:
72 __MSR(CNTPS_TVAL_EL1, val);
73 break;
74 default:
75 break;
76 }
77
78 __DSB();
79 __ISB();
80 }
81
ARM_TIMER_GetCount(ARM_TIMER_type_t timer,uint32_t * val)82 __STATIC_INLINE void ARM_TIMER_GetCount(ARM_TIMER_type_t timer, uint32_t *val)
83 {
84 switch (timer) {
85 case ARM_TIMER_PHYSICAL:
86 __MRS(CNTP_TVAL_EL0, val);
87 break;
88 case ARM_TIMER_VIRTUAL:
89 __MRS(CNTV_TVAL_EL0, val);
90 break;
91 case ARM_TIMER_HYPERVISOR_PHYSICAL:
92 __MRS(CNTHP_TVAL_EL2, val);
93 break;
94 case ARM_TIMER_PHYSICAL_SECURE:
95 __MRS(CNTPS_TVAL_EL1, val);
96 break;
97 default:
98 break;
99 }
100 }
101
ARM_TIMER_Start(ARM_TIMER_type_t timer,bool irq_enable)102 __STATIC_INLINE void ARM_TIMER_Start(ARM_TIMER_type_t timer, bool irq_enable)
103 {
104 uint64_t ctl = 1UL << 0;
105
106 if (!irq_enable)
107 ctl |= 1UL << 1;
108
109 switch (timer) {
110 case ARM_TIMER_PHYSICAL:
111 __MSR(CNTP_CTL_EL0, ctl);
112 break;
113 case ARM_TIMER_VIRTUAL:
114 __MSR(CNTV_CTL_EL0, ctl);
115 break;
116 case ARM_TIMER_HYPERVISOR_PHYSICAL:
117 __MSR(CNTHP_CTL_EL2, ctl);
118 break;
119 case ARM_TIMER_PHYSICAL_SECURE:
120 __MSR(CNTPS_CTL_EL1, ctl);
121 break;
122 default:
123 break;
124 }
125 }
126
ARM_TIMER_GetCounterCount(ARM_TIMER_type_t timer,uint64_t * val)127 __STATIC_FORCEINLINE void ARM_TIMER_GetCounterCount(ARM_TIMER_type_t timer, uint64_t *val)
128 {
129 switch (timer) {
130 case ARM_TIMER_PHYSICAL:
131 __MRS(cntpct_el0, val);
132 break;
133 case ARM_TIMER_VIRTUAL:
134 __MRS(cntvct_el0, val);
135 break;
136 default:
137 break;
138 }
139 }
140
141 #ifdef __cplusplus
142 }
143 #endif
144
145 #endif /* __TIMER_ARMV8A_H */
146
