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Searched refs:APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (Results 1 – 25 of 45) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h1913 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1915 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h1911 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1913 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h1911 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1913 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h1913 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1915 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h1913 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1915 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h1911 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1913 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
DMIMX8MN6_ca53.h1940 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1942 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h1717 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1719 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h1717 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1719 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h1717 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1719 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h1717 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1719 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h1717 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1719 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h2201 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
2204 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
DMIMX8QM6_dsp.h2163 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
2166 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h1943 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1945 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h1943 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1945 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h1943 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1945 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
DMIMX8MM6_ca53.h1973 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1975 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h1943 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1945 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/
DMIMX8MM2_cm4.h1943 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1945 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/
DMIMX8MM4_cm4.h1943 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
1945 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h2102 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
2104 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h2102 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
2104 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h2102 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
2104 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h2085 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) macro
2087 …(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)

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