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Searched refs:APBH_CH5_CMD_NANDLOCK_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h4171 #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) macro
4173 … (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h4171 #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) macro
4173 … (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h4171 #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) macro
4173 … (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h4171 #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) macro
4173 … (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h4171 #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) macro
4173 … (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h3578 #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) macro
3581 … (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
DMIMX8QM6_dsp.h3540 #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) macro
3543 … (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
DMIMX8QM6_cm4_core1.h2935 #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) macro
2937 … (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
DMIMX8QM6_cm4_core0.h2935 #define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) macro
2937 … (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)