Home
last modified time | relevance | path

Searched refs:ANADIG_PLL (Results 1 – 25 of 47) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_clock.c177 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
178 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
180 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
184 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
186 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
188 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
190 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
197 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
203 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
211 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
Dfsl_clock.h1640 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1645 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1650 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1671 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1676 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1681 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1686 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1691 return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_clock.c177 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
178 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
180 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
184 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
186 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
188 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
190 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
197 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
203 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
211 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
Dfsl_clock.h1640 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1645 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1650 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1671 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1676 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1681 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1686 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1691 return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_clock.c177 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
178 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
180 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
184 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
186 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
188 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
190 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
197 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
203 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
211 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
Dfsl_clock.h1640 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1645 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1650 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1671 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1676 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1681 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1686 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1691 return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_clock.c177 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
178 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
180 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
184 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
186 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
188 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
190 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
197 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
203 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
211 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
Dfsl_clock.h1640 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1645 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1650 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
1671 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1676 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1681 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1686 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
1691 return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_clock.c210 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
211 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
213 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
217 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
219 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
221 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
223 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
230 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
236 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
245 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
Dfsl_clock.h2197 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2202 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2207 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2228 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2233 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2238 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2243 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2248 return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2253 return (bool)((ANADIG_PLL->PLL_VIDEO_CTRL & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_clock.c210 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
211 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
213 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
217 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
219 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
221 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
223 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
230 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
236 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
245 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
Dfsl_clock.h2197 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2202 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2207 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2228 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2233 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2238 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2243 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2248 return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2253 return (bool)((ANADIG_PLL->PLL_VIDEO_CTRL & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_clock.c210 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
211 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
213 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
217 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
219 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
221 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
223 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
230 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
236 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
245 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
Dfsl_clock.h2164 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2169 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2174 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2195 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2200 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2205 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2210 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2215 return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2220 return (bool)((ANADIG_PLL->PLL_VIDEO_CTRL & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_clock.c210 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
211 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
213 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
217 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
219 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
221 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
223 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
230 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
236 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
245 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
Dfsl_clock.h2197 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2202 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2207 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2228 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2233 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2238 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2243 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2248 return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2253 return (bool)((ANADIG_PLL->PLL_VIDEO_CTRL & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_clock.c210 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
211 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
213 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
217 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
219 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
221 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
223 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
230 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
236 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
245 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
Dfsl_clock.h2197 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2202 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2207 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2228 return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2233 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2238 return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2243 return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2248 return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
2253 return (bool)((ANADIG_PLL->PLL_VIDEO_CTRL & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_clock.c210 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
211 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
213 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
217 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
219 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
221 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
223 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
230 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
236 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
245 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_clock.c210 if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && in CLOCK_InitArmPll()
211 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == in CLOCK_InitArmPll()
213 ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == in CLOCK_InitArmPll()
217 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) in CLOCK_InitArmPll()
219 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; in CLOCK_InitArmPll()
221 if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) in CLOCK_InitArmPll()
223 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; in CLOCK_InitArmPll()
230 reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); in CLOCK_InitArmPll()
236 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
245 ANADIG_PLL->ARM_PLL_CTRL = reg; in CLOCK_InitArmPll()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1175/
Dfsl_pm_device.c882 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
883 ANADIG_PLL->SYS_PLL1_CTRL &= ~(ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
886 ANADIG_PLL->SYS_PLL3_CTRL &= ~(ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
888 ANADIG_PLL->SYS_PLL3_UPDATE &= in PM_DEV_SetClockSourcesControlBySetpoint()
891 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
892 ANADIG_PLL->SYS_PLL2_UPDATE &= in PM_DEV_SetClockSourcesControlBySetpoint()
895 ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
896 ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
930 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
931 ANADIG_PLL->SYS_PLL1_CTRL |= (ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1171/
Dfsl_pm_device.c882 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
883 ANADIG_PLL->SYS_PLL1_CTRL &= ~(ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
886 ANADIG_PLL->SYS_PLL3_CTRL &= ~(ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
888 ANADIG_PLL->SYS_PLL3_UPDATE &= in PM_DEV_SetClockSourcesControlBySetpoint()
891 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
892 ANADIG_PLL->SYS_PLL2_UPDATE &= in PM_DEV_SetClockSourcesControlBySetpoint()
895 ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
896 ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
930 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
931 ANADIG_PLL->SYS_PLL1_CTRL |= (ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1172/
Dfsl_pm_device.c882 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
883 ANADIG_PLL->SYS_PLL1_CTRL &= ~(ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
886 ANADIG_PLL->SYS_PLL3_CTRL &= ~(ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
888 ANADIG_PLL->SYS_PLL3_UPDATE &= in PM_DEV_SetClockSourcesControlBySetpoint()
891 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
892 ANADIG_PLL->SYS_PLL2_UPDATE &= in PM_DEV_SetClockSourcesControlBySetpoint()
895 ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
896 ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
930 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
931 ANADIG_PLL->SYS_PLL1_CTRL |= (ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1176/
Dfsl_pm_device.c882 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
883 ANADIG_PLL->SYS_PLL1_CTRL &= ~(ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
886 ANADIG_PLL->SYS_PLL3_CTRL &= ~(ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
888 ANADIG_PLL->SYS_PLL3_UPDATE &= in PM_DEV_SetClockSourcesControlBySetpoint()
891 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
892 ANADIG_PLL->SYS_PLL2_UPDATE &= in PM_DEV_SetClockSourcesControlBySetpoint()
895 ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
896 ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
930 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
931 ANADIG_PLL->SYS_PLL1_CTRL |= (ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1173/
Dfsl_pm_device.c882 ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
883 ANADIG_PLL->SYS_PLL1_CTRL &= ~(ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
886 ANADIG_PLL->SYS_PLL3_CTRL &= ~(ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
888 ANADIG_PLL->SYS_PLL3_UPDATE &= in PM_DEV_SetClockSourcesControlBySetpoint()
891 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
892 ANADIG_PLL->SYS_PLL2_UPDATE &= in PM_DEV_SetClockSourcesControlBySetpoint()
895 ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
896 ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
930 ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK; in PM_DEV_SetClockSourcesControlBySetpoint()
931 ANADIG_PLL->SYS_PLL1_CTRL |= (ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK | in PM_DEV_SetClockSourcesControlBySetpoint()
[all …]

12