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Searched refs:AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_anatop_ai.h365 …t32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK)
366 #define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U) macro
Dfsl_clock.c1441 return ((tmp32 & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) == AI_RCOSC400M_STAT0_CLK1M_ERR_MASK); in CLOCK_OSC_CheckLocked1MHzErrorFlag()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_anatop_ai.h365 …t32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK)
366 #define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U) macro
Dfsl_clock.c1432 return ((tmp32 & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) == AI_RCOSC400M_STAT0_CLK1M_ERR_MASK); in CLOCK_OSC_CheckLocked1MHzErrorFlag()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_anatop_ai.h365 …t32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK)
366 #define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U) macro
Dfsl_clock.c1441 return ((tmp32 & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) == AI_RCOSC400M_STAT0_CLK1M_ERR_MASK); in CLOCK_OSC_CheckLocked1MHzErrorFlag()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_anatop_ai.h365 …t32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK)
366 #define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U) macro
Dfsl_clock.c1441 return ((tmp32 & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) == AI_RCOSC400M_STAT0_CLK1M_ERR_MASK); in CLOCK_OSC_CheckLocked1MHzErrorFlag()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_anatop_ai.h365 …t32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK)
366 #define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U) macro
Dfsl_clock.c1441 return ((tmp32 & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) == AI_RCOSC400M_STAT0_CLK1M_ERR_MASK); in CLOCK_OSC_CheckLocked1MHzErrorFlag()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_anatop_ai.h365 …t32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK)
366 #define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U) macro
Dfsl_clock.c1432 return ((tmp32 & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) == AI_RCOSC400M_STAT0_CLK1M_ERR_MASK); in CLOCK_OSC_CheckLocked1MHzErrorFlag()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_anatop_ai.h365 …t32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK)
366 #define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U) macro
Dfsl_clock.c1441 return ((tmp32 & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) == AI_RCOSC400M_STAT0_CLK1M_ERR_MASK); in CLOCK_OSC_CheckLocked1MHzErrorFlag()