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Searched refs:AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_anatop_ai.h352 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK)
353 #define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U) macro
Dfsl_clock.c1386 tmp32 &= ~(AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK | AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK); in CLOCK_OSC_Set1MHzOutputBehavior()
1396 tmp32 |= AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK; in CLOCK_OSC_Set1MHzOutputBehavior()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_anatop_ai.h352 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK)
353 #define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U) macro
Dfsl_clock.c1377 tmp32 &= ~(AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK | AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK); in CLOCK_OSC_Set1MHzOutputBehavior()
1387 tmp32 |= AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK; in CLOCK_OSC_Set1MHzOutputBehavior()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_anatop_ai.h352 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK)
353 #define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U) macro
Dfsl_clock.c1386 tmp32 &= ~(AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK | AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK); in CLOCK_OSC_Set1MHzOutputBehavior()
1396 tmp32 |= AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK; in CLOCK_OSC_Set1MHzOutputBehavior()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_anatop_ai.h352 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK)
353 #define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U) macro
Dfsl_clock.c1386 tmp32 &= ~(AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK | AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK); in CLOCK_OSC_Set1MHzOutputBehavior()
1396 tmp32 |= AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK; in CLOCK_OSC_Set1MHzOutputBehavior()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_anatop_ai.h352 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK)
353 #define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U) macro
Dfsl_clock.c1386 tmp32 &= ~(AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK | AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK); in CLOCK_OSC_Set1MHzOutputBehavior()
1396 tmp32 |= AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK; in CLOCK_OSC_Set1MHzOutputBehavior()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_anatop_ai.h352 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK)
353 #define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U) macro
Dfsl_clock.c1377 tmp32 &= ~(AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK | AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK); in CLOCK_OSC_Set1MHzOutputBehavior()
1387 tmp32 |= AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK; in CLOCK_OSC_Set1MHzOutputBehavior()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_anatop_ai.h352 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK)
353 #define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U) macro
Dfsl_clock.c1386 tmp32 &= ~(AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK | AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK); in CLOCK_OSC_Set1MHzOutputBehavior()
1396 tmp32 |= AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK; in CLOCK_OSC_Set1MHzOutputBehavior()