Searched refs:AI_RCOSC400M_CTRL2_TUNE_START_MASK (Results 1 – 14 of 14) sorted by relevance
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/ |
| D | fsl_anatop_ai.h | 329 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK)
330 #define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U) macro
|
| D | fsl_clock.c | 1331 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
1335 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/ |
| D | fsl_anatop_ai.h | 329 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK)
330 #define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U) macro
|
| D | fsl_clock.c | 1322 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
1326 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/ |
| D | fsl_anatop_ai.h | 329 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK)
330 #define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U) macro
|
| D | fsl_clock.c | 1331 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
1335 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/ |
| D | fsl_anatop_ai.h | 329 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK)
330 #define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U) macro
|
| D | fsl_clock.c | 1331 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
1335 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/ |
| D | fsl_anatop_ai.h | 329 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK)
330 #define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U) macro
|
| D | fsl_clock.c | 1331 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
1335 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/ |
| D | fsl_anatop_ai.h | 329 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK)
330 #define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U) macro
|
| D | fsl_clock.c | 1322 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
1326 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/ |
| D | fsl_anatop_ai.h | 329 …2_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK)
330 #define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U) macro
|
| D | fsl_clock.c | 1331 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
1335 ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_START_MASK); in CLOCK_OSC_EnableOscRc400MTuneLogic()
|
