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Searched refs:AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_anatop_ai.h334 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK)
335 #define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) macro
Dfsl_clock.c1368 tmp32 &= ~AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK; in CLOCK_OSC_SetOscRc400MTuneValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_anatop_ai.h334 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK)
335 #define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) macro
Dfsl_clock.c1359 tmp32 &= ~AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK; in CLOCK_OSC_SetOscRc400MTuneValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_anatop_ai.h334 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK)
335 #define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) macro
Dfsl_clock.c1368 tmp32 &= ~AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK; in CLOCK_OSC_SetOscRc400MTuneValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_anatop_ai.h334 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK)
335 #define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) macro
Dfsl_clock.c1368 tmp32 &= ~AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK; in CLOCK_OSC_SetOscRc400MTuneValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_anatop_ai.h334 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK)
335 #define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) macro
Dfsl_clock.c1368 tmp32 &= ~AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK; in CLOCK_OSC_SetOscRc400MTuneValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_anatop_ai.h334 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK)
335 #define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) macro
Dfsl_clock.c1359 tmp32 &= ~AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK; in CLOCK_OSC_SetOscRc400MTuneValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_anatop_ai.h334 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK)
335 #define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) macro
Dfsl_clock.c1368 tmp32 &= ~AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK; in CLOCK_OSC_SetOscRc400MTuneValue()