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Searched refs:AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_anatop_ai.h311 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK)
312 #define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) macro
Dfsl_clock.c1276 …tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) | AI_RCOSC400M_CTRL1_TARGET_COUNT(targetC… in CLOCK_OSC_SetOscRc400MFastClkCount()
1416 …targetCount = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) >> AI_RCOSC400M_CTRL1_TARG… in CLOCK_OSC_SetLocked1MHzCount()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_anatop_ai.h311 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK)
312 #define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) macro
Dfsl_clock.c1267 …tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) | AI_RCOSC400M_CTRL1_TARGET_COUNT(targetC… in CLOCK_OSC_SetOscRc400MFastClkCount()
1407 …targetCount = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) >> AI_RCOSC400M_CTRL1_TARG… in CLOCK_OSC_SetLocked1MHzCount()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_anatop_ai.h311 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK)
312 #define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) macro
Dfsl_clock.c1276 …tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) | AI_RCOSC400M_CTRL1_TARGET_COUNT(targetC… in CLOCK_OSC_SetOscRc400MFastClkCount()
1416 …targetCount = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) >> AI_RCOSC400M_CTRL1_TARG… in CLOCK_OSC_SetLocked1MHzCount()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_anatop_ai.h311 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK)
312 #define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) macro
Dfsl_clock.c1276 …tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) | AI_RCOSC400M_CTRL1_TARGET_COUNT(targetC… in CLOCK_OSC_SetOscRc400MFastClkCount()
1416 …targetCount = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) >> AI_RCOSC400M_CTRL1_TARG… in CLOCK_OSC_SetLocked1MHzCount()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_anatop_ai.h311 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK)
312 #define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) macro
Dfsl_clock.c1276 …tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) | AI_RCOSC400M_CTRL1_TARGET_COUNT(targetC… in CLOCK_OSC_SetOscRc400MFastClkCount()
1416 …targetCount = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) >> AI_RCOSC400M_CTRL1_TARG… in CLOCK_OSC_SetLocked1MHzCount()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_anatop_ai.h311 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK)
312 #define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) macro
Dfsl_clock.c1267 …tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) | AI_RCOSC400M_CTRL1_TARGET_COUNT(targetC… in CLOCK_OSC_SetOscRc400MFastClkCount()
1407 …targetCount = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) >> AI_RCOSC400M_CTRL1_TARG… in CLOCK_OSC_SetLocked1MHzCount()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_anatop_ai.h311 …(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK)
312 #define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) macro
Dfsl_clock.c1276 …tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) | AI_RCOSC400M_CTRL1_TARGET_COUNT(targetC… in CLOCK_OSC_SetOscRc400MFastClkCount()
1416 …targetCount = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) >> AI_RCOSC400M_CTRL1_TARG… in CLOCK_OSC_SetLocked1MHzCount()