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Searched refs:AIPS_OPACR_SP5_MASK (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K144W_AIPS.h317 #define AIPS_OPACR_SP5_MASK (0x400U) macro
320 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)
DS32K116_AIPS.h317 #define AIPS_OPACR_SP5_MASK (0x400U) macro
320 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)
DS32K118_AIPS.h317 #define AIPS_OPACR_SP5_MASK (0x400U) macro
320 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)
DS32K142_AIPS.h317 #define AIPS_OPACR_SP5_MASK (0x400U) macro
320 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)
DS32K142W_AIPS.h317 #define AIPS_OPACR_SP5_MASK (0x400U) macro
320 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)
DS32K144_AIPS.h317 #define AIPS_OPACR_SP5_MASK (0x400U) macro
320 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)
DS32K146_AIPS.h317 #define AIPS_OPACR_SP5_MASK (0x400U) macro
320 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)
DS32K148_AIPS.h332 #define AIPS_OPACR_SP5_MASK (0x400U) macro
335 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h1395 #define AIPS_OPACR_SP5_MASK (0x400U) macro
1401 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h1395 #define AIPS_OPACR_SP5_MASK (0x400U) macro
1401 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h1395 #define AIPS_OPACR_SP5_MASK (0x400U) macro
1401 … (((uint32_t)(((uint32_t)(x)) << AIPS_OPACR_SP5_SHIFT)) & AIPS_OPACR_SP5_MASK)