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Searched refs:AHB_SECURE_CTRL_RAM31_RULE_RULE5_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h4241 #define AHB_SECURE_CTRL_RAM31_RULE_RULE5_MASK (0x300000U) macro
4249 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h4245 #define AHB_SECURE_CTRL_RAM31_RULE_RULE5_MASK (0x300000U) macro
4253 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h4244 #define AHB_SECURE_CTRL_RAM31_RULE_RULE5_MASK (0x300000U) macro
4252 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE5_MASK)