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Searched refs:AHB_SECURE_CTRL_RAM31_RULE_RULE4_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h4231 #define AHB_SECURE_CTRL_RAM31_RULE_RULE4_MASK (0x30000U) macro
4239 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h4235 #define AHB_SECURE_CTRL_RAM31_RULE_RULE4_MASK (0x30000U) macro
4243 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h4234 #define AHB_SECURE_CTRL_RAM31_RULE_RULE4_MASK (0x30000U) macro
4242 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM31_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_RAM31_RULE_RULE4_MASK)