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Searched refs:AHB_SECURE_CTRL_RAM30_RULE_RULE0_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h4104 #define AHB_SECURE_CTRL_RAM30_RULE_RULE0_MASK (0x3U) macro
4112 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h4108 #define AHB_SECURE_CTRL_RAM30_RULE_RULE0_MASK (0x3U) macro
4116 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h4107 #define AHB_SECURE_CTRL_RAM30_RULE_RULE0_MASK (0x3U) macro
4115 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM30_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM30_RULE_RULE0_MASK)