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Searched refs:AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h3584 #define AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK (0x3U) macro
3592 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h3584 #define AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK (0x3U) macro
3592 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h3669 #define AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK (0x3U) macro
3677 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h3673 #define AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK (0x3U) macro
3681 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h3672 #define AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK (0x3U) macro
3680 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM25_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM25_RULE_RULE0_MASK)