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Searched refs:AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h2995 #define AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK (0x300U) macro
3003 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h2995 #define AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK (0x300U) macro
3003 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h3080 #define AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK (0x300U) macro
3088 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h3084 #define AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK (0x300U) macro
3092 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h3083 #define AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK (0x300U) macro
3091 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h3321 #define AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK (0x300U) macro
3324 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h3321 #define AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK (0x300U) macro
3324 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE2_MASK)