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Searched refs:AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h2985 #define AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK (0x30U) macro
2993 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h2985 #define AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK (0x30U) macro
2993 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h3070 #define AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK (0x30U) macro
3078 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h3074 #define AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK (0x30U) macro
3082 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h3073 #define AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK (0x30U) macro
3081 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h3316 #define AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK (0x30U) macro
3319 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h3316 #define AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK (0x30U) macro
3319 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM18_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_RAM18_RULE_RULE1_MASK)