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Searched refs:AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h2366 #define AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK (0x3U) macro
2374 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h2366 #define AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK (0x3U) macro
2374 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h2451 #define AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK (0x3U) macro
2459 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h2455 #define AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK (0x3U) macro
2463 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h2454 #define AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK (0x3U) macro
2462 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h2982 #define AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK (0x3U) macro
2985 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h2982 #define AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK (0x3U) macro
2985 …(uint32_t)(x)) << AHB_SECURE_CTRL_RAM11_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_RAM11_RULE_RULE0_MASK)